Crimping memory module and equipment

Abstract

The invention provides a crimping memory module and equipment, and relates to the technical field of semiconductors. The crimping memory module comprises a crimping memory circuit board; the plurality of memory chips are arranged on the crimping memory circuit board; the power supply management device is arranged on the crimping memory circuit board and electrically connected with the plurality of memory chips, the power supply management device comprises a preset number of power supply management chips, and the power supply management device is used for providing electric energy generated by the preset number of power supply management chips to the plurality of memory chips as power supply electric energy, the preset number of the power management chips in the power management device is preset according to the power demand of the plurality of memory chips. According to the embodiment of the invention, the crimping memory module can have a power supply scheme suitable for the crimping memory module.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly to a press-fit memory module and equipment. Background Art

[0002] With the development of semiconductor technology, Compress Attached Memory Module (CAMM) has become one of the important research directions of semiconductor technology due to its thinner thickness, better heat dissipation and lower power consumption.

[0003] However, current press-fit memory modules lack a suitable power supply solution for themselves.

[0004] Therefore, how to provide a press-fit memory module with a power supply solution suitable for itself has become a technical problem that needs to be solved urgently. Summary of the invention

[0005] The present disclosure provides a crimped memory module and device, which at least to a certain extent overcomes the problem that the crimped memory module lacks a power supply solution suitable for its own power supply needs.

[0006] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by the practice of the present disclosure.

[0007] According to one aspect of the present disclosure, there is provided a press-fit memory module, comprising:

[0008] Press-fit memory circuit boards;

[0009] A plurality of memory chips are disposed on a press-fit memory circuit board;

[0010] A power management device is arranged on a crimped memory circuit board and is electrically connected to multiple memory chips. The power management device includes a preset number of power management chips, which are used to provide the electric energy generated by the preset number of power management chips as power supply energy to the multiple memory chips, wherein the preset number of power management chips in the power management device is preset according to the power consumption requirements of the multiple memory chips.

[0011] In one embodiment, the power management device includes multiple power management chips, wherein the power management chip includes a first power supply pin, and the first power supply pins of the multiple power management chips are connected to provide electric energy generated by the multiple power management chips to multiple memory chips through the connected first power supply pins.

[0012] In one embodiment, the first power supply pin includes N power transmission pins, each power transmission pin is used to output a power supply voltage, wherein the i-th power transmission pins of multiple power management chips are connected to provide the power supply voltage output by the connected i-th power transmission pin to multiple memory chips, wherein N is an integer greater than or equal to 1, and i is any integer less than or equal to N.

[0013] In one embodiment, the module further includes: configuring a serial detection chip for storing preset power quantity information, wherein the preset power quantity information is used to indicate the quantity of power management chips in the power management device.

[0014] In one embodiment, the power management chip further includes a mode register, which is used to store preset power configuration information of the power management chip to which it belongs, wherein the preset power configuration information is configured by the chip control device based on preset power quantity information in the configuration serial detection chip.

[0015] In one embodiment, the configuration serial detection chip includes a first communication pin, and each power management chip includes a second communication pin, wherein the first communication pin is respectively connected to the second communication pin of each power management chip to perform communication connection between the configuration serial detection chip and each power management chip.

[0016] In one embodiment, the serial detection chip is configured to include a first power supply pin, and each power management chip further includes a second power supply pin;

[0017] In which, when the power management device includes multiple power management chips, the second power pin of the target power management chip in the power management device is connected to the first power pin, and the second power pins of other power management chips in the power management device except the target power management chip are left vacant, so that the electric energy output by the second power pin of the target power management chip can be provided to the configured serial detection chip as the power supply energy for the configured serial detection chip.

[0018] In one embodiment, each power management chip includes a status signal pin, which is used to output a first level indicating that each power management chip is normal or a second level indicating that each power management chip is faulty, wherein, when the power management device includes multiple power management chips, the status signal pins of the multiple power management chips are connected to a status signal transmission line, wherein, when the status signal pins of one or more power management chips output the second level, the level on the status signal transmission line is adjusted to the second level, and the second level on the status signal transmission line represents a fault in the power management device.

[0019] In one embodiment, each power management chip includes an enable pin, which is used to start or shut down each power management chip, wherein the enable pin of each power management chip is used to receive a control instruction sent by a chip control device, and the control instruction is used to start or shut down each power management chip.

[0020] In one embodiment, each power management chip includes a communication address pin, which is used to indicate the communication address of each power management chip, wherein the communication address pins of multiple power management chips correspond to different voltages, and different voltages represent different communication addresses.

[0021] In one embodiment, a first power supply pin of one of the multiple power management chips is directly connected to a first conductive line, and a first power supply pin of another power management chip among the multiple power management chips is connected to the first conductive line or a first power supply pin of one of the power management chips through a connector.

[0022] In one embodiment, the connecting member includes: one or more of a resistor with a preset resistance, a connecting line, a switching element, and a fuse device.

[0023] In one embodiment, the connector includes a fuse device, which is a fuse or an anti-fuse;

[0024] Among them, for each other power management chip, when the fuse device corresponding to each other power management chip is in a low-impedance state, each other power management chip supplies power to multiple memory chips; when the fuse device is in a high-impedance state, each other power management chip does not supply power to multiple memory chips.

[0025] In one embodiment, the resistance state of the fuse device is adjusted by the tester when the actual number of the power management chips powered is wrong.

[0026] In one embodiment, a test machine determines whether there is an error in the actual quantity based on preset power quantity information, wherein the preset power quantity information is stored in a configuration serial detection chip and is used to indicate the number of power management chips in a power management device; wherein, when the actual quantity is wrong and the actual quantity is greater than the quantity indicated by the preset power quantity information, the test machine adjusts the first target fuse device to a high impedance state to disconnect the power management chip corresponding to the first target fuse device from the power management device; wherein, when the actual quantity is wrong and the actual quantity is less than the quantity indicated by the preset power quantity information, the test machine adjusts the fuse device to a low impedance state to connect the power management chip corresponding to the second target fuse device to the power management device.

[0027] In one embodiment, each power management chip is used to provide power to some of the memory chips.

[0028] In one embodiment, multiple memory chips can be divided into multiple groups, each group of memory chips belongs to a memory channel, each power management chip corresponds to at least one memory channel, and each power management chip is used to provide power to the memory chips in the corresponding memory channel.

[0029] According to yet another aspect of the present disclosure, there is provided an electronic device comprising the above-mentioned crimped memory module.

[0030] The crimped memory module and device provided by the embodiments of the present disclosure can flexibly set the preset number of power management chips in the power management device according to the power demand of the memory chip, so that the power generated by the preset number of power management chips can flexibly meet the power demand of various crimped memory modules, avoiding the occurrence of voltage drops due to insufficient power supply. Furthermore, the technical solution provided by the embodiments of the present disclosure can realize flexible power supply to the crimped memory module while ensuring the stability of power supply, so that the crimped memory module can have a power supply solution suitable for itself.

[0031] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0033] Figure 1 A schematic structural diagram of a press-fit memory module provided by an embodiment of the present disclosure is shown;

[0034] Figure 2 A schematic structural diagram of a press-fit memory module provided by an embodiment of the present disclosure is shown;

[0035] Figure 3 A schematic structural diagram of an exemplary press-fit memory module provided by an embodiment of the present disclosure is shown;

[0036] Figure 4 A schematic diagram of the structure of an exemplary power management chip provided by an embodiment of the present disclosure is shown;

[0037] Figure 5 A schematic structural diagram of another exemplary press-fit memory module provided by an embodiment of the present disclosure is shown;

[0038] Figure 6A schematic structural diagram of another exemplary crimped memory module provided by an embodiment of the present disclosure is shown;

[0039] Figure 7 A schematic diagram of the structure of another compression-bonded memory module provided by an embodiment of the present disclosure is shown;

[0040] Figure 8 A schematic diagram showing the structure of another exemplary power management chip provided by an embodiment of the present disclosure is shown;

[0041] Fig. 9 A schematic diagram showing the structure of another exemplary power management chip provided by an embodiment of the present disclosure is shown;

[0042] Fig.10 A schematic diagram showing the structure of another exemplary power management chip provided by an embodiment of the present disclosure is shown;

[0043] Fig.11 A schematic diagram showing the structure of another exemplary power management chip provided by an embodiment of the present disclosure is shown;

[0044] Fig.12 A schematic diagram showing the structure of another exemplary power management chip provided by an embodiment of the present disclosure is shown;

[0045] Fig.13 A schematic diagram showing the structure of another exemplary power management chip provided by an embodiment of the present disclosure is shown;

[0046] Fig.14 A schematic diagram showing the structure of another exemplary power management chip provided by an embodiment of the present disclosure is shown;

[0047] Fig.15 A schematic diagram of the structure of an exemplary first power management chip provided by an embodiment of the present disclosure is shown;

[0048] Fig.16 A schematic diagram of the structure of an exemplary second power management chip provided by an embodiment of the present disclosure is shown;

[0049] Fig.17 A schematic diagram of the structure of an exemplary serial detection chip configuration provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0050] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the disclosure will be more comprehensive and complete and to fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0051] As mentioned in the background technology, Compress Attached Memory Module (CAMM) has become one of the important research directions of semiconductor technology.

[0052] Figure 1 FIG. 2 shows a schematic diagram of a structure of a compression-bonded memory module provided by an embodiment of the present disclosure. Figure 1 As shown, the compression memory module 10 and the system main board 20 can be arranged between the top bolster plate 30 and the bottom bolster plate 40, and the compression memory module 10 can be fixed on the compression connector 50 of the system main board 20 by using screws. In some embodiments, the external connection end of the compression memory module 10 can be a contact. Accordingly, the compression memory module 10 can be connected and fixed to the system main board by combining contacts and screws.

[0053] However, the standard for press-fit memory modules has not yet been finalized. The inventors have found through research that in an exemplary scenario, a small outline dual in-line memory module (Small outline Dual In-line Memory Module, SoDIMM) has only one memory channel, while a press-fit memory module can have two independent memory channels. Therefore, in theory, the load of a press-fit memory module is twice that of a small outline dual in-line memory module. Therefore, if the power supply design of a small outline dual in-line memory module is borrowed, that is, if a power management chip (Power Management Integrated Circuit, PMIC) is used to power the memory chip in the press-fit memory module, then in extreme cases, the power demand of the press-fit memory module may not be met, causing voltage drops and the like.

[0054] Therefore, how to provide a press-fit memory module with a power supply solution suitable for itself has become a technical solution that needs to be solved urgently.

[0055] Based on this, the embodiments of the present disclosure provide a press-fit memory module and device, which can be applied to semiconductor storage scenarios, such as module design scenarios, especially power supply design scenarios of CAMM modules. Through the technical solution provided by the embodiments of the present disclosure, while ensuring the stability of power supply, flexible power supply to the press-fit memory module can be achieved, so that the press-fit memory module can have a power supply solution suitable for itself.

[0056] Before describing the technical solutions provided by the embodiments of the present disclosure, the technical terms involved in the embodiments of the present disclosure are described first.

[0057] (1) Power Management Integrated Circuit (PMIC), which is an integrated circuit used for voltage conversion, voltage regulation, and battery management. For example, in the field of semiconductor technology, its important role may be to provide power support for other chips on the memory module (such as memory chips, etc.).

[0058] (2) A configuration serial presence detect chip (Serial Presence Detect, SPD), i.e., a chip for storing the SPD information of the module. Exemplarily, the SPD information includes important information of the storage module, such as chip information of the memory mode, module manufacturer information, operating frequency, operating voltage, speed, capacity, voltage, row and column address bandwidth and other information. Exemplarily, the configuration serial detection chip may be an electrically erasable programmable read-only memory (EEPROM). Exemplarily, the chip control device may access the SPD information in the configuration serial detection chip through an Inter-Integrated Circuit (I2C) bus or a System Management Bus (SMBus).

[0059] After introducing the above technical terms, the technical solutions provided by the embodiments of the present disclosure are described below.

[0060] Figure 2 FIG. 2 shows a schematic diagram of a structure of a compression-bonded memory module provided by an embodiment of the present disclosure. Figure 2 As shown, the compression memory module 20 may include a compression memory circuit board 21, a plurality of memory chips 22 and a power management device 23. The compression memory module may have two independent memory channels. Next, each part of the compression memory module will be described in turn.

[0061] The crimped memory circuit board 21 may be a circuit board used to realize electrical connection between devices in the crimped memory module 20, such as a printed circuit board (PCB) or other circuit board. The specific form of the crimped memory circuit board 21 is not limited.

[0062] The memory chip 22 may be disposed on the compression memory circuit board 10 .

[0063] In terms of the arrangement, in some embodiments, the memory chip 22 can be arranged on one side surface of the pressed memory circuit board 10. In other embodiments, the memory chip 22 can be arranged on both sides surface of the pressed memory circuit board 10.

[0064] In terms of specific form, in some embodiments, the memory chip 22 may be a chip for data storage. Exemplarily, the memory chip 22 may be a dynamic random access memory chip (DRAM), a static random access memory chip (SRAM), or a flash memory chip. For example, the memory chip 22 may be a dual data rate synchronous dynamic random access memory (DDR SDRAM) or a low power dual data rate synchronous dynamic random access memory (LPDDRSDRAM). For example, the semiconductor memory may be DDR5, DDR6, LPDDR4, LPDDR5, LPDDR6, etc. The present disclosure does not limit the specific form of the memory chip 22.

[0065] After the memory chip 22 is introduced, the power management device 23 will be described next.

[0066] The power management device 23 may be disposed on the compression memory circuit board 21 and electrically connected to the plurality of memory chips 22. The power management device 23 includes a preset number (e.g., K) of power management chips 2311 to 231K, and is used to provide the power generated by the preset number of power management chips 2311 to 231K as power supply power to the plurality of memory chips 20. The number of power management chips in the power management device 23 (i.e., K) is set according to the power demand of the plurality of memory chips 20.

[0067] Next, the power management device 23 will be specifically described from aspects such as the setting position, specific structure, number of power management chips, and power supply method.

[0068] In terms of the installation position, in some embodiments, the power management chips 2311 to 231K can be installed on a memory bar (raw card) of a press-fit memory module.

[0069] In terms of specific structure, in some embodiments, in order to provide power supply to the memory chip, when the power management device 23 includes multiple power management chips 2311 to 231K, each power management chip includes a first power supply pin A1, wherein the first power supply pin A1 can be a pin for providing power supply to the memory chip.

[0070] Specifically, the first power supply pins A1 of the plurality of power management chips are connected to provide the power generated by the plurality of power management chips 2311 to 231K to the plurality of memory chips through the connected first power supply pins A1. Exemplarily, the first power supply pins of the plurality of power management chips 2311 to 231K can be connected to the same first conductive line to provide the power generated by the plurality of power management chips to the plurality of memory chips 22 through the first conductive line.

[0071] In one example, Figure 3 FIG. 1 shows a schematic diagram of the structure of an exemplary compression-bonded memory module provided by an embodiment of the present disclosure. Figure 3 As shown, in the case where the power management device 23 includes two power management chips, namely, the first power management chip 23111 and the second power management chip 2312, the first power management chip 23111 and the second power management chip 2312 are connected to each other with their respective first power supply pins A1, so as to provide the electric energy generated by the first power management chip 2311 and the second power management chip 2312 to the memory chip through the connected first power supply pins A1. For example, the power supply voltage V0 outputted after the first power supply pins A1 of the first power management chip 2311 and the second power management chip 2312 are connected can be provided to the memory chip as the power supply voltage of the memory chip.

[0072] Through the embodiment of the present disclosure, multiple power management chips can jointly supply power to multiple memory chips through the first power supply pin, thereby meeting the power requirements of multiple memory chips, avoiding the occurrence of voltage drops due to insufficient power supply, and ensuring power supply stability.

[0073] In one embodiment, in order to provide multiple power supply voltages to the memory chip, each first power supply pin A1 includes N power transmission pins, each power transmission pin is used to output a power supply voltage. Wherein, N is an integer greater than or equal to 1. For example, Figure 4 FIG. 1 shows a schematic diagram of the structure of an exemplary power management chip provided by an embodiment of the present disclosure. Figure 4As shown, for the first power management chip 2311, it may include multiple power transmission pins, such as power transmission pins A111, A112 and A113. The second power management chip 2312 may include multiple power transmission pins, such as power transmission pins A121, A122 and A123. In a specific example, in order to ensure the stable output of voltage, each power transmission pin may include a switching voltage pin, a startup voltage pin and a feedback voltage pin. For example, taking the power transmission pins A111 and A121 as examples, it may include a switching voltage pin SWA, a startup voltage pin SWA_BOOT and a feedback voltage pin SWA_FB_P. Taking the power transmission pins A112 and A122 as examples, it may include a switching voltage pin SWB, a startup voltage pin SWB_BOOT and a feedback voltage pin SWB_FB_P. Taking the power transmission pins A113 and A123 as examples, it may include a switching voltage pin SWC, a startup voltage pin SWC_BOOT and a feedback voltage pin SWC_FB_P.

[0074] Specifically, the i-th power transmission pins of the multiple power management chips are connected to provide the power supply voltage output by the connected i-th power transmission pins to the multiple memory chips. Wherein, i is any integer less than or equal to N. Exemplarily, the i-th power transmission pin can be connected to the i-th first conductive line to provide the power supply voltage output by the i-th power transmission pin to the multiple memory chips through the i-th first conductive line.

[0075] In one example, see Figure 4 The first power transmission pin A111 of the first power management chip 2311 is connected to the first power transmission pin A121 of the second power management chip 2312 to output the first power supply voltage VDD; the second power transmission pin A112 of the first power management chip 2311 is connected to the second power transmission pin A122 of the second power management chip 2312 to output the second power supply voltage VDDQ; the third power transmission pin A113 of the first power management chip 2311 is connected to the third power transmission pin A123 of the second power management chip 2312 to output the third power supply voltage VPP.

[0076] Through the embodiments of the present disclosure, N power transmission pins of multiple power management chips can be connected separately to provide N power transmission voltages to the memory chip through N power transmission pins, so that the power management device can achieve stable output of multiple power transmission voltages, thereby improving the power supply capacity of the power management device.

[0077] In some embodiments, Figure 5 FIG. 2 shows a schematic diagram of the structure of another exemplary compression-bonded memory module provided by an embodiment of the present disclosure. Figure 5As shown, the first power supply pin A1 of one of the multiple power management chips 2311 to 231K (for example, the first power management chip 2311) is directly connected to the first conductive line L1, and the first power supply pin A1 of other power management chips 2311 to 231K (for example, the second power management chip 2312 to 231K) is connected to the first conductive line L1 or the first power supply pin A1 of one of the power management chips (for example, the first power management chip 2311) through a connector 232.

[0078] Through this embodiment, multiple power management chips 2311 to 231K can be connected to the first conductive line L1 through the connector 232, so that the power supply voltage that can meet the power demand of the crimped memory module can be output through the first conductive line L1, thereby ensuring the power supply quality of the power management device 23.

[0079] In one embodiment, the connector 232 may be an electrical element for electrical connection. Exemplarily, the connector 232 may include: one or more of a resistor with a preset resistance, a connecting wire, a switch element, and a fuse device.

[0080] Wherein, the resistor may be an electrical element having ohmic characteristics. For example, see Figure 3 , the connector 232 may be Figure 3 The resistor R1 in the embodiment of the present disclosure may be 0 ohm. For example, in order to improve the power supply quality, the preset resistance value of the resistor R1 may be 0 ohm. It should be noted that the preset resistance value may also be selected from other resistance values ​​according to the actual situation and specific scenario, and no specific limitation is made to this. Also, it should be noted that the 0 ohm resistor in the embodiment of the present disclosure may refer to a resistor with a very small resistance value.

[0081] The connecting line may be a line that can electrically connect devices, such as a wire.

[0082] The switch element may be an electrical device that performs a switching function, for example, a semiconductor switch such as a metal oxide semiconductor field effect transistor (MOS), and there is no specific limitation on this. It should be noted that it may also be other electrical components that can realize a switching function, and there is no specific limitation on this.

[0083] The fuse device may be an electrical element that switches between a low resistance state and a high resistance state through a fusing operation. For example, the fuse device may be a one-time programmable (OTP) device such as a fuse or an antifuse, and no specific limitation is made to this.

[0084] Through this embodiment, multiple power management chips can be electrically connected through components such as resistors with preset resistance values, connecting wires, switch elements, and fuses, thereby ensuring the power supply capacity of the power management device 23. Optionally, when the connecting member 232 includes a switch element and / or a fuse, flexible power supply of the power management device 20 can be achieved.

[0085] In one example, for each other power management chip, when the fuse device corresponding to each other power management chip is in a low impedance state, each other power management chip supplies power to the multiple memory chips. When the fuse device is in a high impedance state, each other power management chip does not supply power to the multiple memory chips.

[0086] Through this example, flexible power supply of multiple power management chips can be achieved by controlling the resistance state of the fuse device.

[0087] In a specific example, the resistance state of the fuse device is adjusted by the test machine when the actual number of the power management chips being supplied is wrong. For example, during chip testing, if it is found that the actual number of the power management chips is inconsistent with the pre-designed number, the actual number of the power management chips being supplied can be adjusted to be consistent with the pre-designed number by adjusting the resistance state of each fuse device.

[0088] For example, see Figure 3 If the resistor R1 is a fuse device in a low-resistance state, the actual number of power management chips being powered is 2. If the pre-designed number is 1, the fuse device can be adjusted to a high-resistance state through fusing processing. At this time, the second power management chip 2312 is disconnected from the power supply line. At this time, only the first power management chip 2311 supplies power to the memory. The actual number of power management chips being powered is adjusted to 1, which is consistent with the pre-designed number.

[0089] For example, the test machine can determine whether there is an error in the actual quantity based on preset power quantity information, wherein the preset power quantity information is stored in the configuration serial detection chip and is used to indicate the quantity of power management chips in the power management device.

[0090] Among them, when the actual number is wrong and the actual number is greater than the number indicated by the preset power quantity information, the test machine adjusts the first target fuse device to a high impedance state to disconnect the power management chip corresponding to the first target fuse device from the power management device. Exemplarily, the power management chip corresponding to the first target fuse device can be selected arbitrarily from a plurality of power management chips, or selected in a preset manner, and there is no specific restriction on this. For example, if the actual number is 5 and the number indicated by the preset power quantity information is 3, then 2 power management chips can be selected from the 5 power management chips connected to the power management device as the power management chips corresponding to the first target fuse device, and disconnected from the power management device, so that the remaining 3 power management chips are used to power the crimped memory module.

[0091] When the actual number is wrong and the actual number is less than the number indicated by the preset power quantity information, the test machine adjusts the fuse device to a low-resistance state to connect the power management chip corresponding to the second target fuse device to the power management device. Exemplarily, the power management chip corresponding to the second target fuse device can be selected arbitrarily from a plurality of power management chips, or selected in a preset manner, and there is no specific restriction on this. For example, if the actual number is 2 and the number indicated by the preset power quantity information is 3, then one power management chip can be selected from the power management chips that are not connected to the power management device as the power management chip corresponding to the second target fuse device to connect to the power management device, so that the two previously connected power management chips and the newly connected one power management chip can jointly power the crimped memory module.

[0092] Through the above example, when the actual number of power management chips supplied by the power management device is wrong, the number of power management chips connected to the power management device can be adjusted according to the relationship between the preset power quantity information and the actual quantity. Therefore, when the power management device cannot normally supply power to the memory chip, the high and low resistance states of the fuse device are adjusted to enable the power management device to meet the power supply requirements of the memory chip, thereby improving the yield of the memory module.

[0093] Through this example, when the actual number of power management chips powered by the power management device is wrong, the error can be corrected by fuse processing in stages such as chip testing, thereby improving the power supply reliability of the power management device and further improving the yield of the crimped memory module.

[0094] After introducing the specific structure of the power management device 23 through the above embodiment, the number of power management chips will be described next.

[0095] In terms of specific quantity, in some embodiments, the preset number of power management chips in the power management device 23 (i.e., the number N) may be any positive integer greater than or equal to 1, for example, 1 or 2. It should be noted that the preset number of power management chips in the embodiment of the present disclosure may be the number of power management chips on the power supply line connected to the power management device, that is, the number of power management chips used to power the memory chip.

[0096] In some embodiments, the preset number of power management chips in the power management device 23 may be determined by the module manufacturer. For example, the number of power management chips may be determined based on the power requirements of the memory chips.

[0097] In one embodiment, the module information of the crimped memory module can be input into a preset chip quantity prediction model, and the prediction result output by the preset chip quantity prediction model can be determined as the preset number of power management chips. Exemplarily, the module information can be the configuration information of the module, such as the chip model of the module, the module model, the memory column (rank) information, the current parameters of the crimped memory module, and the module capacity. One or more of these. It should be noted that other information can also be selected as configuration information according to the actual setting situation and the specific setting scenario, and there is no specific limitation on this. Exemplarily, the preset chip quantity prediction model can be a neural network model, a mathematical model, etc., and there is no specific limitation on it.

[0098] In another embodiment, the actual value of the module information of the crimped memory module can be obtained. When the actual value of the module information is within a preset value range, the number of chips corresponding to the preset value range is determined as the preset number of power management chips. In one example, the current required for the crimped memory module can be obtained. When the required current is less than or equal to the preset current threshold, the preset number of power management chips is 1. When the required current is greater than the preset current threshold, the number of power management chips is preset to 2. For example, Figure 3 For example, when the required current is less than or equal to the preset current threshold, that is, when the current required for crimping the memory module is relatively small, only one current management chip is needed for power supply, and there is no need to weld resistor R1, nor to set the second power management chip 2312. Also, when the required current is greater than the preset current threshold, that is, when the current required for crimping the memory module is relatively large, two current management chips are needed for power supply, and at this time, the first power management chip 2311 and the second power management chip 2312 can be welded together through resistor R1.

[0099] Through this embodiment, the preset number of power management chips can be accurately set, thereby improving the power supply accuracy and flexibility of the power management chip.

[0100] After introducing the number of power management chips in the power management device, the power supply method of the power management device is described in detail.

[0101] In some embodiments, each power management chip is used to provide power to some of the multiple memory chips. For example, the multiple memory chips can be divided into M groups, N power management chips correspond to N groups of memory chips one by one, and each power management chip is used to supply power to a group of memory chips corresponding to it.

[0102] For example, Figure 6 FIG. 2 shows a schematic diagram of the structure of another exemplary compression-bonded memory module provided by an embodiment of the present disclosure. Figure 6 As shown, the first power management chip 2311 can provide power supply energy for the memory chips 22 in the first row, and the second power management chip 2312 can provide power supply energy for the memory chips 22 in the second row.

[0103] In one embodiment, the plurality of memory chips may be divided into a plurality of groups, each group of memory chips belonging to a memory channel. Each power management chip corresponds to at least one memory channel, and each power management chip is used to provide power supply energy to the memory chips in the corresponding memory channel. Figure 6 For example, if the memory chips 22 in the first row belong to the first memory channel and the memory chips 22 in the second row belong to the second memory channel, the first power management chip 2311 can provide power for each memory chip 22 in the first memory channel, and the second power management chip 2312 can provide power for each memory chip in the second memory channel.

[0104] Since the press-fit memory module often has multiple independent memory channels, such as two independent DDR5 memory channels, through this embodiment, the memory chip of each memory channel of the press-fit memory module can be independently powered by one or more power management chips, thereby ensuring the power supply requirements of the press-fit memory module.

[0105] Through the embodiments of the present disclosure, each power management chip can be used to provide power to some of the multiple memory chips, thereby achieving accurate power supply to the crimped memory module and improving power supply stability and reliability.

[0106] In other embodiments, the output end (such as the first power supply pin A1) of each power management chip of the plurality of power management chips may be connected together, so that the power of the plurality of power management chips can be used to power each memory chip.

[0107] The crimped memory module provided by the embodiment of the present disclosure can flexibly set the preset number of power management chips in the power management device according to the power demand of the memory chip, so that the power generated by the preset number of power management chips can flexibly meet the power demand of various crimped memory modules, avoiding the occurrence of voltage drops due to insufficient power supply. Furthermore, the technical solution provided by the embodiment of the present disclosure can realize flexible power supply to the crimped memory module while ensuring the stability of power supply, so that the crimped memory module can have a power supply solution suitable for itself.

[0108] Also, it should be noted that, considering that the press-fit memory module has two independent memory channels, its load is theoretically twice that of the small form factor dual in-line memory module. The power supply requirements of the press-fit memory module can be met by two memory management chips, avoiding the risk of voltage drop when the press-fit memory module is powered by the small form factor dual in-line memory module power supply solution, and achieving stable power supply to the press-fit memory module.

[0109] Also, it should be noted that, through the embodiments of the present disclosure, different flexible power supply schemes can be selected according to the module information of the crimped memory module (such as the configuration information of the crimped memory module, the capacity of the crimped memory module), such as the optional power supply scheme of choosing to use 1 power management chip or 2 power management chips for power supply. Exemplarily, when there are fewer memory particles on the crimped memory module, 1 power management chip can be used for power supply to reduce the cost of the crimped memory module while meeting the power supply requirements. Also, when there are more memory particles on the crimped memory module, 2 power management chips can be used to reduce the voltage drop in extreme cases to improve the stability of the power supply.

[0110] Figure 7 A schematic structural diagram of another crimped memory module provided by an embodiment of the present disclosure is shown. Figure 7 and Figure 2 The difference is that the compression memory module can also include a serial detection chip 24.

[0111] The serial detection chip 24 is configured to store preset power quantity information X1, wherein the preset power quantity information X1 is used to indicate the number of power management chips in the power management device 23. It should be noted that the preset power quantity information X1 may also include other power configuration information of the power management device 23, which is not specifically limited.

[0112] Exemplarily, the configuration serial detection chip 24 may include at least one field for storing the preset power quantity information X1. Each field may include one or more bits. In the embodiment of the present disclosure, the preset power quantity information X1 may be written in the at least one field. For example, the preset power quantity information X1 may be written in one bit of the configuration serial detection chip 24.

[0113] For example, taking the case where the preset power quantity information X1 is written into 1 bit, the first value of the bit indicates quantity 1 (i.e., the press-fit memory module is powered by 1 power management chip), and the second value of the bit indicates quantity 2 (i.e., the press-fit memory module is powered by 2 power management chips). One of the first value and the second value is 0, and the other is 1.

[0114] Through this embodiment, after power configuration is performed, the number of power management chips in the power management device 23 can be stored in the preset power quantity information X1 of the configuration serial detection chip 24 to accurately record the quantity information of the power management chips for subsequent power management.

[0115] In one embodiment, the preset power quantity information X1 can be written into the preset power quantity information X1 by the module manufacturer after configuring the power management chip of the power management device 23. For example, if the module manufacturer determines that the press-fit memory module requires one power management chip for power supply, one power management chip is set on the press-fit memory module (or multiple power management chips are set but only one power management chip is used for power supply), and 0 is written to the bit corresponding to the preset power quantity information X1; for another example, if the module manufacturer determines that the press-fit memory module requires two power management chips for power supply, two power management chips are set on the press-fit memory module, and the first power supply pins of the two power management chips are connected through a connector, and 1 is written to the bit corresponding to the preset power quantity information X1.

[0116] Through this embodiment, after the module manufacturer completes the configuration of the power management chip, the number of power management chips can be written into the preset power quantity information of the configuration serial detection chip, so that in the subsequent process of crimping the memory module, the accurate number of power management chips in the crimped memory module can be obtained based on the preset power quantity information, thereby enabling the crimped memory module to be accurately subsequently configured and tested, thereby improving the convenience and accuracy of the crimped memory module process.

[0117] In some embodiments, the power management chip includes a mode register, and the mode register is used to store preset power configuration information of the power management chip. The preset power configuration information is obtained by the chip control device based on the preset power quantity information in the configuration serial detection chip. For example, Figure 8 FIG. 2 shows a schematic diagram of the structure of another exemplary power management chip provided by an embodiment of the present disclosure. Figure 8 As shown, the first power management chip 2311 may include a first mode register MR1, in which the preset power configuration information X21 of the first power management chip 2311 is stored. The second power management chip 2312 may include a second mode register MR2, in which the preset power configuration information X22 of the second power management chip 2312 is stored.

[0118] The preset power configuration information may refer to the power configuration information of the power management chip. Exemplarily, the preset power configuration information may include one or more of the configuration information such as overvoltage, overcurrent, overtemperature, power-on sequence, power-off sequence, etc. It should be noted that the preset power configuration information may also include other power information that needs to be configured according to the actual chip situation and specific chip scenario, and there is no specific limitation on this.

[0119] Exemplarily, the mode register may include at least one field for storing preset power configuration information. Each field may include one or more bits. In the embodiment of the present disclosure, the preset power configuration information may be written into the at least one field.

[0120] The chip control device may refer to a device having a chip control function. Exemplarily, the chip control device may be a host device (Host), such as a system on a chip (SOC), etc. It should be noted that the chip controller may also be other host devices such as a processor (Central Processing Unit, CPU), and there is no specific limitation on this.

[0121] In one embodiment, the chip control device may configure the preset power configuration information according to the provisions of the preset standard protocol and the quantity indicated by the preset power quantity information. The preset standard protocol may be a protocol that specifies the power management chip. Exemplarily, the preset standard protocol may be a Joint Electron Device Engineering Council (JEDEC) standard protocol.

[0122] It should be noted that, in the embodiment of the present disclosure, when there are multiple power management chips, the configuration information of the multiple power management chips may be the same or different, and there is no specific limitation on this.

[0123] In one embodiment, the chip management device can access the power management chip through a communication bus such as I2C, and configure various information in the power management chip. Optionally, the chip management device can achieve I2C communication with the power management chip by configuring a serial detection chip, and configure the power management chip by configuring the serial detection chip.

[0124] Through this embodiment, the chip control device configures the preset power configuration information of the power management chip based on the preset power quantity information in the configuration serial detection chip, thereby realizing accurate and flexible power configuration of the power management chip according to the number of power management chips, thereby improving the power supply reliability and power supply flexibility of the crimped memory module.

[0125] In some embodiments, in order to realize the communication connection between the configuration serial detection chip and each power management chip, the configuration serial detection chip includes a first communication pin, and each power management chip includes a second communication pin. Among them, the first communication pin is respectively connected to the second communication pin of each power management chip to realize the communication connection between the serial detection chip and each power management chip. Exemplarily, the communication connection can be an I2C communication connection. It should be noted that other communication technologies that can realize communication between the power management chip and the configuration serial detection chip can also be selected according to the actual communication situation and specific communication scenarios, such as I3C, SMBus and other serial communication connections, etc., and there is no specific limitation on this.

[0126] In one embodiment, continue with Figure 3 For example, the first communication pin B1 of the serial detection chip 24 can be connected to the second communication pin B2 of the first power management chip 2311 and the second communication pin B2 of the second power management chip 2312 respectively, so as to realize the local I2C communication connection between the serial detection chip 24 and the first power management chip 2311 and the second power management chip 2312.

[0127] In one example, Fig. 9 FIG. 2 shows a schematic diagram of the structure of another exemplary power management chip provided by an embodiment of the present disclosure. Fig. 9As shown, the first communication pin B1 of the serial detection chip 24 may include a first clock line pin LSCL and a first bidirectional data line pin LSDA; the second communication pin B2 of the first power management chip 2311 may include a second clock line pin SCL1 and a second bidirectional data line pin SDA1; the second power management chip 2312 may include a third clock line pin SCL2 and a third bidirectional data line pin SDA2.

[0128] Specifically, the first clock line pin LSCL of the serial detection chip 24 can be connected to the second clock line pin SCL1 and the third clock line pin SCL2 respectively, and the first bidirectional data line pin LSDA can be connected to the second bidirectional data line pin SDA1 and the third bidirectional data line pin SDA2 respectively.

[0129] Through this embodiment, by configuring the first communication pin of the serial detection chip to connect with the second communication pin of each power management chip, it is possible to configure the communication connection between the serial detection chip and the power management chip, thereby facilitating various management such as power configuration on the power management chip.

[0130] In one embodiment, continue to see Figure 3 The serial detection chip 24 may further include a third communication pin B0, so as to realize communication connection with the chip control device through the third communication pin B0. For example, the host I2C communication with the chip control device may be realized.

[0131] For example, see Fig. 9 The third communication pin B0 includes a fourth clock line pin HSCL and a fourth bidirectional data line pin HSDA, so as to realize I2C communication with the chip control device through the fourth clock line pin HSCL and the fourth bidirectional data line pin HSDA.

[0132] Through this embodiment, the communication connection between the chip control device and the configuration serial detection chip 24 can be realized through the third communication pin B0, so that the chip control device can communicate with each power management chip through the configuration serial detection chip 24, so that external devices such as the chip control device can perform power management operations such as chip configuration on each power management device.

[0133] After introducing the communication method of the press-fit memory module, the power supply method of the press-fit memory module will be introduced next.

[0134] In some embodiments, the power management chip can also supply power to the configuration serial detection chip. Accordingly, the configuration serial detection chip 24 includes a first power pin, and each power management chip also includes a second power pin.

[0135] Wherein, in the case where the power management device includes multiple power management chips, the second power supply pin of the target power management chip in the power management device is connected to the first power supply pin, and the second power supply pins of other power management chips in the power management device except the target power management chip are left vacant, so that the electric energy output by the second power supply pin of the target power management chip is provided to the configured serial detection chip as the power supply electric energy for the configured serial detection chip. Exemplarily, the target power management chip can be one or more in the power management device. It should be noted that the target power management device can be selected according to the actual power supply situation and specific scenario, and there is no specific limitation on this.

[0136] In one example, Fig.10 FIG. 2 shows a schematic diagram of the structure of another exemplary power management chip provided by an embodiment of the present disclosure. Fig.10 As shown, the first power pin of the serial detection chip 24 may include an SPD power pin VDDSPD and an input-output power pin VIO, the second power pin of the first power management chip 2311 may include a power pin VOUT1 and a power pin VOUT2, and the second power pin of the second power management chip 2312 may include a power pin VOUT1 and a power pin VOUT2.

[0137] Exemplarily, when the first power management chip 2311 is used as the target power management chip and the second power management chip 2312 is used as the other power management chip, the power supply pin VOUT1 of the first power management chip 2311 is connected to the SPD power supply pin VDDSPD of the configuration serial detection chip 24 to provide the first power supply voltage Vddspd to the configuration serial detection chip 24, and the power supply pin VOUT2 of the first power management chip 2311 is connected to the input and output power supply pin VIO of the configuration serial detection chip 24 to provide the second power supply voltage VDDIO to the configuration serial detection chip 24. And, the power supply pin VOUT1 and the power supply pin VOUT2 of the second power management chip 2312 remain vacant. In this way, the first power management chip 2311 can be used to supply power to the configuration serial detection chip 24. Among them, for the first power supply voltage Vddspd and the second power supply voltage VDDIO, they can be the power supply voltages required by the serial detection chip 24. Among them, for example, the first power supply voltage Vddspd can be 1.8V (volts), and the second power supply voltage VDDIO can be 1V. It should be noted that the first power supply voltage Vddspd and the second power supply voltage VDDIO may also be set to other voltage values ​​according to specific scenarios and actual requirements, and there is no specific limitation on this.

[0138] In this embodiment, the target power management chip can be used to power the configuration serial detection chip, so that the normal operation of the configuration serial detection chip can be ensured without an additional external power supply, thereby ensuring the normal operation of the entire crimped memory module. In addition, by keeping other power management chips idle, the power waste of other power management chips is avoided, thereby improving the power utilization efficiency of the power management chips.

[0139] In some embodiments, each power management chip includes a status signal pin. The status signal pin can indicate whether the working status of the power management chip is normal. Specifically, the status chip pin is used to output a first level indicating that each power management chip is normal or a second level indicating that each power management chip is faulty. One of the first level and the second level is a high level, and the other of the first level and the second level is a low level. Exemplarily, the first level can be a high level and the second level can be a low level. That is, when the power management chip is normal, its status signal pin is pulled up to a high level; when the power management chip fails, its status signal pin is pulled down to a low level. In one example, Fig.11 FIG. 2 shows a schematic diagram of the structure of another exemplary power management chip provided by an embodiment of the present disclosure. Fig.11 As shown, the first power management chip 2311 may include a first state signal pin PWR_GOOD1, and the second power management chip 2312 may include a second state signal pin PWR_GOOD2. Taking the first power management chip 2311 as an example, when the first power management chip 2311 is normal, the first state signal pin PWR_GOOD1 outputs a high level, and when the first power management chip 2311 fails, the first state signal pin PWR_GOOD1 outputs a low level.

[0140] Wherein, in the case where the power management device includes multiple power management chips, the status signal pins of the multiple power management chips are connected to the status signal transmission line. Wherein, when the status signal pins of one or more power management chips output the second level, the level on the status signal transmission line is adjusted to the second level, and the second level on the status signal transmission line indicates a failure of the power management device. In one example, continue to see Fig.11 The first status signal pin PWR_GOOD1 of the first power management chip 2311 and the second status signal pin PWR_GOOD2 of the second power management chip 2312 are both connected to the status signal transmission line L2. When the first power management chip 2311 and / or the second power management chip 2312 fails, the level on the status signal transmission line L2 is a low level; when the first power management chip 2311 and the second power management chip 2312 are both normal, the level on the status signal transmission line L2 is a high level.

[0141] In this embodiment, due to the status signal transmission line, when the level of the status signal pins of each power management chip is the first level, it is adjusted to the first level; and when the level of the status signal pins of any one or more power management chips is the second level, the status signal transmission line is adjusted to the second level. Since the first level indicates that the power management chip is normal and the second level indicates that the power management chip is faulty, accordingly, in the embodiment of the present disclosure, when the power management chips in the power management device are all normal, the status signal transmission line can output the first level indicating that the power management device is normal; and when any one or more power management chips in the power management device are faulty, the status signal transmission line can output the second level indicating that the power management device is faulty. Thus, the working state of the power management device can be accurately indicated by the output level of the status signal transmission line, so as to accurately and quickly perceive the fault state of the power management device. Further, it can be convenient to manage and maintain the power management device when the power management device is abnormal during subsequent use, testing, etc.

[0142] In some embodiments, in order to facilitate the control of the power management chip, each power management chip includes an enable pin, which is used to turn on or off each power management chip. Among them, the enable pin of each power management chip is used to receive a control instruction sent by the chip control device. Among them, the control instruction is used to turn on or off each power management chip. It should be noted that the control instructions received by each power management chip may be the same or different, and there is no specific limitation on this. And, it should also be noted that in the embodiments of the present disclosure, the chip control device may send a control instruction directly to the enable pin, or send a control instruction to the enable pin under the forwarding of other devices or equipment, and there is no specific limitation on this.

[0143] In one example, Fig.12 FIG. 2 shows a schematic diagram of the structure of another exemplary power management chip provided by an embodiment of the present disclosure. Fig.12 As shown, the first power management chip 2311 may include a first enable pin VR_EN1, and the second power management chip 2312 may include a second enable pin VR_EN2. The first enable pin VR_EN1 and the second enable pin VR_EN2 may receive a control instruction PWR_EN. Exemplarily, the control instruction PWR_EN may be a level signal, such as a high level indicating turning on the power management chip, and a low level indicating turning off the power management chip.

[0144] Through this embodiment, the chip control device can flexibly and accurately control the opening or closing of each power management chip through the enable pin of each power management chip, so that the power management device can be accurately controlled with the power management chip as the granularity, thereby improving the control accuracy. Furthermore, when the power supply requirements of some chips on the crimped memory module change, the number of power management chips can be changed. For example, some power management chips can be turned off, and the remaining power management chips can be used to power the crimped memory module, taking into account the power supply accuracy and the rational use of electric energy, and improving the power supply flexibility. And, further, when the power management chip fails, each power management chip or the failed power management chip can be quickly turned off, thereby improving the safety of the power management device.

[0145] In some embodiments, in order to achieve correct communication of the power management device, each power management chip includes a communication address pin, and the communication address pin is used to indicate the communication address of each power management chip. Among them, the communication address pins of multiple power management chips correspond to different voltages, and different voltages represent different communication addresses. For example, different voltages can be applied to the communication address pins of different power management chips to represent different communication addresses of the power management chips.

[0146] In one example, Fig.13 FIG. 2 shows a schematic diagram of the structure of another exemplary power management chip provided by an embodiment of the present disclosure. Fig.13 As shown, the first power management chip 2311 may include a first communication address pin PID1, and the second power management chip 2312 may include a second communication address pin PID2. The first communication address pin PID1 is grounded, and a preset power supply voltage is applied to the second communication address pin PID2. Exemplarily, the preset power supply voltage may be the second power supply voltage VDDIO.

[0147] Through this embodiment, by configuring different voltages for the communication address pins of the power management chip, different communication addresses can be configured for different power management chips in the same power management device, thereby enabling communication between the power management chips of the power management device.

[0148] In some embodiments, in addition to the pins shown in combination with the above embodiments, the power management chip may also include one or more other pins. Fig.14 FIG. 2 shows a schematic diagram of the structure of another exemplary power management chip provided by an embodiment of the present disclosure. Fig.14 As shown, the power management chip may further include at least one of the following pins 1-8.

[0149] Pin 1, power ground pin PGND, is used to form a discharge path for dangerous current in high-power circuits. Fig.14 , the power ground pin PGND is grounded.

[0150] Pin 2, analog ground pin AGND, is used to form a discharge path for the current of the analog signal. Fig.14 , the analog ground pin AGND is grounded.

[0151] Pin 3, empty pins NC, NC1-3, these pins are not connected to the internal functional circuit of the device. Fig.14 , the empty pins NC and NC1-3 are grounded.

[0152] Pin 4, general status interrupt signal output pin GSI_n, which is used to output the general status interrupt signal. Fig.14 As shown, the general status interrupt signal output pin GSI_n may not be connected to the outside of the power management device. For example, the general status interrupt signal output pin GSI_n may be connected to a reference position point of a voltage-dividing structure. Exemplarily, the voltage-dividing structure may include a first voltage-dividing resistor Ra and a second voltage-dividing resistor Rb. Among them, one end of the first voltage-dividing resistor Ra is applied with a first power supply voltage Vddspd, the other end of the voltage-dividing voltage Ra and one end of the second voltage-dividing resistor Rb are both connected to the reference position point, and the other end of the second voltage-dividing resistor Rb is grounded.

[0153] Pins 5-8, a first voltage input pin VIN_BULK_A, a second voltage input pin VIN_BULK_B, a third voltage input pin VIN_BULK_C, and a fourth voltage input pin VIN are respectively used to receive an input voltage VIN_BULK so that the power management chip can generate supply voltages such as a first supply voltage VDD, a second supply voltage VDDQ, and a third supply voltage VPP based on the input voltage VIN_BULK.

[0154] In some embodiments, in addition to the pins shown in the above embodiments, the serial detection chip can also include one or more other pins. Fig.14 The serial detection chip may also include at least one of pins 9-11.

[0155] Pin 9, address pin HSA.

[0156] Pin 10, ground pin Gnd.

[0157] Pin 11, ground / thermal pad pin Gnd / Thermal Pad. Fig.14 , ground / thermal pad pin Gnd / Thermal Pad is grounded.

[0158] In order to facilitate an overall understanding of the technical solutions provided by the embodiments of the present disclosure, Fig.15 A schematic diagram of the structure of an exemplary first power management chip provided by an embodiment of the present disclosure is shown; Fig.16 A schematic diagram of the structure of an exemplary second power management chip provided by an embodiment of the present disclosure is shown; Fig.17 FIG. 1 is a schematic diagram showing an exemplary structure of a serial detection chip provided by an embodiment of the present disclosure. Figure 15-17 The technical solution provided by the embodiment of the present disclosure is described.

[0159] like Fig.15 and Fig.16 As shown, in order to improve the quality of the input voltage VIN_BULK, the first power management chip also includes a first filtering unit Q1, and the second power management chip also includes a second filtering unit Q2. Exemplarily, the first filtering unit Q1 may include a plurality of capacitors in parallel, such as capacitors C3-C5 and capacitors C7-C14. For example, and again exemplarily, the second filtering unit Q2 may include a plurality of capacitors in parallel, such as capacitors C41-C51. Among them, for any one of the first filtering unit Q1 and the second filtering unit Q2, there are at least two types of capacitors with different capacitance in any one of the filtering units to achieve filtering of different frequencies such as high frequency and low frequency. It should be noted that each capacitor can also be selected as other parameters according to actual scenarios and specific requirements, and there is no specific restriction on its device parameters.

[0160] The first enable pin VR_EN1 of the first power management chip and the second enable pin VR_EN2 of the second power management chip can be connected together through a resistor R111 to receive a control instruction PWR_EN_0. Exemplarily, in order to avoid power loss, the resistor R111 can be 0 ohm. It should be noted that the resistance value of the resistor R111 can also be selected as other parameters according to actual scenarios and specific requirements, and there is no specific restriction on its device parameters.

[0161] The first state signal pin PWR_GOOD1 of the first power management chip and the second state signal pin PWR_GOOD2 of the second power management chip can be connected together through a resistor R112 to output a state signal PWR_GOOD_0. For example, when the level signal on the first state signal pin PWR_GOOD1 and / or the level signal PWR_GOOD2_01 on the second state signal pin PWR_GOOD2 is low, the output state signal PWR_GOOD_0 is low. For example, in order to avoid power loss, the resistor R112 can be 0ohm. It should be noted that the resistance value of the resistor R112 can also be selected as other parameters according to actual scenarios and specific requirements, and there is no specific restriction on its device parameters.

[0162] For the first power management chip and the second power management chip, the switch voltage pin SWA is connected to the startup voltage pin SWA_BOOT through the capacitor C6 (or capacitor C36, it should be noted that, for the sake of simplicity, the different devices of the second power management chip and the first power management chip at the same position are output in the form of brackets), the switch voltage pin SWA is connected to the inductor L1 (or inductor L4), and the other end of the inductor L1 (or inductor L4) is connected to the feedback voltage pin SWA_FB_P. Exemplarily, in order to improve the power transmission quality of the first power supply voltage V_MEM_VDD, the other end of the inductor L1 (or inductor L4) is respectively connected to the capacitor C1, the capacitor C2, the capacitor C27, the capacitor C28 (or the capacitors C37-C40), and the other ends of the capacitors C1, the capacitor C2, the capacitor C27, the capacitor C28 (or the capacitors C37-C40) are all grounded.

[0163] And, the switch voltage pin SWB is connected to the startup voltage pin SWB_BOOT through the capacitor C15 (or the capacitor C52), the switch voltage pin SWB is connected to the inductor L2 (or the inductor L5), and the other end of the inductor L2 (or the inductor L5) is connected to the feedback voltage pin SWB_FB_P. Exemplarily, in order to improve the power transmission quality of the second power supply voltage V_MEM_VDDQ, the other end of the inductor L2 (or the inductor L5) is respectively connected to the capacitor C16, the capacitor C17, the capacitor C29, and the capacitor C30 (or the capacitors C53-C56), and the other ends of the capacitors C16, the capacitor C17, the capacitor C29, and the capacitor C30 (or the capacitors C53-C56) are all grounded.

[0164] And, the switch voltage pin SWC is connected to the startup voltage pin SWC_BOOT through the capacitor C18 (or capacitor C57), the switch voltage pin SWC is connected to the inductor L3 (or inductor L6), and the other end of the inductor L3 (or inductor L6) is connected to the feedback voltage pin SWC_FB_P. Exemplarily, in order to improve the power transmission quality of the third power supply voltage V_MEM_VPP, the other end of the inductor L3 (or inductor L6) is respectively connected to the capacitor C19 and the capacitor C20 (or capacitor C58, capacitor C59), and the other ends of the capacitor C19 and the capacitor C20 (or capacitor C58, capacitor C59) are grounded. It should be noted that each capacitor and inductor can also be selected as other parameters according to the actual scenario and specific requirements, and there is no specific restriction on its device parameters.

[0165] And, the general status interrupt signal output pin GSI_n of the first power management chip can be connected to one end of the resistor R105 and one end of the resistor R106 respectively, one end of the resistor R105 is used to receive the first power supply voltage Vddspd_1P8V, and the other end of the resistor R106 is grounded. The general status interrupt signal output pin GSI_n of the second power management chip can be connected to one end of the resistor R109 and one end of the resistor R110 respectively, one end of the resistor R109 is used to receive the first power supply voltage Vddspd_1P8V, and the other end of the resistor R110 is grounded. In one example, the resistance of the resistor R105 and the resistor R109 can be 1K (kilo ohms). In another example, the resistance of the resistor R106 and the resistor R110 can be 0ohm. It should be noted that each capacitor and capacitor can also be selected as other parameters according to the actual scenario and specific requirements, and there is no specific restriction on its device parameters.

[0166] And, for any one of the first power management chip and the second power management chip, its power supply pin VOUT_1.8V (also called power supply pin VOUT1) can be grounded through capacitor C22 (capacitor C62) and capacitor C25 (capacitor C63), and the power supply pin VOUT_1.0V (also called power supply pin VOUT2) can be grounded through capacitor C21 (capacitor C60) and capacitor C23 (capacitor C61). It should be noted that each capacitor can also be selected as other parameters according to actual scenarios and specific requirements, and there is no specific restriction on its device parameters.

[0167] Also, please continue to see Fig.17 , the SPD power pin VDDSPD of the serial detection chip can be grounded through capacitor C26, and the input and output power pin VIO can be grounded through capacitor C24. It should be noted that each capacitor can also be selected as other parameters according to actual scenarios and specific requirements, and there is no specific restriction on its device parameters.

[0168] It should be noted that other contents of the first power management chip, the second power management chip and the configuration serial detection chip can refer to the relevant description of the above part of the embodiment of the present disclosure, and will not be repeated here.

[0169] Based on the same inventive concept, the embodiment of the present disclosure further provides a power management device, which is arranged on a compression memory circuit board of a compression memory module and is connected to a plurality of memory chips of the compression memory module.

[0170] Specifically, the power management device includes: a preset number of power management chips, which are used to provide the electric energy generated by the preset number of power management chips as power supply energy to the plurality of memory chips.

[0171] The preset number of power management chips in the power management device is related to the power requirements of the multiple memory chips.

[0172] In one embodiment, the power management device includes a plurality of power management chips.

[0173] The power management chip includes a first power supply pin, and the first power supply pins of multiple power management chips are connected to provide the electric energy generated by the multiple power management chips to the multiple memory chips through the connected first power supply pins.

[0174] In one embodiment, the first power supply pin includes N power transmission pins, and each power transmission pin is used to output a power supply voltage.

[0175] The i-th power transmission pins of the multiple power management chips are connected to provide the power supply voltage output by the connected i-th power transmission pins to the multiple memory chips. Wherein, N is an integer greater than or equal to 1, and i is any integer less than or equal to N.

[0176] In one embodiment, the power management chip further includes a mode register.

[0177] The mode register is used to store the preset power configuration information of the power management chip to which it belongs.

[0178] The preset power supply configuration information is obtained by configuring the chip control device based on the preset power supply quantity information in the configuration serial detection chip.

[0179] In one embodiment, when the serial detection chip is configured to include a first communication pin, each power management chip includes a second communication pin.

[0180] The first communication pin is respectively connected to the second communication pin of each power management chip to configure the communication connection between the serial detection chip and each power management chip.

[0181] In one embodiment, the serial detection chip is configured to include a first power supply pin, and each power management chip further includes a second power supply pin.

[0182] In which, when the power management device includes multiple power management chips, the second power pin of the target power management chip in the power management device is connected to the first power pin, and the second power pins of other power management chips in the power management device except the target power management chip are left vacant, so that the electric energy output by the second power pin of the target power management chip can be provided to the configured serial detection chip as the power supply energy for the configured serial detection chip.

[0183] In one embodiment, each power management chip includes a status signal pin, and the status signal pin is used to output a first level indicating that each power management chip is normal or a second level indicating that each power management chip is faulty.

[0184] In which, when the power management device includes multiple power management chips, the status signal pins of the multiple power management chips are connected to the status signal transmission line, wherein when the status signal pins of one or more power management chips output the second level, the level on the status signal transmission line is adjusted to the second level, and the second level on the status signal transmission line indicates a failure of the power management device.

[0185] In one embodiment, each power management chip includes an enable pin, and the enable pin is used to start or shut down each power management chip.

[0186] The enable pin of each power management chip is used to receive a control instruction sent by the chip control device, and the control instruction is used to turn on or off each power management chip.

[0187] In one embodiment, each power management chip includes a communication address pin, which is used to indicate the communication address of each power management chip, wherein the communication address pins of multiple power management chips correspond to different voltages, and different voltages represent different communication addresses.

[0188] In one embodiment, a first power supply pin of one of the multiple power management chips is directly connected to a first conductive line, and a first power supply pin of another power management chip among the multiple power management chips is connected to the first conductive line or a first power supply pin of one of the power management chips through a connector.

[0189] In one embodiment, the connecting member includes: one or more of a resistor with a preset resistance, a connecting line, a switching element, and a fuse device.

[0190] In one embodiment, the connector includes a fuse device, which is a fuse or an anti-fuse; wherein, for each other power management chip, when the fuse device corresponding to each other power management chip is in a low-impedance state, each other power management chip supplies power to multiple memory chips; when the fuse device is in a high-impedance state, each other power management chip does not supply power to multiple memory chips.

[0191] In one embodiment, the resistance state of the fuse device is adjusted by the tester when the actual number of the power management chips powered is wrong.

[0192] In one embodiment, a test machine determines whether there is an error in the actual quantity based on preset power quantity information, wherein the preset power quantity information is stored in a configuration serial detection chip and is used to indicate the number of power management chips in a power management device; wherein, when the actual quantity is wrong and the actual quantity is greater than the quantity indicated by the preset power quantity information, the test machine adjusts the first target fuse device to a high impedance state to disconnect the power management chip corresponding to the first target fuse device from the power management device; wherein, when the actual quantity is wrong and the actual quantity is less than the quantity indicated by the preset power quantity information, the test machine adjusts the fuse device to a low impedance state to connect the power management chip corresponding to the second target fuse device to the power management device.

[0193] In one embodiment, each power management chip is used to provide power to some of the memory chips.

[0194] In one embodiment, multiple memory chips can be divided into multiple groups, each group of memory chips belongs to a memory channel, each power management chip corresponds to at least one memory channel, and each power management chip is used to provide power to the memory chips in the corresponding memory channel.

[0195] The power management device provided in the embodiment of the present disclosure can flexibly set the preset number of power management chips in the power management device according to the power demand of the memory chip, so that the power generated by the preset number of power management chips can flexibly meet the power demand of various crimped memory modules, avoiding the occurrence of voltage drops due to insufficient power supply. Furthermore, the technical solution provided in the embodiment of the present disclosure can realize flexible power supply to the crimped memory module while ensuring the stability of power supply, so that the crimped memory module can have a power supply solution suitable for itself.

[0196] It should be noted that the specific content of the power management device can be found in the above-mentioned embodiments of the present disclosure. Figure 2-Figure 17 The relevant description is omitted here.

[0197] Based on the same inventive concept, the embodiment of the present disclosure also provides a serial detection chip.

[0198] A preset power quantity information is stored on the configuration serial detection chip, and the preset power quantity information is used to indicate the number of power management chips in the power management device, wherein the power management device is arranged on a crimped memory circuit board of a crimped memory module and is connected to multiple memory chips of the crimped memory module. The power management device includes a preset number of power management chips, which are used to provide electric energy generated by a preset number of power management chips as power supply energy to multiple memory chips, wherein the preset number of power management chips in the power management device is related to the power demand of multiple memory chips.

[0199] In one embodiment, the configuration serial detection chip includes a first communication pin, and each power management chip includes a second communication pin, wherein the first communication pin is respectively connected to the second communication pin of each power management chip to perform communication connection between the configuration serial detection chip and each power management chip.

[0200] In one embodiment, the configuration serial detection chip includes a first power pin, and each power management chip also includes a second power pin; wherein, when the power management device includes multiple power management chips, the second power pin of the target power management chip in the power management device is connected to the first power pin, and the second power pins of other power management chips in the power management device except the target power management chip are left vacant, so that the electric energy output by the second power pin of the target power management chip can be provided to the configuration serial detection chip as the power supply electric energy of the configuration serial detection chip.

[0201] The configuration serial detection chip provided in the embodiment of the present disclosure can flexibly set the preset number of power management chips in the power management device according to the power demand of the memory chip, so that the electric energy generated by the preset number of power management chips can flexibly meet the power demand of various crimped memory modules, avoiding the occurrence of voltage drops due to insufficient power supply. Furthermore, the technical solution provided in the embodiment of the present disclosure can realize flexible power supply to the crimped memory module while ensuring the stability of power supply, so that the crimped memory module can have a power supply solution suitable for itself. In addition, after the power supply configuration is performed, the number of power management chips in the power management device 23 can be stored in the preset power quantity information X1 of the configuration serial detection chip 24 to accurately record the quantity information of the power management chip, which is convenient for subsequent power management.

[0202] It should be noted that the specific content of configuring the serial detection chip can be found in the above-mentioned embodiment of the present disclosure. Figure 2-Figure 17 The relevant description is omitted here.

[0203] Based on the same inventive concept, the embodiment of the present disclosure also provides an electronic device, which may include the press-fit memory module provided by any of the above embodiments of the present disclosure. Figure 2-Figure 17 The relevant description is omitted here.

[0204] Among them, the electronic device of the embodiment of the present disclosure may be an electronic device loaded with a memory. Exemplarily, the electronic device may be a mobile terminal, a computer, a server, a virtual reality device, an Internet of Things device, etc.

[0205] The electronic device provided by the embodiment of the present disclosure can flexibly set the preset number of power management chips in the power management device according to the power demand of the memory chip, so that the power generated by the preset number of power management chips can flexibly meet the power demand of various crimped memory modules, avoiding the occurrence of voltage drops due to insufficient power supply. Furthermore, the technical solution provided by the embodiment of the present disclosure can realize flexible power supply to the crimped memory module while ensuring the stability of power supply, so that the crimped memory module can have a power supply solution suitable for itself.

[0206] In the description of this specification, the description with reference to the terms "some embodiments", "exemplarily", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0207] Although the embodiments of the present disclosure have been shown and described above, it is to be understood that the above embodiments are exemplary and cannot be construed as limitations on the present disclosure. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present disclosure. Therefore, any changes or modifications made in accordance with the claims and specification of the present disclosure shall fall within the scope covered by the patent of the present disclosure.

Claims

1. A crimped memory module, It is characterized in that The module includes: Press-fit memory circuit boards; A plurality of memory chips are arranged on the crimped memory circuit board; A power management device is arranged on the crimped memory circuit board and is electrically connected to the multiple memory chips. The power management device includes a preset number of power management chips, which are used to provide the electric energy generated by the preset number of power management chips as power supply energy to the multiple memory chips, wherein the preset number of power management chips in the power management device is preset according to the power consumption requirements of the multiple memory chips.

2. The module according to claim 1, It is characterized in that The power management device includes multiple power management chips, wherein the power management chip includes a first power supply pin, and the first power supply pins of the multiple power management chips are connected to provide the electric energy generated by the multiple power management chips to the multiple memory chips through the connected first power supply pins.

3. The module according to claim 2, It is characterized in that The first power supply pin includes N transmission pins, each transmission pin is used to output a power supply voltage, wherein the i-th transmission pins of the multiple power management chips are connected to provide the power supply voltage output by the connected i-th transmission pin to the multiple memory chips, wherein N is an integer greater than or equal to 1, and i is any integer less than or equal to N.

4. The module according to claim 1, It is characterized in that The module also includes: A serial detection chip is configured to store preset power quantity information, wherein the preset power quantity information is used to indicate the quantity of power management chips in the power management device.

5. The module according to claim 4, It is characterized in that The power management chip also includes a mode register, which is used to store preset power configuration information of the power management chip to which it belongs, wherein the preset power configuration information is configured by the chip control device based on preset power quantity information in the configuration serial detection chip.

6. The module according to claim 4, It is characterized in that The configuration serial detection chip includes a first communication pin, and each power management chip includes a second communication pin, wherein the first communication pin is respectively connected to the second communication pin of each power management chip to establish a communication connection between the configuration serial detection chip and each power management chip.

7. The module according to claim 4, It is characterized in that The configured serial detection chip includes a first power pin, and each power management chip also includes a second power pin; wherein, when the power management device includes multiple power management chips, the second power pin of the target power management chip in the power management device is connected to the first power pin, and the second power pins of other power management chips in the power management device except the target power management chip are left vacant, so that the electric energy output by the second power pin of the target power management chip can be provided to the configured serial detection chip as the power supply electric energy of the configured serial detection chip.

8. The module according to claim 1, It is characterized in that Each power management chip includes a status signal pin, and the status signal pin is used to output a first level indicating that each power management chip is normal or a second level indicating that each power management chip is faulty. When the power management device includes multiple power management chips, the status signal pins of the multiple power management chips are connected to a status signal transmission line. When the status signal pins of one or more power management chips output the second level, the level on the status signal transmission line is adjusted to the second level, and the second level on the status signal transmission line indicates a fault in the power management device.

9. The module according to claim 1, It is characterized in that Each power management chip includes an enable pin, which is used to start or shut down each power management chip, wherein the enable pin of each power management chip is used to receive a control instruction sent by a chip control device, and the control instruction is used to start or shut down each power management chip.

10. The module according to claim 1, It is characterized in that Each power management chip includes a communication address pin, and the communication address pin is used to indicate the communication address of each power management chip, wherein the communication address pins of the multiple power management chips correspond to different voltages, and the different voltages represent different communication addresses.

11. The module according to claim 2, It is characterized in that The first power supply pin of one of the multiple power management chips is directly connected to the first conductive line, and the first power supply pin of other power management chips among the multiple power management chips is connected to the first conductive line or the first power supply pin of one of the power management chips through a connector.

12. The module according to claim 11, It is characterized in that The connecting member comprises: one or more of a resistor with a preset resistance, a connecting line, a switch element and a fuse device.

13. The module according to claim 11, It is characterized in that The connecting member includes a fuse device, and the fuse device is a fuse or an anti-fuse; Wherein, for each other power management chip, when the fuse device corresponding to each other power management chip is in a low resistance state, each other power management chip supplies power to the multiple memory chips; When the fuse device is in a high impedance state, each of the other power management chips does not supply power to the multiple memory chips.

14. The module according to claim 13, It is characterized in that The resistance state of the fuse device is adjusted by the test machine when the actual number of the power management chips supplied with power is wrong.

15. The module according to claim 14, It is characterized in that The test machine determines whether there is an error in the actual quantity based on preset power quantity information, wherein the preset power quantity information is stored in a configuration serial detection chip and is used to indicate the quantity of the power management chips in the power management device; Wherein, when the actual number is wrong and the actual number is greater than the number indicated by the preset power quantity information, the test machine adjusts the first target fuse device to a high impedance state to disconnect the power management chip corresponding to the first target fuse device from the power management device; When the actual number is wrong and is less than the number indicated by the preset power quantity information, the test machine adjusts the fuse device to a low resistance state to connect the power management chip corresponding to the second target fuse device to the power management device.

16. The module according to claim 1, It is characterized in that Each of the power management chips is used to provide power supply energy to some of the memory chips.

17. The module according to claim 16, It is characterized in that The multiple memory chips can be divided into multiple groups, each group of memory chips belongs to one memory channel, each power management chip corresponds to at least one memory channel, and each power management chip is used to provide power supply energy to the memory chips in the corresponding memory channel.

18. An electronic device, It is characterized in that include: A crimped memory module as claimed in any one of claims 1 to 17.

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