Nonvolatile memory device

Abstract

A non-volatile memory device is disclosed. The nonvolatile memory device includes a memory array including N + 1 resistive memory cells representing a bit sequence of N bits per word line, where N is an integer greater than or equal to 2.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2023-0162483 filed in the Korean Intellectual Property Office on November 21, 2023, Korean Patent Application No. 10-2024-0000869 filed in the Korean Intellectual Property Office on January 3, 2024, and Korean Patent Application No. 10-2024-0046037 filed in the Korean Intellectual Property Office on April 4, 2024, the entire disclosures of which are incorporated herein by reference for all purposes. Technical Field

[0002] The following description relates to a nonvolatile memory device that provides a memory read operation and a memory write operation based on XOR. Background Art

[0003] Semiconductor memory devices can be classified into volatile memory devices and non-volatile memory devices. When the power supply is interrupted, the volatile memory device loses the stored data, and the non-volatile memory device does not lose. The volatile memory device has a relatively high read speed and write speed, but loses the stored content when the external power supply is cut off. On the other hand, compared with the volatile memory device, the non-volatile memory device has a relatively low read speed and write speed, but retains the stored content when the external power supply is interrupted. Summary of the invention

[0004] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

[0005] In one general aspect, a nonvolatile memory device includes a memory array including N+1 resistive memory cells representing a bit sequence of N bits per word line, where N is an integer greater than or equal to 2.

[0006] When the bit value of the bit position in the bit sequence is a first bit value, the resistance values ​​of adjacent memory elements corresponding to the bit position among the N+1 resistive memory cells are the same, and when the bit value of the bit position is a second bit value, the resistance values ​​of adjacent memory elements corresponding to the bit position among the N+1 resistive memory cells are different.

[0007] The memory device may further include a write encoder configured to generate N+1 write signals based on a reference signal and N bit signals respectively indicating bit values ​​of a bit sequence, the N+1 write signals respectively indicating resistance values ​​to be set for the N+1 resistive memory cells.

[0008] The write encoder may include a plurality of exclusive-OR (XOR) elements, wherein an output of at least one of the plurality of XOR elements is connected to an input of another XOR element.

[0009] The write encoder may generate the N+1 write signals including outputs of the plurality of XOR elements and a reference signal.

[0010] The write encoder may include: a first XOR element configured to receive a bit signal corresponding to a most significant bit (MSB) and a reference signal, and generate a first XOR result between the bit value of the MSB and the bit value of the reference signal; and a second XOR element configured to receive a subsequent bit signal of the MSB and the first XOR result, and generate a second XOR result between the bit value of the subsequent bit signal and the first XOR result.

[0011] The memory device may set a resistance value according to a result of encoding a bit sequence based on XOR for a resistive memory cell arranged along a word line selected for writing.

[0012] The memory device may set one resistance value combination among available resistance value combinations for N+1 resistive memory cells of a word line selected for writing, the available resistance value combination representing a bit sequence.

[0013] The memory device may select a resistance value combination for writing that is predicted to have low power consumption from among available resistance value combinations.

[0014] The memory device may select a resistance value combination having a small number of resistance changes required for the N+1 resistive memory cells from among available resistance value combinations based on resistance values ​​set for the N+1 resistive memory cells of the word line selected for writing.

[0015] The memory device can change the resistance value of a resistive memory cell including a resistance value different from the resistance value combination selected from among N+1 resistive memory cells of a word line selected for writing, and can maintain the resistance value of a resistive memory cell including a resistance value the same as the resistance value combination selected from among N+1 resistive memory cells of a word line selected for writing.

[0016] The memory device may further include a read circuit configured to generate a bit read signal based on an XOR result of resistance values ​​set for N+1 resistive memory cells arranged along a word line selected for reading.

[0017] The readout circuit may include an XOR element connected to two adjacent resistive memory cells among the N+1 resistive memory cells.

[0018] The readout circuit may output a comparison result between delays occurring in two adjacent resistive memory cells as bit values ​​of the two adjacent resistive memory cells according to the parasitic capacitance value and the resistance value set for the two adjacent resistive memory cells.

[0019] In another general aspect, a method for operating a nonvolatile memory device includes: setting a resistance value representing an N-bit bit sequence for N+1 resistive memory cells in a memory array arranged about a word line selected for writing; and outputting N-bit read signals from the N+1 resistive memory cells in the memory array arranged about a word line selected for reading, wherein N is an integer greater than or equal to 2.

[0020] The step of setting the resistance value may include: when the bit value of the bit position in the bit sequence is the first bit value, setting the same resistance value for adjacent memory elements corresponding to the bit position; and when the bit value of the bit position is the second bit value, setting different resistance values ​​for adjacent memory elements corresponding to the bit position.

[0021] The step of setting the resistance value may include: generating, by a write encoder, N+1 write signals based on a reference signal and N bit signals respectively indicating bit values ​​of a bit sequence, the N+1 write signals respectively indicating resistance values ​​to be set for the N+1 resistive memory cells; and setting the resistance values ​​of the N+1 resistive memory cells to the N+1 write signals by a write driver.

[0022] The step of setting the resistance value may include writing one resistance value combination among available resistance value combinations into N+1 resistive memory cells of the word line selected for writing, the available resistance value combination representing a bit sequence.

[0023] The step of setting the resistance value may further include selecting a resistance value combination with low predicted power consumption for writing from among the available resistance value combinations.

[0024] The outputting may include generating N-bit read signals based on an XOR result of resistance values ​​set for N+1 resistive memory cells arranged along a word line selected for reading.

[0025] In another general aspect, a method for encoding a bit value by using two resistive memory cells adjacent to each other includes: when the bit value is a first value, setting the same resistance value for the two resistive memory cells; and when the bit value is a second value different from the first value, setting different resistance values ​​for the two resistive memory cells.

[0026] The encoding may be an XOR, where the first value is 0 and the second value is 1.

[0027] The encoding may be an exclusive-NOR (XNOR), where the first value is one and the second value is zero.

[0028] N bit values ​​can be encoded by using N+1 resistive memory cells.

[0029] N+1 resistive memory cells may be connected to a shared word line, where N is an integer greater than or equal to 2.

[0030] Other features and aspects will be apparent from the following detailed description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 An example memory array of a memory device according to one or more embodiments is shown.

[0032] Figure 2 An example configuration of a memory device according to one or more embodiments is shown.

[0033] Figure 3 One or more operating methods of a memory device according to one or more embodiments are shown.

[0034] Figure 4 A read operation of a memory device according to one or more embodiments is shown.

[0035] Figure 5 An example of a bit sequence using a combination of resistance values ​​in a memory device according to one or more embodiments is shown.

[0036] Figure 6 , Fig. 7A and Figure 7B A read operation by a sensing circuit in a memory device is shown according to one or more embodiments.

[0037] Figure 8 , Fig.9A and Fig. 9B A write operation by a write circuit in a memory device is shown according to one or more embodiments.

[0038] Throughout the drawings and detailed description, unless otherwise described or provided, the same or similar reference numerals in the drawings will be understood to represent the same or similar elements, features and structures. The drawings may not be to scale, and the relative sizes, proportions and depictions of the elements in the drawings may be exaggerated for clarity, illustration and convenience. DETAILED DESCRIPTION

[0039] The following specific embodiments are provided to help the reader obtain a comprehensive understanding of the method, device and / or system described herein. However, after understanding the disclosure of the application, various changes, modifications and equivalents of the method, device and / or system described herein will be clear. For example, the order of operations described herein is merely an example, and is not limited to those orders set forth herein, but except for the operations that must occur in a specific order, the order of operations can be changed as will be clear after understanding the disclosure of the application. In addition, for greater clarity and simplicity, the description of known features after understanding the disclosure of the application can be omitted.

[0040] The features described herein may be implemented in different forms and should not be construed as being limited to the examples described herein. Rather, the examples described herein are provided merely to illustrate some of the many possible ways to implement the methods, devices, and / or systems described herein that will be clear after understanding the disclosure of the present application.

[0041] The terms used herein are only used to describe various examples and will not be used to limit the disclosure. Unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. As used herein, the term "and / or" includes any one of the associated listed items and any combination of any two or more. As non-limiting examples, the terms "include", "comprise" and "have" illustrate the existence of the features, quantities, operations, components, elements and / or combinations thereof, but do not exclude the existence or addition of one or more other features, quantities, operations, components, elements and / or combinations thereof.

[0042] Throughout the specification, when a component or element is described as being "connected to," "coupled to," or "engaged to" another component or element, it may be directly "connected to," "coupled to," or "engaged to" the other component or element, or one or more other components or elements may reasonably exist between them. When a component or element is described as being "directly connected to" another component or element, "directly coupled to," or "directly engaged to" another component or element, there may not be other elements between them. Similarly, expressions such as "between" and "immediately between," and "adjacent to" and "immediately adjacent to" may also be interpreted as described above.

[0043] Although terms such as "first," "second," and "third," or A, B, (a), (b), etc. may be used herein to describe various members, components, regions, layers, or portions, these members, components, regions, layers, or portions are not limited by these terms. For example, each of these terms is not used to define the nature, order, or sequence of the corresponding member, component, region, layer, or portion, but is only used to distinguish the corresponding member, component, region, layer, or portion from other members, components, regions, layers, or portions. Therefore, without departing from the teachings of the examples, the first member, first component, first region, first layer, or first portion referred to in the examples described herein may also be referred to as the second member, second component, second region, second layer, or second portion.

[0044] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those generally understood by a person of ordinary skill in the art to which the present disclosure belongs based on an understanding of the disclosure of the present application. Unless explicitly defined as such herein, terms (such as those defined in a general dictionary) will be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the disclosure of the present application, and should not be interpreted in an idealized or overly formal sense. The use of the term "may" with respect to an example or embodiment herein (e.g., with respect to what an example or embodiment may include or may achieve) indicates that there is at least one example or embodiment that includes or achieves such a feature, but all examples are not limited thereto.

[0045] Figure 1 An example memory array of the memory device 100 is shown in accordance with one or more embodiments.

[0046] The non-volatile memory device 100 (or memory device 100) may include a memory array 110. Here, an electronic device (such as a non-volatile memory device 100) represents one or more processors or one or more processors and a memory storing instructions configured to perform one or more or any combination of the operations or methods described herein. The one or more processors may be corresponding dedicated hardware-based computers or other dedicated hardware. The one or more processors may be configured to execute such instructions. One or more memories may store instructions that, when executed by one or more processors, configure the one or more processors to perform one or more or any combination of the operations of the methods described herein.

[0047] The memory array 110 may include resistive memory cells (or cells). The resistive memory cells may be arranged along lines. For example, the resistive memory cells may be arranged along word lines and column lines. The word lines may also be referred to as row lines.

[0048] The memory array 110 may have N+1 resistive memory cells 111 representing a bit sequence of N bits for each word line. N may be greater than or equal to 2 (e.g., N is an integer greater than or equal to 2). The bit sequence may be a sequence of bit values. Here, a bit sequence including N bit values ​​("N-bit sequence") is mainly described. A combination of N+1 resistance values ​​(e.g., high / low) individually set for the N+1 resistive memory cells 111 corresponding to any one of the word lines may correspond to (represent / represent) the N-bit sequence. Figure 1 As shown in , the first resistive memory cell to the N+1th resistive memory cell can be arranged along the same word line. The N+1 resistance values ​​representing the desired N-bit sequence can be determined based on the result of encoding the N-bit sequence. The encoding can be based on, for example, an exclusive OR (XOR) scheme. For example, the bit value can depend on the XOR of the values ​​of two cells (for example, if they are the same, then "1", otherwise "0"). The following reference Figure 5 Describes the mapping relationship between a resistance value combination (e.g., the values ​​in N+1 cells) and a bit sequence (e.g., an N-bit sequence). The resistance value combination may be a combination of resistance values ​​individually set for the corresponding N+1 resistive memory cells 111 of the word line corresponding to the resistance value combination; the resistance value combination may also be referred to as a resistance value sequence.

[0049] The resistive memory cell may include a resistive memory element (or referred to as a memory element or a resistive element). The resistive memory element (e.g., a magnetic tunnel junction (MTJ)) may be an element having a set resistance value and may have one of a plurality of resistance values. The resistive memory element may have a resistance value, such as a first resistance value or a second resistance value. The first resistance value may be less than the second resistance value. The first resistance value may be a resistance value in a low resistance state (LRS) (e.g., R P , in the MTJ example, represents a resistance parallel), and the second resistance value may be a resistance value in a high resistance state (HRS) (eg, R AP , in the MTJ example, the resistors are antiparallel). Figure 2 As described, the resistive memory element of the resistive memory cell may be, for example, a magnetic random access memory (MRAM).

[0050] According to an embodiment, the resistance state (e.g., resistance value) of a plurality of resistive memory elements may be configured / may be used to represent a single bit value. For example, a single bit value may be determined based on two resistance values ​​of two adjacent resistive memory elements. For example, the same resistance state of two adjacent resistive memory elements may represent a first bit value (e.g., bit value 0), and the different resistance states of two adjacent resistive memory elements may represent a second bit value (e.g., bit value 1). For example, when the bit value of a particular bit position in a bit sequence is a first bit value, the resistance values ​​of two adjacent memory elements (among the N+1 resistive memory cells 111) corresponding to the particular bit position may be the same. When the bit value of a particular bit position is a second bit value, the resistance values ​​of two adjacent memory elements (among the N+1 resistive memory cells 111) corresponding to the particular bit position may be different.

[0051] The operating method of the memory device 100 (e.g., a memory encoding method) may involve encoding a bit value by using two adjacent resistive memory cells, that is, mapping the bit value to the appropriate resistance value of the adjacent resistive memory cells so that they can be decoded later to retrieve (reconstruct) the bit value therefrom. For example, when the bit value is a first value, the memory encoding method may set the resistance value of the two adjacent resistive memory cells to be the same. When the bit value is a second value, the memory encoding method may set the resistance value of the two adjacent resistive memory cells to be different. In the memory encoding method, N bit values ​​may be encoded as the resistance value of N+1 resistive memory cells that will store N bit values ​​(and the corresponding resistance of the N+1 resistive memory cells set accordingly). The N+1 resistive memory cells may be connected to a shared word line (N may be greater than or equal to 2).

[0052] For reference, a non-limiting example in which the first bit value is 0 and the second bit value is 1 is mainly described herein. The memory encoding method may be based on an XOR in which the first value is 0 and the second value is 1. The encoding of mapping the bit value 0 to two equal resistance values ​​of two resistive memory elements and mapping the bit value 1 to two different resistance values ​​of two resistive memory elements may be referred to as XOR encoding (here, "same" is functional - differences within tolerance are expected). As described below, the resistance values ​​set by such a mapping can be converted into bit values ​​by an XOR decoding operation. However, the examples are not limited to this. The memory encoding method may alternatively be based on an exclusive-not-or (XNOR, also called exclusive-or) in which the first value is 1 and the second value is 0. This may be referred to as XNOR encoding. Reference is made below Fig. 7A Describe the operation of XOR encoding, refer to Fig.9A The operation of XOR decoding is described below with reference to Figure 7B The operation of XNOR encoding is described below with reference to Fig. 9BDescribes the operation of XNOR decoding.

[0053] In some embodiments, the memory device 100 may have a memory macro structure having a resistive memory cell having a resistance value obtained by encoding a bit sequence based on XOR encoding. The memory macro structure of the memory device 100 may have a reduced area overhead and an increased read margin for an existing resistive memory device. Therefore, the memory device 100 may use less power to perform a read process compared to an existing resistive memory device.

[0054] Figure 2 An example configuration of a memory device 100 according to one or more embodiments is shown.

[0055] The memory device 100 may include a memory array 110 , a line selection circuit 230 , a read circuit 250 , and a write circuit 270 .

[0056] As described above, the memory array 110 may include N+1 resistive memory cells representing / representing an N-bit sequence for each line (eg, word line). Figure 2 In the example shown in , the memory array 110 may have M+1 word lines and N+1 column lines. The N+1 column lines may include N data column lines and one reference column line (left side). Here, M may be greater than or equal to 1, and N may be an integer greater than or equal to 2. The memory array 110 may include a total of (M+1)×(N+1) resistive memory cells.

[0057] exist Figure 2 In the example shown in , the resistive memory cell may have a 1T 1R (e.g., one transistor / one resistor) structure, i.e., one transistor and one resistive element. One transistor of the cell may operate as a switch element for controlling access to a corresponding resistive element of the cell (among the resistive elements arranged along the line). As described below, the switch element (e.g., transistor) of the resistive memory cell may be turned on by the word line driver 231. Referring to Figure 2 , the resistive memory cell may include an MRAM element as a resistive memory element.

[0058] The MRAM element may include, for example, a magnetic tunnel junction (MTJ) element. Figure 2 ,MTJ i,j It is the MTJ element of the i-th word line (among the word lines) and the j-th data column line (among the data column lines). i is an MTJ element of an i-th word line and a reference line (eg, a reference column line). i may be greater than or equal to 0 and less than or equal to M, and j may be greater than or equal to 0 and less than or equal to N-1.

[0059] The MTJ element may be a memory element whose resistance value changes according to the spin state of internal electrons. For example, the MRAM element may have a resistance value similar to that of the HRS R according to the configuration / implementation. AP and LRS R P The MRAM element can be non-volatile because the spin state of the internal electrons is maintained even when the power supply voltage is removed. The size and leakage current of the MRAM element can be small. The MRAM element is mainly described herein as an example of a resistive memory element, but the example is not limited thereto. The resistive memory element can be, for example, a ferroelectric RAM (FRAM) element, a phase change memory (PCM) element, a 3D XPoint element, a spin transfer torque (STT)-MRAM element, a nano RAM (NRAM) element, a resistive RAM (ReRAM) element, a conductive bridge RAM (CBRAM), or any other suitable resistive memory element.

[0060] The line selection circuit 230 may select at least one word line from among a plurality of word lines for a read operation or a write operation. The line selection circuit 230 may include an address decoder 232 and a word line driver 231 .

[0061] The address decoder 232 may identify a word line corresponding to a given address from among the word lines. For example, the memory device may receive an access request to a memory (e.g., the memory array 110) from an external device (e.g., a host). The access request may be a request for access for a read operation or a write operation and may include information (e.g., a memory address) indicating a memory location in the memory (e.g., the memory array 110) intended to be accessed. By decoding the memory address, the address decoder 232 may generate information indicating a word line among the word lines corresponding to the requested memory location.

[0062] The word line driver 231 may activate a word line corresponding to an access request. For example, the word line driver 231 may enable a signal (e.g., a word line selection signal) applied to a word line selected from among the word lines. The word line driver 231 may enable an activation signal applied to a word line indicated by a result of decoding the access request by the address decoder 232. The switch element (e.g., a transistor) of the corresponding resistive memory cell connected to the selected word line may be turned on by the enabled signal applied to the selected word line. The resistive memory elements arranged along the selected word line may be connected to corresponding column lines, respectively. The memory device may set (e.g., write) the resistance value of the resistive memory element of the activated word line, or may read a previously stored resistance value. A resistive element may store data.

[0063] The readout circuit 250 can read data (e.g., an N-bit sequence) recorded in the N+1 resistive memory cells of the memory array 110. For example, the readout circuit 250 can generate a bit read signal based on the result of XOR between the resistance values ​​set for the N+1 resistive memory cells arranged along the word line selected for reading. Figure 5 As described, the resistance value combination (e.g., N+1 resistance values) can be mapped to a bit sequence (e.g., an N-bit sequence) based on XOR encoding. The readout circuit 250 may include N readout units (e.g., a first readout unit to an N-th readout unit) of the corresponding column configured to generate N corresponding bit read signals, respectively. Since each readout unit includes its own logic element and / or logic circuit (e.g., an XOR circuit), the readout unit can have a relatively simplified structure and reduced power consumption. In addition, since a comparison (e.g., XOR) between resistive memory cells along adjacent column lines is performed, a readout margin can be ensured and a more efficient read operation can be enabled.

[0064] The write circuit 270 may write a resistance value (according to the value of the corresponding N-bit sequence) to the resistive memory cell of the memory array 110. If the memory access request is a request for writing, the memory access request may include a memory address and a value (e.g., a bit sequence) to be recorded in the memory address. For the resistive memory cell of the word line activated for the memory access request, the write circuit 270 may set a resistance value corresponding to the result of XOR encoding of the bit sequence of the memory access request. The write circuit 270 may include a reference write circuit 271, a write encoder 273, and a write driver 275.

[0065] The reference write circuit 271 may set the resistance value of the resistive memory element arranged along the reference column line. For example, the reference write circuit 271 may set the resistance value determined according to the XOR encoding for the resistive memory element corresponding to the reference column line in the selected word line. As described below, the reference resistance value of the word line may indicate how to perform XOR decoding on the resistive memory element of the word line.

[0066] although Figure 2 The reference write circuit 271 is shown as being separate from the write encoder 273 and the write driver 275, but the example is not limited thereto. The configuration and / or function of the reference write circuit 271 may be integrated into the write encoder 273 and / or the write driver 275. The functional division between components is arbitrary and unimportant.

[0067] The write encoder 273 may generate N+1 write signals respectively indicating the resistance values ​​to be set for the N+1 resistive memory cells of the selected row / word line, which may be based on the reference signal and the N bit signals respectively indicating the bit values ​​of the N bit sequence (data to be stored). The reference signal may be a signal indicating a bit value corresponding to the resistance value (e.g., a reference resistance value) set for the resistive memory elements arranged along the reference column line in the corresponding word line. The N bit signals may be signals respectively indicating the bit values ​​corresponding to the bit positions of the N bit sequence. Each of the N+1 write signals may indicate the resistance value set for the corresponding resistive memory cell in the word line.

[0068] In summary, the write driver 275 may convert the binary N+1 write signals into corresponding voltages / currents to be written, respectively. More specifically, the write driver 275 may set the resistance value of the resistive memory cell to be written on the word line selected for writing according to the result of XOR encoding of the bit sequence to be written. Each of the N+1 write signals may indicate the resistance value to be set for the respectively corresponding resistive memory element at a specific position among the N+1 resistive memory elements in the selected word line. The write driver 275 may set the resistance value indicated by the specific write signal for the corresponding resistive memory cell. The write driver 275 may set the resistance values ​​of the N+1 resistive memory cells by using the N+1 write signals. For example, if the bit value of the specific write signal is 0, the write driver 275 may set the resistance value (e.g., R) of the first resistance state (e.g., LRS) for the corresponding resistive memory cell. P For another example, if the bit value of a particular write signal is 1, the write driver 275 may set a resistance value (eg, R ) of a second resistance state (eg, HRS) for the corresponding resistive memory cell. AP The write driver 275 may set the resistance value determined based on the XOR encoding for each resistive memory element of the activated word line by enabling a setting signal (eg, voltage and / or current) corresponding to the corresponding write signal of each resistive memory element of the activated word line.

[0069] According to some embodiments, in a memory device, two resistance values ​​set for two corresponding adjacent resistive memory cells arranged along a word line (in a row direction) together represent / represent one bit value. The memory device can read the bit value of the resistive memory element regardless of the resistance shift of the resistive memory element corresponding to the position of the resistive memory element in the memory array 110 (for example, caused by wiring resistance, which may vary among the resistive memory elements due to the varying circuit position of the resistive memory element and the corresponding wiring length).

[0070] In some embodiments, the reference resistor for reading the resistance value of a particular resistive memory cell may be the resistance value of the resistive memory cell on the row of the particular resistive memory cell. REF The resistance of each resistive memory cell (e.g., R LRS or R HRS ), there is a problem that the resistance of each resistive memory cell depends on its row position and / or its column position. On the other hand, some embodiments of the memory device described herein can avoid such a problem because the resistance value of each resistive memory cell is compared with the resistance value of an adjacent (e.g., adjacent to the right in the row direction) resistive memory cell (e.g., a resistive memory cell adjacent to each resistive memory cell on the right side of each resistive memory cell along the row direction), and a read offset (position-dependent resistance component) can be suppressed even in different column positions.

[0071] Despite the variation of the resistance value of the resistive memory element (e.g., MTJ), the memory device can read the bit value according to the combination of resistance values ​​(i.e., according to the resistance value of each resistive memory element) by providing a further increased read margin. When comparing adjacent resistive memory elements, since the resistive memory elements are implemented with the same material, the process, voltage, and temperature (PVT) variation 211 moves in the same direction for each element, and a more robust read characteristic can be provided.

[0072] In addition, in other technologies, LRS may be a state having a resistance lower than a reference resistance, and HRS may be a state having a resistance higher than a reference resistance. In contrast, in some embodiments described herein, LRS may be a state just lower than HRS, and HRS may be a state higher than LRS. Therefore, in a memory device according to some embodiments, the readout margin considered for identifying a resistance state may be substantially increased compared to the prior art. For example, the readout margin may be increased by approximately two times. This is because an adjacent MTJ element having a symmetrical layout (e.g., on the right side along the row direction) may be used as a reference. Therefore, since the memory device ensures a relatively large noise margin, the memory device may provide further robustness of the readout result against PVT variations 211.

[0073] The two MTJs can be references to each other and can be implemented in a small area. As described above, the memory device 100 can generate an N-bit sequence through N+1 resistive memory cells (e.g., N+1 resistive memory elements). Therefore, since only one column line is added in the entire macro structure, the area overhead for providing the aforementioned possible benefits is tiny.

[0074] The memory device according to some embodiments may be nonvolatile, but the memory device according to some embodiments may effectively reduce power consumption and may prevent leakage current by retaining data even when power is turned off. The memory device may be used in various hardware including a neuromorphic processor, a mobile device, or an edge device. The memory device may provide reduced power consumption and reduced area in read and write operations.

[0075] Figure 3 An operating method of a memory device according to one or more embodiments is illustrated.

[0076] In operation 310, the nonvolatile memory device may set a resistance value for representing an N-bit sequence for N+1 corresponding resistive memory cells in a memory array arranged along a word line selected for writing. Here, N may be an integer greater than or equal to 2. For example, a word line driver of the memory device may select a word line corresponding to a memory write request (or referred to as a write request). The write circuit may set a resistance value determined based on an XOR encoding of a bit sequence corresponding to the memory write request for the resistive memory cells arranged along the selected word line. When the bit value of a bit position in the bit sequence is a first bit value, the memory device may set the same resistance value for adjacent memory elements corresponding to the bit position. When the bit value of a bit position is a second bit value, the memory device may set different resistance values ​​for adjacent memory elements corresponding to the bit position. Refer to the following Figure 8 , Fig.9A and Fig. 9B A write operation of a memory device is described.

[0077] In operation 330, the nonvolatile memory device may output N bit read signals from N+1 resistive memory cells arranged along the word line selected for reading in the memory array. For example, a word line driver of the memory device may select a word line corresponding to a memory read request (or referred to as a read request). The read circuit may determine the bit read signal based on an XOR operation of the resistance value set for the resistive memory cell of the word line corresponding to the memory read request. Figures 4 to 7A and Figure 7B A read operation of a memory device is described.

[0078] Figure 4 A read operation of a memory device according to one or more embodiments is shown. Figure 5 An example of a bit sequence using a combination of resistance values ​​in a memory device according to one or more embodiments is shown.

[0079] In operation 431, a memory device according to an embodiment may activate a word line corresponding to a memory read request. For example, the memory device may identify a word line indicated by a memory address of the memory read request. The memory device may activate the resistive memory cell by connecting the resistive memory elements of the identified word line to the corresponding column lines, respectively.

[0080] In operation 433, the memory device may output a bit read signal according to a combination of resistance values ​​stored in two adjacent resistive memory cells (along the same row). The memory device may determine a bit read signal indicating a bit value for each of two adjacent resistive memory cells in the resistive memory element arranged along the word line. The memory device may determine a bit value corresponding to the resistance value of two adjacent resistive memory cells based on a mapping according to XOR encoding. The mapping according to XOR encoding is described below by Tables 1 and 2. Table 1 is a truth table of an XOR element (or XOR circuit) provided as a reference.

[0081] Table 1

[0082] As shown in Table 1, in XOR, when inputs A and B are the same, output Q is 0, and when inputs A and B are different, output Q is 1. The resistance value of the first resistance state (eg, LRS) itself (eg, R P ) or a signal corresponding to the resistance value of the first resistance state (e.g., a voltage signal or a current signal) may represent a first logic value (e.g., a logic value L or 0). The resistance value of the second resistance state (e.g., HRS) itself (e.g., R AP ) or a signal corresponding to the resistance value of the second resistance state (e.g., a voltage signal or a current signal) may represent a second logic value (e.g., a logic value H or 1). Referring to the truth table shown in Table 1, inputs A and B of the XOR operation are logic values ​​corresponding to the resistance values ​​set for the adjacent resistive memory elements, and the output Q may be a bit value. Therefore, the mapping between the resistance value according to the XOR encoding and the combination of each bit value may be represented by the following Table 2.

[0083] Table 2

[0084] As shown in Table 2 above, a bit value of 0 may be used as a state in which the resistance values ​​of the two resistive memory cells are the same (R AP , R AP ) or (R P , R P ) are written and read. A bit value of 1 can be used as a state in which the resistance values ​​of the two resistive memory cells are different (R AP , R P) or (R P , R AP ) is written and read. The XOR operation result between the logic values ​​corresponding to the resistance values ​​stored in the two resistive memory cells can be the bit value of the corresponding bit position. Therefore, the XOR encoding result of the bit value can be the resistance value stored in the two adjacent resistive memory cells corresponding to the bit position.

[0085] In operation 435, the memory device may output a read result based on the bit read signal. As described above, the resistive memory cells arranged along each word line of the memory array may have a resistance value corresponding to the result of the XOR-based encoding of the bit sequence. According to some embodiments, the memory device may determine the bit sequence to be read by decoding the resistance value combination based on the XOR operation. For example, the memory device may generate a bit read signal by performing the operation according to operation 433 together for each pair of adjacent resistive memory cells (along the word line / row). For reference, when there are N+1 resistive memory cells, there are N adjacent pairs, and the operation according to operation 433 may be performed on the N adjacent pairs simultaneously and / or in parallel. The memory device may generate an N-bit sequence corresponding to the resistance value combination (e.g., a resistance value sequence) as a read result by combining (joining) the bit values ​​respectively indicated by the generated bit read signals.

[0086] To help understand the XOR-based decoding of N+1 resistor values ​​into N bit values, consider Figure 5 Example 510 shown in . Example 510 involves representing a 4-bit sequence 530 (4 data bits or bit values) by 4 data column lines COL[3:0] and a reference column line REF_COL (5 resistance values). As an example, the 4-bit sequence 530 is represented by RDATA[3:0], and the data of the 4-bit sequence 530 can be "1011". The first resistance value combination 511 (top right) is a first way to represent the example 4-bit sequence 530 ("1011"), and the second resistance value combination 512 (bottom right) is a second way to represent the same 4-bit sequence 530 ("1011").

[0087] In the case of the first resistance value combination 511, in the 4-bit sequence 530, if the reference resistance value (RREF) is R AP , then as RDATA[3] (for example, the most significant bit (MSB)) 1 is represented by (RAP, R P ) (i.e., XOR of RREF and MSB). And, 0 as RDATA[2] (e.g., MSB-1) is represented by (R P , R P ) (i.e., the XOR of MSB and MSB-1). Similarly, RDATA[1] and RDATA[0] are represented by (RP , R AP ) (i.e., XOR of MSB-1 and LSB+1) and (R AP , R P ) (ie, XOR of LSB+1 and LSB). Therefore, when these resistance values ​​are combined, the first resistance value combination 511 may be (R AP , R P , R P , R AP , R P ), (R AP , R P , R P , R AP , R P ) is a first resistor having a resistance value R AP The reference resistance value.

[0088] On the other hand, in the case of the second resistance value combination 512, if the reference resistance value is R P , then the second resistance value combination 512 can be (R P , R AP , R AP , R P , R AP ). The reference resistance value may be a resistance value that is a reference for the resistance value combination (or resistance value sequence), and may be, for example, a first resistance value. The memory device may select the resistance value combination by determining the value of a write signal indicating the reference resistance value. For example, the memory device may determine the value of a write signal indicating the reference resistance value to be 1 (same as R AP The memory device can select the first resistance value combination 511 by determining the value of the write signal indicating the reference resistance value to be 0 (corresponding to R P Correspondingly) to select the second resistance value combination 512.

[0089] As described in the above example, according to XOR encoding, two resistance value combinations can always represent a bit sequence. For example, a memory device (e.g., a write driver 275 included in the memory device) can set (e.g., write) one resistance value combination among available resistance value combinations for N+1 resistive memory cells of a word line selected for writing, and the available resistance value combinations represent a bit sequence. Figure 5 As shown in FIG. 1 , due to XOR encoding, the resistance value combinations representing one bit sequence may be in a complementary relationship. In other words, the resistance value of any one of the resistance value combinations may have a logic value opposite to the resistance value of another resistance value combination in the corresponding column line. As described above, since the two resistance value combinations correspond to the same bit sequence, the memory device may output the same bit sequence as a result of reading the two resistance value combinations.

[0090] Figure 5 Only an example of a single 4-bit bit sequence (i.e., a 4-bit sequence) is shown. Tables 3 and 4 show that two resistance value combinations can be used for all 4-bit bit sequences. In the following Tables 3 and 4, COL[4] can be a reference column line, and COL[3:0] can be a data column line. Table 3 shows that when a low resistance value (or first resistance value) R is set for the resistive memory cell of COL[4] P Table 4 shows the resistance value combinations corresponding to the 4-bit sequence when the high resistance value (or the second resistance value) R is set for the resistive memory cell of COL[4]. AP (ie, reference resistance value) is a combination of resistance values ​​corresponding to the 4-bit sequence.

[0091] Table 3

[0092] Table 4

[0093] The above provides a description of a 4-bit sequence, but the two resistance value combinations are also applicable to any N-bit sequence greater than or equal to 4 bits. Table 5 below shows the resistance value combinations to which an 8-bit sequence (ie, 8-bit sequence) 10010101 is mapped.

[0094] Table 5

[0095] Therefore, even if the number N of bits constituting the bit sequence increases, the memory device can represent N bits (eg, 8 bits) through N+1 (eg, 9) resistive memory elements.

[0096] Figure 6 , Fig. 7A and Figure 7B A read operation by a sensing circuit in a memory device is shown according to one or more embodiments.

[0097] In operation 631, the memory device may wait for a memory access request in an idle state. The memory device may initiate an operation for a memory read in response to receiving a memory read request.

[0098] In operation 632, the memory device may activate word line 720 based on decoding of the address of the read request. Fig. 7A, the address decoder 232 may receive the address ADDR of the memory read request. The address decoder 232 may provide information indicating the word line 720 corresponding to the result of decoding the address ADDR. For example, the word line driver may activate the word line 720 corresponding to the address ADDR. By enabling a signal according to the word line 720 selected in the memory array, the word line driver may allow a read pulse to be sent to the resistive memory element located in the selected word line 720.

[0099] In operation 633, the memory device may generate an edge of a strobe signal STRB. For example, a strobe signal generating circuit (not shown) of the memory device may generate the strobe signal STRB. The strobe signal STRB may be provided to Fig. 7A 1 and 2. The read pulse generator 710 and the reset generator 731 shown in FIG. Both the rising edge and the falling edge of the selection signal STRB may be used.

[0100] In operation 634, the memory device may generate a reset signal (Reset) in response to an edge. For example, the reset generator 731 may generate a reset signal in response to the strobe signal STRB. The reset generator 731 may detect both a rising edge and a falling edge of the strobe signal STRB. The reset generator 731 may send a reset signal (e.g., a pulse (e.g., a short pulse)) to a reset port (R) of the SR latch of the readout circuit 250 at each rising edge and each falling edge of the strobe signal STRB. Therefore, the data stored in the node Q of the SR latch may be initialized to 0 at each edge of the strobe signal STRB.

[0101] In operation 635, the memory device may transmit the edge to the memory array. Fig. 7A , the read pulse generator 710 of the memory device may include a buffer (BUF) connected to each column line (eg, a bit line), and may drive the bit line by supplying a strobe signal STRB to the corresponding column line through the buffer.

[0102] In operation 636, the memory device may set a latch circuit (eg, an SR latch) using an XOR operation result according to the delay difference. According to an embodiment, the sensing circuit 250 may include an XOR element connected to a corresponding "pair of adjacent resistive memory cells" among the N+1 resistive memory cells. Fig. 7AAn example is shown in which the first readout unit 751 and the second readout unit 752 include XOR elements, respectively. In the first readout unit 751, the XOR element may output a comparison result between the resistance value of the first resistive memory element A and the resistance value of the adjacent second resistive memory element B. For example, the first readout unit 751 may output 0 when the resistance value of the first resistive memory element A and the resistance value of the second resistive memory element B are the same, and may output 1 when the resistance value of the first resistive memory element A and the resistance value of the second resistive memory element B are different.

[0103] exist Fig. 7A In the example shown in , a voltage may be provided to an input terminal of the XOR element by power driven to the bit line. The time during which the voltage is charged or discharged may vary according to the parasitic capacitance formed along the bit line and the resistance value set for the resistive memory cell. The XOR element may output a comparison result of the resistance values ​​set for two resistive memory elements (e.g., 0 when the resistance values ​​of the two resistive memory elements are the same, and 1 when the resistance values ​​of the two resistive memory elements are different) by a delay (e.g., a charging delay or a discharging delay) that varies according to the resistance value set for each resistive memory element. For example, the readout circuit 250 may output a comparison result (e.g., a delay difference) between the delays occurring in two adjacent resistive memory cells as the bit values ​​of the two adjacent resistive memory cells according to the parasitic capacitance value and the resistance value set for the two adjacent resistive memory cells. Each XOR circuit of the readout circuit 250 may output the XOR output as "1" when the delay difference exceeds a threshold value, and may output the XOR output as "0" when the delay difference is less than or equal to the threshold value.

[0104] For example, the first resistive memory element A and the second resistive memory element B of a word line corresponding to the first address A0 among the plurality of word lines may have resistance values ​​R P and R AP Until the first resistor value R is connected to the XOR element and is set P It may take a first time t for the voltage of the node of the first resistive memory element A to reach the threshold voltage. P Until the second resistor value R is connected to the XOR element and is set AP It may take a second time t for the voltage at the node of the second resistive memory element B to reach the threshold voltage. AP . First time t P Can be less than the second time t AP Therefore, until the voltages of the first resistive memory element A and the second resistive memory element B reach the threshold voltage, the first time t Pand the second time t AP Therefore, the voltages at the two input terminals of the XOR element may be different due to the delay difference t AP -t P The XOR element can be delayed by the difference t AP -t P During this period, an output pulse (or pulse signal) corresponding to "1" (or logic value H) is generated. This output pulse can be sent to the set port (S) of the SR latch in the corresponding read unit. The node Q of the SR latch can output a signal corresponding to "1" (or logic value H).

[0105] For another example, the first resistive memory element A and the second resistive memory element B of the word line corresponding to the second address A1 among the plurality of word lines may have resistance values ​​R AP and R P Similarly, until the voltages of the first resistive memory element A and the second resistive memory element B reach the threshold voltage, the first time t starting from the falling edge of the selection signal STRB may be respectively AP and the second time t P For reference, the rising edge can be the voltage charging time, and the falling edge can be the voltage discharging time. The XOR element can be used at the delay difference t AP -t P During this period, an output pulse corresponding to the logic value H is generated. The node Q of the SR latch can output a signal corresponding to "1" (or logic value H).

[0106] In yet another example, the first resistive memory element A and the second resistive memory element B of the word line corresponding to the third address A2 may have resistance values ​​R P and R P In this case, the same delay (eg, t P ). Therefore, the XOR element may provide a signal corresponding to "0" (or a logic value L). Therefore, the SR latch may maintain a value of 0 (eg, a signal corresponding to a logic value L) initialized by the reset signal. AP The same, so the output of the SR latch can be maintained at 0.

[0107] For reference, although Fig. 7AOnly an example of the first resistive memory element A and the second resistive memory element B in the word line 720 corresponding to the first address A0 is shown, but the same or similar description also applies to other resistive memory cells among the N+1 resistive memory cells including the resistive memory elements of the reference column line and the resistive memory elements of the data column line.

[0108] In addition, since the resistance value of the resistive memory element may not be ideal or completely the same, an error may occur. Therefore, even when the same resistance value is set, a delay difference may occur. Therefore, the XOR element (or XOR circuit) may be designed to output a pulse signal corresponding to "1" (or logic value H) only when the delay difference occurring at the two input terminals exceeds a threshold value. In addition, the XOR element may also be designed so that the threshold value can be variably adjusted.

[0109] although Fig. 7A An example of reading using a delay difference is shown, but the example is not limited thereto. The memory device may output a result of sensing a voltage difference by supplying power to a resistive memory element. The memory device may output a result of sensing a current difference by applying a voltage to a resistive memory element. The memory device may be implemented in a "various structure that can compare resistance values ​​set for two adjacent resistive memory elements".

[0110] In operation 637, the memory device may read the output of the latch circuit through a clock synchronized with the edge. For example, the memory device may read the bit value set for the node Q of the SR latch through an input / output (I / O) logic via a clock synchronized with the rising and falling edges of the selection signal STRB. As described above, the bit values ​​of the resistive memory cells located in the same word line 720 may be read together.

[0111] When the output of the bit read signal is completed, the memory device may return to operation 631 and may wait for the next memory access request in an idle state.

[0112] although Fig. 7A XOR encoding is mainly shown, but the example is not limited thereto. The memory device may have a resistance value set based on XNOR encoding instead of XOR encoding. Figure 7B shows the operation of reading the resistance value that has been XNOR-encoded, and Fig. 9B XNOR decoding is shown.

[0113] According to an embodiment, a memory device can read a bit sequence from a resistance value set based on XNOR encoding. Fig. 7A The first readout unit 751 including the XOR element and the second readout unit 752 are different, Figure 7BThe readout circuit 250b shown in FIG. 1 may include a readout unit 751b and a readout unit 752b having an XNOR element. In the readout circuit 250b, the output waveform of the XNOR element and the output waveform of the node QB of the SR latch may be waveforms in opposite phases to the output waveform of the XOR element and the output waveform of the node Q of the SR latch. Other operations of the readout circuit 250b may be the same as those described above with reference to FIG. Fig. 7A The operation of the readout circuit 250 described above is similar. Operation 631, operation 632, operation 633, operation 634, and operation 635 are similar to those in Fig. 7A For all intents and purposes, the description of the XOR operation is conceptually applicable to the XNOR operation.

[0114] Alternatively, the memory device may set a latch circuit using an XNOR operation result according to the delay difference in operation 636. According to an embodiment, the sensing circuit 250b may include an XNOR element connected to two adjacent resistive memory cells among the N+1 resistive memory cells. Figure 7B An example is shown in which the first readout unit 751b and the second readout unit 752b include XNOR elements, respectively. For example, the first readout unit 751b may output 1 when the resistance value of the first resistive memory element A and the resistance value of the second resistive memory element B are the same, and may output 0 when the resistance value of the first resistive memory element A and the resistance value of the second resistive memory element B are different.

[0115] exist Figure 7B In the example shown, a voltage may be provided to an input terminal of the XNOR element by power driven to the bit line. The time during which the voltage is charged or discharged may vary according to the parasitic capacitance formed along the bit line and the resistance value set for the resistive memory cell. The XNOR element may output a comparison result of the resistance values ​​set for two resistive memory elements (e.g., 1 when the resistance values ​​of the two resistive memory elements are the same, and 0 when the resistance values ​​of the two resistive memory elements are different) by a delay (e.g., a charging delay or a discharging delay) that varies according to the resistance value set for each resistive memory element. For example, the readout circuit 250b may output a comparison result (e.g., a delay difference) between delays occurring in two adjacent resistive memory cells according to the parasitic capacitance value and the resistance value set for the two adjacent resistive memory cells. For example, each XNOR circuit of the readout circuit 250b may output the XNOR output as "0" when the delay difference exceeds a threshold value, and may output the XNOR output as "1" when the delay difference is less than or equal to the threshold value.

[0116] For example, among the word lines, when the resistance values ​​stored in the first resistive memory element A and the second resistive memory element B of the word line corresponding to the first address A0 are R P and R AP When the XNOR element has a delay difference t AP -t P During this period, an output pulse corresponding to "0" (or logic value L) is generated. This output pulse can be sent to the set port of the SR latch in the corresponding read unit. The node QB of the SR latch can output a signal corresponding to "0" (or logic value L). For reference, although Fig. 7A A NOR gate based SR latch is shown for high-active operation, but Figure 7B An SR latch based on a NAND gate is shown for active low operation. The output pulse generated in the XNOR element may be input to a node SN of the SR latch, and Figure 7B The SR latch can generate an output at node QB.

[0117] For another example, among the word lines, when the resistance values ​​stored in the first resistive memory element A and the second resistive memory element B of the word line corresponding to the second address A1 are R AP and R P When the XNOR element has a delay difference t AP -t P During this period, an output pulse corresponding to the logic value L is generated. The node QB of the SR latch can output a signal corresponding to "0" (or logic value L).

[0118] In yet another example, when the resistance values ​​stored in the first resistive memory element A and the second resistive memory element B of the word line corresponding to the third address A2 are R P and R P When the XNOR element is set to "1" (or logic value H), the XNOR element can provide a signal corresponding to "1" (or logic value H). Therefore, the SR latch can maintain the reset signal (input to the reset signal) at the node QB. Figure 7B The reset port RN of the fourth address A3 is initialized to a value 1 (eg, a signal corresponding to a logic value H). AP The same, so the output of the SR latch can be maintained at 1.

[0119] In operation 637, the memory device may read the output of the latch circuit through a clock synchronized with the edge. For example, the memory device may read the bit value set for the node QB of the SR latch through the I / O logic via a clock synchronized with the rising and falling edges of the selection signal STRB.

[0120] Figure 8 , Fig.9A and Fig. 9B A write operation by a write circuit in a memory device is shown according to one or more embodiments.

[0121] In operation 811, the memory device may wait for a memory access request in an idle state. The memory device may initiate an operation for a memory write in response to receiving a memory write request.

[0122] In operation 813, the memory device may perform XOR encoding on the data. According to an embodiment, the memory device may perform XOR encoding on the N-bit sequence included in the data of the memory write request by writing the encoder 273. For example, the write encoder 273 may include an XOR element. For example, the XOR element may be implemented as an XOR gate. According to the truth table described in Table 1 above, the XOR gate may output 0 when the inputs are the same, and may output 1 when the inputs are different.

[0123] Reference Fig.9A In the write encoder 273, the output of at least one of the plurality of XOR elements may be connected to one of the inputs of another XOR element. For example, the outputs of the remaining XOR elements except the XOR element 939 corresponding to the least significant bit (LSB) among the plurality of XOR elements may be connected to the inputs of different (next / adjacent) XOR elements, respectively. The write encoder 273 may generate N+1 write signals “including the outputs of the plurality of XOR elements and the reference signal REF”. Reference Fig.9A , a total of nine write signals (ie, N write signals XOR[7:0] as outputs of N XOR elements and a reference signal REF) may be generated, where N = 8. The memory device may convert the bit sequence DATA[7:0] into the write signal XOR[7:0].

[0124] The write encoder 273 may include a first XOR element 931 and a second XOR element 932 to a last XOR element 939 corresponding to the LSB. The first XOR element 931 may receive a bit signal DATA[7] corresponding to the MSB and a reference signal REF, and may generate a first XOR result between the bit value of the MSB and the bit value of the reference signal REF. The second XOR element 932 may receive a bit signal (DATA[6]) corresponding to a subsequent bit of the MSB and the first XOR result, and may generate a second XOR result between the bit value of the bit signal (DATA[6]) corresponding to the subsequent bit and the first XOR result. The write encoder 273 may generate a write signal corresponding to the XOR encoding result by providing the output of the XOR element and the bit signal corresponding to the subsequent bit as an input to the subsequent XOR element. Each write signal output from the XOR element of the write encoder 273 may indicate a value according to the corresponding XOR result.

[0125] According to the embodiment, as mentioned above with reference to Figure 5 As described above, the same bit sequence can be represented by two resistance value combinations. For example, depending on whether the corresponding reference signal REF is 1 or 0, other resistance value combinations can change accordingly. Each of the resistance value combinations can be a value that is inverted from the other resistance value combinations. The memory device can select any one of the two available resistance value combinations for the same bit sequence. For example, the available resistance value combinations of data (e.g., bit sequence DATA[7:0]) 10010101 can be represented by the following Table 6.

[0126] Table 6

[0127] According to an embodiment, the memory device may select a resistance value combination with low (e.g., lowest) predicted power consumption for writing from among the available resistance value combinations. For example, the control circuit (not shown) of the memory device may predict power consumption for each of the available resistance value combinations of the corresponding word line. For example, the control circuit may count the number of resistance changes (e.g., the number of resistance flips) required to write each resistance value combination into the resistive memory cell of the corresponding word line. The control circuit may count the number of required resistance changes from LRS to HRS and the number of required resistance changes from HRS to LRS. The control circuit may calculate the number of memory cells whose resistance needs to be changed in the N+1 resistive memory cells, and calculate the total power consumption estimate based on the number of memory cells whose resistance needs to be changed and the power consumption required in the corresponding resistance change. In addition, the memory device may select a resistance value combination with a small total number of resistance changes required for the N+1 resistive memory cells (e.g., the smallest) from among the available resistance value combinations based on the resistance values ​​set for the N+1 resistive memory cells of the word line 901 selected for writing.

[0128] The control circuit may select any one of the available resistance value combinations in consideration of the power consumption for reading. For example, a current may be supplied to each resistive memory element for reading, and the bit value may be read based on the voltage. In this case, the read power consumption of the resistance value combination in which "the number of resistive memory elements under LRS in the same word line is greater than the number of resistive memory elements under HRS" may be less than the read power consumption of the resistance value combination in the opposite manner. Therefore, the control circuit may select a resistance value combination with a high ratio of LRS from among the available resistance value combinations.

[0129] The control circuit may provide a reference signal REF having a value determined according to the selected resistance value combination. As described above, the write encoder 273 may generate a write signal by providing a bit signal and a reference signal REF to XOR elements connected in series.

[0130] The memory device may activate a word line corresponding to the memory write request in operation 815. The memory device may activate the word line based on decoding of an address of the write request.

[0131] In operation 817, the memory device may record the encoded data in the activated word line. For example, the write driver 275 may receive the write signal XOR[7:0] from the write encoder 273. The write driver 275 may set the resistance value combination COL[7:0] corresponding to the write signal XOR[7:0] for the resistive memory cells of the selected word line 901. The reference write circuit 271 may set the resistance value COL_REF corresponding to the reference signal REF for the resistive memory cells placed along the reference column line. The memory device may change the resistance value of the resistive memory cell including the resistance value different from the resistance value combination selected from the N+1 resistance value combinations of the word line selected for writing, and maintain the resistance value of the resistive memory cell including the same resistance value as the resistance value combination selected from the N+1 resistance value combinations of the word line selected for writing. In this case, the memory device may skip writing of the resistance value of the resistive memory cell whose resistance value before the change will be the same as the resistance value after the change.

[0132] Since the write encoder 273 has a simple structure, the area, power consumption, and delay overhead for the write operation may be small. In addition, the write encoder 273 may operate quickly at a supply voltage of a normal logic level.

[0133] although Fig.9A XOR encoding is shown, but the example is not limited thereto. Fig. 9B As shown in , the memory device can perform XNOR encoding.

[0134] According to an embodiment, the memory device may set a resistance value corresponding to a bit sequence according to a result of performing XNOR encoding. Fig.9A The write encoder 273 including XOR element 931 and elements 932 to 939 is different, Fig. 9B The write encoder 273b shown in FIG. 1 may include an XNOR element 931b and elements 932b to 939b. Only the type of element may be different, and Fig. 9B The connection relationship between the components can be Fig.9A The connection relationship between the components is the same. The operation of the write driver 275b can be the same as Fig.9A Operations 811 and 815 are similar to those in Fig.9A and therefore repeated descriptions are omitted.

[0135] Optionally, in operation 813, the memory device may perform XNOR encoding on the data. Fig. 9B The write encoder 273b performs XNOR encoding on the N-bit sequence included in the data of the memory write request. For example, the write encoder 273b may include multiple XNOR elements. For example, the XNOR element may be implemented as an XNOR gate. The XNOR gate may output 1 when the inputs are the same, and may output 0 when the inputs are different.

[0136] Reference Fig. 9B In the write encoder 273b, the output of at least one of the plurality of XNOR elements may be connected to the input of another XNOR element. For example, the outputs of the remaining XNOR elements except the XNOR element 939b corresponding to the LSB among the plurality of XNOR elements may be connected to the inputs of different XNOR elements, respectively. The write encoder 273b may generate N+1 write signals including the outputs of the plurality of XNOR elements and the reference signal REF. Fig. 9B , a total of nine write signals (ie, N write signals XNOR[7:0] as outputs of N XNOR elements and a reference signal REF) may be generated, where N = 8. The memory device may convert the bit sequence DATA[7:0] into the write signal XNOR[7:0].

[0137] The write encoder 273b may include a first XNOR element 931b and a second XNOR element 932b to a last XNOR element 939b corresponding to the LSB. The first XNOR element 931b may receive a bit signal DATA[7] corresponding to the MSB and a reference signal REF, and may generate a first XNOR result between the bit value of the MSB and the bit value of the reference signal REF. The second XNOR element 932b may receive a bit signal (DATA[6]) corresponding to a subsequent bit of the MSB and the first XNOR result, and may generate a second XNOR result between the bit value of the bit signal corresponding to the subsequent bit and the first XNOR result. The write encoder 273b may generate a write signal corresponding to the XNOR encoding result by providing the output of the XNOR element and the bit signal corresponding to the subsequent bit as an input to the subsequent XNOR element. Each of the write signals output from the plurality of XNOR elements of the write encoder 273b may indicate a value according to the corresponding XNOR result.

[0138] Alternatively, the write driver 275b may receive a write signal XNOR[7:0] from the write encoder 273b in operation 817. The write driver 275b may set a resistance value according to the received write signal XNOR[7:0].

[0139] The examples described herein can be implemented using hardware components, software components, and / or combinations thereof. The processing device can be implemented using one or more general-purpose computers or special-purpose computers (such as, for example, processors, controllers, and arithmetic logic units (ALUs), digital signal processors (DSPs), microcomputers, field programmable gate arrays (FPGAs), programmable logic units (PLUs), microprocessors, or any other device capable of responding and executing instructions in a defined manner). The processing device can run an operating system (OS) and one or more software applications running on the OS. The processing unit can also access, store, manipulate, process, and generate data in response to the execution of the software. For simplicity, the description of the processing unit is used as a singular, however, those skilled in the art will understand that the processing unit may include multiple processing elements and multiple types of processing elements. For example, the processing unit may include multiple processors, or a single processor and a single controller. In addition, different processing configurations are feasible (such as parallel processors).

[0140] Software may include computer programs, code snippets, instructions, or partial combinations thereof, to individually or collectively instruct or configure a processing unit to operate as required. Software and data may be stored in any type of machine, component, physical or virtual device, or computer storage medium or computer storage device that can provide instructions or data to a processing unit or can be parsed by a processing unit. Software may also be distributed on networked computer systems so that the software is stored and executed in a distributed manner. Software and data may be stored by one or more non-transitory computer-readable recording media.

[0141] The method according to the above example can be recorded in a non-transitory computer-readable medium including program instructions to implement various operations of the above example. The medium may also include data files, data structures, etc., alone or in combination with program instructions. The program instructions recorded on the medium may be program instructions specially designed and constructed for the purpose of example, or they may be categories known and available to technicians in the field of computer software. Examples of non-transitory computer-readable media include: magnetic media (such as hard disks, floppy disks, and tapes), optical media (such as CD-ROM disks and DVDs), magneto-optical media (such as optical disks), and hardware devices (such as read-only memory (ROM), RAM, flash memory, etc.) specially configured to store and execute program instructions. Examples of program instructions include: both machine code (such as generated by a compiler) and files containing higher-level codes that can be executed by a computer using a parser.

[0142] The above-mentioned means may act as one or more software modules in order to perform the operations of the above-mentioned examples, and vice versa.

[0143] As described above, although examples have been described with reference to limited drawings, those skilled in the art may apply various technical modifications and variations based thereon. For example, if the described techniques are performed in a different order and / or if the components in the described systems, architectures, devices, or circuits are combined in a different manner and / or replaced or supplemented by other components or their equivalents, appropriate results may be achieved.

[0144] Accordingly, other implementations, other examples, and equivalents are within the scope of the appended claims.

[0145] Here about Figures 1 to 9BThe described computing devices, vehicles, electronic devices, processors, memories, image sensors, vehicle / operating function hardware, advanced driver assistance systems (ADAS) / autonomous driving (AD) systems, displays, information output systems and hardware, storage devices, and other devices, devices, units, modules, and components are implemented or represent hardware components by hardware components. Examples of hardware components that can be used to perform the operations described in this application include, where appropriate, controllers, sensors, generators, drivers, memories, comparators, arithmetic logic units, adders, subtractors, multipliers, dividers, integrators, and any other electronic components configured to perform the operations described in this application. In other examples, one or more hardware components of the hardware components that perform the operations described in this application are implemented by computing hardware (e.g., by one or more processors or computers). A processor or computer may be implemented by one or more processing elements (such as logic gate arrays, controllers and arithmetic logic units, digital signal processors, microcomputers, programmable logic controllers, field programmable gate arrays, programmable logic arrays, microprocessors, or any other device or combination of devices configured to respond and execute instructions in a defined manner to achieve desired results). In one example, the processor or computer includes or is connected to one or more memories storing instructions or software executed by the processor or computer. The hardware components implemented by the processor or computer can execute instructions or software (such as, operating system (OS) and one or more software applications running on OS) for performing the operations described in this application. The hardware components can also access, manipulate, process, create and store data in response to the execution of instructions or software. For simplicity, the singular term "processor" or "computer" can be used for the description of the examples described in this application, but in other examples, multiple processors or computers can be used, or the processor or computer can include multiple processing elements or multiple types of processing elements or both. For example, a single hardware component or two or more hardware components can be implemented by a single processor, or two or more processors, or a processor and a controller. One or more hardware components can be implemented by one or more processors, or a processor and a controller, and one or more other hardware components can be implemented by one or more other processors, or another processor and another controller. One or more processors, or a processor and a controller can implement a single hardware component or two or more hardware components. The hardware components may have any one or more of different processing configurations, examples of which include a single processor, independent processors, parallel processors, single instruction single data (SISD) multiprocessing, single instruction multiple data (SIMD) multiprocessing, multiple instruction single data (MISD) multiprocessing, and multiple instruction multiple data (MIMD) multiprocessing.

[0146] Figures 1 to 9BThe method for performing the operations described in the present application shown in the figure is performed by computing hardware (e.g., by one or more processors or computers), which is implemented as executing instructions or software as described above to perform the operations performed by the method described in the present application. For example, a single operation or two or more operations can be performed by a single processor or two or more processors, or a processor and a controller. One or more operations can be performed by one or more processors or a processor and a controller, and one or more other operations can be performed by one or more other processors, or another processor and another controller. One or more processors, or a processor and a controller can perform a single operation or two or more operations.

[0147] Instructions or software for controlling computing hardware (e.g., one or more processors or computers) to implement hardware components and perform the methods described above may be written as computer programs, code segments, instructions, or any combination thereof to separately or collectively instruct or configure one or more processors or computers to operate as a machine or special-purpose computer to perform the operations performed by the hardware components and methods described above. In one example, the instructions or software include machine code (such as machine code generated by a compiler) that is directly executed by one or more processors or computers. In another example, the instructions or software include higher-level code that is executed by one or more processors or computers using an interpreter. Instructions or software may be written in any programming language based on the block diagrams and flow charts shown in the accompanying drawings and the corresponding descriptions herein, which disclose algorithms for performing the operations performed by the hardware components and methods described above.

[0148] Instructions or software for controlling computing hardware (e.g., one or more processors or computers) to implement hardware components and perform the methods described above, as well as any associated data, data files, and data structures, may be recorded, stored, or fixed in or on one or more non-transitory computer-readable storage media. Examples of non-transitory computer-readable storage media include: read-only memory (ROM), random access programmable read-only memory (PROM), electrically erasable programmable read-only memory (EEPROM), random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, non-volatile memory, CD-ROM, CD-R, CD+R, CD-RW, CD+RW, DVD-ROM, DVD-R, DVD+R, DVD-RW, DVD+RW, DVD-RAM, BD-ROM, BD-R, BD-R LTH, BD-RE, Blu-ray or optical disk storage device, hard disk drive (HDD), solid state drive (SSD), card-type memory (such as, multimedia card or micro card (for example, secure digital (SD) or extreme digital (XD))), magnetic tape, floppy disk, magneto-optical data storage device, optical data storage device, hard disk, solid state disk and any other device configured to store instructions or software and any associated data, data files and data structures in a non-transitory manner and provide the instructions or software and any associated data, data files and data structures to one or more processors or computers so that one or more processors or computers can execute the instructions. In one example, the instructions or software and any associated data, data files and data structures are distributed on a networked computer system so that the instructions and software and any associated data, data files and data structures are stored, accessed and executed by one or more processors or computers in a distributed manner.

[0149] Although the present disclosure includes specific examples, it will be clear after understanding the disclosure of the present application that various changes in form and detail may be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein should be considered to be descriptive only and not for limiting purposes. The description of the features or aspects in each example should be considered to be applicable to similar features or similar aspects in other examples. If the described techniques are performed in a different order and / or if the components in the described systems, architectures, devices, or circuits are combined in different ways and / or replaced or supplemented by other components or their equivalents, suitable results may be achieved.

[0150] Therefore, the scope of the disclosure may be defined by the claims and their equivalents in addition to the above disclosure, and all variations within the scope of the claims and their equivalents should be construed as being included in the disclosure.

Claims

1. A non-volatile memory device, comprising: A memory array includes N+1 resistive memory cells representing a bit sequence of N bits for each word line, wherein N is an integer greater than or equal to 2.

2. The nonvolatile memory device according to claim 1, wherein: When the bit value of the bit position in the bit sequence is the first bit value, the resistance values ​​of adjacent resistive memory cells corresponding to the bit position among the N+1 resistive memory cells are the same, and When the bit value of the bit position in the bit sequence is the second bit value, the resistance values ​​of adjacent resistive memory cells corresponding to the bit position among the N+1 resistive memory cells are different.

3. The nonvolatile memory device of claim 1 , further comprising: A write encoder is configured to generate N+1 write signals based on a reference signal and N bit signals respectively indicating bit values ​​of a bit sequence, the N+1 write signals respectively indicating resistance values ​​to be set for the N+1 resistive memory cells.

4. The nonvolatile memory device according to claim 3, wherein: The write encoder includes a plurality of XOR elements, wherein an output of at least one XOR element of the plurality of XOR elements is connected to an input of another XOR element of the plurality of XOR elements.

5. The nonvolatile memory device according to claim 3, wherein: The write encoder is configured to generate the N+1 write signals including outputs of a plurality of XOR elements and a reference signal.

6. The nonvolatile memory device according to claim 3, wherein: Write encoders include: a first XOR element configured to receive a bit signal corresponding to a most significant bit of the bit sequence and a reference signal, and generate a first XOR result between a bit value of the most significant bit and a bit value of the reference signal; and The second XOR element is configured to receive the bit signal corresponding to the bit subsequent to the most significant bit and the first XOR result, and generate a second XOR result between the bit value of the bit signal corresponding to the subsequent bit and the first XOR result.

7. The nonvolatile memory device according to claim 1, wherein: Resistance values ​​according to a result of encoding a bit sequence based on an exclusive OR are set for N+1 resistive memory cells arranged along a word line selected for writing.

8. The nonvolatile memory device according to claim 1, wherein: The nonvolatile memory device also includes a write driver configured to set one resistance value combination among available resistance value combinations representing a bit sequence for N+1 resistive memory cells of a word line selected for writing.

9. The nonvolatile memory device according to claim 8, wherein: A resistance value combination for writing with predicted low power consumption is selected from among the available resistance value combinations.

10. The nonvolatile memory device according to claim 8, wherein: A resistance value combination whose number of memory cells whose resistance needs to be changed among the N+1 resistive memory cells of the word line for writing is small is selected from among available resistance value combinations based on the resistance values ​​set for the N+1 resistive memory cells of the word line selected for writing.

11. The nonvolatile memory device according to claim 8, wherein: The write driver is configured as: changing the resistance value of a resistive memory cell including a resistance value different from the resistance value combination selected from among the N+1 resistive memory cells of the word line selected for writing, and The resistance value of the resistive memory cell including the same resistance value as the resistance value combination selected from among the N+1 resistive memory cells of the word line selected for writing is maintained.

12. The nonvolatile memory device of claim 1, further comprising: The readout circuit is configured to generate a bit read signal based on an exclusive OR result of resistance values ​​set for N+1 resistive memory cells arranged along a word line selected for reading.

13. The nonvolatile memory device according to claim 12, wherein: The sensing circuit includes an XOR element connected to two adjacent resistive memory cells among N+1 resistive memory cells arranged along a word line selected for reading.

14. The nonvolatile memory device according to claim 12, wherein: The readout circuit is configured as: A comparison result between delays occurring in the two adjacent resistive memory cells is output as bit values ​​of the two adjacent resistive memory cells according to the parasitic capacitance value and the resistance value set for the two adjacent resistive memory cells.

15. An operating method of a non-volatile memory device, the operating method comprising: Setting resistance values ​​representing a bit sequence of N bits for N+1 resistive memory cells arranged along a word line selected for writing in a memory array; as well as N-bit read signals are output from N+1 resistive memory cells arranged along a word line selected for reading in a memory array, where N is an integer greater than or equal to 2.

16. The operating method according to claim 15, wherein: The steps to set the resistance value are: When the bit value of the bit position in the bit sequence is the first bit value, setting the same resistance value for adjacent resistive memory cells corresponding to the bit position; and When the bit value of the bit position is the second bit value, different resistance values ​​are set for adjacent resistive memory cells corresponding to the bit position.

17. The operating method according to claim 15, wherein: The steps to set the resistance value are: generating, by a write encoder, N+1 write signals based on a reference signal and N bit signals indicating bit values ​​of a bit sequence, the N+1 write signals respectively indicating resistance values ​​to be set for N+1 resistive memory cells arranged along a word line selected for writing; and The resistance values ​​of the N+1 resistive memory cells arranged along the word line selected for writing are set by using the N+1 write signals through the write driver.

18. The operating method according to claim 15, wherein: The steps to set the resistance value are: One resistance value combination among available resistance value combinations representing a bit sequence is written into N+1 resistive memory cells of a word line selected for writing.

19. The operating method according to claim 18, wherein: The steps to set the resistance value also include: A resistance value combination with low predicted power consumption for writing is selected from among the available resistance value combinations.

20. The operating method according to any one of claims 15 to 19, wherein: The output steps include: The N-bit read signals are generated based on an exclusive OR result of resistance values ​​set for N+1 resistive memory cells arranged along a word line selected for reading.

21. A method of encoding a bit value by using two resistive memory cells adjacent to each other, the method comprising: When the bit value is a first value, setting a same resistance value for the two resistive memory cells; and, When the bit value is a second value different from the first value, different resistance values ​​are set for the two resistive memory cells.

22. The method of claim 21, wherein: The encoding is an XOR, where the first value is 0 and the second value is 1.

23. The method of claim 21, wherein: The encoding is XOR, where the first value is 1 and the second value is 0.

24. The method of claim 21, further comprising: N bit values ​​are encoded by using N+1 resistive memory cells.

25. The method of claim 24, wherein: N+1 resistive memory cells are connected to a shared word line, where N is an integer greater than or equal to 2.

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