Voltage configuration method of memory array

Abstract

The invention provides a voltage configuration method of a storage array, which can be applied to the technical field of circuits. The method comprises the steps that under the condition that the storage array responds to read operation, the write word line and the write bit line are configured to be first voltage, so that a write transistor is in a turn-off state; configuring the read bit line to be a second voltage, wherein the second voltage is greater than the first voltage; determining a selected state of a read word line of the storage array, wherein the selected state represents whether a storage unit associated with the read word line executes a read operation or not; and according to the selected state and the second voltage, performing voltage configuration on the read word line so as to control the conduction state of the read transistor.

Description

Technical Field

[0001] The present disclosure relates to the field of circuit technology, and more specifically to a voltage configuration method for a storage array. Background Art

[0002] Embedded dynamic random access memory (eDRAM) is a design that integrates DRAM into a system chip. Typically, each eDRAM cell consists of a capacitor and a transistor and has a high storage density.

[0003] In the traditional 2T1C read scheme, VDD is applied to the read word line of the selected row and VSS is applied to the read bit line, while VSS is applied to the unselected row. At this time, the read transistor of the 2T1C unit storing "1" in the unselected row is in the open state, resulting in an additional leakage path. A large current will appear on the read bit line of the 2T1C unit storing "0" in the selected row, resulting in additional power consumption and read errors. Summary of the invention

[0004] In view of the above problems, the present disclosure provides a voltage configuration method for a memory array.

[0005] According to a first aspect of the present disclosure, a voltage configuration method for a storage array is provided, wherein the storage array comprises a plurality of storage cells, each storage cell comprises a write transistor, a storage node and a read transistor, wherein a first end of the write transistor is connected to a write bit line, a second end of the write transistor is connected to a write word line, a first end of the storage node is connected to a third end of the write transistor, a second end of the storage node is grounded, a first end of the read transistor is connected to a read word line, a second end is connected to a third end of the storage node, and the third end of the read transistor is connected to a read bit line, and the method comprises: in a case where the storage array responds to a read operation, configuring the write word line and the write bit line to a first voltage so that the write transistor is in an off state; configuring the read bit line to a second voltage, the second voltage being greater than the first voltage; determining a selected state of a read word line of the storage array, the selected state representing whether a storage cell associated with the read word line performs a read operation; and performing voltage configuration on the read word line according to the selected state and the second voltage to control the on state of the read transistor.

[0006] According to an embodiment of the present disclosure, a read word line is voltage configured according to a selected state and a second voltage, including: when the selected state represents that a storage unit associated with the read word line does not perform a read operation, the read word line is configured to a third voltage to put the read transistor in an off state, wherein the third voltage is the same as the second voltage.

[0007] According to an embodiment of the present disclosure, when the selected state indicates that the memory cell associated with the read word line performs a read operation, the read word line is configured to a fourth voltage to turn on the read transistor, wherein the second voltage is greater than the fourth voltage.

[0008] According to an embodiment of the present disclosure, the method also includes: when the storage array responds to a write operation, configuring the read word line and the read bit line to a second voltage, configuring the write word line to a fifth voltage, the fifth voltage being greater than the second voltage, so that the read transistor is in an off state and the write transistor is in an on state; determining the type of write data, the type of write data characterizing the direction of charge flow between the write bit line and the storage node in the storage cell associated with the write bit line; and performing voltage configuration on the write bit line according to the type of write data.

[0009] According to an embodiment of the present disclosure, voltage configuration is performed on the write bit line according to the type of write data, including: when the type of write data indicates that charge flows from the write bit line to the storage node, configuring the write bit line to a second voltage.

[0010] According to an embodiment of the present disclosure, when the type of written data indicates that charges flow from the write bit line to the storage node, the charges are stored from the write bit line to the storage node, so that the voltage value of the storage node increases.

[0011] According to an embodiment of the present disclosure, the write bit line is voltage configured according to the type of write data, and further includes: when the type of write data represents that charge flows from a storage node to the write bit line, the write bit line is configured to a sixth voltage, wherein the sixth voltage is less than the second voltage.

[0012] According to an embodiment of the present disclosure, when the type of written data represents that charges flow from a storage node to a write bit line, the charges are released from the storage node to the write bit line, so that the voltage value of the storage node decreases.

[0013] According to an embodiment of the present disclosure, the write word line is configured to be at a fifth voltage to increase the data retention time of the memory array.

[0014] According to an embodiment of the present disclosure, both the write transistor and the read transistor are complementary metal oxide semiconductor transistors or indium gallium zinc oxide thin film transistors.

[0015] According to an embodiment of the present disclosure, when the memory array responds to a read operation, the write word line and the write bit line are configured to a first voltage so that the write transistor is in an off state; the read bit line is configured to a second voltage, the second voltage being greater than the first voltage; the selected state of the read word line of the memory array is determined, the selected state representing whether the memory cell associated with the read word line performs a read operation; and the read word line is voltage-configured according to the selected state and the second voltage to control the on state of the read transistor. Since the voltage configuration of the read word line is determined by judging whether the memory cell associated with the read word line performs a read operation to control the on state of the read transistor, leakage caused by the read transistor being always in an on state is avoided, and the leakage path when the memory array is read out is eliminated, thereby reducing the read power consumption and the read error. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above contents and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0017] Figure 1 A schematic diagram of a storage array according to an embodiment of the present disclosure is schematically shown;

[0018] Figure 2 A flowchart of a voltage configuration method for a storage array according to an embodiment of the present disclosure is schematically shown;

[0019] Figure 3 A schematic diagram of a storage array under a read operation according to an embodiment of the present disclosure is schematically shown;

[0020] Figure 4 The flowchart schematically shows a method for configuring voltage of a storage array during a write operation according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In the following detailed description, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0022] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise", "include", etc. used herein indicate the existence of the features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

[0023] All terms (including technical and scientific terms) used herein have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0024] When using expressions such as "at least one of A, B, and C, etc.", they should generally be interpreted according to the meaning of the expression commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0025] An embodiment of the present disclosure provides a voltage configuration method for a storage array. When the storage array responds to a read operation, the write word line and the write bit line are configured to a first voltage so that the write transistor is in an off state; the read bit line is configured to a second voltage, and the second voltage is greater than the first voltage; the selected state of the read word line of the storage array is determined, and the selected state indicates whether the storage unit associated with the read word line performs a read operation; and the read word line is voltage configured according to the selected state and the second voltage to control the conduction state of the read transistor.

[0026] Figure 1 A schematic diagram of a storage array according to an embodiment of the present disclosure is schematically shown; Figure 2 The flowchart of the voltage configuration method of the memory array according to the embodiment of the present disclosure is schematically shown.

[0027] According to a first aspect of the present disclosure, a voltage configuration method for a storage array is provided. Figure 1 As shown, the above-mentioned storage array includes multiple storage cells, each storage cell includes a write transistor N1, a storage node SN and a read transistor N2, the first end of the write transistor N1 is connected to the write bit line, the second end of the write transistor N1 is connected to the write word line, the first end of the storage node SN is connected to the third end of the write transistor N1, the second end of the storage node SN is grounded, the first end of the read transistor N2 is connected to the read word line, the second end is connected to the third end of the storage node SN, and the third end of the read transistor N2 is connected to the read bit line.

[0028] like Figure 2 As shown, the voltage configuration method of the memory array includes operations S210 to S240.

[0029] In operation S210, in case that the memory array responds to a read operation, a write word line and a write bit line are configured to a first voltage so that the write transistor is in an off state.

[0030] In operation S220, the read bit line is configured to be a second voltage, the second voltage being greater than the first voltage;

[0031] In operation S230 , a selected state of a read word line of the memory array is determined, the selected state indicating whether a memory cell associated with the read word line performs a read operation.

[0032] In operation S240 , a voltage configuration is performed on the read word line according to the selected state and the second voltage to control a conduction state of the read transistor.

[0033] According to an embodiment of the present disclosure, the memory array may be a 2T1C eDRAM array or a 2T0C eDRAM memory array.

[0034] According to an embodiment of the present disclosure, the write transistor N1 and the read transistor N2 may each be a transistor used in a dynamic random access memory (DRAM) and a static random access memory (SRAM).

[0035] According to an embodiment of the present disclosure, the storage node SN may be a capacitor for storing written data.

[0036] According to an embodiment of the present disclosure, a write bit line (WBL) is a conductive line in an SRAM storage array for writing data, and is used to store and transfer data bits.

[0037] According to an embodiment of the present disclosure, a write word line (WWL) is a control signal line for selecting a specific row in an SRAM storage array. When the write word line is set to a high level, a write transistor N1 connected to the write word line will be turned on.

[0038] According to an embodiment of the present disclosure, a read bit line (RBL) is a conductive line in an SRAM storage array for reading data, and is used to store and transfer data bits.

[0039] According to an embodiment of the present disclosure, a read word line (RWL) is a control signal line for selecting a specific row in an SRAM storage array. When the read word line is set to a high level, a read transistor N2 connected to the read word line will be turned on.

[0040] According to an embodiment of the present disclosure, the read operation is used to implement data reading by turning on the read transistor N2 .

[0041] According to an embodiment of the present disclosure, the first voltage may be a low voltage VSS, which generally refers to a negative ground or a zero potential point of a circuit, ie, the write word line and the write bit line are configured to 0V.

[0042] According to an embodiment of the present disclosure, the second voltage may be a high voltage VDD, and may be configured according to actual requirements, for example, the read bit line may be configured to 0.9V.

[0043] According to an embodiment of the present disclosure, when the memory array responds to a read operation, WWL and WBL are set to VSS, and RBL is set to VDD, wherein the write transistor N1 is turned off due to WWL being VSS, to avoid a read error caused by the operation of the write transistor N1 during the read operation.

[0044] According to an embodiment of the present disclosure, since a plurality of groups of storage cells of "write transistor N1-storage node SN-read transistor N2" are provided on the storage array, in the case of a read operation, the data on the storage cells of the selected row can be read by controlling the selected state of RWL.

[0045] According to an embodiment of the present disclosure, the conduction state of the read transistor N2 is controlled according to the voltage difference between the voltage value of the read word line in the memory cell corresponding to the selected state and the second voltage.

[0046] According to an embodiment of the present disclosure, when the memory array responds to a read operation, the write word line and the write bit line are configured to a first voltage so that the write transistor is in an off state; the read bit line is configured to a second voltage, the second voltage being greater than the first voltage; the selected state of the read word line of the memory array is determined, the selected state representing whether the memory cell associated with the read word line performs a read operation; and the read word line is voltage-configured according to the selected state and the second voltage to control the on state of the read transistor. Since the voltage configuration of the read word line is determined by judging whether the memory cell associated with the read word line performs a read operation to control the on state of the read transistor, leakage caused by the read transistor being always in an on state is avoided, and the leakage path when the memory array is read out is eliminated, thereby reducing the read power consumption and the read error.

[0047] According to an embodiment of the present disclosure, voltage configuration is performed on a read word line according to a selected state and a second voltage, including:

[0048] When the selected state indicates that the memory cell associated with the read word line does not perform a read operation, the read word line is configured to a third voltage to turn off the read transistor, wherein the third voltage is the same as the second voltage.

[0049] According to an embodiment of the present disclosure, when the RWL selection state is unselected, that is, the storage unit associated with the read word line does not perform a read operation, RWL is configured to a third voltage VDD (for example, 0.9V) that is the same as the second voltage. At this time, since RWL and RBL are both high voltages and have the same voltage value, there is no voltage difference between the first end and the third end of the read transistor, so that no current flows in the read transistor, and the read transistor is in an off state, and no current flows.

[0050] According to an embodiment of the present disclosure, when the selected state indicates that the memory cell associated with the read word line performs a read operation, the read word line is configured to a fourth voltage to turn on the read transistor, wherein the second voltage is greater than the fourth voltage.

[0051] According to an embodiment of the present disclosure, when the RWL selection state is selected, that is, the memory cell associated with the read word line performs a read operation, RWL is configured to a fourth voltage VSS (0V). At this time, RWL is a low voltage, RBL is a high voltage, there is a voltage difference between the first terminal and the third terminal of the read transistor, and current flows from RBL to RWL through the read transistor, that is, the read transistor is in an on state.

[0052] Figure 3 A schematic diagram of a storage array during a read operation according to an embodiment of the present disclosure is schematically shown.

[0053] According to the embodiments of the present disclosure, Figure 3 As shown, when the unselected row RWL is configured to VDD and RBL is configured to VDD, the read transistor N2 of the memory cell corresponding to the unselected row is in the off state regardless of whether the storage node SN is "1" or "0", thereby eliminating unnecessary leakage paths, thereby reducing read power consumption and read errors.

[0054] Figure 4 The flowchart schematically shows a method for configuring voltage of a storage array during a write operation according to an embodiment of the present disclosure.

[0055] According to the embodiments of the present disclosure, Figure 4 As shown, the above method also includes operations S410~S430.

[0056] In operation S410, when the memory array responds to a write operation, the read word line and the read bit line are configured to a second voltage, and the write word line is configured to a fifth voltage, which is greater than the second voltage, so that the read transistor is in an off state and the write transistor is in an on state.

[0057] In operation S420 , a type of write data is determined, the type of write data representing a flow direction of charges between a write bit line and a storage node in a memory cell associated with the write bit line.

[0058] In operation S430 , voltage configuration is performed on the write bit line according to the type of write data.

[0059] According to an embodiment of the present disclosure, the write operation is used to write data to the storage node by turning on the write transistor.

[0060] According to an embodiment of the present disclosure, the fifth voltage may be VDDH, which has a higher voltage value than the second voltage VDD, for example, may be configured as 1.1V.

[0061] According to an embodiment of the present disclosure, the types of write operations include "1" and "0", where "1" means that the storage node stores high voltage data, and "0" means that the storage node stores low voltage data.

[0062] According to an embodiment of the present disclosure, for data of different levels, the WBL needs to adaptively adjust the configured voltage value to implement writing of write data of different voltages.

[0063] According to an embodiment of the present disclosure, voltage configuration is performed on the write bit line according to the type of write data, including: when the type of write data indicates that charge flows from the write bit line to the storage node, configuring the write bit line to a second voltage.

[0064] According to an embodiment of the present disclosure, when the type of written data indicates that charges flow from the write bit line to the storage node, the charges are stored from the write bit line to the storage node, so that the voltage value of the storage node increases.

[0065] According to an embodiment of the present disclosure, when the type of written data characterizes that the storage node stores charge, that is, the charge flows from the write bit line to the storage node, WBL is configured to be a high voltage VDD. At this time, since WBL is a high voltage and the storage node is grounded, the charge flows from WBL to the storage node, so that the voltage value of the storage node increases.

[0066] According to an embodiment of the present disclosure, voltage configuration is performed on the write bit line according to the type of write data, further comprising:

[0067] In the case where the type of the written data represents that the charge flows from the storage node to the write bit line, the write bit line is configured to a sixth voltage, wherein the sixth voltage is less than the second voltage.

[0068] According to an embodiment of the present disclosure, when the type of written data represents that charges flow from a storage node to a write bit line, the charges are released from the storage node to the write bit line, so that the voltage value of the storage node decreases.

[0069] According to an embodiment of the present disclosure, when the type of written data characterizes the release of charge from the storage node, that is, the charge flows from the storage node to the write bit line, WBL is configured to be a low voltage VSS (sixth voltage). At this time, since WBL is a low voltage and the storage node is a high voltage, the charge is released from the storage node to the write bit line, so that the voltage value of the storage node is reduced.

[0070] According to an embodiment of the present disclosure, the write word line is configured to be at a fifth voltage to increase the data retention time of the memory array.

[0071] According to the embodiments of the present disclosure, the write word line is configured as the fifth voltage VDDH to increase the voltage written to the storage node to increase the retention time of the stored data, so that the circuit can keep the stored data for a long time without losing it.

[0072] According to an embodiment of the present disclosure, both the write transistor and the read transistor are complementary metal oxide semiconductor transistors or indium gallium zinc oxide thin film transistors.

[0073] According to the embodiments of the present disclosure, the method of the present disclosure is not limited to the 2T1C memory array, but is also applicable to the 2T0C memory array; wherein the read transistors and write transistors in the memory cells of 2T0C and 2T1C are not limited to CMOS transistors (complementary metal oxide semiconductor transistors), but can also be applied to IGZO transistors (indium gallium zinc oxide thin film transistors), which can be selected according to actual needs.

[0074] According to the embodiments of the present disclosure, an integrated circuit chip including the storage array of the present disclosure can be obtained through front-end design, back-end design, and wafer manufacturing of digital circuits and analog circuits, wherein the process adopts a 28nm process.

[0075] According to the embodiment of the present disclosure, in actual chip testing, when performing a write operation, the WWL voltage is set to 1.1V, and the WBL voltage is set to 0.9 or 0V according to the type of written data; when performing a read operation, the RWL voltage of the selected row is set to 0V, the RBL voltage is set to 0.9V, and the RWL voltage of the unselected row is set to 0.9V. Compared with the traditional 2T1C array current read voltage configuration scheme, the example of the present disclosure reduces the read power consumption by 1.49 times and increases the read margin by 1.67 times, thereby reducing the read error.

[0076] It will be appreciated by those skilled in the art that the features described in the various embodiments of the present disclosure may be combined and / or combined in a variety of ways, even if such combinations or combinations are not explicitly described in the present disclosure. In particular, without departing from the spirit and teachings of the present disclosure, the features described in the various embodiments of the present disclosure may be combined and / or combined in a variety of ways. All of these combinations and / or combinations fall within the scope of the present disclosure.

[0077] The embodiments of the present disclosure are described above. However, these embodiments are only for illustrative purposes and are not intended to limit the scope of the present disclosure. Although the embodiments are described above, this does not mean that the measures in the various embodiments cannot be used in combination to advantage. Without departing from the scope of the present disclosure, those skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A voltage configuration method for a storage array, characterized in that: The memory array comprises a plurality of memory cells, each of the memory cells comprises a write transistor, a storage node and a read transistor, a first end of the write transistor is connected to a write bit line, a second end of the write transistor is connected to a write word line, a first end of the storage node is connected to a third end of the write transistor, a second end of the storage node is grounded, a first end of the read transistor is connected to a read word line, a second end is connected to a third end of the storage node, and a third end of the read transistor is connected to a read bit line, the method comprises: When the memory array responds to a read operation, the write word line and the write bit line are configured to a first voltage so that the write transistor is in an off state; configuring the read bit line to a second voltage, the second voltage being greater than the first voltage; Determining a selected state of the read word line of the memory array, the selected state indicating whether the memory cell associated with the read word line performs the read operation; The read word line is voltage-configured according to the selected state and the second voltage to control the conduction state of the read transistor.

2. The method according to claim 1, characterized in that The step of configuring the voltage of the read word line according to the selected state and the second voltage includes: When the selected state indicates that the memory cell associated with the read word line does not perform the read operation, the read word line is configured to a third voltage to turn off the read transistor, wherein the third voltage is the same as the second voltage.

3. The method according to claim 1, characterized in that The step of configuring the voltage of the read word line according to the selected state and the second voltage further includes: When the selected state indicates that the memory cell associated with the read word line performs the read operation, the read word line is configured to a fourth voltage to turn on the read transistor, wherein the second voltage is greater than the fourth voltage.

4. The method according to claim 1, characterized in that The method further comprises: When the memory array responds to a write operation, the read word line and the read bit line are configured to the second voltage, and the write word line is configured to a fifth voltage, wherein the fifth voltage is greater than the second voltage, so that the read transistor is in an off state and the write transistor is in an on state; determining a type of write data, wherein the type of write data represents a direction of charge flow between the write bit line and the storage node in the storage cell associated with the write bit line; The write bit line is voltage-configured according to the type of the write data.

5. The method according to claim 4, characterized in that The step of configuring the voltage of the write bit line according to the type of the write data comprises: When the type of the write data indicates that the charge flows from the write bit line to the storage node, the write bit line is configured to be the second voltage.

6. The method according to claim 5, characterized in that In the case where the type of the write data indicates that the charge flows from the write bit line to the storage node, the charge is stored from the write bit line to the storage node, so that the voltage value of the storage node increases.

7. The method according to claim 5, characterized in that The step of configuring the voltage of the write bit line according to the type of the write data further comprises: In a case where the type of the write data indicates that the charge flows from the storage node to the write bit line, the write bit line is configured to be a sixth voltage, wherein the sixth voltage is less than the second voltage.

8. The method according to claim 7, characterized in that In the case where the type of the write data indicates that the charge flows from the storage node to the write bit line, the charge is released from the storage node to the write bit line, so that the voltage value of the storage node decreases.

9. The method according to claim 4, characterized in that The write word line is configured as the fifth voltage to increase the data retention time of the memory array.

10. The method according to claim 1, characterized in that The write transistor and the read transistor are both complementary metal oxide semiconductor transistors or indium gallium zinc oxide thin film transistors.

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