Static random access memory, processing circuit chip and electronic equipment

Abstract

The invention discloses a static random access memory, a processing circuit chip and electronic equipment, a memory cell array is arranged on a first side of a substrate, a plurality of grooves extend into the substrate from the surface of a second side of the substrate along a third direction, the grooves are prevented from being limited by channels in the first direction, and the line width of the grooves in the first direction can be released. The power line is arranged on the second side of the substrate and connected with the power patch cord in the groove, and the connecting part is further connected with the power patch cord in the groove through the contact hole, so that power is supplied to the storage unit through the power line, the groove, the contact hole and the connecting part. By arranging the power line on the second side of the substrate, power is supplied to the memory unit in a back power supply network mode, the space of the layer where the word line or the bit line is located can be released, the width of the word line or the bit line can be increased without additionally increasing the layout area of the memory unit, the resistance of the word line or the bit line is reduced, and the memory efficiency is improved. And the overall performance of the static random access memory is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a static random access memory, a processing circuit chip and an electronic device. Background Art

[0002] Static random access memory (SRAM) is a memory device with static access function. It can save the data stored inside without refreshing the circuit. It is widely used in the design of digital and various electronic circuit products. Usually, SRAM includes an array composed of memory cells. The performance of the memory cell has a decisive influence on the performance of SRAM, so the performance of the memory cell becomes very important. Summary of the invention

[0003] The present application provides a static random access memory, a processing circuit chip and an electronic device for improving performance.

[0004] In a first aspect, the present application provides a static random access memory (SRAM), which includes a substrate, a plurality of memory cells, a plurality of trenches arranged at intervals, a power transfer line filled in each trench, a power supply line, and a first connection layer. The substrate has a first side and a second side along a third direction, and a plurality of memory cell arrays are arranged on the first side of the substrate. The plurality of trenches extend from the surface of the second side of the substrate into the substrate along the third direction, and the plurality of trenches extend along a second direction and are arranged along a first direction. The distance between the bottom of the trench and the surface of the substrate facing the memory cell side is greater than zero, so that the trench does not penetrate the substrate, which can avoid the limitation of the trench by the channel in the first direction and can release the line width of the trench in the first direction. The power supply line is arranged on the second side of the substrate, and the power supply line is connected to the power transfer line in the trench. The first connection layer is arranged on the side of the memory cell facing away from the substrate, and the first connection layer includes a connection portion. The connection portion is connected to the memory cell, and the connection portion is also connected to the power transfer line in the trench through a contact hole that communicates with the trench, so as to arrange the power transfer line between the power supply line and the connection portion. With this arrangement, power is supplied to the memory cell through the power supply line, the trench, the contact hole, and the connection portion. Moreover, by arranging the power supply line on the second side of the substrate, that is, transferring the power supply line to the back of the substrate, power is supplied to the memory cell in the form of a Backside Power Delivery Network (BSPDN). In addition, in the static random access memory of the prior art, the power supply line is usually arranged on the side of the substrate facing the memory cell (i.e., the front of the substrate), which limits the line width of the word line or the bit line, resulting in a series of problems caused by RC delay in the word line or the bit line. Therefore, for the static random access memory provided by the embodiments of the present application, by arranging the power supply line on the back of the substrate, not only can the space of the layer where the word line or the bit line is located be released, but also the layout area of the memory cell does not need to be increased additionally, and the width of the word line or the bit line can be increased, the resistance of the word line or the bit line can be reduced, thereby improving a series of problems caused by RC delay in the word line or the bit line during the read and write operations, and improving the overall performance of the static random access memory.

[0005] In addition, the third direction is perpendicular to the plane of the substrate, and the first direction and the second direction are parallel to the plane of the substrate and intersect with each other. For example, the first direction and the second direction are perpendicular to each other.

[0006] Generally, it is necessary to input a first power supply voltage to the storage unit. To this end, the storage unit has a first side and a second side along a first direction, and the plurality of grooves include a first groove and a second groove. The first groove is provided on the first side of the storage unit, and the second groove is provided on the second side of the storage unit. In addition, the power line includes a first power line for transmitting the first power supply voltage, and the first power line is connected to the power adapter wires in the first groove and the second groove, respectively. In addition, the storage unit has a first pull-down tube and a second pull-down tube, and the connecting portion includes a first connecting portion and a second connecting portion. The first connecting portion is connected to the first pole of the first pull-down tube, and the first connecting portion is also connected to the power adapter wire in the first groove through a first contact hole that interpenetrates with the first groove, and the second connecting portion is connected to the first pole of the second pull-down tube, and the second connecting portion is also connected to the power adapter wire in the second groove through a second contact hole that interpenetrates with the second groove. In this way, the first pole of the first pull-down tube and the first pole of the second pull-down tube can be electrically connected to the first power line, respectively, so as to input the first power supply voltage to the first pole of the first pull-down tube and the first pole of the second pull-down tube.

[0007] Through the above-mentioned settings, the static random access memory provided by the embodiment of the present application transfers the first power line to the back of the substrate, and realizes the structure of inputting the first power supply voltage to the storage unit in the BSPDN manner. In addition, in the static random access memory of the prior art, the first power line is usually arranged on the side of the substrate facing the storage unit (i.e., the front of the substrate) and the first power line is arranged on the same layer as the word line, thereby limiting the line width of the word line, resulting in the problem of a slow rise rate of the high-level voltage of the word line due to RC delay (delay). To this end, in the static random access memory provided by the embodiment of the present application, by transferring the first power line 371 to the back of the substrate, not only can the space of the layer where the word line is located be released, but also the width of the word line can be increased without additionally increasing the layout area of ​​the storage unit, thereby reducing the resistance of the word line, and improving the problem of a slow rise rate of the high-level voltage of the word line due to RC delay, thereby increasing the rise rate of the high-level voltage of the word line.

[0008] In a specific implementation, the static random access memory also includes a second interconnection layer arranged on the side of the first connection layer facing away from the substrate, and the second interconnection layer includes a plurality of word lines arranged at intervals from each other, and the plurality of word lines are extended along the first direction and arranged along the second direction. The storage unit also includes a first selection tube and a second selection tube, and the gate of the first selection tube and the gate of the second selection tube are respectively connected to the word line. Moreover, when the first power line and the word line are arranged in the same layer, the width of the word line in the second direction is used as the first set width. In the present application, by removing the first power line from the layer where the word line is located, the space originally occupied by the first power line can be released, so that the width of each word line in the second direction can be increased by 20% to 40% on the basis of the first set width, thereby increasing the width of the word line and reducing the resistance of the word line, and improving the problem of the slow rise rate of the high-level voltage of the word line caused by RC delay, thereby increasing the rise rate of the high-level voltage of the word line.

[0009] Generally, it is necessary to input a second power supply voltage to the storage unit. For this purpose, the power line includes a second power supply line for transmitting the second power supply voltage, the plurality of grooves include a third groove, the storage unit includes a first pull-up tube and a second pull-up tube, and the third groove is arranged between the first pull-up tube and the second pull-up tube in the storage unit, and the power adapter line in the third groove is connected to the second power supply line. Also, the connection part includes a third connection part and a fourth connection part, the third connection part is connected to the first pole of the first pull-up tube, the third connection part is also connected to the power adapter line in the third groove through a third contact hole that interpenetrates with the third groove, the fourth connection part is connected to the first pole of the second pull-up tube, and the fourth connection part is also connected to the power adapter line in the third groove through a fourth contact hole that interpenetrates with the third groove. With this arrangement, the first pole of the first pull-up tube and the first pole of the second pull-up tube can be electrically connected to the second power supply line respectively, so as to input the second power supply voltage to the first pole of the first pull-up tube and the first pole of the second pull-up tube.

[0010] Through the above-mentioned setting, the static random access memory provided by the embodiment of the present application transfers the second power line to the back of the substrate, and realizes the structure of inputting the second power supply voltage to the storage unit in the BSPDN mode. In addition, in the static random access memory of the prior art, the second power line is usually arranged on the side of the substrate facing the storage unit (i.e., the front of the substrate) and the second power line is arranged on the same layer as the bit line, thereby limiting the line width of the bit line, resulting in the problem of slow discharge rate of the bit line due to RC delay (delay). To this end, in the static random access memory provided by the embodiment of the present application, by transferring the second power line to the back of the substrate, not only can the space of the layer where the bit line is located be released, but also the layout area of ​​the storage unit can be increased without additionally increasing the layout area of ​​the storage unit, thereby reducing the resistance of the bit line, and improving the problem of slow discharge rate of the bit line caused by RC delay during read and write operations, thereby increasing the discharge rate of the bit line and improving the overall performance of the static random access memory.

[0011] In a specific implementation, the static random access memory also includes a first interconnection layer arranged on the side of the first connection layer facing away from the substrate, the first interconnection layer includes a plurality of bit lines arranged at intervals from each other, and the plurality of bit lines are extended along the second direction and arranged along the first direction. In addition, the storage unit also includes a first selection tube and a second selection tube, the plurality of bit lines include a first bit line and a second bit line, the first pole of the first selection tube is connected to the first bit line, and the first pole of the second selection tube is connected to the second bit line. Also, when the second power line and the bit line are arranged in the same layer, the width of the bit line in the first direction is used as the second set width. In the present application, by removing the second power line from the layer where the bit line is located, the space originally occupied by the second power line can be released, so that the width of each bit line in the first direction can be increased by 20% to 40% on the basis of the second set width, thereby increasing the width of the bit line and reducing the resistance of the bit line, and improving the problem of slow discharge rate of the bit line caused by RC delay, thereby increasing the discharge rate of the bit line.

[0012] In some embodiments, the second power line and the first power line are insulated from each other. For example, if the second power line and the first power line are arranged in different layers, an insulating layer is also arranged between the second power line and the first power line. The first power line is arranged between the second power line and the substrate, or the second power line is arranged between the first power line and the substrate. Of course, the second power line and the first power line can also be arranged in the same layer.

[0013] Exemplarily, the shape of the first power line is set to be a strip structure or a grid structure.

[0014] Exemplarily, the second power line is configured to be in a strip structure or a grid structure.

[0015] In some embodiments, the distance between the trench and the surface of the substrate facing the memory cell is 40 nm to 60 nm.

[0016] In some embodiments, the storage unit is set as a 6T Cell, that is, the storage unit includes: a first pull-up tube, a second pull-up tube, a first pull-down tube, a second pull-down tube, a first gate tube and a second gate tube, and the first pull-down tube, the first pull-up tube, the second pull-up tube and the second pull-down tube are arranged in sequence along the first direction, the first gate tube and the first pull-down tube are arranged in a straight line along the second direction, and the second gate tube and the second pull-down tube are arranged in another straight line along the second direction.

[0017] Since the fin field-effect transistor (Fin Field-Effect Transistor, Fin FET) has the advantages of strong current control capability, reduced leakage current and increased switching speed, based on this, the first pull-up tube, the second pull-up tube, the first pull-down tube, the second pull-down tube, the first gating tube and the second gating tube can be respectively set as Fin FETs. Exemplarily, the fin channel of the first pull-up tube, the fin channel of the second pull-up tube, the fin channel of the first pull-down tube, the fin channel of the second pull-down tube, the fin channel of the first gating tube and the fin channel of the second gating tube extend along the second direction respectively.

[0018] In order to reduce the complexity of the fin channel patterning, in the same memory cell, the fin channel of the first gate tube and the fin channel of the first pull-down tube are arranged as an integrated structure.

[0019] In order to reduce the complexity of the fin channel patterning, in the same memory cell, the fin channel of the second gate tube and the fin channel of the second pull-down tube are set as an integrated structure.

[0020] In some embodiments, the plurality of storage cells in the present application include a plurality of first storage cell groups and a plurality of second storage cell groups, wherein the first storage cell groups are arranged along a first direction F1, and each first storage cell group includes a plurality of storage cells arranged along a second direction. Furthermore, the second storage cell groups are arranged along the second direction, and each second storage cell group includes a plurality of storage cells arranged along the first direction. Exemplarily, adjacent first storage cell groups may be arranged in mirror symmetry, or two adjacent second storage cell groups may be arranged in mirror symmetry.

[0021] Exemplarily, the fin-type channels of the first pull-down tubes adjacent to each other along the second direction are set as an integrated structure, and the fin-type channels of the first gate tubes adjacent to each other along the second direction are also set as an integrated structure. Thus, the fin-type channels of the first pull-down tubes and the fin-type channels of the first gate tubes in the plurality of storage cells arranged along the second direction are respectively formed by the fin-type channels extending along the second direction, further reducing the complexity of the channel patterning.

[0022] Exemplarily, the fin-type channels of the second pull-down tubes adjacent to each other along the second direction are integrated into a one-piece structure, and the fin-type channels of the second selection tubes adjacent to each other along the second direction are also integrated into a one-piece structure. Thus, the fin-type channels extending along the second direction are used to form the fin-type channels of the second pull-down tubes and the fin-type channels of the second selection tubes in the plurality of storage cells arranged along the second direction, respectively, further reducing the complexity of the channel patterning.

[0023] Exemplarily, the fin-type channels of the first pull-up tubes adjacent to each other along the second direction are integrated into an integrated structure. Thus, the fin-type channels of the first pull-up tubes in the two storage cells are formed by using the fin-type channels extending along the second direction, further reducing the complexity of the channel patterning.

[0024] Exemplarily, the fin-type channels of the second pull-up tubes adjacent to each other along the second direction are also integrated into a structure. Thus, the fin-type channels of the second pull-up tubes in the two storage cells are formed by using the fin-type channels extending along the second direction, further reducing the complexity of the channel patterning.

[0025] In order to further improve the density of the storage unit, since two adjacent storage units arranged along the second direction are arranged in mirror symmetry, the first connection portions connecting two adjacent first pull-down tubes along the second direction can share the same first contact hole. With this arrangement, the number of first contact holes can be reduced, and the complexity of the layout design can be reduced. In addition, the first groove can be made to penetrate each first contact hole in the corresponding first storage unit group, so that the same first groove can be used to provide the first power supply voltage VSS for the first pull-down tube in the corresponding first storage unit.

[0026] In order to further improve the density of the storage unit, since two adjacent storage units arranged along the second direction are arranged in mirror symmetry, the second connection parts connecting two adjacent second pull-down tubes along the second direction can share the same second contact hole. With this arrangement, the number of second contact holes can be reduced, and the complexity of layout design can be reduced. In addition, the second groove can also penetrate each second contact hole in the corresponding first storage unit group, so that the same second groove can be used to provide the first power supply voltage for the second pull-down tube in the corresponding first storage unit.

[0027] In order to further improve the density of the storage unit, since two adjacent storage units arranged along the first direction are arranged in mirror symmetry, the first groove between the two adjacent storage units along the first direction can be set as the same groove. This arrangement can reduce the number of first grooves and reduce the complexity of layout design.

[0028] In order to further improve the density of the storage unit, since two adjacent storage units arranged along the first direction are arranged in mirror symmetry, the second grooves between the two adjacent storage units along the first direction can be set as the same groove. This arrangement can reduce the number of second grooves and reduce the complexity of layout design.

[0029] In order to further improve the density of the storage unit, the first connection portion connecting two first pull-down tubes adjacent to each other in the first direction can share the same first contact hole. With this arrangement, the number of first contact holes can be further reduced, and the complexity of the layout design can be reduced. In addition, a first groove can be used to penetrate each first contact hole in two adjacent first storage unit groups, so that the same first groove can be used to provide the first power supply voltage for the first pull-down tubes in two adjacent first storage units.

[0030] In order to further improve the density of the storage unit, the second connection parts connected to the second pull-down tubes adjacent to each other in the first direction can share the same second contact hole. With this arrangement, the number of second contact holes can be further reduced, and the complexity of the layout design can be reduced. In addition, a second groove can be used to penetrate each second contact hole in two adjacent first storage unit groups, so that the same second groove can be used to provide the first power supply voltage for the second pull-down tubes in two adjacent first storage units.

[0031] In order to further improve the density of the storage unit, since two adjacent storage units arranged along the second direction are arranged in mirror symmetry, the third connection parts connected to the two adjacent first pull-up tubes along the second direction can share the same third contact hole. With this arrangement, the number of third contact holes can be further reduced, and the complexity of the layout design can be reduced. In addition, a third groove can be used to penetrate each third contact hole in the corresponding first storage unit group, so that the same third groove can be used to provide the second power supply voltage for the first pull-up tube in the first storage unit.

[0032] In order to further improve the density of the storage unit, since two adjacent storage units arranged along the second direction are arranged in mirror symmetry, the fourth connection parts connected to the two adjacent second pull-up tubes along the second direction can share the same fourth contact hole. With this arrangement, the number of fourth contact holes can be further reduced, and the complexity of the layout design can be reduced. In addition, a third groove can be used to penetrate each fourth contact hole in the corresponding first storage unit group, so that the same third groove can be used to provide the second power supply voltage for the second pull-up tube in the first storage unit.

[0033] In order to further improve the density of the memory cell, a third trench may be interpenetrated with each third contact hole and each fourth contact hole in the corresponding first memory cell group, so that the same third trench can be used to provide a second power supply voltage for the first pull-up tube and the second pull-up tube in the first memory cell group.

[0034] In a second aspect, the present application further provides a processing circuit chip, which includes any static random access memory in the above-mentioned first aspect and one or more processing circuits, and the static random access memory is used to store data required for the operation of one or more processing circuits.

[0035] Since any of the above static random access memories has good performance, after the static random access memory is applied to a processing circuit chip, the performance of the processing circuit chip can also be improved.

[0036] In a third aspect, the present application further provides an electronic device, the electronic device comprising a bus and a processing circuit chip of the second aspect, the bus being connected to the processing circuit chip. The electronic device may be any electrical device, such as a terminal device, a communication device, and an electronic device. Among them, the terminal device includes but is not limited to mobile phones, computers, televisions, TV set-top boxes, watches, personal computers (PCs), wearable devices, workstations and other devices. Communication equipment includes but is not limited to wireless networks, fixed networks, servers, smart broadband, etc. Electronic devices include but are not limited to device modules, memories, digital logic circuits, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A structural block diagram of an electronic device provided in an embodiment of the present application;

[0038] Figure 2 A schematic diagram of the structure of an SRAM provided in an embodiment of the present application;

[0039] Figure 3 A circuit diagram of a storage unit of an SRAM provided in an embodiment of the present application;

[0040] Figure 4 A schematic diagram of a layout structure of an SRAM provided in an embodiment of the present application;

[0041] Figure 5a for Figure 4 Schematic diagram of the cross-sectional structure along the AA' tangent direction;

[0042] Figure 5b for Figure 4 Schematic diagram of the cross-sectional structure along the BB' tangent direction;

[0043] Figure 6 For Figure 4 Schematic diagram of the layout structure after adding word lines;

[0044] Figure 7 A schematic diagram of another layout structure of the SRAM provided in the embodiment of the present application;

[0045] Figure 8 A schematic diagram of simulation results of inputting a high-level voltage to a static random access memory provided by an embodiment of the present application when the word lines have different widths;

[0046] Fig. 9 A schematic diagram of simulation results of read and write operations of a static random access memory provided in an embodiment of the present application when the bit lines are at different widths.

[0047] Reference numerals

[0048] 100-electronic device; 110-processing circuit chip; 111-processor; 112-GPU; 113-first RAM; 120-second RAM; 130-communication chip; 140-power management chip; 150-bus; 0122-SRAM; 1021-row decoding circuit; 1~N-word line circuit; 1022-read and write drive circuit; 1023-column decoding circuit; 200 / 200a / 200b / 200c / 200d / 200e / 200f / 200g / 200h-storage unit; T1_S / T2_S / T3_S / T4_S / T5_S / T6_S-first pole; GT1-first groove; GT2-second groove; GT3-third groove; 300-substrate; 311 / 312 / 313-power adapter; 320-first connection layer; 321-first connection part; 322-second connection connection portion; 323-third connection portion; 324-fourth connection portion; 325-first bit line connection portion; 326-second bit line connection portion; 331-STI structure; 332-isolation medium; 333 / 334 / 381 / 382-insulating layer; 340-first interconnection layer; 350-second interconnection layer; 371-first power line; 372-second power line; S1-first side; S2-second side; Za_1 / Za_2-first storage cell group; Zb_1 / Zb_2 / Zb_3 / Zb_4-second storage cell group; F1-first direction; F2-second direction; F3-third direction; WL-word line; BL-first bit line BL; BLB-second bit line; CT1-first contact hole; CT2-second contact hole; CT3-third contact hole; CT4-fourth contact hole; BT1-first bit line connection hole; BT2-second bit line connection hole. DETAILED DESCRIPTION

[0049] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings. The specific operating methods in the method embodiments can also be applied to device embodiments or system embodiments. It should be noted that in the description of the present application, "multiple" can be understood as "at least two". In addition, it should be understood that in the description of the present application, words such as "first" and "second" are only used to distinguish the purpose of description, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order.

[0050] It should be noted that the same reference numerals in the drawings of this application represent the same or similar structures, and thus their repeated description will be omitted. The words expressing positions and directions described in this application are all explained using the drawings as examples, but they can be changed as needed, and the changes are included in the protection scope of this application. The drawings of this application are only used to illustrate the relative position relationship and do not represent the true proportion.

[0051] The SRAM provided in the embodiment of the present application can be applied to electronic devices having SRAM. Electronic devices include, for example, but are not limited to, terminal devices, communication devices, and electronic devices. Among them, terminal devices include, but are not limited to, mobile phones, computers, televisions, TV set-top boxes, watches, personal computers (PCs), wearable devices, workstations and other devices. Communication equipment includes, but is not limited to, wireless networks, fixed networks, servers, smart broadband, etc. Electronic devices include, but are not limited to, device modules, memories, digital logic circuits, etc., which are not listed one by one here. It is understandable that the specific implementation of SRAM can be determined according to the actual application scenario and is not limited here.

[0052] Figure 1 A structural block diagram of an electronic device provided in an embodiment of the present application, referring to Figure 1, the electronic device 100 includes: a bus 150, and a processing circuit chip 110 connected to the bus 150. The processing circuit chip 110 can be used to process data, such as processing application data, processing image data, and caching temporary data. For example, the processing circuit chip 110 can be a central processing unit (CPU), a system on chip (SOC), an electronic control unit (ECU), etc. In one embodiment, the processing circuit chip 110 may include an application processor (AP) 111 for processing applications, a graphics processing unit (GPU) 112 for processing image data, and a first random access memory (RAM) 113 for caching high-speed data. The first RAM 113 may be an SRAM or an embedded flash (EFlash), etc. The above-mentioned AP 111, GPU 112 and first RAM 113 may be integrated into a die, or may be respectively set in multiple dies. The electronic device may also include a second RAM 120 connected to the processing circuit chip through the bus. The second RAM 120 may be a dynamic random access memory (DRAM). The second RAM 120 may be used to store volatile data, such as temporary data generated by a processing circuit chip. The storage capacity of the second RAM 120 is generally greater than that of the first RAM 113, but the reading speed is generally slower than that of the first RAM 113. In addition, the electronic device may further include a communication chip 130 and a power management chip 140 connected to the processing circuit chip via a bus. The communication chip 130 may be used for processing a protocol stack, or for amplifying and filtering analog radio frequency signals, or for simultaneously implementing the above functions. The power management chip 140 may be used to power other chips. In one embodiment, the processing circuit chip and the second RAM 120 may be packaged in a packaging structure, such as by using 2.5D (dimension) or 3D packaging, etc., to obtain a faster data transmission rate between chips. By way of example, there may be one or more processors, the specific number of which may be determined according to the requirements of the actual application scenario, and is not limited here.

[0053] Figure 2 A schematic diagram of the structure of the SRAM provided in the embodiment of the present application. Figure 2, taking the first RAM 113 as an SRAM as an example, the SRAM 0122 mainly includes a plurality of memory cells (cells) 200, and the plurality of memory cells 200 constitute an N×M memory array, wherein M and N are both integers greater than or equal to 1. Exemplarily, the plurality of memory cells 200 are arranged as a plurality of memory cell rows (such as row 1 to row N) along the second direction F2, and the plurality of memory cells 200 are arranged as a plurality of memory cell columns (such as column 1 to column M) along the first direction F1. In addition, the SRAM 0122 further includes a plurality of word lines WL, a plurality of first bit lines BL, and a plurality of second bit lines BLB. The plurality of word lines WL extend along the first direction F1, and the plurality of word lines WL are arranged along the second direction F2. The plurality of first bit lines BL and the plurality of second bit lines BLB extend along the second direction F2, and the plurality of first bit lines BL and the plurality of second bit lines BLB are alternately arranged along the first direction F1 (i.e., a first bit line BL is provided between two adjacent second bit lines BLB). A plurality of memory cell rows correspond to a plurality of word lines one by one, and each memory cell row is connected to a corresponding word line to drive the memory cell through the word line. Also, a plurality of memory cell columns correspond to a plurality of first bit lines BL and a plurality of second bit lines BLB one by one, and each memory cell column is connected to a corresponding first bit line BL and second bit line BLB to transmit data through the first bit line BL and second bit line BLB.

[0054] Reference Figure 2 , SRAM 0122 also includes: a row decoding circuit 1021, word line circuits 1 to N, a read / write driver circuit 1022, and a column decoding circuit 1023. Among them, the input ends of the word line circuits 1 to N are respectively connected to the output ends of the row decoding circuit 1021, and the output ends of the word line circuits 1 to N are respectively connected to the word lines connected to the N memory cell rows in a one-to-one correspondence. For example, word line circuit 1 is connected to the word line connected to the memory cell row (such as row 1), word line circuit 2 is connected to the word line connected to the memory cell row (such as row 2)... word line circuit N-1 is connected to the word line connected to the memory cell row (such as row N-1), and word line circuit N is connected to the word line connected to the memory cell row (such as row N). In addition, the read / write driver circuit 1022 is respectively connected to the column decoding circuit 1023 and each first bit line BL and each second bit line BLB.

[0055] During operation, the processor 111 can read and write data in the SRAM 0122. Specifically, the processor 111 can send address information to the SRAM 0122, and the address information can indicate the storage address of the target data in the SRAM 0122. Exemplarily, the address information sent by the processor 111 includes row address information and column address information. The SRAM 0122 is connected to the processor 111 and can receive the address information output by the processor 111. In the SRAM 0122, the row decoding circuit 1021 is a row decoder, which can decode the row address information to determine the target storage cell row where the target data is located, and the target word line circuit corresponding to the target storage cell row. As in the above example, the row decoding circuit 1021 can determine that the target storage cell row is the second row storage cell (i.e., the storage cell row corresponding to row 2), and the target word line circuit is word line circuit 2.

[0056] The row decoding circuit 1021 can further send decoding selection signals to word line circuits 1 to N. The decoding selection signal sent to the target word line circuit can instruct the target word line circuit to work, and the decoding selection signal sent to other word line circuits except the target word line circuit can instruct other word line circuits to wait.

[0057] As in the above example, word line circuit 2 is the target word line circuit, and the decoding selection signal sent to word line circuit 2 can instruct word line circuit 2 to work, and the decoding selection signal sent to word line circuit 1 and word line circuit 3 to word line circuit N can instruct the word line circuit to wait.

[0058] In one example, the decoding selection signal can indicate the word line circuit to work or wait through different level states. For example, when the decoding selection signal is at a high level, it can indicate that the word line circuit receiving the decoding selection signal is working, and when the decoding selection signal is at a low level, it can indicate that the word line circuit receiving the decoding selection signal is waiting.

[0059] In yet another example, the decoded selection signal may also carry selection information, and the word line circuit may determine whether to work next or wait by analyzing the selection information carried by the decoded selection signal.

[0060] The word line circuit can work or wait according to the decoding selection signal. The word line circuit can output a word line signal to the connected word line, and the word line signal can turn on or off the corresponding memory cell row. Generally speaking, the word line signal turns on or off the memory cell row through different level states. For example, when the word line signal is at a high level, the word line signal can turn on the memory cell row, and when the word line signal is at a low level, the word line signal can turn off the memory cell row. In the case where the decoding selection signal indicates that the word line circuit is working, the word line signal output by the word line circuit can be at a high level, thereby turning on the corresponding memory cell row. In the case where the decoding selection signal indicates that the word line circuit is waiting, the word line circuit can remain at a low level, thereby turning off the corresponding memory cell row.

[0061] The column decoding circuit 1023 can decode the column address information to determine the target storage cell column where the target data is located. Then, the instruction information is sent to the read / write driver circuit 1022 to instruct the read / write driver circuit 1022 to read / write the data in the target storage cell column. At this time, the read / write driver circuit 1022 can read / write the data in the target storage cell column in the target storage cell row only when the target storage cell row is turned on.

[0062] Figure 3 A circuit diagram of a storage unit of an SRAM provided in an embodiment of the present application. Figure 3, the storage unit 200 can be set as a 6T Cell, which includes: a first pull-up tube T1, a second pull-up tube T2, a first pull-down tube T3, a second pull-down tube T4, a first selection tube T5 and a second selection tube T6. Among them, the first electrode of the first pull-up tube T1 and the first electrode of the second pull-up tube T2 receive the second power supply voltage VDD. The second electrode of the first pull-up tube T1 is connected to the second electrode of the first pull-down tube T3, and the second electrode of the second pull-up tube T2 is connected to the second electrode of the second pull-down tube T4. The first electrode of the first pull-down tube T3 and the first electrode of the second pull-down tube T4 receive the first power supply voltage VSS. The gate of the second pull-up tube T2 is connected to the gate of the second pull-down tube T4, the second electrode of the first pull-up tube T1, the second electrode of the first pull-down tube T3 and the second electrode of the first selection tube T5 are connected to each other to form a first storage node Q. The gate of the first pull-up tube T1, the gate of the first pull-down tube T3, the second electrode of the second pull-up tube T2, the second electrode of the second pull-down tube T4, and the second electrode of the second selection tube T6 are connected to each other to form a second storage node QB. The gate of the first selection tube T5 and the gate of the second selection tube T6 are connected to the same word line WL, and the first selection tube T5 and the second selection tube T6 are driven to be turned on and off through the word line WL. The first electrode of the first selection tube T5 is connected to the first bit line BL, and data is transmitted through the first bit line BL. The first electrode of the second selection tube T6 is connected to the second bit line BLB, and data is transmitted through the second bit line BLB. In addition, the first pull-up tube T1 and the first pull-down tube T3 serve as the first inverter, and the second pull-up tube T2 and the second pull-down tube T4 serve as the second inverter, then the output end of the first inverter is electrically connected to the input end of the second inverter, forming the first storage node Q. The output end of the second inverter is connected to the input end of the first inverter, forming the second storage node QB. Since the first inverter and the second inverter are cross-coupled and serve as a latch circuit, when one storage node is pulled down to a low potential, the other storage node is pulled up to a high potential.

[0063] Exemplarily, when the memory cell is working, when the word line signal transmitted on the word line is at a high level, the word line signal can control the first selection tube T5 and the second selection tube T6 to be turned on, so that the data in the memory cell can be read and written through the first bit line and the second bit line.

[0064] Exemplarily, the first pull-up tube T1, the second pull-up tube T2, the first pull-down tube T3, the second pull-down tube T4, the first gating tube T5 and the second gating tube T6 can be set as field effect transistors (Field Effect Transistor, FET). Optionally, the FET in the storage unit can be set as a P-type field effect transistor (PFET) or an N-type field effect transistor (NFET). For example, the first pull-up tube T1 and the second pull-up tube T2 are respectively set as PFETs, and the first pull-down tube T3, the second pull-down tube T4, the first gating tube T5 and the second gating tube T6 are respectively set as NFETs. In addition, for the convenience of expression, the first pole of each FET in the present application can refer to the source, and the second pole refers to the drain. Alternatively, the first pole can also refer to the drain, and the second pole of the transistor refers to the source. The following description will be made by taking as an example that the first pull-up tube T1 and the second pull-up tube T2 are respectively configured as PFETs, and the first pull-down tube T3 , the second pull-down tube T4 , the first gate tube T5 , and the second gate tube T6 are respectively configured as NFETs.

[0065] Figure 4 A schematic diagram of a layout structure of an SRAM provided in an embodiment of the present application, Figure 5a for Figure 4 Schematic diagram of the cross-sectional structure along the AA' tangent direction, Figure 5b for Figure 4 Schematic diagram of the cross-sectional structure along the BB' tangent direction, Figure 6 For Figure 4 Schematic diagram of the layout structure after adding word lines. It can be understood that in order to Figures 4 to 6 The positional relationship of the main film layers or structures is clearly described in Figures 4 to 6 Some membrane layers are hidden in the figure. For example, Figure 4 The word lines, insulating layers, gates of various FETs, and other film layers are hidden in the figure. Figure 6 The substrate, insulating layer, gates of each FET and other film layers are hidden in the figure. For the positional relationship of these hidden film layers, please refer to Figure 5a and Figure 5b .

[0066] Reference Figure 4 , Figure 5a , Figure 5b as well as Figure 6The SRAM includes a substrate 300, the substrate 300 has a first side S1 and a second side S2 along a third direction F3, the first side S1 of the substrate 300 is provided with a plurality of memory cells 200 arranged in an array, and the memory cells 200 include: a first pull-up tube T1, a second pull-up tube T2, a first pull-down tube T3, a second pull-down tube T4, a first selection tube T5, and a second selection tube T6. Among them, the first pull-down tube T3, the first pull-up tube T1, the second pull-up tube T2, and the second pull-down tube T4 are sequentially arranged in intervals along the first direction F1, the first selection tube T5 and the first pull-down tube T3 are arranged in a straight line along the second direction F2, and the second selection tube T6 and the second pull-down tube T4 are arranged in another straight line along the second direction F2. Furthermore, the first pull-up tube T1, the first pull-down tube T3 and the second gating tube T6 are arranged in a straight line along the first direction F1, and the second pull-up tube T2, the second pull-down tube T4 and the first gating tube T5 are arranged in another straight line along the first direction F1. In addition, the third direction F3 is perpendicular to the plane where the substrate 300 is located, and the first direction F1 and the second direction F2 are parallel to the plane where the substrate 300 is located and intersect with each other. For example, the first direction F1 and the second direction F2 are perpendicular to each other. Exemplarily, the substrate 300 includes but is not limited to a silicon substrate, a silicon-on-insulator (SOI) substrate, etc. This application is specifically described by taking the substrate as a silicon substrate as an example.

[0067] Since the fin field-effect transistor (Fin Field-Effect Transistor, Fin FET) has the advantages of strong current control capability, reduced leakage current and increased switching speed, based on this, each FET in the storage unit of the present application can be set as a Fin FET, that is, the first pull-up tube T1, the second pull-up tube T2, the first pull-down tube T3, the second pull-down tube T4, the first gating tube T5 and the second gating tube T6 are respectively set as Fin FETs. And, referring to Figure 4 ,and Figure 6 The fin channel of the first pull-up tube T1, the fin channel of the second pull-up tube T2, the fin channel of the first pull-down tube T3, the fin channel of the second pull-down tube T4, the fin channel of the first gate tube T5 and the fin channel of the second gate tube T6 extend along the second direction F2 respectively.

[0068] In order to reduce the complexity of fin channel patterning, refer to Figure 4 In the same memory cell 200 , the fin channel of the first gate tube T5 and the fin channel of the first pull-down tube T3 are set as an integrated structure.

[0069] In order to reduce the complexity of fin channel patterning, refer to Figure 4In the same memory cell 200 , the fin channel of the second gate tube T6 and the fin channel of the second pull-down tube T4 are set as an integrated structure.

[0070] Figure 7 Another schematic diagram of the layout structure of the SRAM provided in the embodiment of the present application, referring to Figure 4 and Figure 7 The plurality of storage cells 200 in the present application may form a plurality of first storage cell groups (e.g., the storage cell columns described above) Za_1 to Za_2 and a plurality of second storage cell groups (e.g., the storage cell rows described above) Zb_1 to Zb_4, wherein the first storage cell groups Za_1 to Za_2 are arranged along a first direction F1, and each of the first storage cell groups Za_1 to Za_2 includes a plurality of storage cells 200 arranged along a second direction F2. Furthermore, the second storage cell groups Zb_1 to Zb_4 are arranged along a second direction F2, and each of the second storage cell groups Zb_1 to Zb_4 includes a plurality of storage cells 200 arranged along the first direction F1. Exemplarily, adjacent first storage cell groups may be arranged in mirror symmetry, and two adjacent second storage cell groups may be arranged in mirror symmetry. For example, the first storage cell group Za_1 is arranged in mirror symmetry with the first storage cell group Za_2, the second storage cell group Zb_1 is arranged in mirror symmetry with the second storage cell group Zb_2, the second storage cell group Zb_2 is arranged in mirror symmetry with the second storage cell group Zb_3, and the second storage cell group Zb_3 is arranged in mirror symmetry with the second storage cell group Zb_4. Based on this, two adjacent storage cells arranged along the second direction F2 can be arranged in mirror symmetry, and two adjacent storage cells arranged along the first direction F1 can also be arranged in mirror symmetry. For example, storage unit 200a is arranged in mirror symmetry with storage unit 200b, storage unit 200a is arranged in mirror symmetry with storage unit 200c, and the implementation methods of the remaining storage units 200d, 200e, 200f, 200g, and 200h can be deduced in turn, and will not be repeated here. Of course, two adjacent second storage cell groups can also be arranged in translation symmetry.

[0071] Continue to refer to Figure 4 , the fin-type channels of the first pull-down tubes T3 adjacent along the second direction F2 are set as an integrated structure, and the fin-type channels of the first selection tubes T5 adjacent along the second direction F2 are also set as an integrated structure. For example, the fin-type channels of the first pull-down tubes T3 in the memory cells 200b and 200c are an integrated structure, and the fin-type channels of the first selection tubes T5 in the memory cells 200a and 200b are an integrated structure. In this way, the fin-type channels extending along the second direction F2 can be used to form the fin-type channels of the first pull-down tubes T3 and the fin-type channels of the first selection tubes T5 in the multiple memory cells arranged along the second direction F2, respectively, so as to further reduce the complexity of the channel patterning.

[0072] Reference Figure 4 , the fin-type channels of the second pull-down tubes T4 adjacent along the second direction F2 are set to an integrated structure, and the fin-type channels of the second selection tubes T6 adjacent along the second direction F2 are also set to an integrated structure. For example, the fin-type channels of the second pull-down tubes T4 in the memory cells 200a and 200b are an integrated structure, and the fin-type channels of the second selection tubes T6 in the memory cells 200b and 200c are an integrated structure. In this way, the fin-type channels extending along the second direction F2 can be used to form the fin-type channels of the second pull-down tubes T4 and the fin-type channels of the second selection tubes T6 in the multiple memory cells arranged along the second direction F2, respectively, so as to further reduce the complexity of the channel composition.

[0073] Reference Figure 4 , the fin-type channels of the first pull-up tubes T1 adjacent to each other along the second direction F2 are set as an integrated structure. For example, the fin-type channels of the first pull-up tubes T1 in the memory cell 200b and the memory cell 200c are an integrated structure, and thus, the fin-type channels of the first pull-up tubes T1 in the two memory cells can be formed by using the fin-type channels extending along the second direction F2, further reducing the complexity of the channel patterning.

[0074] Reference Figure 4 , the fin-type channels of the second pull-up tubes T2 adjacent to each other along the second direction F2 are also set as an integrated structure. For example, the fin-type channels of the second pull-up tubes T2 in the memory cells 200a and 200b are an integrated structure. With this arrangement, the fin-type channels of the second pull-up tubes T2 in the two memory cells can be formed by using the fin-type channels extending along the second direction F2, further reducing the complexity of the channel patterning.

[0075] It is understandable that the fin channel in each Fin FET may have a channel region, a source region and a drain region arranged on both sides of the channel region. Moreover, the fin channel of each Fin FET in the present application may be one, two, three or more, and its specific value may be determined according to the needs of the actual application scenario, which is not limited here. Also, the structure of each Fin FET in the present application may be basically the same as the structure of the Fin FET in the prior art, which is not repeated here. In addition, the above content of the present application is described by taking each FET as a Fin FET as an example. In actual applications, each FET in the storage unit of the present application may also be set to a FET of other structures, which is not limited here.

[0076] In order to isolate the channels of each FET, refer to Figure 5a and Figure 5bA shallow trench isolation (STI) structure 331 is also provided in the substrate 300 to define the area occupied by the channel of each FET in the substrate, and the channels of different FETs are isolated by the STI structure 331.

[0077] Reference Figures 4 to 6 An isolation medium 332 is provided between different FETs, a first connection layer 320 is provided on the side of the isolation medium 332 facing away from the substrate, a first interconnection layer 340 is provided on the side of the first connection layer 320 facing away from the substrate 300, and the first interconnection layer 340 includes a plurality of bit lines spaced apart from each other, the plurality of bit lines extend along the second direction F2 and are arranged along the first direction F1. In order to achieve the connection between the bit lines and the corresponding FETs, the plurality of bit lines may include a plurality of first bit lines BL and a plurality of second bit lines BLB, and the plurality of first bit lines BL and the plurality of second bit lines BLB are alternately arranged along the first direction F1 (i.e., a first bit line BL is provided between two adjacent second bit lines BLB). Among them, one first storage unit group corresponds to one first bit line BL and one second bit line BLB. For example, the orthographic projection of the first bit line BL on the substrate 300 can be set between the orthographic projection of the first pull-up tube T1 and the orthographic projection of the first pull-down tube T3 in the corresponding first storage cell group on the substrate, and the orthographic projection of the second bit line BLB on the substrate 300 can be set between the orthographic projection of the second pull-up tube T2 and the orthographic projection of the second pull-down tube T4 in the corresponding first storage cell group on the substrate. In addition, the first connection layer 320 also includes a first bit line connection portion 325 and a second bit line connection portion 326 arranged in each storage cell. In addition, in the same storage cell, the first bit line connection portion 325 is connected to the first electrode (for example, the source region of the fin channel of the first selection tube T5) T5_S, and the first electrode of the first selection tube T5 is also connected to the corresponding first bit line BL through the first bit line connection hole BT1, so that the first electrode of the first selection tube T5 is electrically connected to the corresponding first bit line BL. Furthermore, in the same memory cell, the second bit line connection portion 326 is connected to the first electrode of the second selection tube T6 (for example, the source region of the fin channel of the second selection tube T6) T6_S, and the first electrode of the second selection tube T6 is also connected to the corresponding second bit line BLB through the second bit line connection hole BT2, so that the first electrode of the second selection tube T6 is electrically connected to the corresponding second bit line BLB.

[0078] Continue to refer to Figures 4 to 6, a second interconnect layer 350 is disposed on a side of the first interconnect layer 340 facing away from the substrate 300. The second interconnect layer 350 includes a plurality of word lines WL arranged at intervals. The plurality of word lines WL extend along a first direction F1 and are arranged along a second direction F2, and one second memory cell group corresponds to one word line WL. To connect the word line WL to the corresponding FET, the first connection layer 320 further includes a first word line connection portion and a second word line connection portion disposed in each memory cell. The gate of the first select transistor T5 is connected to the corresponding word line WL through the first word line connection portion, so that the first select transistor T5 is electrically connected to the word line WL. Moreover, the gate of the second select transistor T6 is connected to the corresponding word line WL through the second word line connection portion, so that the second select transistor T6 is electrically connected to the word line WL. It is worth mentioning that Figures 4 to 6 the first word line connection portion and the second word line connection portion are not shown in the figure, and their implementation manners can refer to the implementation manners of the first bit line connection portion 325 and the second bit line connection portion 326. In addition, an insulating layer 334 is disposed between the second interconnect layer 350 and the first interconnect layer 340, and an insulating layer 333 is disposed between the first interconnect layer 340 and the first connection layer 320.

[0079] Continue to refer to Figure 4 to Figure 5b, a plurality of trenches (e.g., GT1, GT2, GT3) spaced from each other are further provided in the substrate 300, and the plurality of trenches (e.g., GT1, GT2, GT3) extend along the second direction F2 and are arranged along the first direction F1, that is, each trench (e.g., GT1, GT2, GT3) is provided as a trench type TSV (trench type silicon through via) structure, and the extension direction of each trench (e.g., GT1, GT2, GT3) is the same as the extension direction of the bit line. Moreover, the plurality of trenches (e.g., GT1, GT2, GT3) extend from the surface of the second side S2 of the substrate 300 to the substrate 300 along the third direction F3, that is, the plurality of trenches (e.g., GT1, GT2, GT3) are respectively embedded in the substrate 300. Furthermore, the distance d1 between the bottom of the multiple trenches (for example, GT1, GT2, GT3) (i.e., the side of the trench close to the memory cell) and the surface of the substrate 300 facing the memory cell (the surface is, for example, the interface between the STI and the substrate 300, or the surface can also be the interface between the bottom of the fin channel of the Fin FET and the substrate 300) is greater than zero, so that the multiple trenches (for example, GT1, GT2, GT3) do not penetrate the substrate. In this way, the groove can be prevented from being restricted by the fin channel in the first direction F1, and the line width of the groove in the first direction F1 can be released. Exemplarily, d1 can be set to 40nm to 60nm. For example, d1 can be set to: 40nm, 45nm, 50nm, 55nm, 60nm. Of course, in actual applications, the specific value of d1 can also be determined according to the needs of the actual application scenario, which is not limited here.

[0080] Reference Figures 4 to 5b , each groove (for example, GT1, GT2, GT3) is filled with a power adapter (for example, 311, 312, 313), that is, the power adapter (for example, 311, 312, 313) is embedded in the substrate 300. Exemplarily, the material of the power adapter can be a metal material, such as Mo, Ru, Co, etc., which is not limited here. Exemplarily, in order to avoid the adverse effect of the power adapter on the substrate, a dielectric layer can also be provided between the substrate and the power adapter. In addition, during the process preparation, after the groove is formed, the metal material can be filled in the groove to form the power adapter (for example, 311, 312, 313).

[0081] Reference Figure 5a and Figure 5b, the second side S2 of the substrate 300 is also provided with a power line, that is, the power line is provided on the back side of the substrate 300. And, the power line is connected to the power adapter line in the groove. In addition, a connection portion connected to the storage unit is also provided in the first connection layer 320, and the connection portion is also connected to the power adapter line in the groove through a contact hole that is mutually interpenetrating with the groove, so that the power adapter line (for example, 311, 312, 313) is provided between the power line and the connection portion, so that the storage unit can be powered by the power line, the groove, the contact hole and the connection portion. In addition, by providing the power line on the second side of the substrate, that is, transferring the power line to the back side of the substrate, the storage unit is powered by the backside power delivery network (BSPDN). And, in the static random access memory of the prior art, the power line is usually provided on the side of the substrate facing the storage unit (that is, the front side of the substrate), thereby limiting the line width of the word line or the bit line, resulting in a series of problems caused by RC delay (delay) in the word line or the bit line. To this end, the static random access memory provided in the embodiment of the present application, by setting the power line on the back side of the substrate, can not only free up the space of the layer where the word line or bit line is located, but also increase the width of the word line or bit line without increasing the layout area of ​​the storage unit, thereby reducing the resistance of the word line or bit line, thereby improving a series of problems caused by RC delay of the word line or bit line during read and write operations, and improving the overall performance of the static random access memory.

[0082] Combination Figure 3 It can be seen that the first power supply voltage VSS needs to be input to the memory cell 200. Figures 4 to 6 , the power line may include a first power line 371 capable of transmitting a first power supply voltage VSS, and an insulating layer 381 is provided between the first power line 371 and the substrate 300. In addition, the plurality of trenches include a plurality of first trenches GT1 and a plurality of second trenches GT2, and the power adapter line 311 filled in the first trench GT1 and the power adapter line 312 filled in the second trench GT2 are connected to the first power line 371 through the conductive material filled in the ordinary via or the trench type TSV structure via, respectively. Thus, the power adapter lines 311 and 312 in the first trench GT1 and the second trench GT2 can be electrically connected to the first power line 371. Exemplarily, the conductive material filled in the ordinary via or the trench-shaped via is the same as the material of the first power line 371, and both can be metal materials. For example, when forming the first power line 371, the ordinary via or the trench type TSV structure via can be directly filled with the material forming the first power line 371.

[0083] It is understandable that the trench type TSV structure used in the present application can solve the problem that the CPP size of the storage unit in the advanced process does not meet the critical dimension (CD) / pitch of the backside single hole type TSV via. Moreover, compared with the single hole TSV, the trench type TSV can also release the alignment window of the process TSV in the first direction and the second direction.

[0084] Reference Figure 4 to Figure 5b The memory cell 200 has a first side and a second side along a first direction F1, a first trench GT1 is provided on the first side of the memory cell 200, a connection portion in the first connection layer 320 may include a first connection portion 321, and the first connection portion 321 is connected to the first electrode (e.g., the source region of the fin channel of the first pull-down tube T3) T3_S, and the first connection portion 321 is also connected to the power adapter line 311 in the first trench GT1 through a first contact hole CT1 that penetrates the first trench GT1, so that the power adapter line 311 is arranged between the first power line 371 and the first connection portion 321. In addition, the first contact hole CT1 is filled with a conductive material (e.g., a metal material). Thus, the first electrode of the first pull-down tube T3 can be connected to the first power line 371 through the first connection portion 321, the conductive material filled in the first contact hole CT1, and the power adapter line in the first trench GT1, so that the first power voltage VSS is transmitted to the first electrode of the first pull-down tube T3. Exemplarily, the conductive material filled in the first contact hole CT1 may be the same as the first connection portion 321. For example, when forming the first connection portion 321, the material forming the first connection portion 321 may be directly used to fill the first contact hole CT1. It is understandable that the first contact hole CT1 passes through the bottom of the first connection portion 321 (i.e., the side of the first connection portion 321 close to the substrate) to the bottom of the first trench GT1 (i.e., the side of the first trench GT1 close to the Fin FET) in the third direction F3, thereby forming a deep via structure. In addition, the positive projection of the first contact hole CT1 on the substrate is located in the isolation region of the FET between two adjacent first storage cell groups.

[0085] Furthermore, a second trench GT2 is provided on the second side of the memory cell 200, and the connection portion in the first connection layer 320 may further include a second connection portion 322, the second connection portion 322 is connected to the first pole (e.g., the source region of the fin-type channel of the second pull-down tube T4) T4_S, and the second connection portion 322 is also connected to the power adapter line 312 in the second trench GT2 through the second contact hole CT2 that interpenetrates with the second trench GT2, so as to set the power adapter line 312 between the first power line 371 and the second connection portion 322. Furthermore, the second contact hole CT2 is filled with a conductive material (e.g., a metal material). Thus, the first pole of the second pull-down tube T4 can be connected to the first power line 371 through the second connection portion 322, the conductive material filled in the second contact hole CT2, and the power adapter line in the second trench GT2, so that the first power supply voltage VSS can be transmitted to the first pole of the second pull-down tube T4. Exemplarily, the conductive material filled in the second contact hole CT2 may be the same as the second connection portion 322. For example, when forming the second connection portion 322, the material forming the second connection portion 322 may be directly used to fill the second contact hole CT2. It is understandable that the second contact hole CT2 extends from the bottom of the second connection portion 322 (i.e., the side of the second connection portion 322 close to the substrate) to the bottom of the second trench GT2 (i.e., the side of the second trench GT2 close to the FinFET) in the third direction F3, thereby forming a deep via structure. In addition, the orthographic projection of the second contact hole CT2 on the substrate is located in the isolation region of the FET between two adjacent first storage cell groups.

[0086] Through the above-mentioned setting, the static random access memory provided by the embodiment of the present application transfers the first power line 371 to the back side of the substrate, and realizes the structure of inputting the first power supply voltage VSS to the storage unit in the BSPDN mode. In addition, in the static random access memory of the prior art, the first power line 371 is usually arranged on the side of the substrate facing the storage unit (i.e., the front side of the substrate) and the first power line 371 is arranged on the same layer as the word line, thereby limiting the line width of the word line, resulting in the problem of the slow rise rate of the high-level voltage of the word line due to RC delay (delay). For this reason, in the static random access memory provided by the embodiment of the present application, by transferring the first power line 371 to the back side of the substrate, not only the space of the layer where the word line is located can be released, but also the width of the word line can be increased without additionally increasing the layout area of ​​the storage unit, thereby reducing the resistance of the word line, and improving the problem of the slow rise rate of the high-level voltage of the word line caused by RC delay, thereby increasing the rise rate of the high-level voltage of the word line.

[0087] In a specific implementation, when the first power line 371 and the word line WL are arranged in the same layer, the width of the word line WL in the second direction F2 is taken as the first set width h10. Figure 6In the embodiment of the present application, by removing the first power line 371 from the layer where the word line WL is located and releasing the space originally occupied by the first power line 371, the width h11 of each word line WL in the second direction F2 can be increased by 20% to 40% on the basis of the first set width h10, that is, h11 is h10*120% to h10*140%. In this way, the width of the word line WL is increased, the resistance of the word line WL is reduced, and the problem of the slow rise rate of the high-level voltage of the word line WL caused by RCdelay can be improved, thereby increasing the rise rate of the high-level voltage of the word line WL. Exemplarily, h11 can be set to: h10*120%, h10*125%, h10*130%, h10*135%, h10*140%, etc. Of course, the specific value of h11 can also be determined according to the needs of the actual application scenario, and is not limited here. It is understandable that the value of h10 may be different in SRAMs of different process sizes, so the specific value of h10 can be determined according to the requirements of the actual application scenario.

[0088] This application is Figure 4 As an example of the structure of the static random access memory shown in FIG. 1 , the case where the high level voltage Vgh is input when the word line is at different widths is simulated. The simulation results are shown in FIG. Figure 8 shown. Figure 8 The schematic diagram of the simulation results of the static random access memory provided by the embodiment of the present application when the word line is at different widths and inputs a high level voltage, L10 represents the voltage curve when the word line inputs a high level voltage Vgh when the width h11 is the first set width h10, L11 represents the voltage curve when the word line inputs a high level voltage Vgh when the width h11 increases by 20% on the basis of the first set width h10, and L12 represents the voltage curve when the word line inputs a high level voltage Vgh when the width h11 increases by 40% on the basis of the first set width h10. Figure 8 , when the width h11 is the first set width h10, the voltage on the word line reaches Vgh*90% at t10. When the width h11 increases by 20% on the basis of the first set width h10, the voltage on the word line reaches Vgh*90% at t11, which is faster than t10 by t10-t11 time (in some structures, this time can be 12ps). When the width h11 increases by 40% on the basis of the first set width h10, the voltage on the word line reaches Vgh*90% at t12, which is faster than t10 by t10-t12 time. It can be seen that increasing the width h11 of the word line by 20% and 40% on the basis of the first set width h10 can improve the problem of slow high-level voltage rise rate of the word line caused by RCdelay, increase the high-level voltage rise rate of the word line, and improve the overall performance of the static random access memory.

[0089] Combination Figure 3 It can be seen that the second power supply voltage VDD needs to be input to the storage unit 200. Figures 4 to 6 , the power line may also include a second power line 372 capable of transmitting a second power supply voltage VDD. In addition, the plurality of grooves also include a third groove GT3, one first storage unit group corresponds to one third groove GT3, and the third groove GT3 is arranged between the first pull-up tube T1 and the second pull-up tube T2 in the corresponding storage unit, and the power adapter line 313 in the third groove GT3 is connected to the second power line 372. In order to input the second power supply voltage VDD to the first pull-up tube T1 and the second pull-up tube T2, the connection part in the first interconnection layer 340 also includes a third connection part 323 and a fourth connection part 324, the third connection part 323 is connected to the first pole (for example, the source region of the fin channel of the first pull-up tube T1) T1_S of the first pull-up tube T1, and the third connection part 323 is also connected to the power adapter line 313 in the third groove GT3 through the third contact hole CT3 that penetrates the third groove GT3, thereby realizing the connection between the first pull-up tube T1 and the second power line 372. Furthermore, the fourth connection portion 324 is connected to the first electrode (e.g., the source region of the fin channel of the second pull-up tube T2) T2_S, and the fourth connection portion 324 is also connected to the power adapter line 313 in the third trench GT3 through the fourth contact hole CT4 that is mutually interpenetrating with the third trench GT3, thereby realizing the connection between the second pull-up tube T2 and the second power line 372. Based on this, the power adapter line 313 can be set between the second power line 372 and the third connection portion 323 and the fourth connection portion 324.

[0090] It is understandable that the third contact hole CT3 is penetrated from the bottom of the third connection part 323 (i.e., the side of the third connection part 323 close to the substrate) to the bottom of the third trench GT3 (i.e., the side of the third trench GT3 close to the FinFET) in the third direction F3, thereby forming a deep via structure. And, the fourth contact hole CT4 is penetrated from the bottom of the fourth connection part 324 (i.e., the side of the fourth connection part 324 close to the substrate) to the bottom of the third trench GT3 (i.e., the side of the fourth trench close to the FinFET) in the third direction F3, thereby forming a deep via structure. In addition, the orthographic projections of the third contact hole CT3 and the fourth contact hole CT4 on the substrate are located in the isolation area between the first pull-up tube T1 and the second pull-up tube T2.

[0091] Through the above-mentioned setting, the static random access memory provided by the embodiment of the present application transfers the second power line 372 to the back of the substrate, and realizes the structure of inputting the second power supply voltage VDD to the storage unit in the BSPDN mode. In addition, in the static random access memory of the prior art, the second power line 372 is usually arranged on the side of the substrate facing the storage unit (i.e., the front side of the substrate) and the second power line 372 is arranged on the same layer as the bit line, thereby limiting the line width of the bit line, resulting in the problem of slow discharge rate of the bit line due to RC delay (delay). For this reason, in the static random access memory provided by the embodiment of the present application, by transferring the second power line 372 to the back of the substrate, not only can the space of the layer where the bit line is located be released, but also the layout area of ​​the storage unit can be increased without additionally increasing the layout area of ​​the storage unit, thereby reducing the resistance of the bit line, and improving the problem of slow discharge rate of the bit line caused by RC delay during read and write operations, thereby improving the discharge rate of the bit line and improving the overall performance of the static random access memory.

[0092] In a specific implementation, when the second power line 372 is arranged in the same layer as the bit line, the width of the bit line in the first direction F1 is used as the second set width h20. Figure 6 In the embodiment of the present application, by removing the second power line 372 from the layer where the bit line is located and releasing the space originally occupied by the second power line 372, the width h21 of each bit line in the first direction F1 can be increased by 20% to 40% on the basis of the second set width h20, that is, h21 is h20*120% to h20*140%. With this setting, the width of the bit line is increased, the resistance of the bit line is reduced, and the problem of slow discharge rate of the bit line caused by RC delay can be improved, thereby increasing the discharge rate of the bit line. Exemplarily, h21 can be set to: h20*120%, h20*125%, h20*130%, h20*135%, h20*140%, etc. Of course, the specific value of h21 can also be determined according to the needs of the actual application scenario, which is not limited here. It is understandable that the value of h20 may be different in SRAMs of different process sizes, so the specific value of h20 can be determined according to the needs of the actual application scenario.

[0093] This application is Figure 4 As an example, the discharge conditions of the static random access memory shown in the figure are simulated when the bit lines are at different widths and the read and write operations are performed. The simulation results are shown in Fig. 9 shown. Fig. 9Schematic diagram of simulation results of read and write operations of a static random access memory provided by an embodiment of the present application when the bit line is at different widths. L30 represents the signal on the word line. L20 represents the voltage change curve during read and write operations on the bit line when the width h21 is the second set width h20. L21 represents the voltage change curve during read and write operations on the bit line when the width h21 is increased by 20% based on the second set width h20. L22 represents the voltage change curve during read and write operations on the bit line when the width h21 is increased by 40% based on the second set width h20. Refer to Fig. 9 , the discharge rate corresponding to the bit line width h21 increased by 40% based on the second set width h20 is greater than the discharge rate corresponding to the bit line width h21 increased by 20% based on the second set width h20, and the discharge rate corresponding to the bit line width h21 increased by 20% based on the second set width h20 is greater than the discharge rate corresponding to the bit line width h21 being the second set width h20. And, through simulation, it can be known that when the bit line width h21 is increased by 20% and 40% based on the second set width h20, the discharge rate of the bit line can be increased by 5% - 9%, so that the speed of the entire read and write operation can be increased by 3% - 5%. Thus, it can be seen that by increasing the bit line width h21 by 20% and 40% based on the second set width h20, the problem of slow discharge rate of the bit line caused by RC delay during read and write operations can be improved, the discharge rate of the bit line can be increased, and the overall performance of the static random access memory can be improved.

[0094] Exemplarily, the second power supply line 372 and the first power supply line 371 are insulated from each other. For example, refer to Figure 5a and Figure 5b , the second power supply line 372 and the first power supply line 371 can be arranged in different layers, and an insulating layer 382 is also provided between the second power supply line 372 and the first power supply line 371. Among them, the first power supply line 371 is arranged between the second power supply line 372 and the substrate, or the second power supply line 372 is arranged between the first power supply line 371 and the substrate. Of course, the second power supply line 372 and the first power supply line 371 can also be arranged in the same layer. In specific implementation, the shapes of the second power supply line 372 and the first power supply line 371 can be set as strip structures or grid-like structures.

[0095] In order to further improve the density of the storage unit, refer to Figure 4 and Figure 7As shown, since the mirror surfaces of two adjacent storage units 200 arranged along the second direction F2 can be symmetrically arranged, the first connection portion 321 connected to the two adjacent first pull-down tubes T3 along the second direction F2 can share the same first contact hole CT1. With this arrangement, the number of first contact holes CT1 can be reduced, and the complexity of layout design can be reduced. In addition, the first trench GT1 can be made to penetrate each first contact hole CT1 in the corresponding first storage unit group (for example, Za_1), so that the same first trench GT1 can be used to provide the first power supply voltage VSS for the first pull-down tube T3 in the corresponding first storage unit (for example, Za_1).

[0096] In order to further increase the density of storage cells, refer to Figure 4 and Figure 7 As shown, since the mirror surfaces of two adjacent storage units 200 arranged along the second direction F2 can be symmetrically arranged, the second connection portion 322 connected to the two second pull-down tubes T4 adjacent to each other along the second direction F2 can share the same second contact hole CT2. With this arrangement, the number of second contact holes CT2 can be reduced, and the complexity of layout design can be reduced. In addition, the second trench GT2 can be made to penetrate each second contact hole CT2 in the corresponding first storage unit group (for example, Za_1), so that the same second trench GT2 can be used to provide the first power supply voltage VSS for the second pull-down tube T4 in the corresponding first storage unit (for example, Za_1).

[0097] In order to further increase the density of storage cells, refer to Figure 4 and Figure 7 As shown, since two adjacent memory cells 200 arranged along the first direction F1 are arranged in mirror symmetry, the first trench GT1 between two adjacent memory cells 200 along the first direction F1 can be arranged as the same trench. This arrangement can reduce the number of first trenches GT1 and reduce the complexity of layout design.

[0098] Furthermore, the first connection portion 321 connected to two first pull-down tubes T3 adjacent to each other along the first direction F1 can share the same first contact hole CT1. With this arrangement, the number of first contact holes CT1 can be further reduced, and the complexity of layout design can be reduced. In addition, a first trench GT1 can be used to penetrate each first contact hole CT1 in two adjacent first storage unit groups, so that the same first trench GT1 can be used to provide the first power supply voltage VSS for the first pull-down tubes T3 in two adjacent first storage units.

[0099] In order to further increase the density of storage cells, refer to Figure 4 and Figure 7As shown, since two adjacent storage units 200 arranged along the first direction F1 are arranged in mirror symmetry, the second trench GT2 between two adjacent storage units 200 along the first direction F1 can be set as the same trench. This arrangement can reduce the number of second trenches GT2 and reduce the complexity of layout design.

[0100] Furthermore, the second connection portion 322 connected to the second pull-down tubes T4 adjacent to each other along the first direction F1 can share the same second contact hole CT2. With this arrangement, the number of second contact holes CT2 can be further reduced, and the complexity of layout design can be reduced. In addition, a second trench GT2 can be used to penetrate each second contact hole CT2 in two adjacent first storage unit groups (e.g., Za_1, Za_2), so that the same second trench GT2 can be used to provide the first power supply voltage VSS for the second pull-down tubes T4 in two adjacent first storage units (e.g., Za_1, Za_2).

[0101] In order to further increase the density of storage cells, refer to Figure 4 and Figure 7 As shown, since two adjacent storage units 200 arranged along the second direction F2 are arranged in mirror symmetry, the third connection portion 323 connected to two adjacent first pull-up tubes T1 along the second direction F2 can share the same third contact hole CT3. With this arrangement, the number of third contact holes CT3 can be further reduced, and the complexity of layout design can be reduced. In addition, a third trench GT3 can be used to penetrate each third contact hole CT3 in the corresponding first storage unit group (for example, Za_1), so that the same third trench GT3 can be used to provide the second power supply voltage VDD for the first pull-up tube T1 in the first storage unit (for example, Za_1).

[0102] In order to further increase the density of storage cells, refer to Figure 4 and Figure 7 As shown, since two adjacent storage units 200 arranged along the second direction F2 are arranged in mirror symmetry, the fourth connection portion 324 connected to two adjacent second pull-up tubes T2 along the second direction F2 can share the same fourth contact hole CT4. With this arrangement, the number of fourth contact holes CT4 can be further reduced, and the complexity of layout design can be reduced. In addition, a third trench GT3 can be used to penetrate each fourth contact hole CT4 in the corresponding first storage unit group (for example, Za_1), so that the same third trench GT3 can be used to provide the second power supply voltage VDD for the second pull-up tube T2 in the first storage unit (for example, Za_1).

[0103] Furthermore, a third trench GT3 can be made to penetrate each third contact hole CT3 and each fourth contact hole CT4 in the corresponding first storage cell group (for example, Za_1), so that the same third trench GT3 can be used to provide the second power supply voltage VDD for the first pull-up tube T1 and the second pull-up tube T2 in the first storage cell group (for example, Za_1).

[0104] It is understandable that, in the embodiment of the present application, the first power line 371 may be arranged on the second side S2 of the substrate 300, the second power line 372 may be arranged on the first side S1 of the substrate 300, and the second power line 372 may be arranged on the same layer as the bit line. Alternatively, the second power line 372 may be arranged on the second side S2 of the substrate 300, the first power line 371 may be arranged on the first side S1 of the substrate 300, and the first power line 371 may be arranged on the same layer as the word line.

[0105] The above contents are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be covered by the protection scope of the present application.

Claims

1. A static random access memory, It is characterized in that include: A substrate having a first side and a second side along a third direction, wherein the third direction is perpendicular to a plane where the substrate is located; A plurality of memory cells are arranged in an array on a first side of the substrate; a plurality of grooves spaced from each other, the plurality of grooves extending from the surface of the second side of the substrate into the substrate along the third direction, the plurality of grooves extending along the second direction and arranged along the first direction, the distance between the bottom of the groove and the surface of the substrate facing the storage unit is greater than zero, and the first direction and the second direction are parallel to the plane where the substrate is located and intersect each other; A power adapter filled in each of the grooves; A power line, disposed on the second side of the substrate, the power line being connected to a power adapter line in the groove; The first connection layer is arranged on the side of the storage unit facing away from the substrate. The first connection layer includes a connection portion, which is connected to the storage unit and is also connected to the power adapter line in the groove through a contact hole that penetrates the groove.

2. The static random access memory according to claim 1, It is characterized in that The memory cell has a first side and a second side along the first direction, the plurality of grooves include a first groove and a second groove, the first side of the memory cell is provided with the first groove, and the second side of the memory cell is provided with the second groove; The power line comprises a first power line for transmitting a first power voltage, the first power line being connected to power adapter lines in the first groove and the second groove respectively; The storage unit includes: a first pull-down tube and a second pull-down tube, the connecting part includes a first connecting part and a second connecting part, the first connecting part is connected to the first pole of the first pull-down tube, and the first connecting part is also connected to the power adapter line in the first groove through a first contact hole that penetrates the first groove, the second connecting part is connected to the first pole of the second pull-down tube, and the second connecting part is also connected to the power adapter line in the second groove through a second contact hole that penetrates the second groove.

3. The static random access memory as claimed in claim 2, It is characterized in that Also includes: A second interconnect layer disposed on a side of the first connection layer facing away from the substrate, the second interconnect layer comprising: a plurality of word lines spaced apart from each other, the plurality of word lines extending along the first direction and arranged along the second direction; The storage unit further includes: a first gate tube and a second gate tube, wherein the gate of the first gate tube and the gate of the second gate tube are respectively connected to the word line, and the width of the word line in the second direction is increased by 20% to 40% based on the first set width.

4. The static random access memory according to any one of claims 1 to 3, It is characterized in that The power line includes a second power line for transmitting a second power supply voltage, the plurality of grooves include a third groove, the storage unit includes a first pull-up tube and a second pull-up tube, the third groove is arranged between the first pull-up tube and the second pull-up tube in the storage unit, and the power adapter line in the third groove is connected to the second power line; The connecting portion includes a third connecting portion and a fourth connecting portion, the third connecting portion is connected to the first pole of the first pull-up tube, and the third connecting portion is also connected to the power adapter line in the third groove through a third contact hole that is mutually interpenetrating with the third groove, the fourth connecting portion is connected to the first pole of the second pull-up tube, and the fourth connecting portion is also connected to the power adapter line in the third groove through a fourth contact hole that is mutually interpenetrating with the third groove.

5. The static random access memory as claimed in claim 4, It is characterized in that Also includes: a first interconnection layer disposed on a side of the first connection layer facing away from the substrate, the first interconnection layer comprising: a plurality of bit lines spaced apart from each other, the plurality of bit lines extending along the second direction and arranged along the first direction; the width of the bit lines in the first direction is increased by 20% to 40% based on the second set width; The storage unit further includes: a first gate tube and a second gate tube, the plurality of bit lines include a first bit line and a second bit line, a first electrode of the first gate tube is connected to the first bit line, and a first electrode of the second gate tube is connected to the second bit line.

6. The static random access memory according to any one of claims 1 to 5, It is characterized in that The distance between the groove and the surface of the substrate facing the storage unit is 40 nm to 60 nm.

7. The static random access memory according to any one of claims 1 to 6, It is characterized in that The storage unit includes: a first pull-up tube, a second pull-up tube, a first pull-down tube, a second pull-down tube, a first gating tube and a second gating tube, and the first pull-down tube, the first pull-up tube, the second pull-up tube and the second pull-down tube are arranged in sequence along a first direction, the first gating tube and the first pull-down tube are arranged in a straight line along a second direction, and the second gating tube and the second pull-down tube are arranged in another straight line along the second direction.

8. The static random access memory according to claim 7, It is characterized in that Two adjacent storage units arranged along the second direction are arranged in mirror symmetry; The first connection portions connected to two first pull-down tubes adjacent to each other along the second direction share the same first contact hole; or, The second connection portions connecting two second pull-down tubes adjacent to each other along the second direction share the same second contact hole.

9. The static random access memory according to claim 7 or 8, It is characterized in that Two adjacent storage units arranged along the first direction are arranged in mirror symmetry; The first trench between two adjacent storage units along the first direction is the same trench; or, The second trenches between two adjacent storage units along the first direction are the same trench.

10. The static random access memory according to any one of claims 7 to 9, It is characterized in that The first connection portions connected to two first pull-down tubes adjacent to each other along the first direction share the same first contact hole; or, The second connection portions connected to the second pull-down tubes adjacent to each other along the first direction share the same second contact hole.

11. The static random access memory according to any one of claims 7 to 10, It is characterized in that Two adjacent storage units arranged along the second direction are arranged in mirror symmetry; The third connection portions connected to two first pull-up tubes adjacent to each other along the second direction share the same third contact hole; or, The fourth connection portions connecting two second pull-up tubes adjacent to each other along the second direction share the same fourth contact hole.

12. The static random access memory according to any one of claims 7 to 11, It is characterized in that The first pull-up tube, the second pull-up tube, the first pull-down tube, the second pull-down tube, the first gate tube and the second gate tube are respectively fin-type field effect transistors, and the fin-type channel of the first pull-up tube, the fin-type channel of the second pull-up tube, the fin-type channel of the first pull-down tube, the fin-type channel of the second pull-down tube, the fin-type channel of the first gate tube and the fin-type channel of the second gate tube respectively extend along the second direction.

13. A processing circuit chip, It is characterized in that It comprises a static random access memory as described in any one of claims 1 to 12 and one or more processors, wherein the static random access memory is used to store data required by the one or more processors during operation.

14. An electronic device, It is characterized in that The invention comprises a bus and the processing circuit chip as claimed in claim 13, wherein the bus is connected to the processing circuit chip.

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