Circuit for determining a write assist circuit enable state of a static random access memory

Abstract

The present disclosure provides a circuit for determining the write assist circuit enable state of a static random access memory, which can be applied to the technical field of integrated circuit design. The circuit comprises: an input unit, the input unit is used for generating an input signal based on a received to-be-written signal, wherein the amplitude of the input signal is related to the size relationship between the to-be-written signal and the current storage data of the storage unit currently accessed by the static random access memory, wherein the current storage data is a previous write signal; an enable control unit comprising a plurality of transistors, the enable control unit is used for controlling the conduction state of each transistor according to the received enable signal and the input signal; an output unit comprising an inverter, the output unit is used for determining the input voltage of the inverter according to the conduction state of each transistor, and the inverter is configured to output a target signal according to the input voltage and a predetermined threshold value, so as to determine the write assist circuit enable state of the static random access memory.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit design technology, and more specifically, to a circuit for determining the write assist circuit enable state of a static random access memory. Background Technology

[0002] As the cell supply voltage decreases, the write capability and read stability of Static Random Access Memory (SRAM) decrease. Therefore, the commonly used negative bit write assist circuit can be used to effectively improve the write capability of SRAM at low voltages and reduce the minimum operating voltage of SRAM.

[0003] In realizing the concept disclosed herein, the inventors discovered that the related art has at least one technical problem: high dynamic power consumption of the write auxiliary circuit. Summary of the Invention

[0004] In view of this, the present disclosure provides a circuit for determining the write assist circuit enable state of a static random access memory.

[0005] One aspect of this disclosure provides a circuit for determining the write assist circuit enable state of a static random access memory, comprising:

[0006] The input unit is used to generate an input signal based on the received signal to be written. The amplitude of the input signal is related to the size relationship between the signal to be written and the data currently stored in the memory cell currently accessed by the static random access memory. The currently stored data is the previously written signal.

[0007] The enable control unit includes multiple transistors. The enable control unit is used to control the conduction state of each of the multiple transistors according to the received enable signal and the input signal.

[0008] The output unit includes an inverter, which is used to determine the input voltage of the inverter based on the respective conduction states of multiple transistors. The inverter is configured to output a target signal based on the input voltage and a predetermined threshold to determine the write auxiliary circuit enable state of the static random access memory.

[0009] According to embodiments of this disclosure, the input unit includes a first NAND gate, a second NAND gate, a seventh PMOS transistor, and an eighth PMOS transistor; the input terminal of the first NAND gate is used to receive a precharge signal and a write signal, and the output terminal of the first NAND gate is connected to the gate of the seventh PMOS transistor; the input terminal of the second NAND gate is used to receive the inverted signals of the precharge signal and the write signal, and the output terminal of the second NAND gate is connected to the gate of the eighth PMOS transistor; the source of the seventh PMOS transistor and the source of the eighth PMOS transistor are used to generate the input signal.

[0010] According to embodiments of this disclosure, the enable control unit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; wherein the drain of the seventh PMOS transistor and the drain of the eighth PMOS transistor are connected to the source of the second PMOS transistor, the gate of the first PMOS transistor is connected to a precharge signal, the gates of the second PMOS transistor, the third PMOS transistor, and the third NMOS transistor are connected to an enable signal, the gates of the fifth PMOS transistor and the fourth NMOS transistor are connected to the inverted signal of the enable signal, the drains of the fourth PMOS transistor, the sixth PMOS transistor, and the fourth NMOS transistor are connected to the input terminal of an inverter, the gate of the sixth PMOS transistor is connected to the output terminal of the inverter, and the source of the sixth PMOS transistor is connected to the drain of the fifth PMOS transistor.

[0011] According to embodiments of this disclosure, the enable control unit further includes: a first NMOS transistor and a second NMOS transistor of different sizes; wherein the drain of the first PMOS transistor, the drain of the second PMOS transistor, the gate of the fourth PMOS transistor, the drain of the first NMOS transistor, and the gate of the second NMOS transistor are connected, and the drain of the third PMOS transistor, the gate of the first NMOS transistor, and the drain of the second NMOS transistor are connected.

[0012] According to embodiments of this disclosure, when the size of the second NMOS transistor is larger than the size of the first NMOS transistor, the source of the first NMOS transistor and the source of the second NMOS transistor are connected to the drain of the third NMOS transistor.

[0013] According to embodiments of this disclosure, the enable control unit further includes a sixth PMOS transistor, the drain of which is connected to the input terminal of the inverter, the gate of which is connected to the output terminal of the inverter, and the source of which is connected to the drain of the fifth PMOS transistor.

[0014] According to an embodiment of this disclosure, when the circuit does not receive a write signal, the precharge signal is low and the enable signal is low, the fourth NMOS transistor and the first PMOS transistor are turned on, the fourth PMOS transistor, the fifth PMOS transistor, the sixth PMOS transistor, the seventh PMOS transistor and the eighth PMOS transistor are all turned off, the second PMOS transistor and the third PMOS transistor are turned on, the gates of the first NMOS transistor and the second NMOS transistor are both charged to a high level, the input voltage of the inverter is low, and the target signal output by the inverter is high, so that the write auxiliary circuit of the static random access memory is disabled.

[0015] According to embodiments of this disclosure, when the size of the signal to be written is the same as the size of the data currently stored in the memory cell currently accessed by the static random access memory, the precharge signal is high, the first PMOS transistor is turned off, one of the first NAND gate and the second NAND gate outputs a high level, and the other outputs a low level, that is, one of the seventh PMOS transistor and the eighth PMOS transistor is turned off, and the other is turned on; after the signal to be written is input for a predetermined period of time, the enable signal is sequentially configured to a high level corresponding to the first period of time and a low level corresponding to the second period of time. When the enable signal is high, the input signal remains at a high level, the gates of the first NMOS transistor and the second NMOS transistor are both at a high level, the gate voltage of the fourth PMOS transistor is an intermediate level between the power supply voltage and ground, the input voltage of the inverter is always lower than the flip threshold voltage, and the target signal is always at a high level, so that the write auxiliary circuit of the static random access memory is disabled.

[0016] According to embodiments of this disclosure, when the size of the data currently stored in the memory cell currently accessed by the static random access memory is different from the size of the data currently stored in the memory cell, and the memory cell currently accessed is in a first state, the precharge signal is high, the first PMOS transistor is turned off, one of the first NAND gate and the second NAND gate outputs a high level, and the other outputs a low level, that is, one of the seventh PMOS transistor and the eighth PMOS transistor is turned off, and the other is turned on; after the signal to be written is input for a predetermined period of time, the enable signal is sequentially configured to a high level corresponding to the first period of time and a low level corresponding to the second period of time. When the enable signal is high, the input signal remains at a high level, the gates of the first NMOS transistor and the second NMOS transistor are both at a high level, the gate voltage of the fourth PMOS transistor is an intermediate level between the power supply voltage and ground, the input voltage of the inverter is always lower than the flip threshold voltage, and the target signal is always at a high level, so that the write auxiliary circuit of the static random access memory is not enabled.

[0017] According to embodiments of this disclosure, when the size of the data currently stored in the memory cell currently accessed by the static random access memory is different from the size of the data currently stored in the memory cell, and the memory cell currently accessed is in the second state, the precharge signal is high, the first PMOS transistor is turned off, one of the first NAND gate and the second NAND gate outputs high, and the other outputs low, that is, one of the seventh PMOS transistor and the eighth PMOS transistor is turned off, and the other is turned on; after the signal to be written is input for a predetermined period of time, the enable signal is sequentially configured to a high level corresponding to the first period of time and a low level corresponding to the second period of time. When the enable signal is high, the voltage of the input signal decreases, the gate voltage of the second NMOS transistor is less than the gate voltage of the first NMOS transistor, the gate voltage of the fourth PMOS transistor is low, the input voltage of the inverter is greater than the flip threshold voltage, the inverter is inverted, and the target signal is low, so that the write auxiliary circuit of the static random access memory is enabled.

[0018] According to embodiments of this disclosure, an input unit is configured to generate an input signal based on a received write signal, enable the conduction state of multiple transistors in the control unit controlled by the enable signal and the input signal, thereby determining the input voltage of the inverter in the output unit, and comparing the input voltage with a predetermined threshold to determine the enable state of the write auxiliary circuit. Since the amplitude of the input signal is related to the magnitude relationship between the write signal and the data currently stored in the memory cell currently accessed by the static random access memory, the enable state of the write auxiliary circuit can be controlled according to the magnitude relationship between the write signal and the data currently stored in the memory cell currently accessed by the static random access memory, so as to reduce unnecessary power consumption while ensuring the write capability of the static random access memory at low voltage. Attached Figure Description

[0019] The above and other objects, features and advantages of this disclosure will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0020] Figure 1 A schematic diagram of a circuit for determining the write assist circuit enable state of a static random access memory according to an embodiment of the present disclosure is shown.

[0021] Figure 2 A circuit diagram illustrating a circuit for determining the write assist circuit enable state of a static random access memory according to an embodiment of the present disclosure is shown.

[0022] Figure 3 The illustration schematically depicts an application scenario of a circuit for determining the write assist circuit enable state of a static random access memory according to an embodiment of the present disclosure. Detailed Implementation

[0023] The embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0024] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0025] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0026] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0027] In the process of realizing the inventive concept disclosed herein, the inventors discovered that when SRAM performs a write operation, the data to be written is difficult to be correctly written to the storage cell, resulting in write failure; at the same time, when SRAM performs a read operation, the data stored inside the storage cell is prone to change, resulting in read corruption. Furthermore, the read auxiliary circuit adopted to improve the read stability of SRAM, especially the word line undervoltage read auxiliary circuit, will further damage the write capability of SRAM.

[0028] Therefore, negative bit write assist circuits are often used to improve the write capability of SRAM at low voltages. However, these write assist circuits themselves have a large dynamic power consumption overhead, which limits the power consumption benefits of reducing the operating voltage.

[0029] In view of this, embodiments of the present disclosure provide a circuit for determining the enable state of a write auxiliary circuit of a static random access memory (SRAM), comprising: an input unit for generating an input signal based on a received write-to-be signal, wherein the amplitude of the input signal is related to the magnitude relationship between the write-to-be signal and the currently stored data of the currently accessed memory cell of the SRAM, and the currently stored data is the prior write signal; an enable control unit including a plurality of transistors for controlling the conduction state of each of the plurality of transistors according to a received enable signal and the input signal; and an output unit including an inverter for determining the input voltage of the inverter according to the conduction state of each of the plurality of transistors, wherein the inverter is configured to output a target signal according to the input voltage and a predetermined threshold to determine the enable state of the write auxiliary circuit of the SRAM.

[0030] Figure 1 A schematic diagram of a circuit for determining the write assist circuit enable state of a static random access memory according to an embodiment of the present disclosure is shown.

[0031] like Figure 1 As shown, this embodiment 100 includes an input unit 110, an enable control unit 120, and an output unit 130.

[0032] According to embodiments of this disclosure, the input unit is used to generate input signals based on the received signal to be written. For example, the signal to be written will be processed by some logic gates (such as NAND gates) and transistors to form specific input signals, which will be sent to the enable control unit.

[0033] According to embodiments of this disclosure, the amplitude of the input signal represents the magnitude of the voltage amplitude, which is related to the magnitude relationship between the signal to be written and the data currently stored in the memory cell currently accessed by the static random access memory. That is, the voltage amplitude of the input signal is not constant, but varies with the magnitude relationship.

[0034] According to embodiments of this disclosure, the prior write signal indicates data that has already been successfully written to the currently accessed memory cell. When performing a new write operation, the signal to be written needs to be compared with the prior write signal (i.e., the currently stored data) to determine their relative magnitudes.

[0035] For example, if the signal to be written is the same as the "previously written signal", it means that the data in the memory cell does not need to be changed, that is, no rewriting is required. The input signal will pass the information to the enable control signal, which in turn controls the target signal of the output cell, avoiding the enabling of the write auxiliary circuit and effectively saving power. Conversely, if the two data sizes are different, it is necessary to decide whether to enable the write auxiliary circuit based on the write operation capability of the memory cell to ensure that the signal to be written can be written correctly.

[0036] According to embodiments of this disclosure, the multiple transistors in the enable control unit include PMOS transistors and NMOS transistors. The conduction state of the multiple transistors is controlled by an enable signal and an input signal. The conduction and cutoff states of each transistor affect the potential of different nodes in the circuit, thereby changing the voltage at the input terminal of the inverter.

[0037] According to embodiments of this disclosure, the output unit includes an inverter configured to output a target signal based on an input voltage and a predetermined flip-flop threshold. When the input voltage is below the flip-flop threshold, the inverter does not flip, i.e., it outputs a high-level target signal; conversely, when the input voltage is above the flip-flop threshold, the inverter flips, and it outputs a low-level target signal.

[0038] According to embodiments of this disclosure, the output of the inverter can be connected to a write auxiliary circuit or an enable control circuit of the write auxiliary circuit. Therefore, the enable state of the write auxiliary circuit can be controlled by the target signal output by the inverter, thus achieving precise control of the enable state of the SRAM write auxiliary circuit to adapt to different write operation requirements and reduce power consumption while ensuring write performance.

[0039] According to embodiments of this disclosure, an input unit is configured to generate an input signal based on a received write signal, enable the conduction state of multiple transistors in the control unit controlled by the enable signal and the input signal, thereby determining the input voltage of the inverter in the output unit, and comparing the input voltage with a predetermined threshold to determine the enable state of the write auxiliary circuit. Since the amplitude of the input signal is related to the magnitude relationship between the write signal and the data currently stored in the memory cell currently accessed by the static random access memory, the enable state of the write auxiliary circuit can be controlled according to the magnitude relationship between the write signal and the data currently stored in the memory cell currently accessed by the static random access memory, so as to reduce unnecessary power consumption while ensuring the write capability of the static random access memory at low voltage.

[0040] According to embodiments of this disclosure, the input unit includes a first NAND gate, a second NAND gate, a seventh PMOS transistor, and an eighth PMOS transistor; the input terminal of the first NAND gate is used to receive a precharge signal and a write signal, and the output terminal of the first NAND gate is connected to the gate of the seventh PMOS transistor; the input terminal of the second NAND gate is used to receive the inverted signals of the precharge signal and the write signal, and the output terminal of the second NAND gate is connected to the gate of the eighth PMOS transistor; the source of the seventh PMOS transistor and the source of the eighth PMOS transistor are used to generate the input signal.

[0041] According to embodiments of this disclosure, the precharge signal can be considered as a reset signal for the circuit. Before a write operation begins, the precharge signal is at a high level to precharge some nodes in the detection circuit to a specific level, ensuring that the circuit is in an initial state when the write operation begins, thereby improving the accuracy and reliability of the circuit results. Conversely, when no write operation is performed, the precharge signal is at a low level.

[0042] According to embodiments of this disclosure, the enable control unit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; wherein the drain of the seventh PMOS transistor and the drain of the eighth PMOS transistor are connected to the source of the second PMOS transistor, the gate of the first PMOS transistor is connected to a precharge signal, the gates of the second PMOS transistor, the third PMOS transistor, and the third NMOS transistor are connected to an enable signal, the gates of the fifth PMOS transistor and the fourth NMOS transistor are connected to the inverted signal of the enable signal, the drains of the fourth PMOS transistor, the sixth PMOS transistor, and the fourth NMOS transistor are connected to the input terminal of an inverter, the gate of the sixth PMOS transistor is connected to the output terminal of the inverter, and the source of the sixth PMOS transistor is connected to the drain of the fifth PMOS transistor.

[0043] According to embodiments of this disclosure, the enable control unit further includes: a first NMOS transistor and a second NMOS transistor of different sizes; wherein the drain of the first PMOS transistor, the drain of the second PMOS transistor, the gate of the fourth PMOS transistor, the drain of the first NMOS transistor, and the gate of the second NMOS transistor are connected, and the drain of the third PMOS transistor, the gate of the first NMOS transistor, and the drain of the second NMOS transistor are connected.

[0044] According to an embodiment of this disclosure, when the size of the second NMOS transistor is larger than the size of the first NMOS transistor, the source of the first NMOS transistor and the source of the second NMOS transistor are connected to the drain of the third NMOS transistor.

[0045] According to embodiments of this disclosure, the enable control unit further includes a sixth PMOS transistor, the drain of which is connected to the input terminal of the inverter, the gate of which is connected to the output terminal of the inverter, and the source of which is connected to the drain of the fifth PMOS transistor.

[0046] According to embodiments of this disclosure, the size of the second NMOS transistor is larger than that of the first NMOS transistor, thus the second NMOS transistor has a stronger driving capability, which in turn controls the gate voltage of the fourth NMOS transistor, thereby changing the input voltage of the inverter.

[0047] Figure 2 A circuit diagram illustrating a circuit for determining the write assist circuit enable state of a static random access memory according to an embodiment of the present disclosure is shown.

[0048] like Figure 2 As shown, input unit 110 includes a first NAND gate NAND1, a second NAND gate NAND2, a seventh PMOS transistor P7, and an eighth PMOS transistor P8. Enable control unit 120 includes a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, and a fourth NMOS transistor N4. Output unit 130 includes an inverter INV1.

[0049] According to an embodiment of this disclosure, the two inputs of the first NAND gate NAND1 are respectively connected to the signal to be written D and the detection circuit precharge signal WF_PRE; the two inputs of the second NAND gate NAND2 are respectively connected to the inverted signal Db of the signal to be written and the detection circuit precharge signal WF_PRE; the gate of the seventh PMOS transistor P7 is connected to the output of the first NAND gate NAND1, and its source is marked WC, which is the input signal; the gate of the eighth PMOS transistor P8 is connected to the output of the second NAND gate NAND2, and its source is marked WT, which is the input signal.

[0050] According to an embodiment of this disclosure, the gate of the first PMOS transistor P1 is connected to the precharge signal WF_PRE of the detection circuit, the source of the first PMOS transistor P1 is connected to the power supply VDD, and the drain of the first PMOS transistor P1 is connected to the drain of the second PMOS transistor P2, the gate of the fourth PMOS transistor P4, the drain of the first NMOS transistor N1, and the gate of the second NMOS transistor N2. The connected node is denoted as A.

[0051] According to an embodiment of this disclosure, the gate of the second PMOS transistor P2 and the gate of the third PMOS transistor P3 are both connected to the detection circuit enable signal WF_DETECT. The source of the second PMOS transistor P2 is connected to the drain of the seventh PMOS transistor P7 and the drain of the eighth PMOS transistor P8. The connection node is denoted as DL.

[0052] According to an embodiment of this disclosure, the source of the third PMOS transistor P3 is connected to the power supply VDD, and the drain of the third PMOS transistor P3 is connected to the gate of the first NMOS transistor N1 and the drain of the second NMOS transistor N2. The connection node is denoted as Ab.

[0053] According to embodiments of this disclosure, the sources of the fourth PMOS transistor P4 and the fifth PMOS transistor P5 are both connected to the power supply VDD. The drain of the fourth PMOS transistor P4 is connected to the drain of the fourth NMOS transistor N4, the drain of the sixth PMOS transistor P6, and the input terminal OUT of the first inverter INV1.

[0054] According to an embodiment of this disclosure, the gate of the fifth PMOS transistor P5 is connected to the inverted signal WF_DETECTb of the detection circuit enable signal, and the drain of the fifth PMOS transistor P5 is connected to the source of the sixth PMOS transistor P6. The gate of the sixth PMOS transistor P6 is connected to the output terminal / OUT of the first inverter INV1. The output terminal of the first inverter INV1 is the target signal.

[0055] According to embodiments of this disclosure, the source of the first NMOS transistor N1 and the source of the second NMOS transistor N2 are connected to the drain of the third NMOS transistor N3. The gate of the third NMOS transistor N3 is connected to the detection circuit enable signal WF_DETECT, and its source is connected to ground VSS. The gate of the fourth NMOS transistor N4 is connected to the inverted signal WF_DETECTb of the detection circuit enable signal, and its source is connected to ground VSS.

[0056] According to embodiments of this disclosure, the input unit, enable control unit, and output unit can effectively control the circuit state during the write operation phase and the non-write operation phase, thereby improving the reliability and stability of the circuit. Furthermore, they can flexibly adjust the conduction and cutoff states of each transistor in the circuit based on the input signal, precharge signal, enable signal, and the level of the signal to be written, in order to complete the corresponding logic operations and signal processing tasks, ensure the correct storage and retrieval of data, and improve the performance and reliability of the storage unit.

[0057] According to an embodiment of this disclosure, when the circuit does not receive a write signal, the precharge signal is low and the enable signal is low, the fourth NMOS transistor and the first PMOS transistor are turned on, the fourth PMOS transistor, the fifth PMOS transistor, the sixth PMOS transistor, the seventh PMOS transistor and the eighth PMOS transistor are all turned off, the second PMOS transistor and the third PMOS transistor are turned on, the gates of the first NMOS transistor and the second NMOS transistor are both charged to a high level, the input voltage of the inverter is low, and the target signal output by the inverter is high, so that the write auxiliary circuit of the static random access memory is disabled.

[0058] According to embodiments of this disclosure, before the write operation begins, i.e., before the circuit requires a write signal input, the precharge signal remains low and the enable signal also remains low. Correspondingly, the gate of the first PMOS transistor is low, and the first PMOS transistor is turned on. The gates of the second and third PMOS transistors are low, and the second and third PMOS transistors are turned on. The gate of the fourth NMOS transistor is high, and the fourth NMOS transistor is turned on. The outputs of the first and second NAND gates are both low, so the gates of the seventh and eighth PMOS transistors are both low, and the seventh and eighth PMOS transistors are both turned off. Since the second and third PMOS transistors are turned on, the gates of the first and second NMOS transistors are charged to a high level. The input voltage of the inverter is low, and the target signal output by the inverter is high, so that the write auxiliary circuit of the static random access memory is disabled.

[0059] According to embodiments of this disclosure, without a write operation, the logic gates and transistors in the circuit perform logic operations to make the input voltage of the inverter low, so the inverter does not invert. Therefore, the target signal controls the write auxiliary circuit to be disabled, effectively reducing circuit power consumption.

[0060] According to embodiments of this disclosure, when the size of the signal to be written is the same as the size of the data currently stored in the memory cell currently accessed by the static random access memory, the precharge signal is high, the first PMOS transistor is turned off, one of the first NAND gate and the second NAND gate outputs a high level, and the other outputs a low level, that is, one of the seventh PMOS transistor and the eighth PMOS transistor is turned off, and the other is turned on; after the signal to be written is input for a predetermined period of time, the enable signal is sequentially configured to a high level corresponding to the first period of time and a low level corresponding to the second period of time. When the enable signal is high, the input signal remains at a high level, the gates of the first NMOS transistor and the second NMOS transistor are both at a high level, the gate voltage of the fourth PMOS transistor is an intermediate level between the power supply voltage and ground, the input voltage of the inverter is always lower than the flip threshold voltage, and the target signal is always at a high level, so that the write auxiliary circuit of the static random access memory is disabled.

[0061] According to embodiments of this disclosure, when the precharge signal is high, the circuit begins a write operation. The gate of the first PMOS transistor is high, and the first PMOS transistor is turned off. The gates of the second and third PMOS transistors are high, and the second and third PMOS transistors are turned off. When the signal to be written is 1, the inverted signal of the signal to be written is 0; conversely, when the signal to be written is 0, the inverted signal of the signal to be written is 1. Therefore, one of the first and second NAND gates outputs a high level, and the other outputs a low level. Thus, when the gate of the seventh PMOS transistor is low, the gate of the eighth PMOS transistor is high, the seventh PMOS transistor is turned off, and the eighth PMOS transistor is turned on; correspondingly, when the gate of the seventh PMOS transistor is high, the gate of the eighth PMOS transistor is low, the seventh PMOS transistor is turned on, and the eighth PMOS transistor is turned off.

[0062] According to embodiments of this disclosure, after a predetermined duration of input of the signal to be written, the enable signal is sequentially configured to a high level corresponding to a first duration and a low level corresponding to a second duration. When the enable signal is high, since the size of the signal to be written is the same as the size of the data currently stored in the memory cell currently accessed by the static random access memory, the input signal remains at a high level. The gate of the fourth PMOS transistor is low, so the fourth PMOS transistor is turned off. The gate of the third PMOS transistor is high, so the third PMOS transistor is turned on. The gates of the first NMOS transistor and the second NMOS transistor are both high, so the first NMOS transistor and the second NMOS transistor are turned on. The gate voltage of the fourth PMOS transistor is an intermediate level between the power supply voltage and ground. Therefore, the input voltage of the inverter is always lower than the flip threshold voltage, and the target signal is always high, so that the write auxiliary circuit of the static random access memory is not enabled.

[0063] According to embodiments of this disclosure, the determining circuit compares the current signal to be written with the previously written signal stored in the currently accessed memory cell and finds that the current signal to be written and the previously written signal have the same size, that is, both are 1 or both are 0. Therefore, there is no need to enable the write auxiliary circuit, avoiding unnecessary circuit power consumption overhead.

[0064] According to embodiments of this disclosure, when the size of the data currently stored in the memory cell currently accessed by the static random access memory is different from the size of the data currently stored in the memory cell, and the memory cell currently accessed is in a first state, the precharge signal is high, the first PMOS transistor is turned off, one of the first NAND gate and the second NAND gate outputs a high level, and the other outputs a low level, that is, one of the seventh PMOS transistor and the eighth PMOS transistor is turned off, and the other is turned on; after the signal to be written is input for a predetermined period of time, the enable signal is sequentially configured to a high level corresponding to the first period of time and a low level corresponding to the second period of time. When the enable signal is high, the input signal remains at a high level, the gates of the first NMOS transistor and the second NMOS transistor are both at a high level, the gate voltage of the fourth PMOS transistor is an intermediate level between the power supply voltage and ground, the input voltage of the inverter is always lower than the flip threshold voltage, and the target signal is always at a high level, so that the write auxiliary circuit of the static random access memory is not enabled.

[0065] According to the embodiments of this disclosure, the first state of the currently accessed memory cell indicates that the memory cell has a high write capability and can successfully write the data to be written without turning on the write auxiliary circuit. That is, the voltage amplitude of the input signal remains at a high level. The specific conduction and cutoff of each transistor are consistent with the above-described case where the size of the signal to be written is the same as the size of the data currently stored in the memory cell currently accessed by the static random access memory, and will not be described in detail here.

[0066] According to embodiments of this disclosure, when the size of the data currently stored in the memory cell currently accessed by the static random access memory is different from the size of the data currently stored in the memory cell, and the memory cell currently accessed is in the second state, the precharge signal is high, the first PMOS transistor is turned off, one of the first NAND gate and the second NAND gate outputs high, and the other outputs low, that is, one of the seventh PMOS transistor and the eighth PMOS transistor is turned off, and the other is turned on; after the signal to be written is input for a predetermined period of time, the enable signal is sequentially configured to a high level corresponding to the first period of time and a low level corresponding to the second period of time. When the enable signal is high, the voltage of the input signal decreases, the gate voltage of the second NMOS transistor is less than the gate voltage of the first NMOS transistor, the gate voltage of the fourth PMOS transistor is low, the input voltage of the inverter is greater than the flip threshold voltage, the inverter is inverted, and the target signal is low, so that the write auxiliary circuit of the static random access memory is enabled.

[0067] According to embodiments of this disclosure, the first state of the currently accessed memory cell indicates that the write capability of the memory cell is low, meaning that the data to be written is difficult to write correctly without activating the write auxiliary circuit. After the write operation begins, the precharge signal is high, and correspondingly, the gate of the first PMOS transistor is high, the first PMOS transistor is turned off, the gates of the second and third PMOS transistors are high, the second and third PMOS transistors are turned off, the gate of the fourth NMOS transistor is low, the fourth NMOS transistor is turned off. When the write signal is 1, the inverted signal of the write signal is 0; conversely, when the write signal is 0, the inverted signal of the write signal is 1. Therefore, one of the outputs of the first NAND gate and the second NAND gate is high, and the other output is low. Therefore, when the gate of the seventh PMOS transistor is low, the gate of the eighth PMOS transistor is high, the seventh PMOS transistor is turned off, and the eighth PMOS transistor is turned on; correspondingly, when the gate of the seventh PMOS transistor is high, the gate of the eighth PMOS transistor is low, the seventh PMOS transistor is turned on, and the eighth PMOS transistor is turned off.

[0068] According to embodiments of this disclosure, after a predetermined duration of input of the signal to be written, the enable signal is sequentially configured to a high level corresponding to a first duration and a low level corresponding to a second duration. When the enable signal is high, since the size of the data currently stored in the memory cell currently accessed by the static random access memory is different from that of the signal to be written, and the write operation capability of the current memory cell is low, the voltage of the input signal gradually decreases. Since the driving capability of the second NMOS transistor is higher than that of the first NMOS transistor, the gate voltage of the second NMOS transistor is lower than that of the first NMOS transistor. The gate voltage of the fourth PMOS transistor is low, and the fourth PMOS transistor is turned on. Therefore, when the enable signal is high, the input voltage of the inverter is quickly charged to a high level. At this time, the input voltage of the inverter is greater than the flip threshold voltage, the inverter is reversed, and the target signal is low, so that the write auxiliary circuit of the static random access memory is enabled.

[0069] According to embodiments of this disclosure, when the signal to be written is different from the stored data in the current memory cell and the current write capability of the memory cell is poor, the output of the target signal will become low level during the SRAM write operation, thereby triggering the enable of the write auxiliary circuit, so that the data can be correctly written into the memory cell, ensuring the write capability of the SRAM.

[0070] To better illustrate the application process of the above circuit, the following will demonstrate... Figure 3 The connection relationship between the above circuit, the write auxiliary circuit, and the memory unit is shown.

[0071] Figure 3 The illustration schematically depicts an application scenario of a circuit for determining the write assist circuit enable state of a static random access memory according to an embodiment of the present disclosure.

[0072] like Figure 3 As shown, this embodiment includes a storage unit, a write column select circuit, a write driver circuit, a write auxiliary circuit enable signal generation circuit, a write auxiliary circuit, and a circuit for determining the enable state of the write auxiliary circuit of the static random access memory. The storage unit is connected to other circuits via bit lines (BL and BLb) and is used to store data to be written. The write column select circuit is connected to the storage unit and is used to select the column to be written, ensuring that the signal to be written can be accurately written to the specified accessed storage unit. The write driver circuit is controlled by the drive signal WREN, receives the signal to be written D and its inverted signal Db, and is connected to VSS_WD, used to drive the signal to be written to the corresponding bit line for writing operation. The input signals WT and WC used to determine the enable state of the write auxiliary circuit of the static random access memory are connected to the output of the write driver circuit. The target signal output terminal / OUT is connected to the write auxiliary circuit enable signal generation circuit, used to generate the enable signal of the write auxiliary circuit, thereby controlling the operating state of the write auxiliary circuit. The output VSS_WD of the write auxiliary circuit is sent to the write driver circuit to adjust the write operation capability.

[0073] In summary, the write auxiliary circuit of this disclosure for determining the enable state of static random access memory enables the SRAM to adaptively trigger the write auxiliary circuit during the write operation by judging the write capability of the accessed memory cell and the relationship between the stored data and the signal to be written, effectively reducing the power consumption of the write auxiliary circuit itself in the SRAM.

[0074] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions. Those skilled in the art will understand that the features described in the various embodiments of the present disclosure can be combined and / or combined in various ways, even if such combinations are not explicitly described in the present disclosure. In particular, the features described in the various embodiments of this disclosure may be combined and / or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0075] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A circuit for determining the enable state of a write auxiliary circuit of a static random access memory, characterized in that, include: An input unit is configured to generate an input signal based on a received signal to be written, wherein the amplitude of the input signal is related to the size relationship between the signal to be written and the data currently stored in the storage cell currently accessed by the static random access memory, and the currently stored data is a previously written signal; An enable control unit includes multiple transistors, which are used to control the conduction state of each of the multiple transistors according to a received enable signal and the input signal. An output unit, including an inverter, is configured to determine the input voltage of the inverter based on the respective conduction states of the plurality of transistors, and the inverter is configured to output a target signal based on the input voltage and a predetermined threshold to determine the write auxiliary circuit enable state of the static random access memory. The input unit includes a first NAND gate, a second NAND gate, a seventh PMOS transistor, and an eighth PMOS transistor. The input terminal of the first NAND gate is used to receive a precharge signal and a write signal, and the output terminal of the first NAND gate is connected to the gate of the seventh PMOS transistor. The input terminal of the second NAND gate is used to receive the inverted signals of the precharge signal and the write signal, and the output terminal of the second NAND gate is connected to the gate of the eighth PMOS transistor. The source terminals of the seventh PMOS transistor and the eighth PMOS transistor are used to generate the input signal.

2. The circuit according to claim 1, characterized in that, The enable control unit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; wherein the drain of the seventh PMOS transistor and the drain of the eighth PMOS transistor are connected to the source of the second PMOS transistor, the gate of the first PMOS transistor is connected to the precharge signal, the gates of the second PMOS transistor, the third PMOS transistor, and the third NMOS transistor are connected to the enable signal, the gates of the fifth PMOS transistor and the fourth NMOS transistor are connected to the inverted signal of the enable signal, the drains of the fourth PMOS transistor, the sixth PMOS transistor, and the fourth NMOS transistor are connected to the input terminal of the inverter, the gate of the sixth PMOS transistor is connected to the output terminal of the inverter, and the source of the sixth PMOS transistor is connected to the drain of the fifth PMOS transistor.

3. The circuit according to claim 2, characterized in that, The enable control unit further includes a first NMOS transistor and a second NMOS transistor of different sizes; wherein the drain of the first PMOS transistor, the drain of the second PMOS transistor, the gate of the fourth PMOS transistor, the drain of the first NMOS transistor, and the gate of the second NMOS transistor are connected, and the drain of the third PMOS transistor, the gate of the first NMOS transistor, and the drain of the second NMOS transistor are connected.

4. The circuit according to claim 3, characterized in that, When the size of the second NMOS transistor is larger than the size of the first NMOS transistor, the source of the first NMOS transistor and the source of the second NMOS transistor are connected to the drain of the third NMOS transistor.

5. The circuit according to claim 4, characterized in that, The enable control unit further includes a sixth PMOS transistor, the drain of which is connected to the input terminal of the inverter, the gate of which is connected to the output terminal of the inverter, and the source of which is connected to the drain of the fifth PMOS transistor.

6. The circuit according to claim 5, characterized in that, When the circuit does not receive a write signal, the precharge signal is low and the enable signal is low. The fourth NMOS transistor and the first PMOS transistor are turned on, while the fourth, fifth, sixth, seventh, and eighth PMOS transistors are all turned off. The second and third PMOS transistors are turned on, and the gates of the first and second NMOS transistors are charged to a high level. The input voltage of the inverter is low, and the target signal output by the inverter is high, so that the write auxiliary circuit of the static random access memory is disabled.

7. The circuit according to claim 5, characterized in that, When the size of the signal to be written is the same as the size of the data currently stored in the memory cell currently accessed by the static random access memory, the precharge signal is high, the first PMOS transistor is turned off, one of the outputs of the first NAND gate and the second NAND gate is high, and the other output is low, that is, one of the seventh PMOS transistor and the eighth PMOS transistor is turned off, and the other is turned on. After the signal to be written is input for a predetermined period of time, the enable signal is sequentially configured to a high level corresponding to the first period of time and a low level corresponding to the second period of time. When the enable signal is high, the input signal remains at a high level, the gates of the first NMOS transistor and the second NMOS transistor are both at a high level, the gate voltage of the fourth PMOS transistor is at an intermediate level between the power supply voltage and ground, the input voltage of the inverter is always lower than the flip threshold voltage, and the target signal is always at a high level, so that the write auxiliary circuit of the static random access memory is disabled.

8. The circuit according to claim 7, characterized in that, When the size of the data to be written is different from the size of the data currently stored in the memory cell currently accessed by the static random access memory, and the memory cell currently accessed is in the first state, the precharge signal is high, the first PMOS transistor is turned off, one of the outputs of the first NAND gate and the second NAND gate is high, and the other output is low, that is, one of the seventh PMOS transistor and the eighth PMOS transistor is turned off, and the other is turned on. After the signal to be written is input for a predetermined period of time, the enable signal is sequentially configured to a high level corresponding to the first period of time and a low level corresponding to the second period of time. When the enable signal is at a high level, the input signal remains at a high level, the gates of the first NMOS transistor and the second NMOS transistor are both at a high level, the gate voltage of the fourth PMOS transistor is at an intermediate level between the power supply voltage and ground, the input voltage of the inverter is always lower than the flip threshold voltage, and the target signal is always at a high level, so that the write auxiliary circuit of the static random access memory is disabled.

9. The circuit according to claim 7, characterized in that, When the size of the data to be written is different from the size of the data currently stored in the memory cell currently accessed by the static random access memory, and the memory cell currently accessed is in the second state, the precharge signal is high, the first PMOS transistor is turned off, one of the outputs of the first NAND gate and the second NAND gate is high, and the other output is low, that is, one of the seventh PMOS transistor and the eighth PMOS transistor is turned off, and the other is turned on. After the signal to be written is input for a predetermined period of time, the enable signal is sequentially configured to a high level corresponding to a first period of time and a low level corresponding to a second period of time. When the enable signal is at a high level, the voltage of the input signal decreases, the gate voltage of the second NMOS transistor is less than the gate voltage of the first NMOS transistor, the gate voltage of the fourth PMOS transistor is at a low level, the input voltage of the inverter is greater than the flip threshold voltage, the inverter is inverted, and the target signal is at a low level, so that the write auxiliary circuit of the static random access memory is enabled.

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