Nonvolatile memory device, operating method of nonvolatile

Abstract

A non-volatile memory device, an operating method thereof, and an operating method of a memory device including the non-volatile memory device and a memory controller are provided. An operating method of a memory device of a memory controller includes transmitting, by the memory controller, a setting feature command including error detection enable information to a non-volatile memory device; transmitting, by the memory controller, the program command and the write data to the non-volatile memory device; performing, by the non-volatile memory device, an error detection operation on the write data of the page buffer circuit prior to programming the write data to the memory cells in response to the program command; transmitting, by the non-volatile memory device, the write data as error data to the memory controller when an error is detected in the write data; and programming, by the non-volatile memory device, the write data to the memory cell when no error is detected in the write data.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0163696 filed in the Korean Intellectual Property Office on November 22, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to a semiconductor memory, and more particularly, to a nonvolatile memory device, an operating method of the nonvolatile memory device, and an operating method of a memory device. Background Art

[0004] Semiconductor memory devices are classified into volatile memory devices and non-volatile memory devices. Volatile memory devices may include, but are not limited to, static random access memory (SRAM) and dynamic random access memory (DRAM), wherein the stored data is lost when the power supply to the memory is cut off. Non-volatile memory devices may include, but are not limited to, flash memory devices, phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), resistive random access memory (RRAM), and ferroelectric random access memory (FeRAM), wherein the stored data is retained even when the power supply to the memory is cut off.

[0005] Recently, as non-volatile memory devices are required to have high capacity and miniaturization, three-dimensional (3D) memory devices in which memory cell arrays and peripheral circuits are vertically positioned have been developed. In addition, in order to increase the capacity of non-volatile memory devices, an increasing number of word lines stacked on a substrate are provided. With the development of semiconductor processes, as the number of steps of memory cells increases, in other words, as the number of stacked word lines increases, the length of the metal line between the peripheral circuit and the memory cell increases. As the length of the metal line between the peripheral circuit and the memory cell increases, the risk of metal line resistance error increases. Summary of the invention

[0006] One or more aspects of the inventive concept provide a nonvolatile memory device having improved reliability, an operating method of the nonvolatile memory device, and an operating method of a memory device.

[0007] According to one aspect of the present disclosure, there is provided an operating method for a storage device including a nonvolatile memory device and a storage controller, the operating method comprising: sending error detection enable information by the storage controller to the nonvolatile memory device; sending a programming command and write data by the storage controller to the nonvolatile memory device; performing an error detection operation on the write data in a page buffer circuit by the nonvolatile memory device based on the error detection enable information; sending the write data as error data to the storage controller by the nonvolatile memory device based on an error detected in the write data; and programming the write data to a memory cell in the nonvolatile memory device by the nonvolatile memory device based on no error detected in the write data.

[0008] According to another aspect of the present disclosure, a method for operating a nonvolatile memory device is provided, the method comprising: receiving error detection enable information from a storage controller; receiving a programming command and write data from the storage controller; performing an error detection operation by detecting whether the same pattern is repeated in the write data of a page buffer circuit based on the error detection enable information; sending the write data as error data to the storage controller based on an error being detected in the write data; and programming the write data to a memory cell in the nonvolatile memory device based on no error being detected in the write data.

[0009] According to one aspect of the present disclosure, a nonvolatile memory device is provided, comprising: a memory cell array comprising a plurality of memory cells; an input / output circuit configured to receive write data from a memory controller; a page buffer circuit connected to the memory cell array and configured to temporarily store the write data from the input / output circuit; and an error detection circuit configured to: receive error detection enable information from the memory controller, based on the error detection enable information, perform an error detection operation by detecting whether the same pattern in the write data is repeated before programming the write data to the memory cell array, based on an error detected in the write data, send the write data as error data to the memory controller, and based on no error detected in the write data, program the write data to the memory cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0011] In the figure:

[0012] Figure 1 is a block diagram showing a storage system according to an embodiment;

[0013] Figure 2 It is shown Figure 1 A block diagram of a non-volatile memory device;

[0014] Figure 3 is a diagram for describing a three-dimensional (3D) vertical (V)-NAND structure applicable to a memory device according to an embodiment;

[0015] Figure 4A , Figure 4B and Figure 4C is a diagram for describing an error in write data according to an embodiment;

[0016] Figure 5 is a flowchart illustrating an operating method of a storage device according to an embodiment;

[0017] Figure 6 is a flow chart illustrating an operating method of a storage controller according to an embodiment;

[0018] Figure 7 is a flowchart illustrating an operating method of a nonvolatile memory device according to an embodiment;

[0019] Figure 8 is a diagram showing a method according to an embodiment of the present invention. Figure 7 Flow chart of operation S330;

[0020] Fig. 9A and Fig. 9B is a diagram for describing the operation of a nonvolatile memory device according to an embodiment;

[0021] Fig.10 is a diagram showing a method according to an embodiment of the present invention. Figure 8 Flow chart of operation S331;

[0022] Fig.11A and Fig. 11B is a diagram for describing the operation of a nonvolatile memory device according to an embodiment;

[0023] Fig.12 is a diagram showing a method according to an embodiment of the present invention. Figure 8 Flow chart of operation S333;

[0024] Fig.13 and Fig.14 is a diagram for describing the operation of a nonvolatile memory device according to an embodiment;

[0025] Fig.15 is a diagram showing a method according to another embodiment Figure 7 Flow chart of operation S330;

[0026] Fig.16 is a flowchart illustrating an operating method of a storage device according to an embodiment;

[0027] Fig.17 is a flowchart illustrating an operating method of a storage device according to an embodiment. DETAILED DESCRIPTION

[0028] Hereinafter, the embodiments will be described in detail by explaining the embodiments with reference to the accompanying drawings so that those skilled in the art can easily embody and practice the inventive concept.

[0029] The following specific examples are provided to help the reader gain a comprehensive understanding of the methods, devices and / or systems described herein. However, various changes, modifications and equivalents of the methods, devices and / or systems described herein will be clear when understanding the disclosure of the present application. For example, except for operations that must occur in a specific order, the order of operations described herein is only exemplary and the present disclosure is not limited to those set forth herein, but can be changed on the contrary, which will be clear when understanding the disclosure of the present application. In addition, for greater clarity and simplicity, the description of features known in the art may be omitted.

[0030] The features described herein may be implemented in different forms and should not be construed as being limited to the examples described herein. Rather, the examples described herein are provided to illustrate only some of the many possible ways to implement the methods, devices, and / or systems described herein, which will become clear upon understanding the disclosure of the present application.

[0031] The terms used herein are only used to describe various examples and are not used to limit the present disclosure. Unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. The terms "comprise", "include" and "have" indicate the presence of the features, quantities, operations, components, elements and / or combinations thereof, but do not exclude the presence or addition of one or more other features, quantities, operations, components, elements and / or combinations thereof.

[0032] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those generally understood by those of ordinary skill in the art to which the present disclosure belongs after understanding the present disclosure. Unless explicitly defined as such herein, terms (e.g., terms defined in a general dictionary) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and should not be interpreted ideally or in an overly formal manner.

[0033] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those of ordinary skill in the art to which the present disclosure belongs and are based on an understanding of the disclosure of the present application. Terms such as those defined in commonly used dictionaries will be interpreted as having a meaning consistent with their meaning in the context of the disclosure of the relevant art and the present application, and are not interpreted in an idealized or overly formal sense, unless explicitly defined as such herein. The use of the term "may" herein with respect to an example or embodiment (e.g., with respect to what an example or embodiment may include or implement) means that there is at least one example or embodiment that includes or implements such a feature, and all example embodiments are not limited thereto.

[0034] The embodiments of the present disclosure are example embodiments, and therefore, the present disclosure is not limited thereto and may be implemented in various other forms. As is conventional in the art, as shown in the figure, the embodiments may be described and illustrated in terms of blocks that perform the functions described. These blocks (which may be referred to herein as units or modules, etc., or as names such as devices, logic, circuits, counters, comparators, generators, converters, etc.) may be physically implemented by analog and / or digital circuits, which may include one or more of logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, etc., and these blocks may also be implemented or driven by software and / or firmware (configured to perform the functions or operations described herein).

[0035] Figure 1 is a block diagram illustrating a storage system 100 according to an embodiment.

[0036] Reference Figure 1 , the storage system 100 may include a host device 10 and a storage device 110. The storage system 100 may be implemented as an electronic device, such as a personal computer (PC), a laptop computer, a mobile phone, a smart phone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital camera, a digital video camera, an audio device, a portable multimedia player (PMP), a personal navigation device or a portable navigation device (PND), an MP3 player, a handheld game console, or an electronic book. However, the present disclosure is not limited thereto, and therefore, according to another embodiment, the storage system 100 may be implemented as another electronic device or in an electronic device. For example, the storage system 100 may be implemented as any of various types of electronic devices, such as a wearable device such as a wristwatch or a head-mounted display (HMD).

[0037] The host device 10 may control data processing operations on the storage device 110, such as data access operations, such as but not limited to data read operations or data write operations. The host device 10 may refer to a data processing device capable of processing data, such as a central processing unit (CPU), a microprocessor, or an application processor (AP). The host device 10 may execute an operating system (OS) and / or various application programs. For example, the host device 10 may include one or more processors configured to execute one or more instructions or software codes to perform various operations.

[0038] For example, the host device 10 may include a host controller 11 and a host memory 12. The host controller 11 may be a device configured to control the overall operation of the host device 10 or allow the host device 10 to control the storage device 110. For example, the host controller 11 may include one or more processors configured to execute one or more instructions or software codes to perform various operations. The host memory 12 may be a buffer memory, a cache memory, or a working memory used in the host device 10.

[0039] In an embodiment, the host memory 12 may be used as a buffer memory for temporarily storing data to be sent to or from the storage device 110. The host device 10 may send a request to the storage device 110, and may receive a response from the storage device 110. For example, in the case where the request is a write request, the request may include write data. For example, in the case where the request is a read request, the response to the request may include read data.

[0040] The storage device 110 may operate under the control of the host device 10. The storage device 110 may include a storage controller 120 and a non-volatile memory (NVM) device 130. The storage controller 120 may perform various management operations for efficiently using the non-volatile memory device 130. The non-volatile memory device 130 may include a plurality of non-volatile memories.

[0041] The storage device 110 may receive the request REQ from the host device 10, and may send a response RSP to the host device 10. In the example case where the request REQ is a write request, the storage controller 120 may control the nonvolatile memory device 130 based on the write request from the host device 10 to write data to the nonvolatile memory device 130. For example, data may be written to the nonvolatile memory device 130 in response to the write request from the host device 10. In the example case where the request REQ is a read request, the storage controller 120 may control the nonvolatile memory device 130 based on the read request from the host device 10 to read data stored in the nonvolatile memory device 130. For example, data may be read from the nonvolatile memory device 130 in response to the read request from the host device 10.

[0042] In the case where the non-volatile memory device 130 includes a flash memory, the flash memory may include a two-dimensional (2D) NAND memory array or a three-dimensional (3D) vertical NAND (VNAND) memory array. In another example, the storage device 110 may include various other types of non-volatile memory devices. For example, the storage device 110 may include, but is not limited to, a magnetic random access memory (MRAM), a spin-transfer torque MRAM, a conductive bridge RAM (CBRAM), a ferroelectric RAM (FeRAM), a phase RAM (PRAM), a resistive RAM, and various other types of memory.

[0043] The nonvolatile memory device 130 may include an error detection circuit 138. The error detection circuit 138 may perform an error detection operation. The error detection circuit 138 may perform an error detection operation to detect whether the same pattern is repeated in the write data. The error detection circuit 138 may perform an error detection operation before programming the write data to the memory cell. The error detection circuit 138 may detect errors in the write data so as to detect resistance errors of metal lines between the memory cell and the peripheral circuit.

[0044] The storage controller 120 may include a central processing unit (CPU) 121, a flash translation layer (FTL) 122, a package manager 123, a buffer memory 124, an error correction code (ECC) engine 125, an AES engine 126, a host interface (I / F) circuit 127, a non-volatile memory interface (I / F) circuit 128 and a bus 129.

[0045] The storage controller 120 may further include a working memory loaded with the FTL 122, and may control a data write operation and a data read operation on the nonvolatile memory device 130 based on the CPU 121 executing the FTL 122. For example, in response to executing the FTL 122, the CPU 121 may control or perform a data write operation and a data read operation on the nonvolatile memory device 130.

[0046] In an embodiment, the CPU 121 may be implemented as a multi-core processor, such as a dual-core processor or a quad-core processor. The FTL 122 and the package manager 123 may be loaded into a working memory of the storage controller 120. For example, the working memory may be implemented as a volatile memory such as SRAM or DRAM or a non-volatile memory such as a flash memory or PRAM.

[0047] The FTL 122 may perform various functions such as address mapping, wear leveling, and garbage collection. Address mapping is an operation of changing a logical address received from the host device 10 into a physical address in the nonvolatile memory device 130 for actually storing data. Wear leveling is a technique for preventing a specific block from being excessively degraded by allowing the blocks in the nonvolatile memory device 130 to be used evenly, and may be implemented by, for example, a firmware technique that balances the erase counts of physical blocks. Garbage collection is a technique for ensuring available capacity in the nonvolatile memory device 130 by copying valid data of a block to a new block and then erasing the existing block.

[0048] The buffer memory 124 may be configured to temporarily store write data received from the host device 10 or read data received from the non-volatile memory device 130 under the control of the storage controller 120. The following description shows an example case where the buffer memory 124 is an SRAM. However, the inventive concept is not limited thereto, and therefore, according to another embodiment, the buffer memory 124 may include, but is not limited to, a high-speed random access memory such as a DRAM or a synchronous DRAM (SDRAM). In another embodiment, the buffer memory 124 may include a non-volatile memory such as a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory device, a PRAM, an MRAM, an RRAM, a FeRAM, or a thyristor RAM (TRAM).

[0049] The packet manager 123 may generate a data packet according to a protocol for interfacing with the host device 10, or may parse various information from a data packet received from the host device 10. The protocol may be predefined or predetermined. For example, the protocol may be any of various protocols for establishing communication between the host device 10 and the storage device 110. The buffer memory 124 may temporarily store data to be written to the nonvolatile memory device 130 or data read from the nonvolatile memory device 130. The buffer memory 124 may be an element provided in the storage controller 120, but may be located outside the storage controller 120.

[0050] The ECC engine 125 may perform error detection and correction functions on read data obtained from the nonvolatile memory device 130. For example, the ECC engine 125 may generate parity bits for write data to be written to the nonvolatile memory device 130, and the generated parity bits may be stored in the nonvolatile memory device 130 together with the write data. In the case of reading data from the nonvolatile memory device 130, the ECC engine 125 may correct errors of the read data using the parity bits read from the nonvolatile memory device 130 together with the read data, and may output the error-corrected read data.

[0051] In an embodiment, the ECC engine 125 may use coded modulation or various other methods to correct errors, and the coded modulation may include but is not limited to soft decoding, low-density parity-check (LDPC) codes, BCH codes, turbo codes, Reed-Solomon codes, convolutional codes, recursive systematic codes (RSC), trellis coded modulation (TCM) or block coded modulation (BCM).

[0052] In an embodiment, the ECC engine 125 may perform an error correction operation. The ECC engine 125 may receive error data from the non-volatile memory device 130, and may perform an error correction operation on the error data. For example, the error data may refer to data in which an error is detected by an error detection operation performed by the non-volatile memory device 130 before performing a programming operation. The ECC engine 125 may detect and correct errors in the error data. In an embodiment, the ECC engine 125 may determine whether an uncorrectable error correction code (UECC) occurs. The abbreviation "UECC" may refer to a state including an error that is not corrected by the ECC engine 125. For example, the ECC engine 125 may detect an error in the error data, and may also determine that the detected error is not corrected by the ECC engine 125.

[0053] In an embodiment, the ECC engine 125 may send status information of the error data to the non-volatile memory interface circuit 128. The ECC engine 125 may send status information indicating whether the error data is corrected to the non-volatile memory interface circuit 128. In the case where the error in the error data is corrected, the ECC engine 125 may send status information indicating a corrected status to the non-volatile memory interface circuit 128. In the case where the error in the error data is not corrected, the ECC engine 125 may send status information indicating an uncorrected status to the non-volatile memory interface circuit 128.

[0054] The AES engine 126 may perform at least one of an encryption operation and a decryption operation on data input to the memory controller 120. For example, the AES engine 126 may perform the encryption operation or the decryption operation using a symmetric key algorithm.

[0055] The host interface circuit 127 may send or receive data packets to or from the host device 10. The data packets sent from the host device 10 to the host interface circuit 127 may include commands, requests RQ, or data to be written to the nonvolatile memory device 130, and the data packets sent from the host interface circuit 127 to the host device 10 may include responses to commands or data read from the nonvolatile memory device 130.

[0056] The nonvolatile memory interface circuit 128 may send data to be written to the nonvolatile memory device 130, or may receive data read from the nonvolatile memory device 130. The nonvolatile memory interface circuit 128 may be implemented to comply with a standard protocol such as Toggle or Open NAND Flash Interface (ONFI).

[0057] In an embodiment, the nonvolatile memory interface circuit 128 may send a set feature command to the nonvolatile memory device 130. The nonvolatile memory interface circuit 128 may send a set feature command to enable or disable an error detection operation of the nonvolatile memory device 130. The nonvolatile memory interface circuit 128 may send a set feature command including error detection enable information to the nonvolatile memory device 130 so that the nonvolatile memory device 130 performs an error detection operation before a programming operation. The nonvolatile memory interface circuit 128 may send a set feature command including error detection disable information to the nonvolatile memory device 130 to prevent the nonvolatile memory device 130 from performing an error detection operation before a programming operation.

[0058] In an embodiment, the nonvolatile memory interface circuit 128 may receive error data from the nonvolatile memory device 130. For example, after the nonvolatile memory interface circuit 128 sends a set feature command including error detection enable information and a program command to the nonvolatile memory device 130, the nonvolatile memory interface circuit 128 may receive error data from the nonvolatile memory device 130. For example, the nonvolatile memory interface circuit 128 may receive error data from the nonvolatile memory device 130 based on the set feature command including the error detection enable information and the program command. The nonvolatile memory interface circuit 128 may send the error data to the ECC engine 125.

[0059] In an embodiment, the nonvolatile memory interface circuit 128 may receive status information of the erroneous data from the ECC engine 125. In the case where the nonvolatile memory interface circuit 128 receives status information indicating a corrected status, the nonvolatile memory interface circuit 128 may send a recovery command RESUME CMD to the nonvolatile memory device 130. In the case where the nonvolatile memory interface circuit 128 receives status information indicating an uncorrected status, the nonvolatile memory interface circuit 128 may perform an input / output regulation operation.

[0060] In an embodiment, the nonvolatile memory interface circuit 128 may perform an input / output adjustment operation with respect to the nonvolatile memory device 130. The nonvolatile memory interface circuit 128 may adjust the voltage input to the nonvolatile memory device 130 to reduce the resistance error of the metal line between the peripheral circuit and the memory cell of the nonvolatile memory device 130. For example, the input / output adjustment operation may refer to an operation of adjusting the power supply voltage VCC or the input / output voltage VCCQ input to the nonvolatile memory device 130. The nonvolatile memory interface circuit 128 may reduce or increase the power supply voltage VCC. The nonvolatile memory interface circuit 128 may reduce or increase the input / output voltage VCCQ. However, the present disclosure is not limited thereto, and therefore, the input / output adjustment operation corresponding to the nonvolatile memory device 130 may be performed in another manner.

[0061] As described above, the nonvolatile memory device 130 of the memory device 110 according to the embodiment can detect a program pattern error by determining whether there is an error in write data before programming the write data. Therefore, the memory device 110 having improved reliability is provided.

[0062] Hereinafter, for convenience of explanation, the terms "error", "failure" and "defect" may be used interchangeably. These terms may have the same or different meanings depending on the context of the embodiment, and the meaning of each term will be understood according to the context of the following embodiments.

[0063] Figure 2 is a block diagram illustrating a nonvolatile memory device according to an embodiment.

[0064] For example, Figure 2 The non-volatile memory device shown may be Figure 1 The non-volatile memory device 130. Figure 1 and Figure 2 , the nonvolatile memory device 130 may include a memory cell array 131 and a peripheral circuit 132. For convenience of explanation, the following example describes an embodiment in which the nonvolatile memory device 130 is a NAND flash memory device, but the inventive concept is not limited thereto, and therefore, the nonvolatile memory device 130 may be a memory device of a different type, and one or more aspects of the inventive concept described below will apply.

[0065] The peripheral circuit 132 may include a page buffer circuit 133, a control logic circuit 134, a voltage generator 135, a row decoder 136, and an input / output (I / O) circuit 137. The control logic circuit 134 may include an error detection circuit 138. However, the present disclosure is not limited thereto, and therefore, according to another embodiment, the nonvolatile memory device 130 may further include a column logic, a predecoder, a temperature sensor, a command decoder, and an address decoder. For example, the peripheral circuit 132 may include one or more other components, including but not limited to a column logic, a predecoder, a temperature sensor, a command decoder, and an address decoder.

[0066] The memory cell array 131 may include a plurality of memory blocks, each of which may include a plurality of cell strings, each of which may include a plurality of memory cells connected in series. The memory cell array 131 may be connected to the page buffer circuit 133 through the bit lines BL, and may be connected to the row decoder 136 through the word lines WL, the string selection lines SSL, and the ground selection lines GSL.

[0067] In an embodiment, each of the plurality of memory blocks may include a plurality of memory cells. Each of the plurality of memory cells may be connected by a word line WL. Each of the plurality of memory cells may be a single level cell (SLC) storing 1 bit of data or a multi level cell (MLC) storing at least 2 bits of data.

[0068] In an embodiment, the memory cell array 131 may include a 3D memory cell array, which may include a plurality of cell strings. Each cell string may include a memory cell connected to a word line vertically stacked on a substrate. U.S. Patent No. 7,679,133, U.S. Patent No. 8,553,466, U.S. Patent No. 8,654,587, U.S. Patent No. 8,559,235, and U.S. Patent Application Publication No. 2011 / 0233648 are incorporated herein by reference.

[0069] In an embodiment, the memory cell array 131 may include a flash memory, and the flash memory may include a 2D NAND memory array or a 3D VNAND memory array. In an embodiment, the memory cell array 131 may include, but is not limited to, MRAM, spin-transfer torque MRAM, CBRAM, FeRAM, PRAM, RRAM, and various other types of memory.

[0070] In an embodiment, the memory cell array 131 may be formed in a cell region of a semiconductor substrate, and the peripheral circuit 132 may be formed in a peripheral region physically separated from the cell region of the semiconductor substrate. In an embodiment, the peripheral circuit 132 may be formed on a semiconductor substrate, and the memory cell array 131 may be stacked on the peripheral circuit 132. That is, the nonvolatile memory device 130 may have a cell on periphery (COP) structure. However, the inventive concept is not limited thereto, and the nonvolatile memory device 130 may be implemented to have any of various structures.

[0071] The page buffer circuit 133 may include a plurality of page buffers PB1 to PBn, and the plurality of page buffers PB1 to PBn may be connected to the memory cells respectively through a plurality of bit lines BL. For example, n may be an integer of 3 or more. The page buffer circuit 133 may select at least one bit line from the bit lines BL based on the column address Y-ADDR. The page buffer circuit 133 may receive write data from the input / output circuit 137. The page buffer circuit 133 may temporarily store the write data.

[0072] The page buffer circuit 133 may operate as a write driver or a sense amplifier according to the operation mode. For example, during a programming operation, the page buffer circuit 133 may apply a bit line voltage corresponding to the data to be programmed to the selected bit line. In an example, the programming operation may refer to a write operation. During a read operation, the page buffer circuit 133 may detect the data stored in the memory cell by detecting the current or voltage of the selected bit line.

[0073] The control logic circuit 134 may control various operations in the nonvolatile memory device 130. The control logic circuit 134 may output various control signals based on the command CMD and / or the address ADDR. For example, the control logic circuit 134 may output a voltage control signal CTRL_vol, a row address X-ADDR, and a column address Y-ADDR.

[0074] The voltage generator 135 may generate various types of voltages for performing program operations, read operations, and erase operations based on the voltage control signal CTRL_vol. For example, the voltage generator 135 may generate a program voltage, a read voltage, a program verification voltage, and an erase voltage as the word line voltage VWL.

[0075] The row decoder 136 may select at least one of the plurality of word lines WL based on the row address X-ADDR and may select one of the plurality of string selection lines SSL. For example, during a program operation, the row decoder 136 may apply a word line voltage VWL to the selected word line during a search operation or a read operation.

[0076] The input / output circuit 137 may provide data DATA received from the memory controller 120 to the page buffer circuit 133 through the data line DL, or may provide the data DATA received through the data line DL to the memory controller 120. For example, the input / output circuit 137 may send write data received from the memory controller 120 to the page buffer circuit 133. In an embodiment, the input / output circuit 137 may send data DATA to the memory controller 120 and receive data DATA from the memory controller 120 in synchronization with the data strobe signal DQS. In an embodiment, data such as data received through the input / output circuit 137 may be received. Figure 2 The command CMD or address ADDR information shown, and the received information can be provided to each corresponding circuit.

[0077] Refer to Figure 1 and Figure 2 , the memory controller 120 may control the operation of the nonvolatile memory device 130. For example, the memory controller 120 may control the nonvolatile memory device 130 by providing a control signal CTRL and a data signal DQ to the nonvolatile memory device 130 through different signal lines or different signal pins.

[0078] For example, the memory controller 120 may provide a chip enable signal CE / , a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE / , a read enable signal RE / , a data select signal DQS, and a data signal DQ to the nonvolatile memory device 130 through different signal pins.

[0079] A chip enable signal CE / , a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE / , a read enable signal RE / , and a data strobe signal DQS may be included in the control signal CTRL provided from the memory controller 120. The memory controller 120 may provide the control signal CTRL and the data signal DQ to the nonvolatile memory device 130 so that the nonvolatile memory device 130 performs various operations.

[0080] The nonvolatile memory device 130 performs corresponding operations in response to the control signal CTRL and the data signal DQ provided from the memory controller 120. For example, based on the control signal CTRL and the data signal DQ provided from the memory controller 120, the nonvolatile memory device 130 may perform one or more operations corresponding to the control signal CTRL and the data signal DQ. For example, the nonvolatile memory device 130 may receive the data signal DQ including the command CMD and the address ADDR from the memory controller 120, and may provide the stored data DATA to the memory controller 120.

[0081] The nonvolatile memory device 130 may determine whether the signal provided by the data signal DQ is a command CMD, an address ADDR, or data DATA based on the control signal CTRL. For example, the nonvolatile memory device 130 may identify the type of the data signal DQ based on the chip enable signal CE / , the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal WE / , the read enable signal RE / , and the data strobe signal DQS.

[0082] Based on various signals from the memory controller 120, the nonvolatile memory device 130 may store data received from the memory controller 120, or may transmit the stored data to the memory controller 120. In the example case where the nonvolatile memory device 130 performs a program operation or a read operation under the control of the memory controller 120, the nonvolatile memory device 130 may provide a ready / busy signal R / B (or status information) to the memory controller 120. For example, the ready / busy signal R / B may indicate a ready state or a busy state. The memory controller 120 may recognize that the nonvolatile memory device 130 is operating in response to the ready / busy signal R / B. In the example case where the ready / busy signal R / B indicates a busy state, the memory controller 120 may not exchange information (command, address, or data) with the nonvolatile memory device 130.

[0083] In an embodiment, the memory controller 120 may send a set feature command or a program command to the nonvolatile memory device 130 through the control signal CTRL and the data signal DQ. The memory controller 120 may receive error data through the control signal CTRL and the data signal DQ.

[0084] The nonvolatile memory device 130 may receive a set feature command or a program command through the control signal CTRL and the data signal DQ. The nonvolatile memory device 130 may send error data to the memory controller 120 through the control signal CTRL and the data signal DQ.

[0085] In an embodiment, the control logic circuit 134 may include an error detection circuit 138. Before performing a programming operation, the error detection circuit 138 may perform an error detection operation on the write data of the page buffer circuit 133. Before the write data is written into the memory cell array 131, the error detection circuit 138 may detect a pattern abnormality of the write data. The error detection circuit 138 may determine whether a specific pattern is repeated in the write data. According to the reduction of semiconductor processes, the risk of errors occurring due to slight damage of metal lines between the memory cells of the memory cell array 131 and the peripheral circuit 132 of the nonvolatile memory device 130 increases. This error is an error that occurs in recently developed products and is expected to continue to occur in next-generation products.

[0086] In an embodiment, an error due to a metal line defect may occur intermittently when the nonvolatile memory device 130 is powered on / off. For example, when the nonvolatile memory device 130 changes from powered on to powered on or from powered on to powered off, a metal line error may occur between the peripheral circuit 132 and the memory cell.

[0087] Generally, in the event of a programming failure, the memory controller 120 may handle the error by writing back the data stored in the buffer memory 124 to the nonvolatile memory device 130 or writing back the data received from the host device 10 to the nonvolatile memory device 130. However, an exceptional programming error may occur instead of an error that occurs while programming data to the memory cell array 131. For example, an error due to an input / output problem may occur between the memory controller 120 and the nonvolatile memory device 130. Such an exceptional programming error may result in a read failure.

[0088] In other words, the error may occur due to an input / output problem. For example, the error may occur due to an input / output problem between the storage controller 120 and the nonvolatile memory device 130. In this case, the storage device 110 may not detect the error during the programming operation, and may detect the error as a read failure through a read operation of the data in which the error has occurred.

[0089] An input / output error may be an error that occurs equally in all memory banks of the nonvolatile memory device 130. The input / output error may be estimated as an error in the storage controller 120 or a substrate (e.g., a printed circuit board (PCB)), but may also be an error in the nonvolatile memory device 130. For example, among write errors in the nonvolatile memory device 130, a write error in metadata may occur. Due to a write error in metadata, a read failure of metadata may occur. In this case, the storage device 110 may enter an unrecognizable or inoperable state, and therefore, all data stored in the storage device 110 may be lost. The nonvolatile memory device 130 according to an embodiment can prevent a read failure of metadata in advance by detecting a data error in advance before a programming operation.

[0090] As described above, the nonvolatile memory device 130 may perform an error detection operation before programming data into memory cells. Therefore, a nonvolatile memory device 130 having improved reliability may be provided.

[0091] Figure 3 is a diagram illustrating a 3D V-NAND structure applicable to a memory device according to an embodiment.

[0092] In an example case where the nonvolatile memory device of the storage device is implemented as a 3D V-NAND type flash memory, each of a plurality of memory blocks constituting a memory cell array may be represented as follows: Figure 3 The equivalent circuit is shown.

[0093] Figure 3 The memory block BLKi is a 3D memory block formed on a substrate in a 3D structure. For example, a plurality of memory NAND strings included in the memory block BLKi may be formed in a direction perpendicular to the substrate.

[0094] Reference Figure 3 , the memory block BLKi may include a plurality of memory NAND strings NS11 to NS31 connected between a first bit line BL1 and a common source line CSL, NS12 to NS32 connected between a second bit line BL2 and a common source line CSL, and NS13 to NS33 connected between a third bit line BL3 and a common source line CSL. Each of the plurality of memory NAND strings NS11 to NS33 may include a string selection transistor SST, a plurality of memory cells (e.g., a first memory cell to an eighth memory cell MC1, MC2, ... and MC8), and a ground selection transistor GST. Although in Figure 3 Each of the plurality of memory NAND strings NS11 to NS33 includes eight memory cells (eg, MC1, MC2, . . . , and MC8), but the inventive concept is not limited thereto.

[0095] The string selection transistor SST may be connected to the corresponding string selection lines SSL1, SSL2, and SSL3. A plurality of memory cells (e.g., MC1, MC2, ..., and MC8) may be connected to the corresponding gate lines WL1, WL2, ..., and WL8, respectively. The gate lines WL1, WL2, ..., and WL8 may correspond to word lines, and some of the gate lines WL1, WL2, ..., and WL8 may correspond to dummy word lines. The ground selection transistor GST may be connected to the corresponding ground selection lines GSL1, GSL2, and GSL3. The string selection transistor SST may be connected to the corresponding first to third bit lines BL1, BL2, and BL3, and the ground selection transistor GST may be connected to the common source line CSL.

[0096] Word lines (eg, WL1) at the same height may be connected in common, and ground selection lines GSL1, GSL2, and GSL3 and string selection lines SSL1, SSL2, and SSL3 may be separated from each other. Figure 3 The middle memory block BLKi is connected to eight gate lines WL1 , WL2 , . . . , and WL8 and three bit lines (ie, first to third bit lines BL1 , BL2 , and BL3 ), but the inventive concept is not limited thereto.

[0097] Figure 4A , Figure 4B and Figure 4C is a diagram for describing an error in write data according to an embodiment.

[0098] Will refer to Figure 4A , Figure 4B and Figure 4C An example of write data in which an error occurs is described. However, the inventive concept is not limited thereto, and various error patterns may exist, and the size of write data may vary according to implementation.

[0099] Reference Figure 2 , Figure 4A , Figure 4B and Figure 4C , the page buffer circuit 133 may store the first write data WD1, the second write data WD2, and the third write data WD3. The first to third write data WD1, WD2, and WD3 may include an error that occurs during an input / output operation before being written to the memory cell array 131. That is, an error may occur while the write data is sent from the memory controller 120 to the page buffer circuit 133 of the nonvolatile memory device 130.

[0100] For example, the first write data WD1 may have a binary format and may be "32 bits". The first write data WD1 may include multiple bit data. The multiple bit data may be arranged in rows and columns. The first write data WD1 may include "4" rows and "8" columns. For example, the first column data CD1 in the first column C1 may be "0011", the second column data CD2 in the second column C2 may be "1111", the third column data CD3 in the third column C3 may be "0110", the fourth column data CD4 in the fourth column C4 may be "0010", the fifth column data CD5 in the fifth column C5 may be "1001", the sixth column data CD6 in the sixth column C6 may be "1111", the seventh column data CD7 in the seventh column C7 may be "1001", and the eighth column data CD8 in the eighth column C8 may be "1100".

[0101] An error may occur in the second column data CD2 and the sixth column data CD6 of the first write data WD1. The second column data CD2 of the first write data WD1 may include only the first value (e.g., "1"). The sixth column data CD6 of the first write data WD1 may include only the first value (e.g., "1"). That is, the first write data WD1 may include an error in which all bits of the column data in the second column C2 and the sixth column C6 have the same value.

[0102] In an embodiment, the error detection circuit 138 may detect whether a pattern such as the first write data WD1 is repeated. The error detection circuit 138 may determine whether an error exists by determining whether all column data of the write data have the same value. For example, based on determining that all column data of the write data have the same value, the error detection circuit 138 may identify an error.

[0103] For example, the second write data WD2 may have a hexadecimal format and may be "32 bytes". The second write data WD2 may include multiple pieces of byte data. The multiple pieces of byte data may be arranged in rows and columns. The second write data WD2 may include "4" rows and "8" columns. For example, the first column data CD1 in the first column C1 may be "34 2E 2C 3E", the second column data CD2 in the second column C2 may be "A4 93D3 58", the third column data CD3 in the third column C3 may be "FF FF FF FF", the fourth column data CD4 in the fourth column C4 may be "FF FF FF FF", the fifth column data CD5 in the fifth column C5 may be "B6 32 73E3", the sixth column data CD6 in the sixth column C6 may be "D3 44 35 89", the seventh column data CD7 in the seventh column C7 may be "11A2 0041", and the eighth column data CD8 in the eighth column C8 may be "23 72 3B 3F".

[0104] The second write data WD2 may have errors in the third column data CD3 and the fourth column data CD4. The third column data CD3 of the second write data WD2 may include only the third value (e.g., “FF”). The fourth column data CD4 of the second write data WD2 may include only the third value (e.g., “FF”). That is, the second write data WD2 may include an error that all bytes of the column data in the third column C3 and the fourth column C4 have the same value.

[0105] In an embodiment, the error detection circuit 138 may detect whether a pattern such as the second write data WD2 is repeated. The error detection circuit 138 may determine whether an error exists by determining whether all column data of the write data have the same value. In another embodiment, the error detection circuit 138 may determine whether an error exists by determining whether multiple adjacent column data of the write data have the same value.

[0106] For example, the third write data WD3 may have a hexadecimal format and may be "32 bytes". The third write data WD3 may include multiple byte data. The multiple byte data may be arranged in rows and columns. The third write data WD3 may include "4" rows and "8" columns. For example, the first row data RD1 in the first row R1 may be "34A4 FF FF B6 D3 11 23", the second row data RD2 in the second row R2 may be "2E 93 59 4D 32 44A2 72", the third row data RD3 in the third row R3 may be "2C D3FF FF 73 35 00 3B", and the fourth row data RD4 in the fourth row R4 may be "3E 58 8E 0F E3 89 41 3F".

[0107] The third write data WD3 may have errors in part of the first row data RD1 and part of the third row data RD3. Errors may occur in the byte data of the first row R1 and the third column C3 and the byte data of the first row R1 and the fourth column C4 of the third write data WD3, and errors may occur in the byte data of the third row R3 and the third column C3 and the byte data of the third row R3 and the fourth column C4 of the third write data WD3. The third write data WD3 may include the same data, such as a third value (e.g., "FF"), in units of specific multiples.

[0108] In an embodiment, the error detection circuit 138 may detect whether a pattern such as the third write data WD3 is repeated. The error detection circuit 138 may determine whether an error exists by determining whether some row data of the write data have the same value. In another embodiment, the error detection circuit 138 may determine whether an error exists by determining whether some odd (or even, or a specific multiple) row data of the write data have the same value.

[0109] As described above, write data may include various patterns of errors due to input / output errors. Error detection circuit 138 may detect various patterns of errors.

[0110] Figure 5 is a flowchart illustrating an operating method of a storage device according to an embodiment.

[0111] Reference Figure 1 and Figure 5In operation S101, the memory controller 120 may send a set feature command SET FEATURE to the nonvolatile memory device 130. The set feature command in operation S101 may be a command for setting whether to perform an error detection operation of the nonvolatile memory device 130. The set feature command may indicate whether to perform an error detection operation of the nonvolatile memory device 130. The memory controller 120 may send a set feature command including error detection enable information to the nonvolatile memory device 130.

[0112] In operation S102, the storage controller 120 may send a program command and write data to the non-volatile memory device 130. The program command may include an address indicating an area of ​​a memory cell storing 1-bit data. For example, the storage controller 120 may store data requiring high reliability in the SLC area. For example, the high reliability data may include, but is not limited to, metadata. The storage controller 120 may instruct the non-volatile memory device 130 to perform an error detection operation on the data requiring high reliability before performing a program operation.

[0113] In operation S103, the nonvolatile memory device 130 may perform an error detection operation. The nonvolatile memory device 130 may perform an error detection operation based on a set feature command including error detection enable information and a program command. The nonvolatile memory device 130 may determine whether there is an error in the write data of the page buffer circuit 133. For example, the nonvolatile memory device 130 may determine whether the same pattern is repeated in the write data in the page buffer circuit 133.

[0114] In operation S104, the nonvolatile memory device 130 may determine whether the write data includes an error. In the case where the nonvolatile memory device 130 determines that the write data includes an error, the nonvolatile memory device 130 performs operation S105, and in the case where the nonvolatile memory device 130 determines that the write data does not include an error, the nonvolatile memory device 130 performs operation S110.

[0115] In operation S105, the nonvolatile memory device 130 may transmit error data to the memory controller 120. For example, the nonvolatile memory device 130 may transmit write data of the page buffer circuit 133 as error data to the memory controller 120. During a programming operation in which an error detection operation is not performed, the nonvolatile memory device 130 does not transmit data to the memory controller 120. However, in a programming operation in which an error detection operation is performed, in the case where an error is detected in write data, the nonvolatile memory device 130 may transmit error data to the memory controller 120.

[0116] In operation S106, the memory controller 120 may perform an error correction operation. In response to receiving error data from the nonvolatile memory device 130, the memory controller 120 may perform an error correction operation on the error data. The memory controller 120 may detect and correct errors in data provided by the nonvolatile memory device 130.

[0117] In operation S107, the memory controller 120 may determine whether UECC of erroneous data occurs. In the case where UECC occurs, the memory controller 120 performs operation S108, and in the case where UECC does not occur, the memory controller 120 performs operation S109.

[0118] In operation S108, the memory controller 120 and the non-volatile memory device 130 may perform an input / output adjustment operation. For example, in the event of a UECC, the memory controller 120 may adjust the voltage input to the non-volatile memory device 130. That is, in the event that an error is not corrected, the memory controller 120 may adjust the voltage input to the non-volatile memory device 130. For example, the memory controller 120 may increase or decrease the power supply voltage VCC. The memory controller 120 may increase or decrease the input / output voltage VCCQ. The memory controller 120 may optimize the input / output of the non-volatile memory device 130. Next, the memory controller 120 performs operation S109.

[0119] In operation S109, the memory controller 120 may send a resume command RESUMECMD to the nonvolatile memory device 130. For example, in the case where the UECC does not occur, the memory controller 120 may send a resume command for the program operation. That is, in the case where the error is corrected, the memory controller 120 may send a resume command for the program operation. The memory controller 120 may resume the stopped program operation.

[0120] In operation S110, the nonvolatile memory device 130 may perform a program operation. In the case where no error is detected, the nonvolatile memory device 130 may program write data to the memory cells.

[0121] although Figure 5 The operation method of the storage device is shown, but the present disclosure is not limited thereto. Therefore, according to another embodiment, in addition to Figure 5 In addition to the operations shown, other operations may be performed. According to an embodiment, the order of operations in the method for operating a storage device is not limited to Figure 5 Examples in .

[0122] As described above, according to an embodiment, the memory device 110 can detect errors in data before programming (or writing) the data to the memory cell. The memory device 110 can reduce errors of the memory device 110 by performing an error detection operation on data requiring reliability. The data reliability of the memory device 110 can be improved.

[0123] Figure 6 is a flowchart illustrating an operating method of a memory controller according to an embodiment.

[0124] Reference Figure 1 , Figure 2 and Figure 6 In operation S201, the memory controller 120 may send a set feature command. The memory controller 120 may send a set feature command to enable error detection. In operation S202, the variable K may be set to 1. For example, the variable K is used to describe an operation of repeatedly sending a program command based on an error of the nonvolatile memory device 130. However, the scope of the inventive concept is not limited to Figure 6 Example operation shown.

[0125] In operation S203, the memory controller 120 may send a program command and write data to the nonvolatile memory device 130. For example, the write data may be metadata requiring high reliability. The program command may be a program command for writing the write data to the SLC area.

[0126] In operation S204, the storage controller 120 may determine whether error data is received from the nonvolatile memory device 130. For example, in the case where the nonvolatile memory device 130 detects an error by performing an error detection operation before the programming operation, the nonvolatile memory device 130 may send error data to the storage controller 120. The storage controller 120 may receive the error data. In the case where the storage controller 120 receives the error data from the nonvolatile memory device 130, the storage controller 120 performs operation S205, and in the case where the storage controller 120 does not receive the error data from the nonvolatile memory device 130, the storage controller 120 does not perform the following operations. In the case where the storage controller 120 does not receive the error data, the storage controller 120 may recognize that no error occurs in the write data. In this case, the storage controller 120 may complete the programming operation.

[0127] In operation S205, the memory controller 120 may perform an error correction operation. The memory controller 120 may perform an error correction operation on data received from the nonvolatile memory device 130. For example, the ECC engine 125 of the memory controller 120 may perform an error correction operation on erroneous data received from the nonvolatile memory device 130.

[0128] In operation S206, the memory controller 120 may determine whether UECC has occurred. The memory controller 120 may determine whether the error correction operation has failed. In the case where the error data includes an error that exceeds the error correction capability of the ECC engine 125, the memory controller 120 may determine that the error correction operation has failed. In the case where UECC has occurred, the memory controller 120 performs operation S208, and in the case where UECC has not occurred, the memory controller 120 performs operation S207. For example, based on the error being uncorrected or uncorrectable, the memory controller 120 performs operation S208, and based on the error being corrected, the memory controller 120 performs operation S207.

[0129] In operation S207, the memory controller 120 may send a resume command. The memory controller 120 may resume the program operation again because the memory controller 120 may correct the error through the error correction operation.

[0130] In operation S208, the memory controller 120 may adjust an input / output of the nonvolatile memory device 130. The memory controller 120 may adjust a power supply voltage or an input / output voltage input to the nonvolatile memory device 130 in order to prevent a metal line error.

[0131] In operation S209, the storage controller 120 may determine whether the variable K is a maximum value. The maximum value may be a predetermined value. The maximum value may be selected by the designer, manufacturer, and / or user to be fixed or variable. After performing the input / output adjustment operation, the storage controller 120 may determine whether the program count (which is the number of times a program command is sent for the same address) is equal to or greater than a threshold value. In the case where the variable K is a maximum value, the storage controller 120 performs operation S211, and in the case where the variable K is not a maximum value, the storage controller 120 performs operation S210.

[0132] In operation S210, the memory controller 120 may increase the variable K by 1. Next, the memory controller 120 may perform operation S203. Because the memory controller 120 fails to correct the error detected by the nonvolatile memory device 130, the memory controller 120 may resend the program command. That is, based on the memory controller 120 determining that the program count is less than the threshold value, the memory controller 120 may resend the program command and write data to the nonvolatile memory device 130. The memory controller 120 may request the nonvolatile memory device 130 to perform the error detection operation and the programming operation again so that data without error is written to the memory cell array 131.

[0133] In operation S211, the memory controller 120 may record a program failure. In the case where an error is detected while the memory controller 120 repeatedly performs the program operation a maximum number of times and the error is not corrected, the memory controller 120 may determine that the program has failed, and may store information about the program failure in the memory. For example, based on the memory controller 120 determining that the program count is equal to or greater than a threshold value, the memory controller 120 may determine that the program has failed, and may store information about the program failure. The memory controller 120 may store information about the program failure in a log page.

[0134] As described above, the memory controller 120 may request the nonvolatile memory device 130 to perform an error detection operation, may receive error data from the nonvolatile memory device 130, and may perform an error correction operation on the error data. In addition, the memory controller 120 may repeatedly send a program command to store data that does not include an error or correctable data in the memory cell array 131.

[0135] Figure 7 is a flowchart illustrating an operating method of a nonvolatile memory device according to an embodiment.

[0136] Reference Figure 1 , Figure 2 and Figure 7 In operation S310, the nonvolatile memory device 130 may receive a set feature command. The nonvolatile memory device 130 may receive a set feature command including error detection enable information from the memory controller 120. Operation S310 may be omitted. The nonvolatile memory device 130 may not perform operation S310.

[0137] For example, the storage controller 120 may send one set feature command, and in the case where the error of the error data is not corrected, may send a plurality of programming commands. That is, the nonvolatile memory device 130 may receive one set feature command, and may receive a plurality of programming commands. Therefore, in the case where the nonvolatile memory device 130 has already received the set feature command including the error detection enabling information, the nonvolatile memory device 130 may not receive the set feature command again. However, the present disclosure is not limited thereto, and therefore, according to another embodiment, the set feature command may be sent again corresponding to each of the plurality of programming commands.

[0138] In operation S320, the nonvolatile memory device 130 may receive a program command and write data. The program command may include an address corresponding to the SLC region, but the inventive concept is not limited thereto. The program command may include an address corresponding to the MLC region.

[0139] In operation S330, the nonvolatile memory device 130 may perform an error detection operation. The nonvolatile memory device 130 may detect an error that occurs before a programming operation. The nonvolatile memory device 130 may pre-check errors that exist in data to be programmed. The nonvolatile memory device 130 may determine whether data is damaged by verifying write data of the page buffer circuit 130 before programming the data to the memory cell.

[0140] In operation S340, the nonvolatile memory device 130 may determine whether the write data includes an error. If the write data includes an error, the nonvolatile memory device 130 performs operation S350, and if the write data does not include an error, the nonvolatile memory device 130 performs operation S360.

[0141] In operation S350, the nonvolatile memory device 130 may transmit error data to the memory controller 120. The nonvolatile memory device 130 may output write data as error data to the data line.

[0142] In operation S360, the nonvolatile memory device 130 may perform a program operation. Since the write data does not include an error, the nonvolatile memory device 130 may program the write data to the memory cell array 131. The nonvolatile memory device 130 may write the write data of the page buffer circuit 133 to the memory cell.

[0143] As described above, the nonvolatile memory device 130 may perform an error detection operation before programming the write data of the page buffer circuit 133 to the memory cell. The nonvolatile memory device 130 may determine whether the write data is damaged by performing the error detection operation. The nonvolatile memory device 130 may enhance data integrity by performing the error detection operation.

[0144] Figure 8 is a diagram showing a method according to an embodiment of the present invention. Figure 7 Flow chart of operation S330.

[0145] Reference Figure 1 , Figure 7 and Figure 8 , Figure 7 Operation S330 may include Figure 8 The nonvolatile memory device 130 may perform an error detection operation before writing data into the memory cell array in response to a program command. The nonvolatile memory device 130 may perform an error detection operation based on a plurality of detection strategies.

[0146] In an embodiment, the nonvolatile memory device 130 may perform error detection operations using multiple detection strategies in response to various error patterns. For example, a first detection strategy may correspond to a first error pattern, and a second detection strategy may correspond to a second error pattern. The first detection strategy may be a strategy for detecting the first error pattern. The second detection strategy may be a strategy for detecting the second error pattern.

[0147] In operation S331, the nonvolatile memory device 130 may detect errors in write data based on a first detection strategy. In order to detect a first error pattern, the nonvolatile memory device 130 may detect errors in write data using the first detection strategy.

[0148] In operation S332, the nonvolatile memory device 130 may determine whether an error in the write data is detected. The nonvolatile memory device 130 may determine whether an error in the write data is detected based on the first detection strategy. In the case where an error is detected, the nonvolatile memory device 130 performs operation S350, and in the case where an error is not detected, the nonvolatile memory device 130 performs operation S333.

[0149] In the case that the nonvolatile memory device 130 detects an error based on the first detection strategy, the nonvolatile memory device 130 may send write data to the memory controller 120. Because the nonvolatile memory device 130 detects an error, the nonvolatile memory device 130 may not use another detection strategy.

[0150] In operation S333, the nonvolatile memory device 130 may detect errors in the write data based on the second detection strategy. To detect the second error pattern, the nonvolatile memory device 130 may detect errors in the write data using the second detection strategy. Next, the nonvolatile memory device 130 performs operation S340.

[0151] As described above, the nonvolatile memory device 130 may perform error detection operations based on a plurality of detection strategies. Therefore, the nonvolatile memory device 130 may detect various patterns of errors.

[0152] Fig. 9A and Fig. 9B is a diagram for describing the operation of the nonvolatile memory device according to the embodiment. Fig.10 It is shown Figure 8 Flow chart of operation S331. Fig.11A and Fig. 11B is a diagram for describing the operation of the nonvolatile memory device according to the embodiment.

[0153] Reference Figure 8 , Fig. 9A , Fig. 9B , Fig.10 , Fig.11A and Fig. 11B , Figure 8 Operation S331 may include operations S410 to S430, and operation S332 may include operations S440 to S460. In operation S410, the nonvolatile memory device 130 may align the write data. In an embodiment, the error detection circuit 138 may realign the write data of the page buffer circuit 133. The error detection circuit 138 may align the write data based on the physical column address.

[0154] exist Fig. 9A In the description, the Figure 4A A method of programming data in the first row R1 (i.e., first row data RD1) to the memory cell array 131. The first row data RD1 of the first write data WD1 may include first bit data BD1 to eighth bit data BD8. The memory cell array 131 may include first memory cells MC1 to eighth memory cells MC8. The first memory cells MC1 to eighth memory cells MC8 may be connected to the word line WL. The first memory cell MC1 may be connected to the first bit line BL1, the second memory cell MC2 may be connected to the second bit line BL2, the third memory cell MC3 may be connected to the third bit line BL3, the fourth memory cell MC4 may be connected to the fourth bit line BL4, the fifth memory cell MC5 may be connected to the fifth bit line BL5, the sixth memory cell MC6 may be connected to the sixth bit line BL6, the seventh memory cell MC7 may be connected to the seventh bit line BL7, and the eighth memory cell MC8 may be connected to the eighth bit line BL8.

[0155] In an embodiment, the host device 10 may send the first write data WD1 aligned based on the logical address to the memory device 110. The memory controller 120 may send the first write data WD1 to the nonvolatile memory device 130. The page buffer circuit 133 may store the first write data WD1. The first row data RD1 of the first write data WD1 may be configured based on the logical address. That is, in the first write data WD1, the first bit data BD1 to the eighth bit data BD8 may be arranged based on the logical address.

[0156] However, the first bit data BD1 to the eighth bit data BD8 may not be stored in the first memory cell MC1 to the eighth memory cell MC8 based on the logical address (or sequentially). The first bit data BD1 may be stored in the first memory cell MC1, the fifth bit data BD5 may be stored in the second memory cell MC2, the second bit data BD2 may be stored in the third memory cell MC3, the sixth bit data BD6 may be stored in the fourth memory cell MC4, the third bit data BD3 may be stored in the fifth memory cell MC5, the seventh bit data BD7 may be stored in the sixth memory cell MC6, the fourth bit data BD4 may be stored in the seventh memory cell MC7, and the eighth bit data BD8 may be stored in the eighth memory cell MC8. Therefore, adjacent bit data in the write data may not be stored in adjacent memory cells.

[0157] For example, in the case where the first bit data BD1 to the eighth bit data BD8 are aligned in the order stored in the memory cells (i.e., referring to the first alignment row data ARD1), the first column C1 may be the first bit data BD1, the second column C2 may be the fifth bit data BD5, the third column C3 may be the second bit data BD2, the fourth column C4 may be the sixth bit data BD6, the fifth column C5 may be the third bit data BD3, the sixth column C6 may be the seventh bit data BD7, the seventh column C7 may be the fourth bit data BD4, and the eighth column C8 may be the eighth bit data BD8.

[0158] exist Fig. 9B In the following, the first write data WD1 and the first aligned write data AWD1 will be described. The first write data WD1 has been referred to Figure 4A Description, therefore, its detailed description will be omitted. The error detection circuit 138 may generate the first aligned write data AWD1 based on the first write data WD1. The first column data CD1 of the first aligned write data AWD1 may be "0011", the second column data CD2 may be "1001", the third column data CD3 may be "1111", the fourth column data CD4 may be "1111", the fifth column data CD5 may be "0110", the sixth column data CD6 may be "1001", the seventh column data CD7 may be "0010", and the eighth column data CD8 may be "1100".

[0159] The error detection circuit 138 may determine whether a specific pattern is repeated based on the aligned write data. For example, the error detection circuit 138 may determine whether an error exists by determining whether all of a plurality of adjacent column data of the write data have the same value. An error may occur in the third column data CD3 and the fourth column data CD4 of the first aligned write data AWD1.

[0160] In operation S420, the error detection circuit 138 may divide the aligned write data into a plurality of groups. For example, the error detection circuit 138 may divide the first aligned write data AWD1 into a first group G1, a second group G2, a third group G3, and a fourth group G4. Fig.11A As shown, the first group G1 may include the first column data CD1 and the second column data CD2, the second group G2 may include the third column data CD3 and the fourth column data CD4, the third group G3 may include the fifth column data CD5 and the sixth column data CD6, and the fourth group G4 may include the seventh column data CD7 and the eighth column data CD8.

[0161] In operation S430, the error detection circuit 138 may count the on / off cells of each group. For example, in the case of counting the off cells of the write data, it may mean counting the number of bit data having a first value (e.g., "1"), and in the case of counting the on cells of the write data, it may mean counting the number of bit data having a second value (e.g., "0"). However, the present disclosure is not limited thereto, and therefore, according to another embodiment, the first value (e.g., "1") may be counted as the on cell of the write data, and the second value (e.g., "0") may be counted as the off cell of the write data.

[0162] In an embodiment, the error detection circuit 138 may count a first value (e.g., “1”) in the write data or aligned write data as a first count C1. The error detection circuit 138 may count a second value (e.g., “0”) in the write data or aligned write data as a second count C2. Fig. 11B As shown, in the first aligned write data AWD1, the first count C1 of the first group G1 may be "4", and the second count C2 of the first group G1 may be "4". In the first aligned write data AWD1, the first count C1 of the second group G2 may be "8", and the second count C2 of the second group G2 may be "0". In the first aligned write data AWD1, the first count C1 of the third group G3 may be "4", and the second count C2 of the third group G3 may be "4". In the first aligned write data AWD1, the first count C1 of the fourth group G4 may be "3", and the second count C2 of the fourth group G4 may be "5".

[0163] In operation S440, the nonvolatile memory device 130 may determine whether the difference DIFF is greater than a threshold value. The threshold value may be a predetermined value. For example, the difference DIFF may be an absolute value of the difference between the first count C1 and the second count C2. For example, the difference DIFF may be obtained by subtracting the first count C1 from the second count C2 or by subtracting the second count C2 from the first count C1. In an embodiment, the error detection circuit 138 may compare the difference of the on / off unit with a threshold value. For example, the error detection circuit 138 may compare the difference between the first count C1 and the second count C2 with a threshold value. In the case where the difference DIFF is greater than the threshold value, the nonvolatile memory device 130 performs operation S450, and in the case where the difference DIFF is equal to or less than the threshold value, the nonvolatile memory device 130 performs operation S460.

[0164] For example, the error detection circuit 138 may compare the difference DIFF with a threshold value for each group. The error detection circuit 138 may calculate the difference of each group. The error detection circuit 138 may calculate the difference DIFF based on the first count C1 and the second count C2. In the first alignment write data AWD1, the difference DIFF of the first group G1 may be "0", the difference DIFF of the second group G2 may be "8", the difference DIFF of the third group G3 may be "0", and the difference DIFF of the fourth group G4 may be "2".

[0165] In operation S450, the nonvolatile memory device 130 may determine that there is an error in the write data. In the case where the difference between the first count C1 and the second count C2 is greater than the threshold value, the error detection circuit 138 may determine that an error has occurred. Next, the nonvolatile memory device 130 performs operation S350. For example, based on determining that the write data includes an error, the nonvolatile memory device 130 may send the write data to the storage controller 120.

[0166] In operation S460, the nonvolatile memory device 130 may determine that there is no error in the write data. In the case where the difference between the first count C1 and the second count C2 is equal to or less than the threshold value, the error detection circuit 138 may determine that no error has occurred. Next, the nonvolatile memory device 130 performs operation S333. For example, based on determining that the write data does not include an error, the nonvolatile memory device 130 may detect an error based on a second detection strategy. That is, in the case where the nonvolatile memory device 130 fails to detect an error based on the first detection strategy, the nonvolatile memory device 130 may detect an error using a second detection strategy that is different from the first detection strategy. However, the present disclosure is not limited thereto, and therefore, according to another embodiment, error detection based on the second detection strategy may not be performed.

[0167] In the example case where the threshold is "7", the error detection circuit 138 may determine that the difference DIFF ("0") of the first group G1 is equal to or less than the threshold. That is, the error detection circuit 138 may determine that there is no error in the first group G1. According to another embodiment, the threshold may be different from "7". Regarding the second group G2, the error detection circuit 138 may determine that the difference DIFF ("8") of the second group G2 is greater than the threshold. That is, the error detection circuit 138 may determine that there is an error in the second group G2. Regarding the third group G3, the error detection circuit 138 may determine that the difference DIFF ("0") is equal to or less than the threshold. That is, the error detection circuit 138 may determine that there is no error in the third group G3. Regarding the fourth group G4, the error detection circuit 138 may determine that the difference DIFF ("2") is equal to or less than the threshold. That is, the error detection circuit 138 may determine that there is no error in the fourth group G4. Because the error detection circuit 138 determines that an error occurs in the second group G2 among the plurality of groups G1 to G4 , the error detection circuit 138 may transmit the first write data WD1 as error data to the memory controller 120 .

[0168] As described above, the nonvolatile memory device 130 may align the write data, and may detect an error based on the aligned write data. The nonvolatile memory device 130 may detect an error using an on / off unit count of the aligned write data. However, the inventive concept is not limited thereto. For example, the nonvolatile memory device 130 may count a first value in the write data as a first count, and may count a second value in the write data as a second count. The nonvolatile memory device 130 may determine whether the difference between the first count and the second count is greater than a threshold. In the case where the difference between the first count and the second count is greater than a threshold, the nonvolatile memory device 130 may determine that an error has occurred. In the case where the difference between the first count and the second count is equal to or less than a threshold, the nonvolatile memory device 130 may determine that no error has occurred. Therefore, the nonvolatile memory device 130 may detect an error using an on / off unit count of the write data stored in the page buffer circuit and not aligned.

[0169] Fig.12 is a diagram showing a method according to an embodiment of the present invention. Figure 8 Flow chart of operation S333 of FIG.

[0170] Reference Figure 8 and Fig.12 , Figure 8Operation S333 may include operations S510 to S540. However, the present disclosure is not limited thereto, and therefore, operation S333 may include other operations or omit some operations. In operation S510, the nonvolatile memory device 130 may align the write data. For example, the nonvolatile memory device 130 may align the write data based on the physical column address. In an embodiment, operation S510 may be omitted. In the case of aligning the write data when an error is detected based on the first detection strategy, the error detection circuit 138 may not perform the operation of aligning the write data.

[0171] In operation S520, the nonvolatile memory device 130 may determine whether data having the same value is repeated. For example, the error detection circuit 138 may determine whether data having the same value (e.g., 0X00 or 0XFF) is repeated in units of physical columns in the aligned write data. In an embodiment, the error detection circuit 138 may determine whether data having the same value is repeated in units of logical columns or in units of specific multiples based on the logical address in the write data. The error detection circuit 138 may determine whether all column data of the write data or the aligned write data have the same value. In the case where the nonvolatile memory device 130 determines that data having the same value is repeated, the nonvolatile memory device 130 performs operation S530, and in the case where the nonvolatile memory device 130 determines that data having the same value is not repeated, the nonvolatile memory device 130 performs operation S540.

[0172] In operation S530, the nonvolatile memory device 130 may determine that an error exists. The nonvolatile memory device 130 may determine that an error exists because data having the same value is repeated in the write data (or aligned write data). Next, the nonvolatile memory device 130 performs operation S350. That is, the nonvolatile memory device 130 may send error data to the memory controller 120.

[0173] In operation S540, the nonvolatile memory device 130 may determine that there is no error. The nonvolatile memory device 130 may determine that there is no error because data having the same value is not repeated in the write data (or aligned write data). Next, the nonvolatile memory device 130 performs operation S360. That is, the nonvolatile memory device 130 may write the write data to the memory cell array 131.

[0174] As described above, the nonvolatile memory device 130 may detect errors in the write data based on the second detection strategy. In an embodiment, the nonvolatile memory device 130 may detect errors in the aligned write data based on the second detection strategy. The nonvolatile memory device 130 may determine whether the write data or all column data in the aligned write data have the same value.

[0175] Fig.13 and Fig.14 is a diagram for describing the operation of the nonvolatile memory device according to the embodiment.

[0176] Reference Fig.13 and Fig.14 , the non-volatile memory device 130 may perform an error detection operation. The non-volatile memory device 130 may detect errors in the written data using the first detection strategy or the second detection strategy. In an embodiment, the non-volatile memory device 130 may detect errors in the aligned written data using multiple detection strategies.

[0177] In an embodiment, the error detection circuit 138 may align the write data. The error detection circuit 138 may generate alignment data by aligning the write data. For example, the write data may be data based on a logical address. In an embodiment, the error detection circuit 138 may align the write data based on a physical address. In an embodiment, the error detection circuit 138 may align the write data by dividing the write data into a plurality of parts and arranging the parts of the write data into a plurality of columns. However, the scope of the inventive concept is not limited thereto, and the error detection circuit 138 may align the write data in various ways.

[0178] Reference Fig.13 , the fourth write data WD4 may have a hexadecimal format and may be "32 bytes". For example, the fourth write data WD4 may be "41 84FF FF 70 37 6F76 99B9 FF FF C3 FA 3B 05E2 51FF FF F4 C1E2 AE 37 14FF FF 2D D2 09 52". The fourth write data WD4 may include a "1" row and a "32" column. The error detection circuit 138 may detect errors using a first strategy. For example, the error detection circuit 138 may align the fourth write data WD4. The error detection circuit 138 may generate the first alignment data AD1 by aligning the fourth write data WD4.

[0179] The error detection circuit 138 may align the write data based on the alignment of the logical address corresponding to the physical address. For example, the error detection circuit 138 may generate the first alignment data AD1 by aligning the fourth write data WD4 based on the physical address. For example, the first alignment data AD1 may be "4199E2 37 84B9 51 14FF FF FF FF FF FF FF FF 70C3 F4 2D 37FAC1 D2 6F 3B E2 09 76 05AE 52".

[0180] The error detection circuit 138 may divide the first alignment data AD1 into a plurality of groups. The error detection circuit 138 may divide the data into a plurality of groups so that one group includes a predetermined number of bit data. For example, the number of byte data included in one group may be "8". That is, the error detection circuit 138 may divide the first alignment data AD1 into a first group G1 to a fourth group G4. The first group G1 may include data from the first column C1 to the eighth column C8, the second group G2 may include data from the ninth column C9 to the sixteenth column C16, the third group G3 may include data from the seventeenth column C17 to the twenty-fourth column C24, and the fourth group G4 may include data from the twenty-fifth column C25 to the thirty-second column C32.

[0181] The error detection circuit 138 may count the on / off cells of each of the plurality of groups. That is, the error detection circuit 138 may count the first count C1 and the second count C2 of each of the plurality of groups. The error detection circuit 138 may compare the difference between the on cell and the off cell with the first threshold. That is, the error detection circuit 138 may calculate the difference DIFF of each group based on the first count C1 and the second count C2. The error detection circuit 138 may compare the difference DIFF of each group with the first threshold. For example, because the second group G2 is "FF FF FF FF FF FF FF FF", the difference DIFF of the second group G2 may be greater than the first threshold. The error detection circuit 138 may determine that an error has occurred.

[0182] In an embodiment, the error detection circuit 138 may detect errors using a second detection strategy. The error detection circuit 138 may determine whether data having the same value is repeated. For example, the error detection circuit 138 may determine whether a specific pattern is repeated in the data. The error detection circuit 138 may determine whether the same value is repeated in units of a specific multiple in the data. In an embodiment, the error detection circuit 138 may determine whether all consecutive column data in the data have the same value.

[0183] In an embodiment, when data of columns equal to or greater than the second threshold value have the same value, the error detection circuit 138 may determine that an error has occurred. In an example case, the second threshold value may be "4". The error detection circuit 138 may determine whether data of consecutive columns have the same value based on the logical address. The error detection circuit 138 may determine whether data of columns equal to or greater than the second threshold value in the fourth write data WD4 have the same value. Fig.13 In the fourth write data WD4, because the data of the third column C3 and the fourth column C4 are the same, the data of the 11th column C11 and the 12th column C12 are the same, the data of the 19th column C19 and the 20th column C20 are the same, and the data of the 27th column C27 to the 28th column C28 are the same, but these columns are not consecutive columns equal to or greater than the second threshold, it can be determined that there is no error.

[0184] The error detection circuit 138 may apply a second detection strategy to the first alignment data AD1 based on the physical address alignment. The error detection circuit 138 may detect an error based on the first alignment data AD1. The error detection circuit 138 may determine whether the data of the columns equal to or greater than the second threshold value in the first alignment data AD1 have the same value. In the first alignment data AD1, since the data of the ninth column C9 to the sixteenth column C16 are the same, and these columns are continuous columns equal to or greater than the second threshold value, it may be determined that an error has occurred. Therefore, the error detection circuit 138 may not detect an error in the data arranged based on the logical address, but may detect an error in the alignment data arranged based on the physical address.

[0185] In an embodiment, the error detection circuit 138 can align the write data by dividing the write data into a plurality of parts and arranging the parts of the write data into a plurality of columns. The error detection circuit 138 can divide the write data into units of predetermined bits or predetermined bytes. The error detection circuit 138 can divide the write data and can align the data including the plurality of columns. That is, the error detection circuit 138 can divide the write data into a plurality of parts in a predetermined unit and can arrange the parts of the write data into a plurality of columns.

[0186] Reference Fig.14 , the error detection circuit 138 may generate the second alignment data AD2 by aligning the fourth write data WD4. For example, the second alignment data AD2 may include "2" rows and "16" columns. That is, the first row data RD1 of the second alignment data AD2 may be "41 84FF FF 7037 6F 76 99B9 FF FF C3 FA 3B 05", and the second row data RD2 of the first alignment data AD1 may be "E2 51FF FF F4 C1 E2 AE 37 14FF FF 2D D2 09 52". For example, the error detection circuit 138 may divide the fourth write data WD4 into units of "16 bytes". The error detection circuit 138 may divide the fourth write data WD4 into units of "16 bytes", and may align the fourth write data WD4 to data including a plurality of columns.

[0187] For example, the error detection circuit 138 may determine whether the data of consecutive columns have the same value in both the first row data RD1 and the second row data RD2. The error detection circuit 138 may determine whether the consecutive column data have the same value. Because the data of the consecutive third column C3 and the fourth column C4 have the third value (e.g., “FF”) and the data of the consecutive 11th column C11 and the 12th column C12 have the third value (e.g., “FF”), the error detection circuit 138 may determine that an error has occurred.

[0188] Fig.15 is a diagram showing a method according to another embodiment Figure 7 Flow chart of operation S330.

[0189] Reference Figure 7 and Fig.15 , Figure 7 Operation S330 may include operations S610 to S650. In an embodiment, the nonvolatile memory device 130 may use a plurality of detection strategies to detect errors of various patterns. The nonvolatile memory device 130 may use a plurality of detection strategies to perform error detection operations.

[0190] In operation S610 , the variable i may be set to 1. For example, the variable i is used to describe an operation of repeatedly performing an error detection operation using a plurality of detection strategies of the nonvolatile memory device 130 , and does not limit the scope of the inventive concept.

[0191] In operation S620, the nonvolatile memory device 130 may detect an error based on the i-th detection strategy. The nonvolatile memory device 130 may detect an error pattern corresponding to the i-th detection strategy. In operation S630, the nonvolatile memory device 130 may determine whether an error has occurred in the write data. When an error is detected, the nonvolatile memory device 130 may perform operation S350. That is, in the case where an error is detected, the nonvolatile memory device 130 may send error data to the storage controller 120. In the case where no error is detected, the nonvolatile memory device 130 may perform operation S640.

[0192] In operation S640, the nonvolatile memory device 130 may determine whether the variable i is a maximum value. The maximum value may be a predetermined value. The maximum value may indicate the number of detection strategies. In the case where the variable i is a maximum value, the nonvolatile memory device 130 may perform operation S360. That is, the nonvolatile memory device 130 may write write data to the memory cell array 131. In the case where the variable i is not a maximum value, the nonvolatile memory device 130 performs operation S650. In operation S650, the nonvolatile memory device 130 may increase the variable i by 1. Next, the nonvolatile memory device 130 may perform operation S620. Because the nonvolatile memory device 130 fails to detect an error, the nonvolatile memory device 130 may use another detection strategy to detect an error.

[0193] Fig.16 is a flowchart illustrating an operating method of a storage device according to an embodiment.

[0194] In operation S710, the memory controller 120 may send a set feature command including error detection enable information to the nonvolatile memory device 130. The nonvolatile memory device 130 may receive the set feature command. In operation S720, the nonvolatile memory device 130 may set an error detection (ED) flag. The nonvolatile memory device 130 may set the error detection flag based on the set feature command including the error detection enable information. For example, in response to receiving the set feature command including the error detection enable information, the nonvolatile memory device 130 may set the error detection flag.

[0195] In an embodiment, the error detection flag may be a flag indicating whether the nonvolatile memory device 130 is to perform an error detection operation when a program command is received. For example, in the case where the error detection flag is set, the nonvolatile memory device 130 may perform an error detection operation before writing data to the memory cell array 131 when a program command is received. In the case where the error detection flag is cleared, the nonvolatile memory device 130 may write data to the memory cell array 131 without performing an error detection operation when a program command is received.

[0196] In operation S730, the memory controller 120 may send a program command and write data. The nonvolatile memory device 130 may receive the program command and write data. In operation S740, the nonvolatile memory device 130 may determine whether the error detection flag is set. In the case where the error detection flag is set, the nonvolatile memory device 130 performs operation S750, and in the case where the error detection flag is not set, the nonvolatile memory device 130 performs operation S760.

[0197] In operation S750, the nonvolatile memory device 130 may perform an error detection operation. For example, when an error is detected, the nonvolatile memory device 130 may send write data of the page buffer circuit 133 to the memory controller 120. In operation S760, the nonvolatile memory device 130 may perform a programming operation. The nonvolatile memory device 130 may program the write data to the memory cell.

[0198] In operation S770, the storage controller 120 may send a set feature command including error detection disabling information to the nonvolatile memory device 130. When programming of data requiring high reliability is completed, the storage controller 120 may request the nonvolatile memory device 130 not to perform an error detection operation for a subsequent program command. For general user data other than metadata, the storage controller 120 may request the nonvolatile memory device 130 to program the data without an error detection operation. However, the present disclosure is not limited thereto, and therefore, the storage controller 120 may request the nonvolatile memory device 130 to perform an error detection operation on various types of data.

[0199] In operation S780, the nonvolatile memory device 130 may clear the error detection flag. For example, the nonvolatile memory device 130 may receive a set feature command including error detection disabling information. The nonvolatile memory device 130 may clear the error detection flag in response to the set feature command including the error detection disabling information.

[0200] As described above, after the program command is completed, the storage controller 120 may send a set feature command including error detection disabling information to the non-volatile memory device 130. The storage controller 120 may use the set feature command to enable or disable error detection of the non-volatile memory device 130. The non-volatile memory device 130 may not perform an error detection operation on data that does not require high reliability. Therefore, the storage device 110 can reduce write latency.

[0201] Fig.17 is a flowchart illustrating an operating method of a storage device according to an embodiment.

[0202] In operation S810, the memory controller 120 may send an error detection programming command and write data to the nonvolatile memory device 130. For example, the error detection programming command may be different from a general programming command. For example, the error detection programming command may be a vendor command. The error detection programming command may be a command for requesting both an error detection operation and a programming operation.

[0203] In operation S820, the nonvolatile memory device 130 may perform an error detection operation. For example, the nonvolatile memory device 130 may perform an error detection operation in response to an error detection program command. In the event that an error is detected in the write data, the nonvolatile memory device 130 may send the write data as error data to the memory controller 120. In operation S830, the nonvolatile memory device 130 may perform a programming operation. The nonvolatile memory device 130 may program the write data to the memory cell.

[0204] In operation S840, the memory controller 120 may send a program command and write data to the nonvolatile memory device 130. In operation S850, the nonvolatile memory device 130 may perform a program operation. For example, the nonvolatile memory device 130 may receive a program command. In response to the program command, the nonvolatile memory device 130 may directly perform a program operation without performing an error detection operation.

[0205] As described above, the memory controller 120 may request the nonvolatile memory device 130 to perform an error detection operation through a vendor command different from the set feature command.

[0206] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A method for operating a storage device including a nonvolatile memory device and a storage controller, the method comprising: sending error detection enabling information by the memory controller to the non-volatile memory device; The storage controller sends a programming command and write data to the non-volatile memory device; performing, by the nonvolatile memory device, an error detection operation on the write data in a page buffer circuit based on the error detection enable information; Based on detecting an error in the write data, sending the write data as error data to the storage controller by the nonvolatile memory device; as well as The write data is programmed, by the nonvolatile memory device, to memory cells in the nonvolatile memory device based on no errors being detected in the write data.

2. The operating method according to claim 1, wherein: Performing the error detection operation includes detecting whether the same pattern is repeated in the write data.

3. The operating method according to claim 1, wherein: The program command includes an address indicating an area of ​​memory cells storing 1-bit data in the nonvolatile memory device.

4. The operating method according to claim 1, further comprising: The storage controller performs one of the following: an error correction operation performed on the error data based on the error data, and an input / output adjustment operation based on the error data being an uncorrectable error; as well as Based on the error being corrected, a recovery command is sent by the memory controller to program the write data.

5. The operating method according to claim 4, wherein: Performing the input / output regulation operation includes regulating a power supply voltage or an input / output voltage input to the nonvolatile memory device.

6. The operating method according to claim 4, further comprising: determining, by the memory controller after performing the input / output adjustment operation, whether a program count, which is the number of times a program command is sent for the same address, is equal to or greater than a threshold; determining, by the memory controller, a program failure and storing information about the program failure based on determining that the program count is equal to or greater than the threshold; as well as Based on determining that the program count is less than the threshold, the program command and the write data are resent by the memory controller to the nonvolatile memory device.

7. The operating method according to claim 1, wherein: Executing the error detection operation includes: performing a first error detection operation based on a first strategy to determine whether an error has occurred in the write data; and Based on not detecting an error in the write data according to the first policy, a second error detection operation is performed based on a second policy to determine whether an error has occurred in the write data, the second policy being different from the first policy.

8. The operating method according to claim 7, wherein: The first error detection operation comprises: counting a first value in the write data as a first count and counting a second value in the write data as a second count; determining whether a difference between the first count and the second count is greater than a threshold; determining that an error has occurred in the write data based on a difference between the first count and the second count being greater than the threshold; and Based on the difference between the first count and the second count being equal to or smaller than the threshold, it is determined that no error has occurred.

9. The operating method according to claim 7, wherein: The first error detection operation comprises: aligning the write data based on a physical column address; dividing the aligned write data into a plurality of groups; and counting the first value in each of the plurality of groups as a first count and counting the second value in each of the plurality of groups as a second count, and for the plurality of groups, determining whether a difference between the first count and the second count for each of the plurality of groups is greater than a threshold; determining that an error has occurred based on a difference between the first count and the second count in one or more of the plurality of groups being greater than the threshold; and Based on the difference between the first count and the second count in each of the plurality of groups being equal to or smaller than the threshold, it is determined that no error has occurred.

10. The operating method according to claim 7, wherein: The second error detection operation includes determining whether all consecutive column data in the write data have the same value.

11. The operating method according to claim 7, wherein: The second error detection operation includes: aligning the write data based on a physical column address; and It is determined whether all consecutive column data in the aligned write data have the same value.

12. The operating method according to claim 1, further comprising: Error detection disable information is sent by the memory controller to the nonvolatile memory device after the program command is completed.

13. A method for operating a non-volatile memory device, the method comprising: receiving error detection enable information from a storage controller; receiving a programming command and write data from the storage controller; performing an error detection operation by detecting whether a same pattern is repeated in the write data of the page buffer circuit based on the error detection enable information; sending the write data as error data to the storage controller based on detecting an error in the write data; as well as Based on no errors being detected in the write data, the write data is programmed to memory cells in the nonvolatile memory device.

14. The operating method according to claim 13, wherein: Receiving the program command and the write data from the memory controller includes receiving a program command including an address indicating an area of ​​memory cells storing 1-bit data in the nonvolatile memory device.

15. The operating method according to claim 13, wherein: Executing the error detection operation includes: counting a first value in the write data as a first count and counting a second value in the write data as a second count; determining whether a difference between the first count and the second count is greater than a threshold; determining that an error has occurred in the write data based on a difference between the first count and the second count being greater than the threshold; and Based on the difference between the first count and the second count being equal to or smaller than the threshold, it is determined that no error has occurred in the write data.

16. The operating method according to claim 13, wherein: The error detection operations performed include: aligning the write data based on a physical column address; dividing the aligned write data into a plurality of groups; counting a first value in each of the plurality of groups as a first count and counting a second value in each of the plurality of groups as a second count; for the plurality of groups, determining whether a difference between the first count and the second count for each of the plurality of groups is greater than a threshold; determining that an error has occurred based on a difference between the first count and the second count in one or more of the plurality of groups being greater than the threshold; and Based on the difference between the first count and the second count in each of the plurality of groups being equal to or smaller than the threshold, it is determined that no error has occurred.

17. The operating method according to claim 13, wherein: Performing the error detection operation includes determining whether all consecutive column data in the write data have the same value.

18. A non-volatile memory device comprising: a memory cell array comprising a plurality of memory cells; an input / output circuit configured to receive write data from a memory controller; a page buffer circuit connected to the memory cell array and configured to temporarily store the write data from the input / output circuit; as well as An error detection circuit is configured to: receiving error detection enable information from the memory controller, performing an error detection operation by detecting whether a same pattern in the write data is repeated before programming the write data into the memory cell array based on the error detection enable information, Based on detecting an error in the write data, sending the write data as error data to the storage controller, and Based on no errors being detected in the write data, the write data is programmed to the plurality of memory cells.

19. The nonvolatile memory device according to claim 18, wherein: The error detection circuit is further configured to: counting a first value in the write data as a first count and counting a second value in the write data as a second count, determining whether a difference between the first count and the second count is greater than a threshold, Based on the difference between the first count and the second count being greater than the threshold, determining that an error has occurred, and Based on the difference between the first count and the second count being equal to or smaller than the threshold, it is determined that no error has occurred.

20. The nonvolatile memory device according to claim 18, wherein: The error detection circuit is further configured to: aligning the write data based on a physical column address, Divide the aligned write data into multiple groups, counting the first value in each of the plurality of groups as a first count and counting the second value in each of the plurality of groups as a second count, for the plurality of groups, determining whether a difference between the first count and the second count is greater than a threshold, determining that an error has occurred based on a difference between the first count and the second count in one or more of the plurality of groups being greater than the threshold, and Based on the difference between the first count and the second count in each of the plurality of groups being equal to or smaller than the threshold, it is determined that no error has occurred.

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