Preparation method of high-voltage-resistant chip and high-voltage-resistant chip

Abstract

According to the preparation method of the high-voltage-resistant chip and the high-voltage-resistant chip, the silicon nitride film with the thickness being at least 6000 angstroms grows on the semi-insulating polycrystalline silicon film, the voltage-resistant bottleneck of a traditional preparation method is successfully broken through, the voltage-resistant capacity of the chip is increased to 3000V or above, the silicon nitride film can effectively restrain the electric leakage phenomenon, and the voltage-resistant performance of the chip is improved. The stability and the reliability of the chip are remarkably improved, the problems of power loss and performance reduction caused by electric leakage are reduced, the service life of the chip is prolonged, and the operation cost of electronic equipment is reduced.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a method for preparing a high-voltage resistant chip and the high-voltage resistant chip. Background Art

[0002] In the context of the rapid development of the semiconductor industry today, the performance improvement of rectifier chips as one of the key electronic components is crucial to meet the growing market demand. At present, the withstand voltage characteristics of most rectifier chips on the market are concentrated in the range of 800-1600V. In order to break through this limitation, the industry generally adopts the method of depositing a semi-insulating polysilicon film on the surface of the chip and continuously increasing the film thickness to increase the withstand voltage characteristics of the chip to more than 2000V (see Chinese invention patent with publication number CN113178388B: Manufacturing method of high-voltage resistant chip and high-voltage resistant chip). However, while this method improves the withstand voltage characteristics, it also brings about the problem of increased leakage, see Table 1, which undoubtedly has a negative impact on the stability and reliability of the chip.

[0003] Table 1 shows that for substrates with the same resistivity and thickness, a semi-insulating polysilicon film was generated. Experiments were conducted in 6 groups to test the film thickness and the withstand voltage and leakage characteristics of the finished chips.

[0004]

[0005] Table 1

[0006] With the rapid advancement of science and technology, the application scenarios of high-power electrical appliances are becoming more and more extensive, and the voltage requirements for rectifier chips are also rising. Existing preparation methods are unable to cope with the higher voltage requirements, and it is difficult to produce high-quality chips that meet both high voltage resistance and low leakage. Summary of the invention

[0007] Based on this, in order to solve the above technical problems, a method for preparing a high-voltage resistant chip is provided.

[0008] The technical solution adopted by the present invention is as follows:

[0009] As a first aspect of the present invention, a method for preparing a high voltage resistant chip is provided, characterized in that it comprises:

[0010] The substrate is subjected to a photolithography process and then etched to form trenches;

[0011] Depositing a semi-insulating polysilicon film and a silicon nitride film sequentially from bottom to top on the substrate, wherein the thickness of the silicon nitride film is at least 6000 angstroms;

[0012] A high-voltage-resistant chip is prepared by using a substrate having the semi-insulating polysilicon film and the silicon nitride film.

[0013] As a second aspect of the present invention, a high voltage resistant chip is provided, characterized in that it comprises a substrate, a semi-insulating polysilicon film, a silicon nitride film, a glass passivation layer and an LTO film, wherein the semi-insulating polysilicon film is arranged on the substrate, the silicon nitride film is arranged on the semi-insulating polysilicon film, the glass passivation layer is arranged on the silicon nitride film, and the LTO film is arranged on the glass passivation layer;

[0014] Wherein, the thickness of the silicon nitride film is at least 6000 angstroms;

[0015] The high-voltage resistant chip is prepared using the method for preparing a high-voltage resistant chip according to the first aspect.

[0016] The present invention has significant beneficial effects, which are mainly reflected in the following aspects:

[0017] 1. Significantly improve voltage resistance: By growing a silicon nitride film with a thickness of at least 6000 angstroms on the semi-insulating polysilicon film, the voltage resistance bottleneck of the traditional preparation method has been successfully broken through, and the voltage resistance of the chip has jumped to 3000V and above, far exceeding the 2000V level that can be achieved by existing technologies. It provides a strong guarantee for meeting the growing high voltage resistance demand of high-power electrical appliances and greatly expands the scope of application of the chip in high-voltage application scenarios.

[0018] 2. Significantly reduce leakage current: Different from the existing technology that simply increases the thickness of the semi-insulating polysilicon film to increase leakage current, the silicon nitride film used in the present invention can effectively suppress leakage current, significantly improve the stability and reliability of the chip, reduce the power loss and performance degradation caused by leakage current, extend the service life of the chip, and reduce the operating cost of electronic equipment.

[0019] 3. Optimize chip performance: Overall, the present invention not only achieves a qualitative leap in the two key performance indicators of voltage resistance and leakage, but also further optimizes the overall performance of the chip. The dual advantages of high voltage resistance and low leakage enable the chip to operate stably in a high-voltage, high-power working environment, providing a solid foundation for the efficient and reliable operation of electronic equipment, and helping to promote technological progress in the field of high-performance chips in the semiconductor industry, which has important practical significance and broad application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments:

[0021] Figure 1 A flow chart of a method for preparing a high voltage resistant chip provided by an embodiment of the present invention;

[0022] Figure 2 A schematic structural diagram of a high-voltage resistant chip provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0023] The following will illustrate the implementation methods of the present invention in conjunction with the drawings in the specification. It should be noted that the implementation methods involved in this specification are not exhaustive and do not represent the only implementation methods of the present invention. The following corresponding embodiments are only for the purpose of clearly illustrating the invention content of the patent of the present invention, and are not intended to limit its implementation methods. For ordinary technicians in this field, different forms of changes and modifications can be made on the basis of the description of this embodiment. All obvious changes or modifications that belong to the technical concept and invention content of the present invention are also within the scope of protection of the present invention.

[0024] like Figure 1 As shown, the embodiment of the present application provides a method for preparing a high voltage resistant chip, comprising:

[0025] S101, selecting a zone melting silicon wafer as a substrate.

[0026] This embodiment takes the preparation of 200milSTD rectifier chip as an example, and selects a zone melting silicon wafer with a resistivity of 160-180Ω·cm and a thickness of 360-370um as the substrate.

[0027] S102, diffuse phosphorus on the substrate: the condition is (1100-1200℃)*(5-7)H, and then diffuse again, the condition is (1200-1300)℃(3-6H).

[0028] The purpose of phosphorus diffusion is to diffuse phosphorus elements into the interior of the substrate. It can be performed on the front side, back side or both sides of the substrate. The specific choice depends on the design and process requirements of the chip. In this embodiment, single-side diffusion is performed on the back side of the substrate.

[0029] S103, etching the oxide layer of the substrate, and then polishing it to reduce the thickness of the substrate from 360-370um to 355-360um.

[0030] Specifically, step S103 is to perform oxide layer etching and polishing on the phosphorus-diffused side of the substrate, in order to remove the phosphorus-silicate glass formed on the substrate during the phosphorus diffusion process.

[0031] S104, oxidize the substrate once to form a protective oxide layer (usually silicon dioxide, SiO 2 ).

[0032] S105. Diffusion of gallium into the substrate: the condition is (1200-1300°C)*(26-31)H.

[0033] Among them, step S105 is to diffuse gallium on the back side of the substrate, thereby paving the way for subsequent boron diffusion.

[0034] S106. Boron diffusion is performed on the substrate: the pre-deposition condition is (1000-1100°C)*(3-6)H, and the re-deposition condition is (1200-1300°C)*(12-16)H.

[0035] Boron diffusion is the process of diffusing the boron element into the interior of the substrate, thereby finally forming a PN junction.

[0036] S107, performing photolithography on the substrate to protect the area on the substrate surface that needs to be protected (the area where the grooves are not formed).

[0037] S108, etching and trenching the substrate to expose the PN junction, and the trenching depth is required to reach 160-180um.

[0038] Among them, the trenching depth reaching 160-180um can appropriately improve the pressure resistance.

[0039] S109. Using low pressure chemical vapor deposition (LPCVD), a semi-insulating polysilicon film and a silicon nitride film are sequentially deposited on the substrate from bottom to top.

[0040] Among them, the semi-insulating polysilicon film can increase the reliability of the chip, such as the performance under extreme environments such as high-temperature leakage and high-temperature reverse bias. The thickness of the silicon nitride film is at least 6000 angstroms.

[0041] The low pressure chemical vapor deposition method is carried out under program control. When growing semi-insulating polysilicon film, when the program runs to the silane (SiH4) test, the MFC opening degree of SiH4 is 60-70%, the test time is 5±1min, and the temperature is 620±5℃. When the program runs to the semi-insulating polysilicon (SIPOS) deposition, the MFC opening degree of SiH4 is 50-60%, the MFC opening degree of nitrous oxide (N2O) is 20-25%, the deposition time is 60±5min, the temperature is 650±5℃, and the program runs to the semi-insulating polysilicon (SIPOS) deposition. When MTO is deposited, the MFC opening degree of SiH4 is 20-25%, the MFC opening degree of N2O is 80-90%, the deposition time is 60 minutes, and the temperature is 680±5°C; when growing silicon nitride film, the MFC opening degree ratio of dichlorosilane (SiH2CL2) / ammonia (NH3) is 35% / 45%, the temperature is 780±5°C, and the deposition time is 8-10 hours. Under the current process conditions, the thickness of the generated silicon nitride film can reach at least 6000 angstroms, and the withstand voltage can reach 3000V and above.

[0042] It should be pointed out that the MFC opening degree of SiH2CL2 ranges from 30% to 40%, and the MFC opening degree of NH3 ranges from 40% to 50%.

[0043] The above-mentioned MFC refers to a gas flow controller, which may be a butterfly valve. Taking the butterfly valve as an example, the opening degree may be understood as the ratio of the opening size of the butterfly valve to the full opening of the butterfly valve.

[0044] In this embodiment, the thickness of the semi-insulating polysilicon film is selected to be 8000-11000 angstroms. If it exceeds 11000 angstroms, it will affect the subsequent etching. The thickness of the silicon nitride film is selected to be 6000-8000 angstroms. If it exceeds 8000 angstroms, it will also affect the subsequent etching.

[0045] S110, using a substrate having a semi-insulating polysilicon film and a silicon nitride film to prepare a high voltage resistant chip, the specific process is as follows:

[0046] S111, glass passivation is performed on the substrate to form a glass passivation layer on the silicon nitride film to protect the PN junction, wherein GP-390 glass powder can be used.

[0047] S112, performing LTO deposition treatment on the substrate to form an LTO film on the glass passivation layer: the MFC opening degree of SiH4 is 50-80%, the MFC opening degree of O2 is 55-85%, and the time is 25-35 minutes.

[0048] The LTO film protects the PN junction and prevents solder from flowing to other areas during the subsequent chip packaging welding process.

[0049] S113, performing secondary photolithography on the substrate.

[0050] S114, performing thin film etching on the substrate.

[0051] S115. Double-sided aluminum treatment is performed on the substrate, and the thickness of the aluminum layer is determined according to customer requirements.

[0052] S116, performing photolithography three times on the substrate.

[0053] S117, performing aluminum etching on the substrate.

[0054] S118, performing alloying process on the substrate.

[0055] S119, performing back metal processing on the substrate.

[0056] Among them, the secondary photolithography and tertiary photolithography are for glass expansion and film removal. Glass expansion refers to melting the glass onto the chip at the required position by high temperature, and film removal refers to removing the film at the position where the film is not needed.

[0057] Finally, if Figure 2As shown, the high-voltage resistant chip prepared includes a substrate 11, a semi-insulating polysilicon film 12, a silicon nitride film 13, a glass passivation layer 14 and an LTO film 15. The semi-insulating polysilicon film 12 is arranged on the substrate 11, the silicon nitride film 13 is arranged on the semi-insulating polysilicon film 12, the glass passivation layer 14 is arranged on the silicon nitride film 13, and the LTO film 15 is arranged on the glass passivation layer 14.

[0058] Among them, the semi-insulating polysilicon film can increase the reliability of the chip, such as the performance under extreme environments such as high temperature leakage, high temperature reverse bias, etc. The thickness of the silicon nitride film 13 is at least 6000 angstroms.

[0059] By generating semi-insulating polysilicon film and silicon nitride film on substrates with the same resistivity and thickness, experiments were conducted in groups to test the film thickness of the silicon nitride film as well as the withstand voltage characteristics and leakage characteristics of the finished chip. It can be seen that the silicon nitride film can significantly improve the withstand voltage capability, and the thicker the film, the smaller the leakage, see Table 2.

[0060]

[0061] Table 2

[0062]

[0063] Table 3

[0064] It can be seen from the above that the embodiments of the present application have significant beneficial effects, which are mainly reflected in the following aspects:

[0065] 1. Significantly improve voltage resistance: By growing a silicon nitride film with a thickness of at least 6000 angstroms on the semi-insulating polysilicon film, the voltage resistance bottleneck of the traditional preparation method has been successfully broken through, and the voltage resistance of the chip has jumped to 3000V and above, far exceeding the 2000V level that can be achieved by existing technologies. It provides a strong guarantee for meeting the growing high voltage resistance demand of high-power electrical appliances and greatly expands the scope of application of the chip in high-voltage application scenarios.

[0066] 2. Significantly reduce leakage: Unlike the existing technology that simply increases the thickness of the semi-insulating polysilicon film to increase leakage, the silicon nitride film used in the embodiment of the present application can effectively suppress the leakage phenomenon, significantly improve the stability and reliability of the chip, reduce the power loss and performance degradation caused by leakage, extend the service life of the chip, and reduce the operating cost of electronic equipment.

[0067] 3. Optimize chip performance: Overall, the embodiments of the present application not only achieve a qualitative leap in the two key performance indicators of withstand voltage and leakage, but also further optimize the overall performance of the chip. The dual advantages of high withstand voltage and low leakage enable the chip to operate stably in a high-voltage, high-power working environment, providing a solid foundation for the efficient and reliable operation of electronic equipment, and helping to promote technological progress in the field of high-performance chips in the semiconductor industry, which has important practical significance and broad application prospects.

[0068] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A method for preparing a high voltage resistant chip, characterized in that: include: The substrate is subjected to a photolithography process and then etched to form trenches; Depositing a semi-insulating polysilicon film and a silicon nitride film sequentially from bottom to top on the substrate, wherein the thickness of the silicon nitride film is at least 6000 angstroms; A high-voltage-resistant chip is prepared by using a substrate having the semi-insulating polysilicon film and the silicon nitride film.

2. The method for preparing a high voltage resistant chip according to claim 1, characterized in that: Before the substrate is subjected to a photolithography process, it also includes: Selecting a zone melting silicon wafer as the substrate; Diffusion of phosphorus on the substrate; etching the oxide layer of the substrate and then polishing it; performing a primary oxidation on the substrate; Diffusion of gallium on the substrate; The substrate is subjected to boron diffusion.

3. The method for preparing a high voltage resistant chip according to claim 1, characterized in that: The method of sequentially depositing a semi-insulating polysilicon film and a silicon nitride film on the substrate from bottom to top further comprises: Using low pressure chemical vapor deposition method, a semi-insulating polysilicon film and a silicon nitride film are sequentially deposited from bottom to top on the substrate; Among them, when performing SIPOS deposition, the MFC opening degree of Si H4 is 50-60%, the MFC opening degree of N2O is 20-25%, the time is 60±5min, and the temperature is 650±5℃; when performing MTO deposition, the MFC opening degree of Si H4 is 20-25%, the MFC opening degree of N2O is 80-90%, the time is 60min, and the temperature is 680±5℃; when growing silicon nitride film, the MFC opening degree of Si H2CL2 is 30-40%, the MFC opening degree of NH3 is 40-50%, the temperature is 780±5℃, and the time is 8-10H.

4. The method for preparing a high voltage resistant chip according to claim 3, characterized in that: Before SIPOS deposition, it also includes: The SiH4 test was conducted with the MFC opening of SiH4 at 60-70%, the time at 5±1min, and the temperature at 620±5℃.

5. The method for preparing a high voltage resistant chip according to claim 1, characterized in that: The method of using the substrate having the semi-insulating polysilicon film and the silicon nitride film to prepare a high voltage resistant chip further comprises: Performing glass passivation on the substrate to form a glass passivation layer on the silicon nitride film; Performing LTO deposition treatment on the substrate to form an LTO film on the glass passivation layer; Performing secondary photolithography on the substrate; Performing thin film etching on the substrate; Performing double-sided aluminum treatment on the substrate; Performing photolithography three times on the substrate; Performing aluminum etching on the substrate; performing an alloying process on the substrate; The substrate is subjected to backside metal treatment.

6. The method for preparing a high voltage resistant chip according to claim 5, characterized in that: During the LTO deposition process, the MFC opening degree of Si H4 is 50-80%, the MFC opening degree of O2 is 55-85%, and the time is 25-35 minutes.

7. A high voltage resistant chip, characterized in that: It includes a substrate, a semi-insulating polysilicon film, a silicon nitride film, a glass passivation layer and an LTO film, wherein the semi-insulating polysilicon film is arranged on the substrate, the silicon nitride film is arranged on the semi-insulating polysilicon film, the glass passivation layer is arranged on the silicon nitride film, and the LTO film is arranged on the glass passivation layer; Wherein, the thickness of the silicon nitride film is at least 6000 angstroms; The high-voltage resistant chip is prepared using the method for preparing a high-voltage resistant chip according to any one of claims 1 to 6.

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