Semiconductor device structure and preparation method thereof

Abstract

The invention provides a semiconductor device structure and a preparation method thereof, and the method comprises the steps: providing a semiconductor substrate which comprises an active region and a gate structure, and forming a silicide barrier layer on the semiconductor substrate; removing a part of the silicide barrier layer in the silicide preparation region, and reserving the silicide barrier layer with a predetermined thickness in the silicide preparation region; pre-amorphization injection is carried out on the silicide preparation area to at least form an amorphization area in the active area, the pre-amorphization injection comprises different inclined injection angles, and the amorphization area comprises transverse expansion and longitudinal expansion towards the lower portion of the gate structure to form an expansion area; removing the residual silicide barrier layer in the silicide preparation region; and forming a metal silicide in the silicide preparation region. According to the invention, the non-crystallization region below the gate structure can be ensured to have enough thickness, the metal silicide with uniform thickness is formed, and the metal silicide can be ensured to completely cover the bottom of the contact hole.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor integrated circuit design and manufacturing, and in particular relates to a semiconductor device structure and a preparation method thereof. Background Art

[0002] The metal silicide process is widely used in the manufacture of semiconductor devices. The metal silicide process is to form metal silicide (Salicide) by reacting metal and silicon (Si). Commonly used metal silicides include NiSi, TiSi 2 、CoSi 2 At present, nickel silicide (NiSi) is usually used as the metal silicide of 40nm process. The unreacted metal can be removed by pickling, while the reacted metal silicide can be retained in the pickling. Finally, the metal silicide is grown only on the active area (AA) and polysilicon gate (Poly) exposed by the silicide barrier layer (SAB).

[0003] The commonly used metal silicide process currently generates metal silicide through pre-cleaning (Pre-Clean), metal deposition (Dep) and two rapid annealing (RTA).

[0004] For smaller device areas, the lateral space for the generation of metal silicide is smaller, and a metal silicide with a bowl-shaped or V-shaped physical structure will be formed in the source and drain (SD) area. The metal silicide is thinner near the channel, usually less than 100 angstroms.

[0005] After contact hole etching and glue layer formation, punch-through defects are likely to occur at the edge of the metal silicide, resulting in leakage issues in the device.

[0006] However, if the edge thickness of the metal silicide is increased simply by increasing the thickness of the metal silicide, the uneven distribution of the silicon grain size (Poly grain size) will cause the metal silicide on the silicon to be thicker, resulting in defects such as local uneven resistance. At the same time, the metal silicide occupies too much volume in the substrate, which also affects the local ion concentration in the substrate, causing device performance to shift.

[0007] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0008] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a semiconductor device structure and a method for preparing the same, so as to solve the problem of uneven thickness of metal silicide in the prior art.

[0009] To achieve the above-mentioned purpose and other related purposes, the present invention provides a method for preparing a semiconductor device structure, the preparation method comprising: providing a semiconductor substrate, the semiconductor substrate comprising an active area arranged in the semiconductor substrate and a gate structure arranged above the active area, a silicide barrier layer being formed on the semiconductor substrate; removing part of the silicide barrier layer in the silicide preparation area, retaining a silicide barrier layer of a predetermined thickness in the silicide preparation area as an injection protection layer; performing pre-amorphization injection on the silicide preparation area to form an amorphized area at least in the active area, the pre-amorphization injection comprising different inclined injection angles so that the amorphized area includes lateral expansion and longitudinal expansion to the bottom of the gate structure to form an expansion area; removing the remaining silicide barrier layer in the silicide preparation area; forming a metal layer in the silicide preparation area, and reacting the metal layer with the semiconductor substrate in the amorphized area through an alloying process to form a metal silicide.

[0010] Optionally, forming the metal silicide includes: depositing a NiPt layer in the silicide preparation area; and reacting the NiPt layer with the semiconductor substrate to form a Ni 2 Si layer; remove the unreacted NiPt layer; and make Ni 2 The Si layer further reacts with the semiconductor substrate to form a NiSi alloy layer.

[0011] Optionally, forming the metal silicide further comprises: a step of depositing a TiN layer on the NiPt layer, wherein the TiN layer is used to prevent the NiPt layer from flowing during the annealing stage, so as to avoid defects such as uneven thickness and resistance value of the metal silicide formed by the reaction.

[0012] Optionally, the gate structure further includes a sidewall portion, and by changing the tilted injection angle of the pre-amorphization injection, the amorphized region of the active region is expanded laterally and vertically below the sidewall portion of the gate structure to form an expansion region.

[0013] Optionally, pre-amorphization implantation of the silicide preparation area includes: vertically implanting ions into the silicide preparation area to form an initial implantation area; setting sidewall portions on both sides of the gate structure or increasing the thickness of the existing sidewall portions; and implanting ions into the silicide preparation area at an inclined implantation angle so that the initial implantation area is laterally and vertically expanded below the sidewall portions of the gate structure to form an expansion area to form an amorphized area.

[0014] Optionally, pre-amorphization implantation of the silicide preparation region includes: performing C ion implantation at a first tilted implantation angle on the silicide preparation region to form a C ion implantation region; performing Ge ion implantation at a second tilted implantation angle on the silicide preparation region to form an amorphized region, wherein the first tilted implantation angle is greater than the second tilted implantation angle so that the C ion implantation region covers the amorphized region.

[0015] Optionally, the silicide preparation area includes the active area and the polysilicon layer of the gate structure; when the active area is pre-amorphized and injected, an amorphized area is simultaneously formed in the polysilicon layer of the gate structure; a metal layer is formed on the active area, and a metal layer is simultaneously formed on the polysilicon layer of the gate structure; when the metal layer is reacted with the amorphized area of ​​the active area through an alloying process to form metal silicide, metal silicide is simultaneously formed in the amorphized area of ​​the polysilicon layer of the gate structure.

[0016] Optionally, the tilted injection angle ranges from 5° to 10°.

[0017] Optionally, the pre-amorphization injection includes: performing pre-amorphization injection into the semiconductor substrate at a certain angle; keeping the direction and angle of the pre-amorphization injection unchanged, rotating the semiconductor substrate 180°, and continuing to perform pre-amorphization injection into the semiconductor substrate to form a symmetrically arranged expansion area in the semiconductor substrate.

[0018] Optionally, the silicide blocking layer includes a silicon dioxide layer, and after a portion of the silicide blocking layer in the silicide preparation region is removed, the predetermined thickness of the remaining silicide blocking layer is 20 angstroms to 60 angstroms.

[0019] Optionally, the ions implanted for the pre-amorphization include one or both of Ge and Ar.

[0020] Optionally, the implantation energy of the pre-amorphization implantation is 5keV to 15keV, and the implantation dose is 5E14atom / cm -2 ~2E15atom / cm -2 .

[0021] Optionally, the cross-sectional shape of the amorphized region including the extension region is U-shaped.

[0022] The present invention also provides a semiconductor device structure, including: a semiconductor substrate, the semiconductor substrate including an active area arranged in the semiconductor substrate and a gate structure arranged above the active area; a metal silicide formed in the active area, the metal silicide covers the surface of the active area and expands laterally and vertically below the gate structure to form a metal silicide expansion area.

[0023] Optionally, the metal silicide includes an initial metal silicide region having a V-shaped cross-section, and a metal silicide extension region formed by longitudinally extending a first extension distance and laterally extending a second extension distance from the bottom of the initial metal silicide region. The joint extension of the first extension distance and the second extension distance changes the structure of the metal silicide from a V-shaped cross-section to a U-shaped cross-section, so that the metal silicide completely covers the bottom of the contact hole.

[0024] As described above, the semiconductor device structure and the method for manufacturing the same of the present invention have the following beneficial effects:

[0025] The present invention forms an amorphous region by Ge and Ar implantation. The depth of the amorphous region is positively correlated with the diffusion range of the metal. The diffusion range of the metal can be controlled by adjusting the implantation energy to obtain a suitable metal silicide thickness.

[0026] The present invention adjusts the injection angle of the pre-amorphization injection so that the amorphized area includes a lateral expansion and a longitudinal expansion to the bottom of the gate structure to form an expansion area, thereby ensuring that the amorphized area below the gate structure has a suitable thickness. After the metal diffuses in the amorphized area, it is easier to form a metal silicide with uniform thickness, thereby effectively increasing the process window for contact hole etching, ensuring that the metal silicide can completely cover the bottom of the contact hole, and avoiding the risk of contact hole punch-through.

[0027] The present invention reserves a silicide barrier layer of a predetermined thickness before pre-amorphization injection. The silicide barrier layer of the predetermined thickness protects and buffers the silicon surface. After injection, the diffusion of ions in the silicon to the periphery is reduced, which can effectively reduce the damage of the pre-amorphization injection to the doping of the source and drain regions, and reduce the barrier lowering effect (DIBL) between the source and drain. The present invention can effectively ensure that the size of the extension area formed after the pre-amorphization injection is the required size by setting the thickness of the silicide barrier layer to 40 angstroms to 60 angstroms, while ensuring that no loss is caused to the ion injection area in the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the specification, are used to illustrate the implementation of the present application, and together with the text description, explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application.

[0029] Figures 1 to 8 The structure schematic diagram shows each step of the method for preparing the semiconductor device structure according to the embodiment of the present invention, wherein: Figure 7 and Figure 8 Shown is a schematic structural diagram of a semiconductor device structure according to an embodiment of the present invention.

[0030] Fig. 9Shown is a schematic diagram of the structure of a traditional metal silicide.

[0031] Component number description

[0032] 101 Semiconductor substrate

[0033] 102 Active Area

[0034] 103 Gate Structure

[0035] 104 Side wall

[0036] 105 Silicide barrier layer

[0037] 106 Amorphous region of active area

[0038] 107 Expansion Area

[0039] 108 Amorphous region of gate structure

[0040] 109 NiPt layer

[0041] 110 TiN layer

[0042] 111 Ni 2 Si layer

[0043] 112 Metal silicide in active area

[0044] 1121 Initial Metal Silicide Region

[0045] 1122 Metal Silicide Expansion Area

[0046] 113 Metal silicide for gate structure DETAILED DESCRIPTION

[0047] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0048] It should be emphasized that the term “include / comprises” when used herein refers to the presence of features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps or components.

[0049] Features described and / or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0050] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0051] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0052] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0053] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0054] like Figures 1 to 9 As shown, this embodiment provides a method for preparing a semiconductor device structure, and the preparation method comprises the following steps:

[0055] First, step 1) is performed to provide a semiconductor substrate 101 . The semiconductor substrate 101 includes an active region 102 disposed in the semiconductor substrate 101 and a gate structure 103 disposed above the active region 102 . A silicide blocking layer 105 is formed on the semiconductor substrate 101 .

[0056] In some embodiments, the semiconductor substrate 101 can be, for example, any suitable semiconductor substrate material, such as pure silicon, silicon germanium (SiGe), silicon carbide (SiC) or silicon on insulator (SOI), etc.; the semiconductor substrate 101 can be doped, such as including a P-type doped region and an N-type doped region.

[0057] In some embodiments, the active region 102 in the semiconductor substrate 101 includes a source region and a drain region of a transistor, a channel region is located between the source region and the drain region, and a gate structure 103 is disposed above the channel region. The source region, the gate structure 103 and the drain region are arranged alternately.

[0058] In some embodiments, the gate structure 103 further includes a spacer 104 . The spacer 104 may be, for example, silicon dioxide, silicon nitride, silicon oxynitride, or a combination of the above materials (ie, a multi-layer spacer).

[0059] Specifically, the semiconductor substrate 101 can be formed by the following steps:

[0060] Step 1-1), forming a gate oxide layer and a polysilicon gate on a substrate;

[0061] Step 1-2), forming a sidewall portion 104 on the sidewall of the polysilicon gate; if it is a multi-layer sidewall, in some embodiments, source and drain lightly doped (LLD) ion implantation can be performed when forming part of the sidewall portion 104, and in other embodiments, it also includes halo ion implantation, both of which are used to improve the short channel effect.

[0062] Step 1-3), performing source and drain implantation and annealing on the substrate to form active regions 102 (source region and drain region) on both sides of the gate structure 103;

[0063] Step 1-4), sequentially depositing a silicon dioxide layer and a silicon nitride layer on the substrate to form a silicide barrier layer 105. The deposition process of the silicon dioxide layer and the silicon nitride layer can be a chemical vapor deposition process (CVD) or an atomic layer deposition process (ALD) to obtain better thickness uniformity.

[0064] like Figure 1 As shown, step 2) is then performed to remove part of the silicide blocking layer 105 in the silicide preparation area, and retain the silicide blocking layer 105 of a predetermined thickness in the silicide preparation area as an implantation protection layer.

[0065] In some embodiments, part of the silicide blocking layer 105 can be removed by photolithography and etching processes. The silicide blocking layer 105 includes a silicon dioxide layer and a silicon nitride layer. After removing part of the silicide blocking layer 105 in the silicide preparation area, the silicon nitride layer in the silicide preparation area will be completely removed, and part of the silicon dioxide layer will be removed, so that the predetermined thickness of the remaining silicide blocking layer 105 is 20 angstroms to 60 angstroms. The present invention reserves a silicide barrier layer 105 of a predetermined thickness before pre-amorphization implantation. The silicide barrier layer 105 of the predetermined thickness protects and buffers the silicon surface. After implantation, the diffusion of ions in the silicon to the periphery is reduced, which can effectively reduce the damage of the pre-amorphization (PAI) implantation to the doping of the source and drain regions, and reduce the barrier lowering effect (DIBL) between the source and drain. More importantly, by selecting the appropriate predetermined thickness, that is, corresponding to a certain specific blocking ability, the PAI ions are implanted to the most appropriate depth, and further ensure that a metal silicide (Salicide) of a desired shape is subsequently formed in the desired region. The present invention sets the thickness of the silicide barrier layer 105 to 40 angstroms to 60 angstroms, which can ensure that the adjustment of the pre-amorphization implantation has less impact on the device and achieves metal silicide in the desired region.

[0066] like Figure 2 As shown, step 3) is then performed to perform pre-amorphization implantation on the silicide preparation area to form an amorphized region 106 at least in the active area 102. The pre-amorphization implantation includes different tilted implantation angles so that the amorphized region 106 includes lateral expansion and longitudinal expansion toward the bottom of the gate structure 103 to form an expansion region 107.

[0067] In some embodiments, the ions implanted for pre-amorphization include one or both of Ge and Ar. The implantation of Ge and / or Ar will not affect the electrical properties of the active region 102, and can convert silicon into an amorphous state. Silicon in an amorphous state is more likely to react with metal to form metal silicide than the region not implanted for pre-amorphization. In some embodiments, the implantation energy of the pre-amorphization implantation is 5keV to 15keV, and the implantation dose is 5E14atom / cm -2 ~2E15atom / cm -2 The present invention forms the amorphous region 106 by implanting Ge and Ar. The depth of the amorphous region 106 is positively correlated with the diffusion range of the metal. The diffusion range of the metal can be controlled by adjusting the implantation energy to obtain a suitable metal silicide thickness.

[0068] In some embodiments, the gate structure 103 includes a sidewall portion 104 , and by changing the tilted injection angle θ of the pre-amorphization injection, the amorphized region 106 of the active region 102 is expanded laterally and vertically below the sidewall portion 104 of the gate structure 103 to form an expansion region 107 .

[0069] In another embodiment, performing pre-amorphization implantation on the silicide preparation region includes:

[0070] Performing vertical ion implantation on the silicide preparation region to form an initial implantation region;

[0071] Disposing sidewalls 104 on both sides of the gate structure 103 or increasing the thickness of the existing sidewalls;

[0072] The silicide preparation region is subjected to tilted ion implantation at an inclined implantation angle θ, so that the initial implantation region is expanded laterally and vertically toward the lower sidewall of the gate structure 103 to form an expansion region 107 , thereby forming an amorphized region 106 .

[0073] In yet another embodiment, performing pre-amorphization implantation on the silicide preparation region includes:

[0074] Performing C (carbon) ion oblique implantation on the silicide preparation region at a first oblique angle to form a C ion implantation region;

[0075] The silicide preparation region is subjected to an inclined implantation of Ge (germanium) ions at a second inclined angle to form an amorphized region, wherein the first inclined angle is greater than the second inclined angle, so that the C ion implantation region covers the amorphized region. In this example, Ge ions are implanted after C ions are implanted, and the C ion implantation region can cover the amorphized region formed by the Ge ion implantation, thereby blocking the diffusion of Ge ions into the channel. At the same time, the C ions do not affect the threshold voltage, thereby ensuring that when Ge is implanted obliquely later, while achieving the target region, it will not excessively diffuse to the threshold voltage adjustment region below the gate structure 103 due to the inclined implantation of Ge, which can well ensure the morphology of the amorphized region and will not affect the threshold voltage of the device.

[0076] In some embodiments, the silicide preparation area is the source and drain area of ​​NMOS. When NMOS needs to perform source and drain lightly doped (LDD) ion implantation, the pre-amorphization implantation can be performed directly using the mask of the source and drain lightly doped (LDD) ion implantation after the source and drain lightly doped (LDD) ion implantation (the above steps 1-2), thereby saving process costs by sharing the mask. The tilt angle of the above pre-amorphization implantation can be 10° to 20° smaller than the angle of the source and drain lightly doped (LDD) ion implantation, so that the source and drain lightly doped (LDD) ion implantation area is deeper into the channel below the gate structure, while the pre-amorphization implantation area only extends to the outer edge of the channel.

[0077] In some embodiments, the tilted implantation angle θ is in a range of 5° to 10°. The tilted implantation angle can effectively improve the bottom morphology of the amorphized region 106 .

[0078] In some embodiments, the cross-sectional shape of the amorphized region 106 including the extension region 107 is U-shaped (the shape shown in the figure is only a schematic diagram).

[0079] In a specific example, the pre-amorphization implantation includes: performing pre-amorphization implantation on the semiconductor substrate 101 at a certain angle, such as 5°; keeping the direction and angle of the pre-amorphization implantation unchanged (i.e., no adjustment is required to the direction of the ion implantation), rotating the semiconductor substrate 101 by 180°, and continuing to perform pre-amorphization implantation on the semiconductor substrate 101 to form symmetrically arranged extension areas 107 in the semiconductor substrate 101. In one embodiment, the projection of the ion implantation direction on the semiconductor substrate 101 is perpendicular to the projection of the sidewall portion 104 of the gate structure 103 on the semiconductor substrate 101, so that the extension areas 107 are symmetrically distributed relative to the central axis of the gate structure 103.

[0080] like Figure 3 As shown, step 4) is then performed to remove the remaining silicide barrier layer 105 in the silicide preparation area.

[0081] like Figures 4 to 7 As shown, step 5) is finally performed to form a metal layer in the silicide preparation area, and the metal layer is reacted with the semiconductor substrate 101 in the amorphized area 106 through an alloying process to form a metal silicide 112.

[0082] In one embodiment, forming the metal silicide 112 includes:

[0083] like Figure 4 As shown, step 5-1) is performed to deposit a NiPt layer 109 in the silicide preparation area, and a TiN layer 110 is deposited on the NiPt layer 109;

[0084] like Figure 5 As shown, step 5-2) is performed to react the NiPt layer 109 with the semiconductor substrate 101 to form Ni 2 Si layer 111; during this process, the TiN layer 110 is used to prevent the NiPt layer 109 from flowing during the annealing stage to avoid defects such as uneven thickness and resistance value of the metal silicide 112 formed by the reaction.

[0085] like Figure 6 As shown, step 5-3) is performed to remove the unreacted NiPt layer 109 and TiN layer 110.

[0086] like Figure 7As shown, step 5-4) is performed to make Ni 2 The Si layer 111 further reacts with the semiconductor substrate 101 to form a metal silicide 112 (NiSi alloy layer).

[0087] In the above process, the NiPt layer 109 reacts more easily with the amorphized region 106, and almost all of the silicon in the amorphized region 106 reacts with the NiPt layer 109 to form a metal silicide 112 (NiSi alloy layer). Therefore, the final morphology of the metal silicide 112 located in the semiconductor substrate 101 is basically consistent with that of the amorphized region 106. Of course, in the actual process, the final morphology of the metal silicide 112 located in the semiconductor substrate 101 may also be slightly larger or slightly smaller than that of the amorphized region 106.

[0088] like Figure 1 to Figure 7 As shown, in this embodiment, the silicide preparation area includes the polysilicon layer of the active area 102 and the gate structure 103; step 3) when the active area 102 is pre-amorphized and injected, an amorphized area 108 is formed in the polysilicon layer of the gate structure 103; step 5) a metal layer is formed on the active area 102, and a metal layer (such as a NiPt layer and a TiN layer) is formed on the polysilicon layer of the gate structure 103; step 5) when the metal layer is reacted with the amorphized area of ​​the active area 102 to form a metal silicide 112 through an alloying process, a metal silicide 113 (such as a NiSi alloy layer) is formed in the amorphized area 108 of the polysilicon layer of the gate structure 103.

[0089] like Figure 7 As shown, this embodiment also provides a semiconductor device structure, which includes: a semiconductor substrate 101, the semiconductor substrate 101 includes an active area 102 arranged in the semiconductor substrate 101 and a gate structure 103 arranged above the active area 102; the active area 102 is formed with a metal silicide 112, the metal silicide 112 covers the surface of the active area 102 and expands laterally and vertically below the gate structure 103 to form a metal silicide expansion area 1122.

[0090] In one embodiment, Figure 8 As shown, the metal silicide 112 includes an initial metal silicide region 1121 with a V-shaped (or bowl-shaped) cross-section, and a metal silicide extension region 1122 formed by longitudinally extending a first extension distance and laterally extending a second extension distance from the bottom of the initial metal silicide region 1121. The joint extension of the first extension distance and the second extension distance changes the structure of the metal silicide 112 from a V-shaped cross-section to a U-shaped cross-section, so that the metal silicide 112 completely covers the bottom of the contact hole.

[0091] Fig. 9The schematic diagram of the structure of metal silicide formed by the traditional process is shown. The cross section of the traditional metal silicide tends to be V-shaped (or bowl-shaped). It can be seen that Fig. 9 The thickness of the metal silicide below the middle gate structure 103 is relatively small. After the contact hole is etched and the adhesive layer is formed, a punch-through defect is likely to occur at the edge of the metal silicide, resulting in device leakage. Figure 8 The schematic diagram of the improved semiconductor device structure of the present invention is shown. Taking the edge of the sidewall portion 104 as the reference line, the metal silicide of the improved semiconductor device structure of the present invention is compared with Fig. 9 Compared with the traditional metal silicide, it has a first extension distance extended vertically and a second extension distance extended horizontally, which is wider and deeper than the traditional structure. It is easier to completely cover the bottom of the contact hole in the subsequent process. That is, when the metal on the top of the substrate reacts with the silicon in the substrate to form metal silicide, the reactant area close to the surface of the substrate is restricted by the amorphized area 106 of the active area and will not extend excessively to the source and drain areas. At the same time, the corners of the bottom extension area 107 are amorphized, so even if they are far away from the top metal, they are easier to react with the metal than the prior art. Therefore, the present invention can realize a metal silicide 112 with a morphology close to a U shape. In a specific example, Figure 8 The width D of the metal silicide on the top surface of the active area 102 can be 30 to 100 nanometers, for example, 50 nanometers, and the lateral extension width D1 of the metal silicide below the edge of the sidewall can be 0.5 nanometers to 5 nanometers; the initial thickness H of the metal silicide below the edge of the sidewall can be 90 to 120 angstroms, and the extension thickness H1 can be 30 angstroms to 50 angstroms, such as 40 angstroms. The final structure of the metal silicide changes from a V-shaped cross-section to a U-shaped cross-section.

[0092] As described above, the semiconductor device structure and the method for manufacturing the same of the present invention have the following beneficial effects:

[0093] The present invention forms an amorphous region by Ge and Ar implantation. The depth of the amorphous region is positively correlated with the diffusion range of the metal. The diffusion range of the metal can be controlled by adjusting the implantation energy to obtain a suitable metal silicide thickness.

[0094] The present invention adjusts the injection angle of the pre-amorphization injection so that the amorphized area includes a lateral expansion and a longitudinal expansion to the bottom of the gate structure to form an expansion area, thereby ensuring that the amorphized area below the gate structure has a suitable thickness. After the metal diffuses in the amorphized area, it is easier to form a metal silicide with uniform thickness, thereby effectively increasing the process window for contact hole etching, ensuring that the metal silicide can completely cover the bottom of the contact hole, and avoiding the risk of contact hole punch-through.

[0095] The present invention reserves a silicide barrier layer of a predetermined thickness before pre-amorphization injection. The silicide barrier layer of the predetermined thickness protects and buffers the silicon surface. After injection, the diffusion of ions in the silicon to the periphery is reduced, which can effectively reduce the damage of the pre-amorphization injection to the doping of the source and drain regions, and reduce the barrier lowering effect (DIBL) between the source and drain. The present invention can effectively ensure that the size of the extension area formed after the pre-amorphization injection is the required size by setting the thickness of the silicide barrier layer to 40 angstroms to 60 angstroms, while ensuring that no loss is caused to the ion injection area in the substrate.

[0096] Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0097] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a semiconductor device structure, It is characterized in that The preparation method comprises: Providing a semiconductor substrate, the semiconductor substrate comprising an active region disposed in the semiconductor substrate and a gate structure disposed above the active region, wherein a silicide blocking layer is formed on the semiconductor substrate; Removing part of the silicide barrier layer in the silicide preparation area, and retaining a silicide barrier layer of a predetermined thickness in the silicide preparation area as an implantation protection layer; Performing pre-amorphization implantation on the silicide preparation region to form an amorphized region at least in the active region, wherein the pre-amorphization implantation includes different tilted implantation angles so that the amorphized region is laterally and vertically extended to form an extended region below the gate structure; removing the remaining silicide barrier layer in the silicide preparation area; A metal layer is formed in the silicide preparation area, and the metal layer is reacted with the semiconductor substrate in the amorphized area through an alloying process to form a metal silicide.

2. The method for preparing a semiconductor device structure according to claim 1, Features: Forming metal silicide includes: Depositing a NiPt layer in the silicide preparation area; The NiPt layer reacts with the semiconductor substrate to form Ni 2 Si layer; Removing the unreacted NiPt layer; The second annealing process makes Ni 2 The Si layer further reacts with the semiconductor substrate to form a NiSi alloy layer.

3. The method for preparing a semiconductor device structure according to claim 2, Features: The forming of the metal silicide further comprises: a step of depositing a TiN layer on the NiPt layer, wherein the TiN layer is used to prevent the NiPt layer from flowing during the annealing stage, so as to avoid defects such as uneven thickness and resistance value of the metal silicide formed by the reaction.

4. The method for preparing a semiconductor device structure according to claim 1, Features: The gate structure also includes a sidewall portion. By changing the tilted injection angle of the pre-amorphization injection, the amorphized region of the active region is expanded laterally and vertically to form an expansion region below the sidewall portion of the gate structure.

5. The method for preparing a semiconductor device structure according to claim 4, Features: The pre-amorphization implantation of the silicide preparation area includes: Performing vertical ion implantation on the silicide preparation region to form an initial implantation region; Arranging sidewalls on both sides of the gate structure or increasing the thickness of the existing sidewalls; Ions are implanted into the silicide preparation region at an inclined implantation angle, so that the initial implantation region is expanded laterally and vertically toward the bottom of the sidewall portion of the gate structure to form an expansion region, thereby forming an amorphized region.

6. The method for preparing a semiconductor device structure according to claim 1, Features: The pre-amorphization implantation of the silicide preparation area includes: Performing C ion oblique implantation on the silicide preparation region at a first oblique implantation angle to form a C ion implantation region; Ge ion is implanted obliquely into the silicide preparation region at a second oblique implantation angle to form an amorphized region, wherein the first oblique implantation angle is greater than the second oblique implantation angle so that the C ion implantation region covers the amorphized region.

7. The method for preparing a semiconductor device structure according to claim 1, Features: The silicide preparation region includes the active region and the polysilicon layer of the gate structure; When the active area is pre-amorphized and implanted, an amorphized area is simultaneously formed in the polysilicon layer of the gate structure; forming a metal layer on the active area and forming a metal layer on the polysilicon layer of the gate structure; When the metal layer reacts with the amorphized region of the active region to form metal silicide through an alloying process, metal silicide is simultaneously formed in the amorphized region of the polysilicon layer of the gate structure.

8. The method for preparing a semiconductor device structure according to claim 1, Features: The tilted injection angle ranges from 5° to 10°.

9. The method for preparing a semiconductor device structure according to claim 1, Features: The pre-amorphization implantation comprises: Performing pre-amorphization implantation on the semiconductor substrate at a certain angle; The direction and angle of the pre-amorphization implantation are kept unchanged, the semiconductor substrate is rotated 180 degrees, and the pre-amorphization implantation is continued to be performed on the semiconductor substrate to form symmetrically arranged extension areas in the semiconductor substrate.

10. The method for preparing a semiconductor device structure according to claim 1, Features: The silicide blocking layer includes a silicon dioxide layer. After removing part of the silicide blocking layer in the silicide preparation area, the predetermined thickness of the remaining silicide blocking layer is 20 angstroms to 60 angstroms.

11. The method for preparing a semiconductor device structure according to claim 1, Features: The pre-amorphization implanted ions include one or both of Ge and Ar.

12. The method for preparing a semiconductor device structure according to claim 1, Features: The implantation energy of the pre-amorphization implantation is 5keV-15keV, and the implantation dose is 5E14atom / cm -2 ~2E15atom / cm -2 .

13. The method for preparing a semiconductor device structure according to claim 1, Features: The cross-sectional shape of the amorphized region including the extended region is U-shaped or square.

14. A semiconductor device structure, It is characterized in that include: A semiconductor substrate, the semiconductor substrate comprising an active region disposed in the semiconductor substrate and a gate structure disposed above the active region; A metal silicide is formed in the active area, and covers the surface of the active area and expands laterally and vertically below the gate structure to form a metal silicide expansion area.

15. The semiconductor device structure according to claim 14, Features: The metal silicide includes an initial metal silicide region with a V-shaped cross-section, and a metal silicide extension region formed by longitudinally extending a first extension distance and laterally extending a second extension distance from the bottom of the initial metal silicide region. The joint extension of the first extension distance and the second extension distance changes the structure of the metal silicide from a V-shaped cross-section to a U-shaped cross-section so that the metal silicide completely covers the bottom of the contact hole.

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