Thin film structure of semiconductor device and preparation method thereof

Abstract

The invention relates to a thin film structure of a semiconductor device and a preparation method thereof. The thin film structure of the semiconductor device comprises a substrate; the conductive layer is located on the substrate, and the conductive layer covers part of the substrate; a first self-alignment layer on the conductive layer; the barrier layer is located on the first self-alignment layer and the substrate which is not covered by the conductive layer, and the barrier layer comprises a first etching stop layer, a second etching stop layer and a third etching stop layer which are sequentially arranged in a stacked mode in the direction perpendicular to the substrate; the dielectric layer is located on the barrier layer. According to the invention, at least when the thin film structure is etched, it can be ensured that the contact hole is completely opened, and the problem that the performance of the semiconductor device is reduced due to the fact that the semiconductor device cannot form ohmic contact due to over-etching of the thin film structure on a salicide (self-alignment layer) is avoided.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor thin film manufacturing, and in particular to a thin film structure of a semiconductor device and a preparation method thereof. Background Art

[0002] In semiconductor manufacturing, ILD refers to the dielectric material used to isolate different metal layers in the multi-layer metal interconnect structure of a chip.

[0003] When etching ILD, most existing processes use a single or double etch stop layer as a barrier layer. Since the barrier layer has a certain thickness, a certain amount of over-etching is required during etching to ensure that the contact hole is fully opened. However, over-etching of the salicide (self-aligned layer) can easily cause the device to be unable to form ohmic contact, resulting in a decrease in device performance. Summary of the invention

[0004] Based on this, it is necessary to provide a thin film structure of a semiconductor device and a preparation method thereof to address the above-mentioned technical problems, so as to at least ensure that the contact hole is fully opened when etching the thin film structure, and avoid the problem that the semiconductor device cannot form ohmic contact due to over-etching of the salicide (self-alignment layer) of the thin film structure, thereby causing the performance of the semiconductor device to deteriorate.

[0005] In order to achieve the above-mentioned purpose and other purposes, in a first aspect, the present disclosure provides a thin film structure of a semiconductor device, including: a substrate; a conductive layer located on the substrate, the conductive layer covering a portion of the substrate; a first self-alignment layer located on the conductive layer; a blocking layer located on the first self-alignment layer and the substrate not covered by the conductive layer, the blocking layer including a first etch stop layer, a second etch stop layer and a third etch stop layer stacked in sequence along a direction perpendicular to the substrate; and a dielectric layer located on the blocking layer.

[0006] In the semiconductor thin film structure in the above embodiment, a first etch stop layer, a second etch stop layer and a third etch stop layer are formed which are stacked in sequence along a direction perpendicular to the substrate. By adding the first etch stop layer, the problem of over-etching of the salicide (self-alignment layer) when etching the thin film structure, which is very easy to occur, is avoided, resulting in the semiconductor device being unable to form an ohmic contact, thereby causing the performance of the semiconductor device to deteriorate.

[0007] In one embodiment, it further includes: a first through hole, the first through hole is located at a first target position of the thin film structure and exposes a portion of the first alignment layer, and the first target position is a position corresponding to the first self-alignment layer in the thin film structure.

[0008] In one of the embodiments, a second self-alignment layer is further included, which is located in the substrate and covers a portion of the top surface of the substrate. A barrier layer and a dielectric layer are formed on the second self-alignment layer and are sequentially stacked in a direction perpendicular to the substrate.

[0009] In one embodiment, a second through hole is further included. The second through hole is located at a second target position of the thin film structure and exposes a portion of the second alignment layer. The second target position is a position corresponding to the second self-alignment layer in the thin film structure.

[0010] In one embodiment, the thickness of the conductive layer is

[0011] In one embodiment, the thickness of the dielectric layer is

[0012] In one embodiment, the thickness of the first etch stop layer is The thickness of the second etch stop layer is The thickness of the third etch stop layer is

[0013] In the thin film structure in the above embodiment, by limiting the thickness of the first etch stop layer, the second etch stop layer and the third etch stop layer, it is ensured that when the thin film structure is etched, the contact hole can be fully opened, and the problem of the semiconductor device being unable to form an ohmic contact due to over-etching of the salicide (self-alignment layer) can be avoided, thereby preventing the performance of the semiconductor device from being degraded.

[0014] In a second aspect, an embodiment of the present disclosure also provides a method for preparing a thin film structure of a semiconductor device, comprising: providing a substrate; forming a conductive layer on the substrate, the conductive layer covering a portion of the substrate; forming a first self-alignment layer on the conductive layer; forming a blocking layer on the first self-alignment layer and the substrate not covered by the conductive layer, the blocking layer comprising a first etch stop layer, a second etch stop layer and a third etch stop layer stacked in sequence along a direction perpendicular to the substrate; and forming a dielectric layer on the blocking layer.

[0015] In the method for preparing the thin film structure of the semiconductor device in the above embodiment, a first etch stop layer, a second etch stop layer and a third etch stop layer which are stacked in sequence along a direction perpendicular to the substrate are formed. By adding the first etch stop layer, the problem of over-etching of the salicide (self-alignment layer) which is very likely to occur when etching the thin film structure, resulting in the inability of the semiconductor device to form an ohmic contact, thereby causing the performance of the semiconductor device to deteriorate, is avoided.

[0016] In one embodiment, the method further includes: using dry etching to etch the thin film structure at a first target position and a second target position to form a first intermediate through hole and a second intermediate through hole, wherein the first intermediate through hole and the second intermediate through hole expose a second etch stop layer; using wet etching to etch the second etch stop layer exposed by the first intermediate through hole and the second intermediate through hole to form a third intermediate through hole and a fourth intermediate through hole, wherein the third intermediate through hole and the fourth intermediate through hole expose the first etch stop layer; using dry etching to etch the first etch stop layer exposed by the third intermediate through hole and the fourth intermediate through hole to form a first through hole and a second through hole, wherein the first through hole and the second through hole expose a first self-alignment layer and a second self-alignment layer; wherein the second sub-alignment layer is formed in the substrate and covers a portion of the top surface of the substrate, and a barrier layer and a dielectric layer are formed on the second self-alignment layer and are sequentially stacked and arranged in a direction perpendicular to the substrate, the first target position is a position corresponding to the first self-alignment layer in the thin film structure, and the second target position is a position corresponding to the second self-alignment layer in the thin film structure.

[0017] In one of the embodiments, when dry etching is used to etch the dielectric layer and the third barrier layer, the etching selectivity ratio of the dry etching between the dielectric layer and the third barrier layer is a first etching selectivity ratio; when wet etching is used, the etching selectivity ratio of the wet etching between the second barrier layer and the third barrier layer is a second etching selectivity ratio; wherein the first etching selectivity ratio is greater than the second etching selectivity ratio.

[0018] In the method for preparing the thin film structure of the semiconductor device in the above-mentioned embodiment, by combining different etching methods, it is ensured that the through holes of the thin film structure are completely opened after etching, and the problem of over-etching of the salicide (self-alignment layer) which is very easy to occur when etching the thin film structure, resulting in the semiconductor device being unable to form an ohmic contact, thereby causing the performance of the semiconductor device to deteriorate, is avoided.

[0019] On the third aspect, the embodiments of the present disclosure also provide a semiconductor device, including: the thin film structure of the semiconductor device in any of the above embodiments, which can at least ensure that the contact hole is fully opened when the thin film structure is etched, and avoid the problem that the semiconductor device cannot form an ohmic contact due to over-etching of the salicide (self-alignment layer) of the thin film structure, thereby causing the performance of the semiconductor device to deteriorate.

[0020] In a fourth aspect, an embodiment of the present disclosure further provides an electronic device, comprising: a thin film structure of a semiconductor device in any of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0022] Figure 1 A schematic flow chart of a method for preparing a thin film structure of a semiconductor device provided in an embodiment;

[0023] Figure 2 A schematic diagram of a thin film structure of a semiconductor device provided in an embodiment Figure 1 ;

[0024] Figure 3 A schematic diagram of a thin film structure of a semiconductor device provided in an embodiment Figure 2 ;

[0025] Figure 4 A schematic diagram of a structure for etching a thin film structure of a semiconductor device provided in an embodiment Figure 1 ;

[0026] Figure 5 A schematic diagram of a structure for etching a thin film structure of a semiconductor device provided in an embodiment Figure 2 ;

[0027] Figure 6 A schematic diagram of a structure for etching a thin film structure of a semiconductor device provided in an embodiment Figure 3 .

[0028] Description of reference numerals:

[0029] 101. substrate; 102. conductive layer; 103. first self-aligned layer; 104. first etch stop layer; 105. second etch stop layer; 106. third etch stop layer; 107. dielectric layer; 201. second self-aligned layer; 301. first middle through hole; 302. second middle through hole; 401. third middle through hole; 402. fourth middle through hole; 501. first through hole; 502. second through hole. DETAILED DESCRIPTION

[0030] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0032] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0033] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0034] When used herein, the singular forms "a", "an" and " / the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of features, integers, steps, operations, elements and / or components can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0035] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic representations of ideal embodiments (and intermediate structures) of the present disclosure, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the present disclosure should not be limited to the particular shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the present disclosure.

[0036] Please refer to Figure 1-Figure 6 The present disclosure provides a method for preparing a thin film structure of a semiconductor device, comprising the following steps:

[0037] Step S1000: providing a substrate 101 .

[0038] Wherein, the substrate 101 can be made of semiconductor material, insulating material, conductor material or any combination thereof. The substrate 101 can be a single-layer structure or a multi-layer structure. For example, the substrate 101 can be a silicon substrate 101, a silicon germanium substrate 101, a silicon germanium carbon substrate 101, a silicon carbide substrate 101, a gallium arsenide substrate 101, an indium arsenide substrate 101, an indium phosphide substrate 101 or other III / V semiconductor substrates 101 or II / VI semiconductor substrates 101. Alternatively, for example, the substrate 101 can be a layered substrate 101 including silicon / silicon carbide, silicon on insulator or silicon germanium on insulator. Therefore, the type of substrate 101 should not limit the scope of protection of the present disclosure.

[0039] Step S2000 : forming a conductive layer 102 on the substrate 101 .

[0040] The conductive layer 102 covers a portion of the substrate 101 .

[0041] Step S3000 : forming a first self-aligned layer 103 on the conductive layer 102 .

[0042] Step S4000: Form a barrier layer on the first self-alignment layer 103 and the substrate 101 not covered by the conductive layer 102.

[0043] Wherein, the barrier layer includes a first etch stop layer 104, a second etch stop layer 105, and a third etch stop layer 106 that are sequentially stacked along the direction perpendicular to the substrate 101.

[0044] Step S5000: Form a dielectric layer 107 on the barrier layer.

[0045] Here, the thin film structure of the semiconductor device formed through the above steps is the ILD. The full name of ILD in the semiconductor is Isolation Layer Definition, that is, isolation layer definition, and it is also called Inter-Layer Dielectric, that is, interlayer barrier. It refers to using a special material layer to isolate the current or signal between different components during the semiconductor manufacturing process.

[0046] In the existing process, the barrier layer of the thin film structure of the semiconductor device is generally a single layer (such as SiN, etc.) or a bilayer structure (such as SiON + SiN, etc.). The thin film etch stop should be when the bottommost barrier layer is etched. However, because the barrier layer has a certain thickness, a certain amount of over-etching is required during etching to ensure that the through hole (contact hole) is completely opened. However, due to the large etch selectivity between the barrier layer and the dielectric layer 107, it is easy to cause over-etching of the salicide (self-alignment layer), and it is easy to etch through the salicide during etching, unable to form an ohmic contact, resulting in the device's performance not meeting expectations.

[0047] Specifically, please refer to Figure 1 , Figure 1 which is the structural schematic diagram of the thin film structure of the semiconductor device provided in the embodiment of the present application. The thin film structure of the semiconductor device provided in the present application includes: a substrate 101; a conductive layer 102 located on the substrate 101, and the conductive layer 102 covers a part of the substrate 101; a first self-alignment layer 103 located on the conductive layer 102; a barrier layer located on the first self-alignment layer 103 and the substrate 101 not covered by the conductive layer 102, and the barrier layer includes a first etch stop layer 104, a second etch stop layer 105, and a third etch stop layer 106 that are sequentially stacked along the direction perpendicular to the substrate 101; a dielectric layer 107 located on the barrier layer.

[0048] In this way, by adding an additional etch stop layer, a first etch stop layer 104 with a relatively large etch selectivity is generated before the original double etch stop layer, forming an etch stop layer (i.e., a barrier layer) with a sandwich structure. This can at least ensure that the contact holes are fully opened during the etching of the thin film structure and avoid the problem that the thin film structure cannot form an ohmic contact due to over-etching of the salicide (self-aligned layer), thereby causing a decline in the performance of the semiconductor device.

[0049] Here, a deposition process can be used to form the thin film structure of the semiconductor device.

[0050] Among them, the first etch stop layer 104 can be SiN, the second etch stop layer 105 can be SiON, and the second etch stop layer 105 can be SiN.

[0051] In one embodiment, the thickness of the conductive layer 102 is

[0052] As an example, the thickness of the conductive layer 102 can be and so on.

[0053] In one embodiment, the thickness of the dielectric layer 107 is

[0054] As an example, the thickness of the dielectric layer 107 can be and so on.

[0055] Among them, the material of the dielectric layer 107 can be PSG (Phosphosilicate Glass), which is a binary glass composed of silicon and phosphorus. PSG plays an important role in semiconductor processes, mainly used for smoothing the underlying layer, filling isolation, and serving as a buffer layer or planarization layer.

[0056] In one embodiment, the thickness of the first etch stop layer 104 is The thickness of the second etch stop layer 105 is The thickness of the third etch stop layer 106 is

[0057] As an example, the thickness of the first etch stop layer 104 can be and so on. Preferably, the thickness of the first etch stop layer 104 can be

[0058] As an example, the thickness of the second etch stop layer 105 can be and so on. Preferably, the thickness of the second etch stop layer 105 can be

[0059] As an example, the thickness of the third etch stop layer 106 may be Preferably, the thickness of the third etch stop layer 106 can be

[0060] In the thin film structure in the above embodiment, by limiting the thickness of the first etch stop layer 104, the second etch stop layer 105 and the third etch stop layer 106, it is ensured that when the thin film structure is etched, the contact hole can be fully opened, and the problem of the semiconductor device being unable to form an ohmic contact due to over-etching of the salicide (self-alignment layer) of the thin film structure, thereby preventing the performance of the semiconductor device from being degraded, can be avoided.

[0061] Optionally, the stacking method of multiple etch stop layers can be more varied and applicable to different process scenarios. The material selection of the bottom new etch stop layer can be wider, forming a composite stop layer with different design schemes, further protecting the salicide opening and device reliability.

[0062] As an example, see Figure 2 In some embodiments, the thin film structure of the semiconductor device further includes a second self-alignment layer 201 , which is located in the substrate 101 and covers a portion of the top surface of the substrate 101 .

[0063] A barrier layer and a dielectric layer 107 are formed on the second self-aligned layer 201 and are sequentially stacked in a direction perpendicular to the substrate 101 .

[0064] As an example, the step of etching the thin film structure of the semiconductor device includes: using dry etching to etch the thin film structure at a first target position and a second target position to form a first intermediate through hole 301 and a second intermediate through hole 302, wherein the first intermediate through hole 301 and the second intermediate through hole 302 expose the second etch stop layer 105; using wet etching to etch the second etch stop layer 105 exposed by the first intermediate through hole 301 and the second intermediate through hole 302 to form a third intermediate through hole 401 and a fourth intermediate through hole 402, wherein the third intermediate through hole 401 and the fourth intermediate through hole 402 expose the first etch stop layer 104; using dry etching to etch the first etch stop layer 104 exposed by the third intermediate through hole 401 and the fourth intermediate through hole 402 to form a first through hole 501 and a second through hole 502, wherein the first through hole 501 and the second through hole 502 expose the first self-alignment layer 103 and the second self-alignment layer 201.

[0065] Among them, the second sub-alignment layer is formed in the substrate 101 and covers a portion of the top surface of the substrate 101. A blocking layer and a dielectric layer 107 are formed on the second self-alignment layer 201 and are stacked in sequence along a direction perpendicular to the substrate 101. The first target position is the position corresponding to the first self-alignment layer 103 in the thin film structure, and the second target position is the position corresponding to the second self-alignment layer 201 in the thin film structure.

[0066] As an example, see Figure 3 , Figure 3 By dry etching, the thin film structure is etched at the first target position and the second target position to form a first middle through hole 301 and a second middle through hole 302. The first middle through hole 301 and the second middle through hole 302 expose the thin film structure of the semiconductor device corresponding to the step of etching the second etch stop layer 105.

[0067] like Figure 3 As shown in , since the etching selectivity ratio between the dielectric layer 107 and the third etch stop layer 106 is greater than the etching selectivity ratio between the third etch stop layer 106 and the second etch stop layer 105, a dry etching process is adopted to etch to the second etch stop layer 105, exposing the second etch stop layer 105 and sealing the surrounding area.

[0068] As an example, see Figure 4 , Figure 4 By adopting wet etching, the second etch stop layer 105 exposed by the first middle through hole 301 and the second middle through hole 302 is etched to form a third middle through hole 401 and a fourth middle through hole 402. The third middle through hole 401 and the fourth middle through hole 402 expose the thin film structure of the semiconductor device corresponding to the step of forming the first etch stop layer 104.

[0069] like Figure 4 As shown in FIG. 1 , the second etch stop layer 105 can be removed by a wet etching process to expose the first etch stop layer 104 .

[0070] In this way, the second etch stop layer 105 can be removed by a wet etching process to expose the first etch stop layer 104 without causing hollowing.

[0071] The wet etching process is carried out under the conditions of using phosphoric acid with a concentration of 60% to 90% and etching at a temperature of 140° C. to 180° C. for 2 to 3 minutes.

[0072] As an example, see Figure 5 , Figure 5By dry etching, the first etch stop layer 104 exposed by the third middle through hole 401 and the fourth middle through hole 402 is etched to form the first through hole 501 and the second through hole 502. The first through hole 501 and the second through hole 502 expose the thin film structure of the semiconductor device corresponding to the step of the first self-alignment layer 103 and the second self-alignment layer 201.

[0073] Here, the first etch stop layer 104 is removed by dry etching process to expose the complete contact hole (the first through hole 501 and the second through hole 502), and the Salicide over-etching will not occur due to the existence of the first etch stop layer 104. It is ensured that the contact hole is fully opened, and the problem that the semiconductor device cannot form an ohmic contact due to over-etching of the Salicide (self-aligned layer) in the thin film structure is avoided, thereby preventing the performance of the semiconductor device from being reduced.

[0074] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0075] Based on the same inventive concept, the disclosed embodiment also provides a thin film structure of a semiconductor device obtained based on the method for preparing the thin film structure of a semiconductor device in the aforementioned embodiment. The implementation scheme of the problem solved by the thin film structure of the semiconductor device is similar to the implementation scheme recorded in the aforementioned method, so the specific limitations in the thin film structure embodiments of one or more semiconductor devices provided below can refer to the limitations of the method for preparing the thin film structure of a semiconductor device in the above text, and will not be repeated here.

[0076] In some embodiments, please refer to Figure 2 , Figure 2 A schematic diagram of a thin film structure of a semiconductor device provided in an embodiment Figure 1, including: a substrate 101; a conductive layer 102, located on the substrate 101, the conductive layer 102 covers a portion of the substrate 101; a first self-aligned layer 103, located on the conductive layer 102; a barrier layer, located on the first self-aligned layer 103 and the substrate 101 not covered by the conductive layer 102, the barrier layer including a first etch stop layer 104, a second etch stop layer 105 and a third etch stop layer 106 stacked in sequence along a direction perpendicular to the substrate 101; a dielectric layer 107, located on the barrier layer.

[0077] In some embodiments, it further includes: a first through hole 501, which is located at a first target position of the thin film structure and exposes a portion of the first alignment layer. The first target position is a position corresponding to the first self-alignment layer 103 in the thin film structure.

[0078] In some embodiments, please refer to Figure 3 , Figure 3 A schematic diagram of a thin film structure of a semiconductor device provided in an embodiment Figure 2 , Figure 3 The structure of the thin film structure of the provided semiconductor device also includes:

[0079] It also includes a second self-aligned layer 201 located in the substrate 101 and covering a portion of the top surface of the substrate 101 . The second self-aligned layer 201 has a barrier layer and a dielectric layer 107 stacked in sequence in a direction perpendicular to the substrate 101 .

[0080] In some embodiments, a second through hole 502 is further included. The second through hole 502 is located at a second target position of the thin film structure and exposes a portion of the second alignment layer. The second target position is a position corresponding to the second self-alignment layer 201 in the thin film structure.

[0081] In some embodiments, the thickness of the conductive layer 102 is

[0082] In some embodiments, the thickness of the dielectric layer 107 is

[0083] In some embodiments, the thickness of the first etch stop layer 104 is The thickness of the second etch stop layer 105 is The thickness of the third etch stop layer 106 is

[0084] In some embodiments, the embodiments of the present disclosure also provide a semiconductor device, including: the thin film structure of the semiconductor device in any of the above embodiments, which can at least ensure that the contact hole is fully opened when the thin film structure is etched, and avoid the problem that the semiconductor device cannot form an ohmic contact due to over-etching of the salicide (self-alignment layer) of the thin film structure, thereby causing the performance of the semiconductor device to deteriorate.

[0085] In some embodiments, the present disclosure provides an electronic device, including a semiconductor device of any one of the disclosed embodiments. The electronic device is, for example but not limited to, a suitable type of electronic product such as a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, etc. Consumer electronic products include mobile phones, tablet computers, laptop computers, desktop monitors, all-in-one computers, etc. Home electronic products include smart door locks, televisions, refrigerators, wearable devices, etc. Vehicle-mounted electronic products include vehicle-mounted navigation systems, vehicle-mounted DVDs, etc. Financial terminal products include The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0086] The above embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the attached claims.

Claims

1. A thin film structure of a semiconductor device, characterized in that: include: substrate; A conductive layer, located on the substrate, wherein the conductive layer covers a portion of the substrate; A first self-aligned layer, located on the conductive layer; A barrier layer, located on the first self-alignment layer and the substrate not covered by the conductive layer, the barrier layer comprising a first etch stop layer, a second etch stop layer and a third etch stop layer which are sequentially stacked in a direction perpendicular to the substrate; The dielectric layer is located on the barrier layer.

2. The thin film structure according to claim 1, characterized in that: Also includes: A first through hole is located at a first target position of the thin film structure and exposes a portion of the first alignment layer, wherein the first target position is a position corresponding to the first self-alignment layer in the thin film structure.

3. The thin film structure according to claim 2, characterized in that: It also includes a second self-alignment layer located in the substrate and covering a portion of the top surface of the substrate. The second self-alignment layer is formed with the barrier layer and the dielectric layer which are sequentially stacked and arranged in a direction perpendicular to the substrate.

4. The thin film structure according to claim 3, characterized in that: It also includes a second through hole, which is located at a second target position of the thin film structure and exposes a portion of the second alignment layer. The second target position is a position corresponding to the second self-alignment layer in the thin film structure.

5. The thin film structure according to claim 1, characterized in that: The thickness of the conductive layer is 6. The thin film structure according to claim 1, characterized in that: The thickness of the dielectric layer is 7. The thin film structure according to claim 1, characterized in that: The thickness of the first etch stop layer is The thickness of the second etch stop layer is The thickness of the third etch stop layer is 8. A method for preparing a thin film structure of a semiconductor device, characterized in that: The method comprises: providing a substrate; forming a conductive layer on the substrate, wherein the conductive layer covers a portion of the substrate; forming a first self-aligned layer on the conductive layer; Forming a barrier layer on the first self-aligned layer and the substrate not covered by the conductive layer, wherein the barrier layer comprises a first etch stop layer, a second etch stop layer and a third etch stop layer which are sequentially stacked in a direction perpendicular to the substrate; A dielectric layer is formed on the barrier layer.

9. The method according to claim 8, characterized in that The method further comprises: Using dry etching, etching the thin film structure at the first target position and the second target position to form a first middle through hole and a second middle through hole, wherein the first middle through hole and the second middle through hole expose the second etch stop layer; Using wet etching, etching the second etch stop layer exposed by the first middle through hole and the second middle through hole to form a third middle through hole and a fourth middle through hole, wherein the third middle through hole and the fourth middle through hole expose the first etch stop layer; Using dry etching, etching the first etch stop layer exposed by the third middle through hole and the fourth middle through hole to form a first through hole and a second through hole, wherein the first through hole and the second through hole expose the first self-alignment layer and the second self-alignment layer; The second sub-alignment layer is formed in the substrate and covers a portion of the top surface of the substrate, the second self-alignment layer is formed with the barrier layer and the dielectric layer stacked in sequence along a direction perpendicular to the substrate, the first target position is the position corresponding to the first self-alignment layer in the thin film structure, and the second target position is the position corresponding to the second self-alignment layer in the thin film structure.

10. The method according to claim 9, characterized in that When the dielectric layer and the third barrier layer are etched by dry etching, the etching selectivity ratio between the dielectric layer and the third barrier layer by dry etching is a first etching selectivity ratio; When wet etching is adopted, the etching selectivity ratio between the second barrier layer and the third barrier layer of the wet etching is a second etching selectivity ratio; Wherein, the first etching selectivity ratio is greater than the second etching selectivity ratio.

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