Semiconductor structure and preparation method thereof

Abstract

The invention relates to the technical field of integrated circuits, in particular to a semiconductor structure and a preparation method thereof. The preparation method of the semiconductor structure comprises the steps of providing a substrate; forming a first dielectric layer on the substrate, wherein a first conductive through hole is formed in the first dielectric layer; a first conductive layer is formed in the first conductive through hole, the first dielectric layer and the first conductive layer have a first warping type, the first dielectric layer and the first conductive layer have a first warping degree, and the first warping degree comprises the warping height of the semiconductor structure after the first dielectric layer and the first conductive layer are formed; based on the first warping type and the first warping degree, a stress buffer layer covering the first dielectric layer and the first conductive layer is formed, the stress buffer layer has a second warping type, the second warping type is opposite to the first warping type, and the first warping degree is in positive correlation with the thickness of the stress buffer layer; and forming a second dielectric layer and a second conductive layer on the stress buffer layer, wherein the second conductive layer is connected with the first conductive layer.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] Integrated circuit advanced manufacturing is usually divided into the front end of line (FEOL) and back end of line (BEOL). As device feature sizes continue to decrease, the current density of metal wiring continues to increase, leading to BEOL delays, which in turn limits circuit performance. In order to enhance circuit performance, copper metal is gradually used to prepare interconnect circuits.

[0003] However, in the copper back-end process, due to the large difference in thermal expansion coefficients between the copper metal layer and the dielectric layer, the stress formed during the chip manufacturing process can cause the wafer to warp. As the thickness of the metal layer continues to increase, the stress of the chip also continues to increase, causing the warping of the wafer to continue to increase. Especially for the thicker top copper metal layer, when the thickness of the copper metal layer reaches or exceeds 3.5μm, the wafer will experience severe warping, which will affect subsequent related process steps. If the wafer warps too much, it may even cause problems such as the machine being unable to transmit and the wafer being broken.

[0004] Therefore, a method for improving wafer warpage is urgently needed. Summary of the invention

[0005] Based on this, it is necessary to provide a semiconductor structure and a preparation method thereof to address the wafer warping problem in the prior art.

[0006] In order to achieve the above object, on the one hand, a method for preparing a semiconductor structure is provided, comprising:

[0007] providing a substrate;

[0008] forming a first dielectric layer on the substrate, wherein the first dielectric layer has a first conductive through hole;

[0009] forming a first conductive layer in the first conductive via, wherein the first dielectric layer and the first conductive layer have a first warpage type, and the first dielectric layer and the first conductive layer have a first warpage, wherein the first warpage includes a warpage height of the semiconductor structure after the first dielectric layer and the first conductive layer are formed;

[0010] Based on the first warping type and the first warping degree, forming a stress buffer layer covering the first dielectric layer and the first conductive layer, the stress buffer layer having a second warping type, the second warping type being opposite to the first warping type, and the first warping degree being positively correlated with a thickness of the stress buffer layer;

[0011] A second dielectric layer and a second conductive layer are formed on the stress buffer layer, wherein the second conductive layer is connected to the first conductive layer.

[0012] In one of the embodiments, when the first warping type conforms to a tensile stress model, the second warping type conforms to a compressive stress model; and when the first warping type conforms to a compressive stress model, the second warping type conforms to a tensile stress model.

[0013] In one embodiment, before forming a stress buffer layer covering the first dielectric layer and the first conductive layer based on the first warping type and the first warping degree, the method includes:

[0014] measuring the first dielectric layer and the first conductive layer;

[0015] When the first dielectric layer and the first conductive layer are warped in an upward direction, it is confirmed that the first warping type conforms to a tensile stress model. When the first dielectric layer and the first conductive layer are warped in a downward direction, it is confirmed that the first warping type conforms to a compressive stress model.

[0016] In one embodiment, the material of the stress buffer layer includes silicon nitride.

[0017] In one embodiment, before forming a stress buffer layer covering the first dielectric layer and the first conductive layer based on the first warping type and the first warping degree, the method includes:

[0018] An etch stop layer covering the first dielectric layer and the first conductive layer is formed.

[0019] In one embodiment, forming a second dielectric layer and a second conductive layer on the stress buffer layer, wherein the second conductive layer is connected to the first conductive layer, comprises:

[0020] forming a second dielectric material layer covering the stress buffer layer;

[0021] Etching the second dielectric material layer and the stress buffer layer to the etch stop layer to form a second conductive via in the second dielectric material layer, and the remaining second dielectric material layer forms a second dielectric layer;

[0022] A second conductive layer is formed in the second conductive through hole, wherein the second conductive layer is connected to the first conductive layer.

[0023] In one embodiment, the forming of the second dielectric material layer covering the stress buffer layer includes:

[0024] Measure the second warpage of the stress buffer layer, where the second warpage includes the warpage height of the semiconductor structure after forming the stress buffer layer;

[0025] When the second warpage is not greater than a preset warpage value, form a second dielectric material layer covering the stress buffer layer.

[0026] On the one hand, a semiconductor structure is provided, including:

[0027] A substrate;

[0028] A first dielectric layer located on the front side of the substrate;

[0029] A first conductive layer located within the first dielectric layer;

[0030] A stress buffer layer covering the side of the first dielectric layer and the first conductive layer away from the substrate, and the side of the stress buffer layer away from the substrate has a flat surface;

[0031] A second dielectric layer covering the side of the stress buffer layer away from the substrate;

[0032] A second conductive layer located within the second dielectric layer, and the second conductive layer is connected to the first conductive layer.

[0033] In one embodiment, the material of the stress buffer layer includes silicon nitride.

[0034] In one embodiment, the semiconductor structure further includes:

[0035] An etch stop layer located on the side of the stress buffer layer close to the substrate.

[0036] The semiconductor structure and its manufacturing method of the present application have the following beneficial effects: First, based on the first warpage type of the first dielectric layer and the first conductive layer, determine the second warpage type of the stress buffer layer, so that the warpage type of the stress buffer layer can balance the warpage types of the first dielectric layer and the first conductive layer, thereby improving the warpage conditions of the first dielectric layer and the first conductive layer and providing a flat surface for the obtained structure. Second, determine the thickness of the stress buffer layer through the first warpage of the first dielectric layer and the first conductive layer, so that the manufacturing process of the stress buffer layer can be precisely controlled. Finally, the material of the stress buffer layer can include silicon nitride, so that the manufacturing cost of the stress buffer layer is low, the process is simple, and the warpage conditions of the obtained structure can be quickly improved. Description of the Drawings

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0038] Figure 1 Schematic diagram of related technology;

[0039] Figure 2 is a flow chart of a method for preparing a semiconductor structure provided in an embodiment;

[0040] Figure 3 is a schematic diagram of a semiconductor structure provided in an embodiment;

[0041] Figure 4 A schematic diagram of a stress buffer layer experiment provided in an embodiment;

[0042] Figure 5 FIG. 4 is a schematic diagram of a semiconductor structure provided in another embodiment.

[0043] Description of reference numerals: semiconductor structure 100 ; substrate 110 ; first dielectric layer 120 ; first conductive layer 130 ; metal barrier layer 131 ; stress buffer layer 140 ; ​​etch stop layer 150 ; third dielectric layer 151 ; second dielectric material layer 160 .

[0044] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more drawings. The additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the embodiments and / or examples currently described, and the best modes of these inventions currently understood. DETAILED DESCRIPTION

[0045] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0047] In each embodiment, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in each embodiment can be understood according to the specific situation.

[0048] It should be understood that when an element or layer is referred to as being "on, adjacent to, or connected to other elements or layers, it may be directly on, adjacent to, or connected to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, or directly connected to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present embodiment, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part.

[0049] Spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used herein to describe the relationship between an element or feature shown in the figures and other elements or features. It should be understood that in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, the element or feature described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0050] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0051] Embodiments of the present application are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the present application, so that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing techniques. The regions shown in the figures are schematic in nature, and their shapes do not represent the actual shapes of the regions of the device and do not limit the scope of the embodiments of the present application.

[0052] As mentioned in the background art, due to the large difference in thermal expansion coefficients between the copper metal layer and the dielectric layer, the stress generated during the chip manufacturing process can cause the wafer to warp. Figure 1 , the semiconductor structure 10 in the related art includes a substrate 11, a first dielectric layer 12, and a copper conductive layer 13. At this time, the thermal expansion coefficients of the three are quite different, resulting in warping on the surface of the structure. This affects the preparation of the second dielectric layer 14 and the third dielectric layer 15. For example, this will cause the semiconductor structure 10 (for example, a chip, a wafer, etc.) after the second dielectric layer 14 and the third dielectric layer 15 are deposited and formed to have more serious warping.

[0053] Based on this, in one embodiment, see Figure 2 , a method for preparing a semiconductor structure 100 is provided. Figure 3 is a schematic diagram of a semiconductor structure 100. The method for preparing the semiconductor structure 100 comprises the following steps:

[0054] Step S2: providing a substrate 110 .

[0055] Step S4: forming a first dielectric layer 120 on the substrate 110 , wherein the first dielectric layer 120 has a first conductive via.

[0056] Step S6: forming a first conductive layer 130 in the first conductive via, wherein the first dielectric layer 120 and the first conductive layer 130 have a first warpage type, and the first dielectric layer 120 and the first conductive layer 130 have a first warpage, wherein the first warpage includes a warpage height of the semiconductor structure 100 after forming the first dielectric layer 120 and the first conductive layer 130.

[0057] Step S8: Based on the first warping type and the first warping degree, a stress buffer layer 140 covering the first dielectric layer 120 and the first conductive layer 130 is formed, wherein the stress buffer layer 140 has a second warping type which is opposite to the first warping type, and the first warping degree is positively correlated with the thickness of the stress buffer layer 140.

[0058] Step S10 : forming a second dielectric layer and a second conductive layer on the stress buffer layer 140 , wherein the second conductive layer is connected to the first conductive layer.

[0059] In step S2, the substrate 110 may be made of semiconductor material, insulating material or any combination thereof. The substrate 110 may be a single-layer structure or a multi-layer structure. For example, the material of the substrate 110 may include silicon, silicon germanium, silicon germanium carbon, etc. The substrate 110 may include a conductive structure, an electronic device, etc. This embodiment does not specifically limit this.

[0060] In step S4, as an example, the first dielectric layer 120 may include film layers such as an etch stop layer 150, a low dielectric constant layer, and a silicon dioxide layer. The material of the first dielectric layer 120 may include silicon carbonitride, carbon silicon oxyhydride, silicon dioxide, and the like. As an example, the first dielectric layer 120 may be formed using one or more of a chemical vapor deposition process, an atomic layer deposition process, a high-density plasma deposition process, a plasma enhanced deposition process, and a spin-on dielectric layer process.

[0061] The first dielectric layer 120 has a plurality of first conductive vias. The first conductive vias may penetrate the first dielectric layer 120. As an example, a first dielectric material layer covering the substrate 110 may be formed first, and then a hard mask layer covering the first dielectric material layer may be formed. The first dielectric material layer is patterned based on the hard mask layer, and after the resulting structure is cleaned, first conductive vias may be formed in the first dielectric material layer, and the remaining first dielectric material layer forms the first dielectric layer 120.

[0062] In step S6, a first conductive layer 130 filling the first conductive via may be formed. As an example, the material of the first conductive layer 130 may include metals such as copper and tungsten.

[0063] Specifically, a metal barrier layer 131 may be deposited in the first conductive via first, and then a first conductive material layer covering the metal barrier layer 131 may be formed. The first conductive material layer outside the first conductive via is removed by a chemical mechanical polishing process or a mechanical polishing process, and the remaining first conductive material layer forms the first conductive layer 130.

[0064] Since the thermal expansion coefficient of the first conductive layer 130 is significantly different from that of the first dielectric layer 120, the semiconductor structure 100 (chip) after the first dielectric layer 120 and the first conductive layer 130 are deposited may be warped. At this time, the first warping type and the corresponding first warping degree of the first dielectric layer 120 and the first conductive layer 130 may be determined. Specifically, the first warping degree may be the warping height of the edge of the obtained structure relative to the center of the obtained structure (e.g., Figure 1 In addition, the first warping degree may also include a warping angle of an edge of the obtained structure relative to a center of the obtained structure.

[0065] In step S8, the stress buffer layer 140 may have a second warpage type. The second warpage type is opposite to the first warpage type. Specifically, when the first warpage type conforms to the tensile stress model, the second warpage type conforms to the compressive stress model, and when the first warpage type conforms to the compressive stress model, the second warpage type conforms to the tensile stress model.

[0066] The thickness of the stress buffer layer 140 may be in the range of 1KÅ~10KÅ. Specifically, the first warpage of the first dielectric layer 120 and the first conductive layer 130 is positively correlated with the thickness of the stress buffer layer 140. Specifically, the greater the first warpage, the thicker the stress buffer layer 140 may be. As an example, when the first warpage type of the first dielectric layer 120 and the first conductive layer 130 conforms to the tensile stress model and the first warpage exceeds 300μm, the stress buffer layer 140 may conform to the compressive stress model and the compressive stress of the stress buffer layer 140 may be in the range of -0.5GPa~-1.3GPa. Therefore, the thickness of the stress buffer layer 140 may be in the range of 8KÅ~10KÅ. Please refer to Figure 4 ,from Figure 4 It can be seen that the original first warpage of the structure was more than 300 μm. After depositing the stress buffer layer 140 , the structure no longer has the problem of wafer warpage.

[0067] Further, the material of the stress buffer layer 140 may include silicon nitride. Exemplarily, when the second warpage type of the stress buffer layer 140 conforms to the compressive stress model, the material of the stress buffer layer 140 may include compressive stress silicon nitride. When the second warpage type of the stress buffer layer 140 conforms to the tensile stress model, the material of the stress buffer layer 140 may include tensile stress silicon nitride. Specifically, when a plasma enhanced chemical vapor deposition process is used, compressive stress silicon nitride or tensile stress silicon nitride can be deposited at a process temperature of 350°C-400°C by adjusting the process pressure, deposition power, gas flow rate, deposition time, etc.

[0068] This embodiment does not limit the specific preparation method of the stress buffer layer 140. It is understood that the stress buffer layer 140 can be formed using one or more processes such as chemical vapor deposition, atomic layer deposition, high-density plasma deposition, plasma enhanced deposition, and spin-on dielectric layer.

[0069] In step S10, a second dielectric layer and a second conductive layer may be formed in the same process chamber as in step S4 and step S6. The second conductive layer may be connected to the first conductive layer. As an example, the material of the second dielectric layer may include silicon dioxide, carbon silicon oxyhydride, silicon carbonitride, etc. The material of the second conductive layer may be the same as the material of the first conductive layer 130.

[0070] In this embodiment, firstly, the second warping type of the stress buffer layer 140 is determined based on the first warping type of the first dielectric layer 120 and the first conductive layer 130, so that the warping type of the stress buffer layer 140 can balance the warping type of the first dielectric layer 120 and the first conductive layer 130, thereby improving the warping of the first dielectric layer 120 and the first conductive layer 130, and providing a flat surface for the obtained structure. Secondly, in this embodiment, the thickness of the stress buffer layer 140 is determined by the first warping of the first dielectric layer 120 and the first conductive layer 130, so that the preparation process of the stress buffer layer 140 can be accurately controlled. Finally, the material of the stress buffer layer 140 in this embodiment can include silicon nitride, so that the preparation cost of the stress buffer layer 140 is low, the process is simple, and the warping of the obtained structure can be quickly improved.

[0071] In one embodiment, see Figure 3 , before step S8, it may include:

[0072] Step S70 : measuring the first dielectric layer 120 and the first conductive layer 130 .

[0073] Step S71: when the first dielectric layer 120 and the first conductive layer 130 are warped upward, it is confirmed that the first warping type conforms to the tensile stress model; when the first dielectric layer 120 and the first conductive layer 130 are warped downward, it is confirmed that the first warping type conforms to the compressive stress model.

[0074] In step S70 , an optical measurement machine may be used to measure the warpage of the semiconductor structure 100 after the first dielectric layer 120 and the first conductive layer 130 are deposited, so as to determine the first warpage type and the first warpage degree.

[0075] In step S71, as an example, when the edge of the obtained structure is higher than the center, it can be considered that the direction of the warping of the semiconductor structure 100 after the deposition of the first dielectric layer 120 and the first conductive layer 130 is upward, and then it can be determined that the first warping type conforms to the tensile stress model. When the edge of the obtained structure is lower than the center, it can be considered that the direction of the warping of the semiconductor structure 100 after the deposition of the first dielectric layer 120 and the first conductive layer 130 is downward, and then it can be determined that the first warping type conforms to the compressive stress model.

[0076] In this embodiment, the obtained structure is measured by an optical measuring machine to determine the first warpage type and the first warpage degree, thereby more accurately determining the warpage degree of the obtained structure, which can help the stress buffer layer 140 improve the warpage of the obtained structure.

[0077] In one embodiment, before step S8, the following steps may be included:

[0078] Step S72 : forming an etch stop layer 150 covering the first dielectric layer 120 and the first conductive layer 130 .

[0079] The etch stop layer 150 can be used in subsequent etching processes. The thickness of the etch stop layer 150 can be in the range of 500Å~2000Å. The material and thickness of the above-mentioned etch stop layer 150 are only for exemplary purposes. In actual embodiments, the above-mentioned materials and thickness are not limited. In addition, before forming the etch stop layer 150, a third dielectric layer 151 with a thickness between 1000Å~3000Å ​​can also be formed. As an example, the material of the third dielectric layer 151 can include materials such as silicon dioxide. The third dielectric layer 151 can be used as a stop layer for subsequent etching of the stress buffer layer 140.

[0080] For further information, see Figure 5 , step S10 may include:

[0081] Step S120 : forming a second dielectric material layer 160 covering the stress buffer layer 140 .

[0082] Step S140 : etching the second dielectric material layer 160 and the stress buffer layer 140 to the etch stop layer 150 , forming a second conductive via in the second dielectric material layer 160 , and the remaining second dielectric material layer 160 forms a second dielectric layer.

[0083] Step S160 : forming a second conductive layer in the second conductive through hole, wherein the second conductive layer is connected to the first conductive layer 130 .

[0084] In step S120, the material of the second dielectric material layer 160 may include silicon dioxide, carbon silicon oxyhydride, silicon carbonitride, etc. This embodiment does not limit the specific material of the second dielectric material layer 160, nor does it limit the specific formation method of the second dielectric material layer 160.

[0085] In step S140, a hard mask layer may be formed on the second dielectric material layer 160, and the hard mask layer may have a pattern. Then, the pattern of the hard mask layer may be transferred to the second dielectric material layer 160 and the stress buffer layer 140 by etching. At this time, a second conductive via may be formed in the second dielectric material layer 160 and the stress buffer layer 140. The second conductive via may at least expose a portion of the first conductive layer 130. Accordingly, at this time, etching may be stopped when etching to the etch stop layer 150. As an example, dry etching or wet etching may be selected for etching, and dry etching may include at least any one of reactive ion etching, inductively coupled plasma etching, or high concentration plasma etching.

[0086] In step S160, the second conductive vias may be filled to form a second conductive layer, which may be connected to the first conductive layer 130 to form a multi-layered conductive film layer. Of course, before forming the second conductive layer, a multi-layer metal barrier layer or the like may also be formed.

[0087] It can be understood that in this embodiment, multiple conductive film layers can be formed on the first conductive layer 130. For example, a third conductive layer, a fourth conductive layer, etc. can be further formed on the second conductive layer. In addition, after the second conductive layer is formed, the warping of the obtained structure can be measured, and the second conductive layer and the second dielectric layer can be formed.

[0088] In addition, step S120 may include:

[0089] Step S121 : measuring a second warpage of the stress buffer layer 140 , where the second warpage includes a warpage height of the semiconductor structure 100 after the stress buffer layer 140 is formed.

[0090] Step S122 : forming a second dielectric material layer 160 covering the stress buffer layer 140 when the second warpage is not greater than a preset warpage value.

[0091] In step S121 to step S122, specifically, the second warpage may include the warping degree and height of the edge of the semiconductor structure 100 relative to the center of the obtained structure after the stress buffer layer 140 is formed. In addition, the second warpage may also include the warping angle of the edge of the semiconductor structure 100 relative to the center of the obtained structure after the stress buffer layer 140 is formed. When the second warpage is not greater than the preset warpage value, it can be considered that the stress buffer layer 140 has a flat surface.

[0092] As an example, an optical measuring machine may be used to measure the warpage of the obtained structure, and after further determining that the warpage of the obtained structure is significantly improved, the second dielectric material layer 160 is formed, thereby facilitating the formation of the second dielectric material layer 160 .

[0093] In this embodiment, firstly, by arranging the stress buffer layer 140 between the etch stop layer 150 and the second dielectric layer, it can be ensured that the warping of the obtained structure is difficult to rebound, so that the obtained structure maintains a flat surface. Secondly, in this embodiment, the etch stop layer 150, the stress buffer layer 140 and the second dielectric layer can be formed in sequence, and then the structure can be processed on the same process machine, further shortening the preparation time and simplifying the preparation process.

[0094] It should be understood that although Figure 2 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 2 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0095] Based on the same inventive concept, please refer to Figure 3 and Figure 5 In one embodiment, a semiconductor structure 100 is provided. It can be understood that the semiconductor structure 100 can be prepared using the method for preparing the semiconductor structure 100 provided in any of the foregoing embodiments or a combination of multiple embodiments. The semiconductor structure 100 may include a substrate 110, a first dielectric layer 120, a first conductive layer 130, a stress buffer layer 140, a second dielectric layer, and a second conductive layer.

[0096] The substrate 110 may be made of semiconductor material, insulating material or any combination thereof. The substrate 110 may be a single-layer structure or a multi-layer structure. For example, the material of the substrate 110 may include silicon, silicon germanium, silicon germanium carbon, etc. The substrate 110 may include a conductive structure, an electronic device, etc. This embodiment does not specifically limit this.

[0097] The substrate 110 may include a front side and a back side that are opposite to each other. The first dielectric layer 120 , the first conductive layer 130 , the stress buffer layer 140 , the second dielectric layer and the second conductive layer may be disposed on the front side of the substrate 110 .

[0098] The first dielectric layer 120 may include an etch stop layer 150, a low dielectric constant layer, a silicon dioxide layer and other film layers. The material of the first conductive layer 130 may include metals such as copper and tungsten. The material of the stress buffer layer 140 may include silicon nitride and the like. The stress buffer layer 140 may be used to buffer the warpage caused by the different thermal expansion coefficients between the first dielectric layer 120 and the first conductive layer 130.

[0099] The material of the second dielectric material layer 160 may include silicon dioxide, carbon silicon oxyhydride, silicon carbonitride, etc. The material of the second conductive layer may include metals such as copper and tungsten, etc. The second conductive layer may be connected to the first conductive layer 130 to form a multi-layered conductive film layer.

[0100] In addition, the semiconductor structure 100 may further include an etch stop layer 150. The etch stop layer 150 may be located on a side of the stress buffer layer 140 close to the substrate 110, that is, the etch stop layer 150 may be located between the stress buffer layer 140 and the first dielectric layer 120. The material of the etch stop layer 150 may include materials such as silicon carbonitride.

[0101] In this embodiment, by arranging the stress buffer layer 140 between the etch stop layer 150 and the second dielectric layer, it can be ensured that the warping of the obtained structure is difficult to rebound, so that the obtained structure maintains a flat surface.

[0102] In the description of the present application, the descriptions with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc., mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In the present application, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that "this embodiment" or "one embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification may not necessarily refer to the same embodiment.

[0103] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of the present application.

[0104] The embodiments described above only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all fall within the scope of protection of the present application. Therefore, the scope of protection of the patent of the present application shall be subject to the attached claims. The above description is only a preferred implementation method of the present application, and does not limit the scope of the patent of the present application. All equivalent structural transformations made by using the contents of the specification and drawings of the present application under the inventive concept of the present application, or direct / indirect application in other related technical fields are included in the scope of protection of the patent of the present application.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; forming a first dielectric layer on the substrate, wherein the first dielectric layer has a first conductive through hole; forming a first conductive layer in the first conductive via, wherein the first dielectric layer and the first conductive layer have a first warpage type, and the first dielectric layer and the first conductive layer have a first warpage, wherein the first warpage includes a warpage height of the semiconductor structure after the first dielectric layer and the first conductive layer are formed; Based on the first warping type and the first warping degree, forming a stress buffer layer covering the first dielectric layer and the first conductive layer, the stress buffer layer having a second warping type, the second warping type being opposite to the first warping type, and the first warping degree being positively correlated with a thickness of the stress buffer layer; A second dielectric layer and a second conductive layer are formed on the stress buffer layer, wherein the second conductive layer is connected to the first conductive layer.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: When the first warping type conforms to the tensile stress model, the second warping type conforms to the compressive stress model; when the first warping type conforms to the compressive stress model, the second warping type conforms to the tensile stress model.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that: Before forming a stress buffer layer covering the first dielectric layer and the first conductive layer based on the first warping type and the first warping degree, the method includes: measuring the first dielectric layer and the first conductive layer; When the first dielectric layer and the first conductive layer are warped in an upward direction, it is confirmed that the first warping type conforms to a tensile stress model. When the first dielectric layer and the first conductive layer are warped in a downward direction, it is confirmed that the first warping type conforms to a compressive stress model.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that: The material of the stress buffer layer includes silicon nitride.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that: Before forming a stress buffer layer covering the first dielectric layer and the first conductive layer based on the first warping type and the first warping degree, the method includes: An etch stop layer covering the first dielectric layer and the first conductive layer is formed.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that: The step of forming a second dielectric layer and a second conductive layer on the stress buffer layer, wherein the second conductive layer is connected to the first conductive layer, comprises: forming a second dielectric material layer covering the stress buffer layer; Etching the second dielectric material layer and the stress buffer layer to the etch stop layer to form a second conductive via in the second dielectric material layer, and the remaining second dielectric material layer forms a second dielectric layer; A second conductive layer is formed in the second conductive through hole, wherein the second conductive layer is connected to the first conductive layer.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that: The forming of a second dielectric material layer covering the stress buffer layer comprises: measuring a second warpage of the stress buffer layer, wherein the second warpage comprises a warpage height of the semiconductor structure after the stress buffer layer is formed; When the second warping degree is not greater than a preset warping value, a second dielectric material layer covering the stress buffer layer is formed.

8. A semiconductor structure, characterized in that: include: substrate; The first dielectric layer is located on the front side of the substrate A first conductive layer, located in the first dielectric layer; A stress buffer layer, covering the first dielectric layer and the first conductive layer on a side away from the substrate, wherein the stress buffer layer has a flat surface on a side away from the substrate; A second dielectric layer, covering a side of the stress buffer layer away from the substrate; The second conductive layer is located in the second dielectric layer, and the second conductive layer is connected to the first conductive layer.

9. The semiconductor structure according to claim 8, characterized in that: The material of the stress buffer layer includes silicon nitride.

10. The semiconductor structure according to claim 8, characterized in that The semiconductor structure further comprises: The etch stop layer is located on a side of the stress buffer layer close to the substrate.

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