Package structure, package system and memory system

Abstract

The embodiment of the invention discloses a packaging body structure, a packaging body system, a manufacturing method of the packaging body system and a memory system, and the packaging body structure comprises a first packaging substrate which is provided with a first surface and a second surface which are oppositely arranged; the first packaging substrate comprises a first corner; the semiconductor device is positioned on the first surface of the first packaging substrate and is coupled with the first packaging substrate; the semiconductor device comprises a second corner; wherein the first corner is aligned with the second corner along a first direction perpendicular to the first packaging substrate; the area of the first package substrate is larger than that of the semiconductor device.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly to a package structure, a package system and a manufacturing method thereof, and a memory system. Background Art

[0002] In the semiconductor manufacturing process, after the wafer is manufactured, it is cut into one or more chips (Die), and the chip is encapsulated with a packaging substrate and other packaging materials to obtain a package structure to prevent the chip from directly contacting the external environment and reduce chip damage. The package structure is used in various integrated circuits to maximize the electrical performance of the chip.

[0003] The package structure can be coupled with the contacts on the printed circuit board (PCB) through processes such as bonding and welding to integrate the package structure into the printed circuit board. The positioning area (or positioning mark) of each package structure is marked on the printed circuit board in a silk-screen manner. Each package structure needs to be aligned with its corresponding positioning area to integrate the package structure into the positioning area. There is still much room for improvement in the process of aligning and integrating the package structure with the printed circuit board. Summary of the invention

[0004] According to some aspects of the embodiments of the present disclosure, a package structure is provided, including: a first package substrate, having a first surface and a second surface arranged opposite to each other; the first package substrate includes a first corner; a semiconductor device, located on the first surface of the first package substrate and coupled to the first package substrate; the semiconductor device includes a second corner; wherein the first corner is aligned with the second corner along a first direction perpendicular to the first package substrate; the area of ​​the first package substrate is larger than the area of ​​the semiconductor device.

[0005] In some embodiments, the first corner is aligned with a third corner of a positioning mark on the printed circuit board.

[0006] In some embodiments, the orthographic projection of the first corner on the plane where the first surface is located coincides with the orthographic projection of the second corner on the plane; or, the orthographic projection of the first corner on the plane where the first surface is located falls within the orthographic projection of the second corner on the plane.

[0007] In some embodiments, an orthographic projection of the semiconductor device on the plane where the first surface is located falls within the first surface.

[0008] In some embodiments, the first packaging substrate includes two first corners, and the semiconductor device includes two second corners; each of the first corners is aligned with a corresponding second corner in the first direction.

[0009] In some embodiments, the two first corners are arranged diagonally.

[0010] In some embodiments, the first surface is a closed polygon formed by a plurality of straight line segments, and the first corner comprises a right angle.

[0011] In some embodiments, the orthographic projection of the semiconductor device on the plane where the first surface is located is a closed polygon surrounded by a plurality of straight line segments, and the second corner comprises a right angle.

[0012] In some embodiments, the semiconductor device further includes: a first conductive channel, which passes through the semiconductor device and is coupled to the first packaging substrate.

[0013] In some embodiments, the package structure further includes: a conductive ball located on the second surface and coupled to the first package substrate.

[0014] According to some aspects of the embodiments of the present disclosure, a packaging system is provided, including: a first packaging substrate, having a first surface and a second surface arranged opposite to each other; the first packaging substrate includes a first corner; a semiconductor device is located on the first surface of the first packaging substrate and is coupled to the first packaging substrate; a second packaging substrate is located on one side of the second surface and is coupled to the first packaging substrate; a positioning mark is provided on the second packaging substrate, and the positioning mark includes a third corner; wherein the first corner is aligned with the third corner along a first direction perpendicular to the second packaging substrate; the area of ​​the first packaging substrate is larger than the area of ​​the positioning mark.

[0015] In some embodiments, the second packaging substrate includes a printed circuit board.

[0016] In some embodiments, the orthographic projection of the first corner on the plane where the first surface is located coincides with the orthographic projection of the third corner on the plane; or, the orthographic projection of the first corner on the plane where the first surface is located falls within the orthographic projection of the third corner on the plane.

[0017] In some embodiments, the first packaging substrate includes two first corners, and the second packaging substrate includes two third corners; each of the first corners is aligned with each of the third corners along the first direction.

[0018] In some embodiments, the two first corners are arranged diagonally.

[0019] In some embodiments, the first surface is a closed polygon formed by a plurality of straight line segments, and the first corner comprises a right angle.

[0020] In some embodiments, the positioning mark is a closed polygon surrounded by multiple straight line segments, and the third corner includes a right angle.

[0021] In some embodiments, the orthographic projection of the positioning mark on the plane where the first surface is located falls within the first surface.

[0022] In some embodiments, the package system further includes: a conductive ball located between the first package substrate and the second package substrate; one side of the conductive ball is coupled to the second surface of the first package substrate, and the other side of the conductive ball is coupled to the second package substrate.

[0023] In some embodiments, the orthographic projection of the semiconductor device on the plane where the first surface is located coincides with the orthographic projection of the positioning mark on the plane; or, the orthographic projection of the semiconductor device on the plane where the first surface is located falls within the orthographic projection of the positioning mark on the plane.

[0024] According to some aspects of the embodiments of the present disclosure, a memory system is provided, comprising the package structure described above, wherein the semiconductor device in the package structure comprises a memory device and / or a memory controller, wherein the memory controller is coupled to the memory device and configured to control the memory device.

[0025] According to some aspects of the embodiments of the present disclosure, a method for manufacturing a packaging system is provided, including: providing a packaging structure, including a first packaging substrate, having a first surface and a second surface relatively arranged, and a semiconductor device located on the first surface; the semiconductor device is coupled to the first packaging substrate, and the first packaging substrate includes a first corner; providing a second packaging substrate; the packaging substrate includes a positioning mark, and the positioning mark includes a third corner; aligning the first corner with the third corner along a first direction perpendicular to the second packaging substrate, and coupling the second surface of the first packaging substrate and the second packaging substrate.

[0026] In some embodiments, aligning the first corner with the third corner to couple the second surface of the first packaging substrate and the second packaging substrate includes: forming a conductive ball on the second surface of the first packaging substrate, aligning the first corner with the third corner, fixing the first packaging substrate to the second packaging substrate through the conductive ball and achieving coupling.

[0027] In some embodiments, the orthographic projection of the first corner on the plane where the first surface is located coincides with the orthographic projection of the third corner on the plane; or, the orthographic projection of the first corner on the plane where the first surface is located falls within the orthographic projection of the third corner on the plane.

[0028] In some embodiments, the first packaging substrate includes two first corners, and the second packaging substrate includes two third corners; each of the first corners is aligned with each of the third corners along the first direction.

[0029] In some embodiments, the two first corners are arranged diagonally.

[0030] In some embodiments, the orthographic projection of the positioning mark on the plane where the first surface is located falls within the first surface.

[0031] In the disclosed embodiment, a semiconductor device is disposed on a first surface of a first package substrate to form a package structure, wherein the semiconductor device is coupled to the first package substrate; a first corner of the first package substrate is aligned with a second corner of the semiconductor device along a first direction perpendicular to the first package substrate to improve the alignment accuracy between the semiconductor device and the first package substrate; the area of ​​the first package substrate is larger than the area of ​​the semiconductor device, which is beneficial to improving the support of the first package substrate for the semiconductor device and the wiring area of ​​the first package substrate. The first package substrate can be integrated on a second package substrate (printed circuit board), and the first corner can be used to align with a third corner of a positioning mark on the second package substrate, thereby improving the alignment accuracy between the package structure and the second package substrate and reducing the occupation of other circuit areas on the second package substrate caused by alignment misalignment. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a schematic diagram of a package structure according to an exemplary embodiment;

[0033] Figure 2 is a schematic diagram of a packaging system according to an exemplary embodiment;

[0034] Figure 3 and Figure 4 is a schematic diagram of alignment between a first packaging substrate and a second packaging substrate according to an exemplary embodiment;

[0035] Figure 5a to Figure 5c is a schematic diagram of a package structure according to an embodiment of the present disclosure;

[0036] Figures 6a to 6e is a schematic diagram of alignment between a semiconductor device and a first packaging substrate in a packaging structure according to an embodiment of the present disclosure;

[0037] Figure 7 is a schematic diagram of alignment of a first packaging substrate and a second packaging substrate in a packaging system according to an embodiment of the present disclosure;

[0038] Figure 8 is a schematic diagram of a package structure including multiple semiconductor chips according to an embodiment of the present disclosure;

[0039] Fig. 9 is a schematic diagram of a packaging system according to an embodiment of the present disclosure;

[0040] Fig.10 is a schematic flow chart of a method for manufacturing a packaging system according to an embodiment of the present disclosure;

[0041] Figures 11a to 11c is a schematic diagram of a method for manufacturing a packaging system according to an embodiment of the present disclosure;

[0042] Fig.12 is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure;

[0043] Fig.13a is a schematic diagram of an exemplary memory card according to an embodiment of the present disclosure;

[0044] Fig.13b is a schematic diagram of an exemplary solid-state drive according to an embodiment of the present disclosure;

[0045] Fig.14 is a schematic diagram of a memory device including a peripheral circuit according to an embodiment of the present disclosure;

[0046] Fig.15 is a cross-sectional schematic diagram of a memory cell array including a NAND memory string according to an embodiment of the present disclosure;

[0047] Fig.16 is a schematic diagram of an exemplary memory device including a memory cell array and a peripheral circuit according to an embodiment of the present disclosure.

[0048] In the above drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar components in different views. Similar reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation. DETAILED DESCRIPTION

[0049] The exemplary embodiments disclosed by the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. In the following description, a large number of specific details are given in order to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of the actual embodiments are not described here, and the known functions and structures are not described in detail.

[0050] In the accompanying drawings, for clarity, the size of the layer, area, element and its relative size may be exaggerated. The same reference numerals represent the same element from beginning to end. It should be understood that when an element or layer is referred to as "on ... ", "adjacent to ... ", "connected to" or "coupled to" other elements or layers, it can be directly on other elements or layers, adjacent to, connected to or coupled to other elements or layers, or there may be an intermediate element or layer. On the contrary, when an element is referred to as "directly on ... ", "directly adjacent to ... ", "directly connected to" or "directly coupled to" other elements or layers, there is no intermediate element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, areas, layers and / or parts, these elements, components, areas, layers and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, area, layer or part from another element, component, area, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, area, layer or part discussed below can be represented as the second element, component, area, layer or part. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section must be present in the present disclosure.

[0051] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0052] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0053] It should be understood that "some embodiments" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiments are included in at least one embodiment of the present disclosure. Therefore, "in some embodiments" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the above-mentioned embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0054] Generally, the semiconductor packaging process may include: providing a semiconductor device with electrical functions, placing the semiconductor device on a packaging substrate, using packaging materials to cover the semiconductor device, the semiconductor device can be coupled through the packaging substrate, and a conductive contact or conductive ball is set on the surface of the side of the packaging substrate where the semiconductor device is not set to form a package junction; wherein the conductive ball can lead out the electrical signal of the packaging substrate to realize the electrical signal interconnection between the semiconductor device and the external integrated circuit. A semiconductor device may include one or more semiconductor chips (Die), and a packaging structure may encapsulate one or more semiconductor devices, that is, a packaging structure may encapsulate one or more semiconductor chips, and a semiconductor chip may be a tube core cut from a finished wafer according to a predetermined cutting path or cutting line. The packaging structure is then integrated into a printed circuit board through welding or patch processing to realize the electrical function of the semiconductor device or semiconductor chip.

[0055] A plurality of package structures, wirings or other electronic components can be integrated on a printed circuit board. To facilitate the integration and interconnection of the various package structures, positioning marks corresponding to the various package structures are marked on the printed circuit board. The package structure is aligned with the corresponding positioning marks, and the contacts of the package structure are welded to the contacts on the printed circuit board to achieve electrical interconnection. After welding, leads can also be set to couple the package structure and the terminals on the printed circuit board.

[0056] Reference Figure 1 As shown, the embodiment of the present disclosure provides a package structure 10, including: a first package substrate 110, having a first surface and a second surface arranged opposite to each other; a semiconductor device 120 located on the first surface of the first package substrate 110, coupled to the first package substrate 110. The first surface is an upper surface in the z direction, the second surface is a lower surface in the z direction, the z direction may be a thickness direction, the x direction may be perpendicular to the z direction, and the y direction involved in other drawings may be perpendicular to the z direction.

[0057] Reference Figure 2 As shown, in some other embodiments, a package system 11 is provided, including a second package substrate 140, and a package structure located on the second package substrate 140, wherein the first package substrate 110 of the package structure and the positioning mark 141 ( Figure 3 The first package substrate 110 may include semiconductor materials, such as silicon interposers, germanium interposers, etc., and may also include materials such as organic resins, glass or ceramics. The second package substrate 140 may include a printed circuit board, or a circuit substrate provided with interconnection circuits, resistors, contacts, terminals or other electronic components. Figure 2 The package structure may include Figure 1 A package structure 10.

[0058] The positioning mark 141 can be printed on the second package substrate 140 by silk screen printing, and a contact point is arranged in the region of the positioning mark 141, which can be coupled with the package structure in a contact manner. For example, the conductive ball 130 on the second surface of the first package substrate 110 of the package structure 10 is welded and coupled with the conductive contact point 1401 on the second package substrate 140; or it is fixed to the second package substrate 140 by plug-in buckle, and the conductive ball 130 is contact-coupled with the conductive contact point 1401 in a non-welding manner, and can be flexibly disassembled.

[0059] In some embodiments, reference Figure 3As shown, the positioning marks 141 on the first packaging substrate 110 and the second packaging substrate 140 have the same size, and the orthographic projection of the first packaging substrate 110 on the second packaging substrate 140 coincides with the positioning mark 141, that is, the orthographic projection of the first packaging substrate 110 on the xoy plane coincides with the orthographic projection of the positioning mark 141 on the xoy plane. Figure 4 As shown, the size of the first packaging substrate 110 is larger than the size of the positioning mark 141 on the second packaging substrate 140 , and the orthographic projection of the positioning mark 141 on the xoy plane falls within the orthographic projection of the first packaging substrate 110 on the xoy plane. Figure 3 and Figure 4 In the embodiment, the first packaging substrate 110 and the positioning mark 141 have the same shape, and the size of the first packaging substrate 110 is greater than or equal to the size of the positioning mark 141. Figure 4 As shown in the example, when the package structure 10 is aligned with the positioning mark 141 along the z direction, the positioning mark 141 will be blocked by the first package substrate 110, making it difficult to align the package structure 10 on the second package substrate 140, thereby reducing the alignment accuracy. Figure 3 As shown in the example, when the package structure 10 is aligned with the positioning mark 141 along the z direction, the positioning mark 141 completely overlaps with the first package substrate 110 and uses the corner for alignment, which improves the alignment accuracy but reduces the area of ​​the first package substrate 110. The contact performance between the terminals on the edge of the positioning mark 141 or adjacent to the edge and the corresponding terminals on the first substrate is reduced, and the terminals are easily exposed, increasing the risk of cold solder joints or broken contacts, and reducing stability. In the embodiment of the present disclosure, the package structure 10 is integrated into the second package substrate 140, and the semiconductor device 120 is coupled to the second package substrate 140 through the first package substrate 110 or other leads to realize the device function. In order to improve the integration of the second package substrate 140, the positioning mark 141 can be arranged in size and shape according to the size of the semiconductor device 120, and the size and shape of the positioning mark 141 can be the same as the size and shape of the semiconductor device 120.

[0060] The disclosed embodiment provides an alignment scheme for a first packaging substrate 110 and a positioning mark 141 on a second packaging substrate 140. The shape of the first packaging substrate 110 is different from the shape of the positioning mark 141. At least one corner on the first packaging substrate 110 is aligned with at least one corner on the positioning mark 141 to improve the alignment accuracy. The area of ​​the first packaging substrate 110 is larger than the area of ​​the positioning mark 141. The area of ​​the first packaging substrate 110 is larger than the area of ​​the positioning mark 141. The area of ​​the first packaging substrate 110 is larger than the area of ​​the semiconductor device 120, thereby increasing the wiring area of ​​the first packaging substrate 110.

[0061] According to some aspects of the embodiments of the present disclosure, referring to Figure 5aAs shown, a package structure 10 is provided, including: a first package substrate 110, having a first surface and a second surface arranged opposite to each other; the first package substrate 110 includes a first corner 1101; a semiconductor device 120, located on the first surface of the first package substrate 110, coupled to the first package substrate 110; the semiconductor device 120 includes a second corner 1201; wherein the first corner 1101 is aligned with the second corner 1201 along a first direction perpendicular to the first package substrate 110; the area of ​​the first package substrate 110 is larger than the area of ​​the semiconductor device 120. Figures 6a to 6e The schematic diagram of the orthographic projection of the semiconductor device 120 on the plane where the first surface is located is shown. The plane where the first surface is located may be an xoy plane. The first corner 1101 and the second corner 1201 are located at Figures 6a to 6e Shown in.

[0062] Figure 5a As shown, the first packaging substrate 110 has a first surface and a second surface arranged opposite to each other along the z direction, the first surface may be an upper surface in the positive z direction, and the second surface may be a lower surface in the negative z direction. The first direction may be the z direction. The first packaging substrate 110 may provide mechanical support for the semiconductor device 120, and may also provide a power supply structure for the semiconductor device 120 to lead out the electrical signals of the semiconductor device 120 and interconnect with structures such as an external printed circuit board or other integrated circuit electrical signals. The first packaging substrate 110 may include semiconductor materials, such as a silicon interposer, a germanium interposer, etc., and may also include materials such as organic resins, glass, or ceramics.

[0063] In some embodiments, the semiconductor device 120 has a first surface and a second surface that are oppositely disposed in the z direction, the first surface may be an upper surface of the semiconductor device 120 in the positive z direction, and the second surface may be a lower surface in the negative z direction. A plurality of first conductive contacts 1231 may be disposed on the second surface of the semiconductor device 120, and the first conductive contacts 1231 are used to couple with the interconnection layer of the first packaging substrate 110.

[0064] In some embodiments, the package structure 10 further includes: a conductive ball 130, which is located on the second surface and coupled to the first package substrate 110. The second surface of the package substrate is provided with a conductive ball 130 or other contacts, and the conductive ball 130 can penetrate the first package substrate 110 and couple with the first conductive contact 1231 to lead out the electrical signal of the semiconductor device 120. The conductive ball 130 can be fixedly coupled with an external integrated circuit as a solder point or pad to lead out the electrical signal of the semiconductor device 120, and can also lead out the heat of the semiconductor device 120 to facilitate heat dissipation. The conductive ball 130 can be used as a contact contact to contact with an external integrated circuit, and can be fixed in a snap-fit ​​manner, and can be flexibly disassembled and assembled. At this time, the two surfaces of the first package substrate 110 and the interior of the first package substrate 110 may not be provided with a conductive structure, and the first package substrate 110 only provides support for the semiconductor device 120. A groove may be provided on the first surface of the first packaging substrate 110, with the opening of the groove facing the first surface, that is, the opening of the groove facing the positive z direction. The groove may provide an accommodating space for the semiconductor device 120, thereby facilitating the fixing of the semiconductor device 120 and providing better protection.

[0065] In some embodiments, the first conductive contact 1231 on the lower surface of the semiconductor device 120 can be used as a bonding pad to bond with the pad on the first package substrate 110 to achieve coupling and fixation. In other embodiments, a solder ball can be set between the semiconductor device 120 and the first package substrate 110, and the first conductive contact 1231 of the semiconductor device 120 and the contact on the first package substrate 110 are soldered and fixed by the solder ball to achieve coupling.

[0066] In some embodiments, the package structure 10 further includes a power supply network, which may include a redistribution layer or other conductive structures. The power supply network may be a part of the first package substrate 110, located on the upper surface of the first package substrate 110, or a part of the power supply network is located on the upper surface of the first package substrate 110, a part of the power supply network is located in the first package substrate 110, and a part of the power supply network is located on the lower surface of the first package substrate 110. The three parts of the power supply network may be coupled through a second conductive channel 111 that penetrates the first package substrate 110. The power supply network may specifically include: a wiring layer, a conductive channel (conductive plug), a conductive contact, a pad or other conductive structure. The conductive ball 130 of this embodiment may be located on the second surface of the first package substrate 110, and the conductive ball 130 does not penetrate the first package substrate 110. The conductive ball 130 may lead the electrical signal of the semiconductor device 120 to be electrically interconnected with the external integrated circuit through the second conductive channel 111, the first conductive contact 1231 and other structures.

[0067] In some embodiments, reference Figure 5bAs shown, a plurality of second conductive contacts 1232 are disposed on the upper surface of the semiconductor device 120 , and the second conductive contacts 1232 are coupled to the first packaging substrate 110 through leads, and specifically can be coupled to contacts on the power supply network on the first packaging substrate 110 through leads.

[0068] Exemplarily, the constituent materials of the first conductive contact 1231 , the second conductive contact 1232 , the lead, other contacts and the power supply network may include but are not limited to: conductive materials such as copper, gold, silver, platinum, aluminum, tungsten, chromium, nickel, titanium, and tin.

[0069] In some embodiments, reference Figure 5c The semiconductor device 120 shown further includes: a first conductive channel 124, which penetrates the semiconductor device 120 and is coupled to the first package substrate 110. The first conductive channel 124 penetrates the semiconductor device 120 and can lead out the electrical signal on the upper surface of the semiconductor device 120 and couple it to the first package substrate 110. For example, the first conductive channel 124 can lead out the electrical signal of the second conductive contact 1232 on the upper surface of the semiconductor device 120 or the internal interconnection layer of the semiconductor device 120, and couple it to the first package substrate 110.

[0070] Figure 5a to Figure 5c The semiconductor device 120 shown includes a semiconductor chip only as an example, and the semiconductor device 120 may also include a plurality of semiconductor chips stacked in the z direction, or may include a plurality of semiconductor chips arranged horizontally in the x direction. Among them, the arrangement mode and type of the semiconductor chips can be selected according to different packaging needs and packaging protocols, and the embodiment of the present disclosure is not limited. When the semiconductor device 120 includes a plurality of semiconductor chips stacked in the z direction, the first surface is the upper surface of the semiconductor chip stacked at the top, and the second surface is the lower surface of the semiconductor chip stacked at the bottom. Exemplarily, the semiconductor chip may include one or more of the following chips: a radio frequency (RF) chip, a positioning (GPS) chip, a storage (DRAM) chip, a storage (NAND) chip, a Bluetooth chip, and a controller chip. Exemplarily, the package structure 10 in the embodiment of the present disclosure can be applied to mobile devices, and the package structure 10 includes but is not limited to: products that execute HBM protocol, products that execute HMC protocol, products that execute Chiplet protocol, products that execute UFS protocol, products that execute EMMC protocol, and products of other protocols.

[0071] In some embodiments, reference Figure 5a to Figure 5cAs shown, the package structure 10 further includes a covering layer 150, which is located on the upper surface of the first package substrate 110, and can cover at least part of the upper surface of the first package substrate 110 while encapsulating the semiconductor device 120. It should be noted that the lower surface of the semiconductor device 120 is disposed on the upper surface of the first package substrate 110, and the lower surface of the semiconductor device 120 and the upper surface of the first package substrate 110 overlap each other in the z direction, the lower surface of the semiconductor device 120 does not contact the covering layer 150, the upper surface and the side of the semiconductor device 120 are covered by the covering layer 150, and the covering layer 150 can contact the upper surface and the side of the semiconductor device 120.

[0072] In some embodiments, the cover layer 150 may include a single-layer packaging material, and the packaging material may include any material known in the art. When the cover layer 150 is a single-layer packaging material, it is an insulating material, including but not limited to: silicon oxide, silicon nitride, silicon oxynitride or resin and other insulating materials. The cover layer 150 provides protection and mechanical support for the semiconductor device 120, reduces damage such as chemical corrosion, mechanical extrusion, vibration, etc. to the package structure 10 during use, and improves the reliability of the package structure 10. The cover layer 150 may include a thermally conductive material, such as a silicone-based thermally conductive material.

[0073] In some embodiments, the cover layer 150 may include a multilayer packaging material, the cover layer 150 may include an insulating layer and a conductive layer, the conductive layer covers the insulating layer, the insulating layer is located between the conductive layer and the semiconductor device 120, and the insulating layer may be in direct contact with the upper surface and side of the semiconductor device 120. The insulating layer may include an insulating material, and the conductive layer may include a conductive material, including but not limited to: copper, gold, silver, platinum, aluminum, tungsten, chromium, nickel, titanium, tin, etc. The conductive layer may be a continuous film layer structure, and the conductive layer may also be a grid structure. The insulating layer provides mechanical support and protection for the semiconductor device 120, and the conductive layer forms a Faraday ring (or a Faraday-like ring) around the semiconductor device 120, reducing the electromagnetic interference of the outside world to the semiconductor device 120 and improving the operating stability of the semiconductor device 120. The conductive layer may be coupled to the ground terminal on the packaging substrate to release the free charge on the conductive layer through the ground terminal, reduce electrostatic damage, and improve stability.

[0074] In some other embodiments, the covering layer 150 also includes a protective layer, which is located at the outermost layer of the covering layer 150, covers the conductive layer, and is used to protect the conductive layer and reduce oxidation of the conductive layer. The covering layer 150 is composed of an insulating layer-conductive layer-protective layer in contact with the semiconductor device 120 from the inside to the outside, wherein the thickness of the insulating layer is the thickest of the three film layers, and the thickness of the conductive layer and the protective layer can be equal and thinner than the thickness of the insulating layer. In addition to being used for electromagnetic shielding and discharging static electricity, the conductive layer can also be used for heat conduction to reduce the operating temperature of the semiconductor device 120. The insulating insulating layer and the protective layer may also include thermal conductive materials for heat conduction and cooling.

[0075] In some embodiments, the contact surface between the semiconductor device 120 and the first packaging substrate 110 may be a rectangle or other polygons such as a pentagon or a hexagon. The orthographic projections of the multiple corners of the semiconductor device 120 on the upper surface of the first packaging substrate 110 are as follows: Figure 6a As shown, the upper surface of the first packaging substrate 110 includes a plurality of corners, wherein at least one of the plurality of corners on the semiconductor device 120 is used as a second corner 1201, and is aligned with at least one of the plurality of corners on the upper surface of the first packaging substrate 110 as a first corner 1101. In some other embodiments, the semiconductor device 120 has only the second corner 1201 for alignment, and the remaining corners are rounded and chamfered.

[0076] It should be pointed out that Figure 6a It can also be Figure 5a or Figure 5b In the top view in the z direction, in the embodiment of the present disclosure, the second corner is Figure 6a The projection of the second corner in the first packaging substrate 110 uses the same reference numeral 1201, which will not be repeated in subsequent figures.

[0077] Reference Figure 6a As shown, one of the multiple corners of the first packaging substrate 110 is used as the first corner 1101 for aligning with the second corner 1201. The semiconductor device 120 may include four corners, which is a cube or a rectangular structure. Its contact surface with the first packaging substrate 110 is a rectangle, and one of the corners is the second corner 1201 for aligning with the first corner 1101 to determine the position of the semiconductor device 120 on the first packaging substrate 110, which is beneficial to control the overall size of the final packaging structure 10, improve the packaging yield, and facilitate the subsequent integration of the packaging structure 10 on the printed circuit board.

[0078] In some embodiments, the orthographic projection of the first corner 1101 on the plane where the first surface is located coincides with the orthographic projection of the second corner 1201 on the plane; or, the orthographic projection of the first corner 1101 on the plane where the first surface is located falls within the orthographic projection of the second corner 1201 on the plane.

[0079] During alignment, the second corner 1201 can be completely aligned with the first corner 1101 in the z direction, that is, the orthographic projection of the first corner 1101 on the plane where the first surface of the first packaging substrate 110 is located coincides with the orthographic projection of the second corner 1201 on the plane. Or there is an alignment error between the second corner 1201 and the first corner 1101, such as Figure 6a For example, the second corner 1201 may protrude from the first corner 1101 in the x-direction or the y-direction, that is, the orthographic projection of the first corner 1101 on the plane where the first surface is located falls within the orthographic projection of the second corner 1201 on the plane, and the distance that the second corner 1201 may protrude from the first corner 1101 in the x-direction or the y-direction may include 0 to 1 mm, such as 0.5 mm or less. For example, Figure 6a In the example, the second corner 1201 and the first corner 1101 are formed by two sides intersecting at a certain angle, which can be both right angles. The distance that the second corner 1201 protrudes from the first corner 1101 in the x direction can refer to the distance between the sides of the first corner 1101 and the second corner 1201 extending in the y direction. Figure 6b As shown, the first corner 1101 may protrude from the second corner 1201 in the x direction or the y direction, that is, the orthographic projection of the second corner 1201 on the plane where the first surface is located falls within the orthographic projection of the first corner 1101 on the plane. Figure 6b The orthographic projection of the semiconductor device 120 on the plane where the first surface is located falls within the first surface.

[0080] In some embodiments, the first package substrate 110 includes two first corners 1101, and the semiconductor device 120 includes two second corners 1201; each first corner 1101 is aligned with a second corner 1201 in a first direction. In some embodiments, the two first corners 1101 are arranged diagonally.

[0081] Reference Figure 6c As shown, the semiconductor device 120 may include two second corners 1201, and the first encapsulation substrate includes two first corners 1101. Each first corner 1101 may be aligned with a second corner 1201 to improve alignment accuracy. The second corner 1201 may be arranged diagonally or non-diagonally on the semiconductor device 120, and the first corner 1101 may be arranged diagonally or non-diagonally on the first encapsulation substrate 110 to align with the first corner 1101.

[0082] In some embodiments, reference Figure 6d As shown, the semiconductor device 120 may include three second corners 1201 , and the first packaging substrate 110 may include three first corners 1101 that are aligned with the second corners 1201 , thereby improving alignment accuracy.

[0083] In some embodiments, reference Figure 6e As shown, the semiconductor device 120 may include four second corners 1201 , and the first packaging substrate 110 may include four first corners 1101 that are aligned with the second corners 1201 , thereby improving alignment accuracy.

[0084] Figure 6c to Figure 6e As shown, the orthographic projection of the first corner 1101 on the plane where the first surface is located coincides with the orthographic projection of the second corner 1201 on the plane; or, the orthographic projection of the first corner 1101 on the plane where the first surface is located falls within the orthographic projection of the second corner 1201 on the plane.

[0085] In some embodiments, the first surface is a closed polygon formed by a plurality of straight line segments, and the first corner 1101 comprises a right angle. In some embodiments, the orthographic projection of the semiconductor device 120 on the plane where the first surface is located is a closed polygon formed by a plurality of straight line segments, and the second corner 1201 comprises a right angle.

[0086] Combination Figures 6a to 6e As shown, the number of corners of the first surface of the first packaging substrate 110 may be greater than the number of the second corners 1201 of the semiconductor device 120. To facilitate wafer dicing, the semiconductor device 120 may be a cube or a cuboid, and the orthographic projection of the semiconductor device 120 on the plane where the first surface is located is a rectangle. The first surface of the first packaging substrate 110 may be a polygonal shape having more corners than the rectangular corners. In some embodiments of the layout design of the first packaging substrate 110, the shape of the first packaging substrate 110 may be formed by cutting away at least one of the four corners of a rectangle. Figures 6a to 6e The shape of the first packaging substrate 110 corresponds to .

[0087] The area of ​​the first packaging substrate 110 is larger than that of the semiconductor device 120, and the orthographic projection area of ​​the semiconductor device 120 on the plane where the first surface of the packaging substrate is located is smaller than the orthographic projection area of ​​the first surface of the first packaging substrate 110 on the plane. The non-overlapping area of ​​the first surface with the semiconductor device 120 in the z direction can be used to set conductive structures such as contacts, terminals, and rewiring to couple with the semiconductor device 120, thereby increasing the wiring area of ​​the first packaging substrate 110.

[0088] In some embodiments, reference Figure 7 As shown, the first corner 1101 is aligned with the third corner 1411 of the positioning mark 141 on the printed circuit board.

[0089] Figure 7 The example of taking Figure 6cA schematic diagram of the alignment scheme of the package structure 10 and the positioning mark 141 on the second package substrate 140, wherein the second package substrate 140 may include a printed circuit board, or may include a circuit substrate provided with interconnection circuits, resistors, contacts, terminals or other electronic components. The orthographic projection of the first corner 1101 on the plane where the first surface is located coincides with the orthographic projection of the third corner 1411 on the plane; or, the orthographic projection of the first corner 1101 on the plane where the first surface is located falls within the orthographic projection of the third corner 1411 on the plane. Figure 6a , Figure 6b , Figure 6d as well as Figure 6e The schematic diagram of the alignment between the package structure 10 and the positioning mark 141 on the second package substrate 140 corresponding to the alignment scheme will not be described in detail.

[0090] The package structure 10 of the embodiment of the present disclosure is integrated onto a printed circuit board. The semiconductor device 120 is coupled to the second package substrate 140 via the first package substrate 110 or other leads to realize the device function. To improve the integration of the second package substrate 140, the positioning mark 141 can be arranged in size and shape according to the size of the semiconductor device 120. The size of the positioning mark 141 can be the same as the size and shape of the semiconductor device 120.

[0091] In the disclosed embodiment, a semiconductor device is disposed on a first surface of a first packaging substrate to form a packaging structure, wherein the semiconductor device is coupled to the first packaging substrate; a first corner of the first packaging substrate is aligned with a second corner of the semiconductor device along a first direction perpendicular to the first packaging substrate to improve the alignment accuracy between the semiconductor device and the first packaging substrate; the area of ​​the first packaging substrate is larger than the area of ​​the semiconductor device, which is beneficial to improving the support of the first packaging substrate for the semiconductor device and the wiring area of ​​the first packaging substrate. The first packaging substrate can be integrated on the second packaging substrate (printed circuit board), the first packaging substrate will not completely cover the second packaging substrate, and the first corner of the first packaging substrate can be used to align with the third corner of the positioning mark on the second packaging substrate, thereby improving the alignment accuracy between the packaging structure and the second packaging substrate and reducing the occupation of other circuit areas on the second packaging substrate caused by alignment misalignment.

[0092] In some embodiments, the semiconductor device 120 further includes: a first conductive channel 124 penetrating the semiconductor device 120 and coupled to the first packaging substrate 110 .

[0093] Reference Figure 5c As shown, the semiconductor device 120 may include a semiconductor chip, and the first conductive channel 124 penetrates the semiconductor chip to lead out the signal on the upper surface of the semiconductor device 120 and couple it to the first packaging substrate 110 .

[0094] The semiconductor device 120 may include a plurality of stacked, coupled semiconductor chips, such as Figure 8 The first semiconductor chip 121 and the second semiconductor chip 122 may be included, and the first semiconductor chip 121 and the second semiconductor chip 122 are bonded through a bonding layer having a plurality of bonding contacts, and the electrical signals are interconnected through the bonding contacts. The first conductive channel 124 may include a first sub-conductive channel 1241 that runs through the first semiconductor chip 121, and a second sub-conductive channel 1242 that runs through the second semiconductor chip 122, and the first sub-conductive channel 1241 and the second sub-conductive channel 1242 are coupled through bonding contacts. Taking two semiconductor chips as an example, the embodiment of the present disclosure does not limit the number and type of semiconductor chips, for example, 3 layers, 4 layers, or even 8 layers and more can be stacked, and the semiconductor chips can also be coupled through solder balls.

[0095] For example, the first semiconductor chip 121 and the second semiconductor chip 122 may both be NAND flash memory chips; the first semiconductor chip 121 may be a DRAM chip, and the second semiconductor chip 122 may be a NAND flash memory chip; the first semiconductor chip 121 may be a logic chip, and the second semiconductor chip 122 may be a NAND flash memory chip or a DRAM chip. The package structure 10 may be a Soc system on chip.

[0096] According to some aspects of the embodiments of the present disclosure, a packaging system is provided. The packaging system can be composed of Figure 5a , Figure 5b , Figure 5c or Figure 8 The packaging structure in the package is integrated into the second packaging substrate 140. A packaging system may include multiple packaging structures. The second packaging substrate 140 may also include interconnection circuits, resistors, contacts, terminals or other electronic components.

[0097] In some embodiments, reference Fig. 9 As shown, a package system 11 is provided, including: a first package substrate 110, having a first surface and a second surface arranged opposite to each other; the first package substrate 110 includes a first corner 1101; a semiconductor device 120, located on the first surface of the first package substrate 110, and coupled to the first package substrate 110; a second package substrate 140, located on one side of the second surface, and coupled to the first package substrate 110; a positioning mark 141 is provided on the second package substrate 140, and the positioning mark 141 includes a third corner 1411; wherein the first corner 1101 is aligned with the third corner 1411 along a first direction perpendicular to the second package substrate 140; and the area of ​​the first package substrate 110 is larger than the area of ​​the positioning mark 141. The positioning mark 141, the first corner 1101, and the third corner 1411 are arranged on the first direction perpendicular to the second package substrate 140. Figure 7 Shown in.

[0098] In some embodiments, the package system 11 further includes: a conductive ball 130 located between the first package substrate 110 and the second package substrate 140 ; ​​one side of the conductive ball 130 is coupled to the second surface of the first package substrate 110 , and the other side is coupled to the second package substrate 140 .

[0099] In some embodiments, the second packaging substrate 140 includes a printed circuit board.

[0100] The second packaging substrate 140 may be provided with a conductive contact 1401 (or a third conductive contact 1401 ), and the conductive ball 130 is coupled to the first packaging substrate 110 to lead out the electrical signal of the semiconductor device 120 , and is coupled to the third conductive contact 1401 to realize the electrical signal interconnection between the semiconductor device 120 and the second packaging substrate 140 . Fig. 9 The packaging system shown in Figure 5a The package structure 10 shown is integrated into a second package substrate 140; or, Fig. 9 The packaging system shown in FIG. 1 may include a package structure 10 (eg, Fig.11a FIG. 4 shows that the package structure 10 is soldered to the second package substrate 140 through the conductive balls 130.

[0101] To improve the integration of the second packaging substrate 140, the size and shape of the positioning mark 141 can be arranged according to the size of the semiconductor device 120. The size of the positioning mark 141 can be the same as the shape of the semiconductor device 120, and the positioning mark 141 can include a rectangle. The alignment method of the first corner 1101 of the first packaging substrate 110 and the third corner 1411 of the second packaging substrate 140 can be similar to Figures 6a to 6e In the alignment method of the first corner 1101 and the second corner 1201 of the semiconductor device 120, the orthographic projection of the first corner on the plane where the first surface is located coincides with the orthographic projection of the third corner 1411 on the plane; or, the orthographic projection of the first corner 1101 on the plane where the first surface is located falls within the orthographic projection of the third corner 1411 on the plane; or, the orthographic projection of the third corner 1411 on the plane where the first surface is located falls within the orthographic projection of the first corner 1101 on the plane.

[0102] In some embodiments, reference Figure 7As shown, the first package substrate 110 includes two first corners 1101, and the second package substrate 140 includes two third corners 1411; each first corner 1101 is aligned with each third corner 1411 along the first direction. In other embodiments, there is one first corner 1101 aligned with one third corner 1411; or, there are three first corners 1101 aligned with three third corners 1411 in one-to-one correspondence; or, there are four first corners 1101 aligned with four third corners 1411 in one-to-one correspondence.

[0103] In some embodiments, the two first corners 1101 are arranged diagonally.

[0104] In some embodiments, the first surface is a closed polygon formed by a plurality of straight line segments, and the first corner 1101 comprises a right angle.

[0105] In some embodiments, the positioning mark 141 is a closed polygon formed by a plurality of straight line segments, and the third corner 1411 comprises a right angle. The number of corners of the first package substrate 110 including the first corner 1101 may be greater than the number of corners of the positioning mark 141 including the third corner 1411 .

[0106] In some embodiments, the orthographic projection of the positioning mark 141 on the plane where the first surface is located falls within the first surface.

[0107] In some embodiments, the orthographic projection of the semiconductor device 120 on the plane where the first surface is located coincides with the orthographic projection of the positioning mark 141 on the plane; or, the orthographic projection of the semiconductor device 120 on the plane where the first surface is located falls within the orthographic projection of the positioning mark 141 on the plane. The size of the positioning mark 141 may be the same as the shape of the semiconductor device 120 and the size in the xoy plane; or, the shape of the positioning mark 141 is the same as the shape of the semiconductor device 120, but the size of the positioning mark 141 in the xoy plane is larger than the size of the semiconductor device 120 in the xoy plane.

[0108] According to some aspects of the embodiments of the present disclosure, Fig.10A schematic flow chart of a method for manufacturing a packaging system is provided, the manufacturing method comprising: providing a packaging structure, comprising a first packaging substrate, having a first surface and a second surface arranged opposite to each other, and a semiconductor device located on the first surface; the semiconductor device is coupled to the first packaging substrate, the first packaging substrate comprising a first corner; providing a second packaging substrate; the packaging substrate comprising a positioning mark, the positioning mark comprising a third corner; aligning the first corner with the third corner along a first direction perpendicular to the second packaging substrate, and coupling the second surface of the first packaging substrate and the second packaging substrate.

[0109] Specifically, refer to Fig.11a As shown, a package structure 10 is provided, and the package structure 10 may not include the conductive ball 130. Fig.11b As shown, a second packaging substrate 140 is provided, and the second packaging substrate 140 can be provided with a third conductive contact 1401. Fig.11a The semiconductor device 120 may further include a plurality of semiconductor chips that are stacked.

[0110] In some embodiments, reference Fig.11c As shown, aligning the first corner 1101 with the third corner 1411 to couple the second surface of the first package substrate 110 and the second package substrate 140 includes: forming a conductive ball 130 on the second surface of the first package substrate 110, aligning the first corner 1101 with the third corner 1411, fixing the first package substrate 110 to the second package substrate 140 through the conductive ball 130 and achieving coupling. The conductive ball 130 is used as a solder ball to solder the first package substrate 110 to the third conductive contact 1401 on the second package substrate 140, and achieve coupling to form Fig. 9 The package system 11 in.

[0111] In some other embodiments, the package structure 10 may include Figure 5a to Figure 5c as well as Figure 8 The package structure 10 including the conductive balls 130 is directly soldered or plug-in non-solderingly contacted with the second package substrate 140 .

[0112] In some embodiments, the orthographic projection of the first corner 1101 on the plane where the first surface is located coincides with the orthographic projection of the third corner 1411 on the plane; or, the orthographic projection of the first corner 1101 on the plane where the first surface is located falls within the orthographic projection of the third corner 1411 on the plane.

[0113] In some embodiments, the first packaging substrate 110 includes two first corners 1101 , and the second packaging substrate 140 includes two third corners 1411 ; each first corner 1101 is aligned with each third corner 1411 along the first direction.

[0114] In some embodiments, the first corner 1101 is arranged diagonally.

[0115] In some embodiments, the orthographic projection of the positioning mark 141 on the plane where the first surface is located falls within the first surface.

[0116] According to some aspects of the embodiments of the present disclosure, a memory system is provided, including a package structure 10 , wherein a semiconductor device 120 in the package structure 10 includes a memory device and / or a memory controller, wherein the memory controller is coupled to the memory device and configured to control the memory device.

[0117] In some embodiments, the memory device and the memory device can be respectively packaged into two package structures 10, and the two package structures 10 are integrated into a printed circuit board to form a package system 11. The printed circuit board also includes other electronic components. The package system 11 serves as a memory system. The memory system of this embodiment can include a memory card and an SSD product.

[0118] In some other embodiments, the memory device and the memory controller may be packaged into a package structure 10, and the package structure 10 serves as a memory system. The memory system of this embodiment may include a universal flash storage (UFS) package or an eMMC package product.

[0119] The memory device in the embodiments of the present disclosure includes but is not limited to a three-dimensional NAND memory. For ease of understanding, a three-dimensional NAND memory is taken as an example for description.

[0120] Fig.12 A block diagram of an exemplary system 100 having a memory device according to some aspects of the present disclosure is shown. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. Fig.12As shown in , system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 108 may be configured to send data to the memory device 104 or receive data from the memory device 104.

[0121] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host 108, and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment SSD or embedded multimedia card (eMMC), which is used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc. and enterprise storage arrays.

[0122] The memory controller 106 may be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) regarding data read from or written to the memory device 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 may communicate with an external device (e.g., a host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI Express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer mini interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, Firewire protocol, etc.

[0123] The memory controller 106 and the one or more memory devices 104 may be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the memory system 102 may be implemented and packaged into different types of terminal electronic products. Fig.13a In one example shown in , the memory controller 106 and the single memory device 104 can be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a processor that connects the memory card 202 to a host (e.g., Fig.12 The memory card connector 204 is coupled to the host 108 in the embodiment. Fig.13b In another example shown in , the memory controller 106 and the plurality of memory devices 104 may be integrated into the SSD 206. The SSD 206 may also include a processor that interfaces the SSD 206 with a host (e.g., Fig.12 In some implementations, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0124] Fig.14 1 is a schematic circuit diagram of an exemplary memory device 300 including peripheral circuits according to some aspects of the present disclosure. The memory device 300 may be Fig.12 300 is an example of a memory device 104 in FIG. The memory device 300 may include a memory cell array 301 and a peripheral circuit 302 coupled to the memory cell array 301. The memory cell array 301 is taken as a three-dimensional NAND-type memory cell array for illustration, wherein the memory cells 306 are provided in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0125] In some embodiments, each memory cell 306 is a single-level cell (SLC) having two possible memory states and can therefore store one bit of data. For example, a first memory state "0" can correspond to a first voltage range, and a second memory state "1" can correspond to a second voltage range. In some embodiments, each memory cell 306 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC can store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed by writing one of three possible nominal storage values ​​to the cell, and a fourth nominal storage value in addition to the three nominal storage values ​​can be used to represent an erased state.

[0126] like Fig.14 As shown in , each NAND memory string 308 may include a lower select gate (BSG) 310 at its source terminal and an upper select gate (TSG) 312 at its drain terminal. BSG 310 and TSG 312 may be configured to activate a selected NAND memory string 308 during read and program operations. In some embodiments, the sources of the NAND memory strings 308 in the same memory block 304 are coupled by the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each NAND memory string 308 is coupled to a corresponding bit line (BL) 316, and data can be read from or written to the bit line 316 via an output bus (not shown). In some embodiments, each NAND memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of a transistor having TSG 312) or a deselect voltage (e.g., 0 V) ​​to a corresponding TSG 312 via one or more TSG lines 313 and / or by applying a select voltage (e.g., higher than the threshold voltage of a transistor having BSG 310) or a deselect voltage (e.g., 0 V) ​​to a corresponding BSG 310 via one or more BSG lines 315.

[0127] like Fig.14As shown in , the NAND memory string 308 can be organized into a plurality of memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic data unit for an erase operation, that is, all memory cells 306 on the same memory block 304 are erased at the same time. In order to erase the memory cells 306 in the selected memory block 304a, the source lines 314 coupled to the selected memory block 304a and the unselected memory blocks 304b in the same plane as the selected memory block 304a can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, the erase operation can be performed at the half-memory block level, at the quarter-memory block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. The memory cells 306 of adjacent NAND memory strings 308 can be coupled by word lines 318, which select which row of memory cells 306 is affected by read and program operations.

[0128] Fig.15 1 shows a cross-sectional schematic diagram of an exemplary memory cell array 301 including NAND memory strings 308 according to some aspects of the present disclosure. Fig.15 As shown, the NAND memory string 308 may include a stacked structure 410, which includes a plurality of gate layers 411 and a plurality of insulating layers 412 that are alternately stacked in sequence, and a memory string 308 that vertically penetrates the gate layers 411 and the insulating layers 412. The gate layers 411 and the insulating layers 412 may be alternately stacked, and two adjacent gate layers 411 are separated by a layer of insulating layer 412. The number of pairs of gate layers 411 and insulating layers 412 in the stacked structure 410 may determine the number of memory cells included in the memory cell array 301.

[0129] The constituent material of the gate layer 411 may include a conductive material. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stacked structure 410 may extend laterally as an upper selection gate line, the gate layer 411 at the bottom of the stacked structure 410 may extend laterally as a lower selection gate line, and the gate layer 411 extending laterally between the upper selection gate line and the lower selection gate line may serve as a word line layer.

[0130] In some embodiments, the stacked structure 410 may be disposed on a substrate 401. The substrate 401 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0131] In some embodiments, the NAND memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes a channel hole filled with (one or more) semiconductor materials (e.g., as a semiconductor channel) and (one or more) dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a column shape). According to some embodiments, the semiconductor channel, the tunneling layer, the storage layer, and the barrier layer are arranged radially from the center of the column toward the outer surface of the column in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0132] Return to reference Fig.14 , the peripheral circuit 302 may be coupled to the memory cell array 301 through the bit line 316, the word line 318, the source line 314, the BSG line 315, and the TSG line 313. The peripheral circuit 302 may include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory cell array 301 by applying a voltage signal and / or a current signal to each target memory cell 306 and sensing a voltage signal and / or a current signal from each target memory cell 306 via the bit line 316, the word line 318, the source line 314, the BSG line 315, and the TSG line 313. The peripheral circuit 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Fig.16 Some exemplary peripheral circuits are shown, and the peripheral circuit 302 includes a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, it may also include Fig.16 Additional peripheral circuits not shown.

[0133] The page buffer / sense amplifier 504 may be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to a control signal from the control logic 512. In one example, the page buffer / sense amplifier 504 may store programming data (write data) to be programmed into the memory cell array 301. In another example, the page buffer / sense amplifier 504 may perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 may also sense a low-power signal from the bit line 316 representing a data bit stored in the memory cell 306, and amplify a small voltage swing to a recognizable logic level in a read operation. The column decoder / bit line driver 506 may be configured to be controlled by the control logic 512, and select one or more NAND memory strings 308 by applying a bit line voltage generated from the voltage generator 510.

[0134] The row decoder / word line driver 508 may be configured to be controlled by the control logic 512 and select / deselect the memory block 304 of the memory cell array 301 and select / deselect the word line 318 of the memory block 304. The row decoder / word line driver 508 may also be configured to drive the word line 318 using the word line voltage generated from the voltage generator 510. In some embodiments, the row decoder / word line driver 508 may also select / deselect and drive the BSG line 315 and the TSG line 313. As described in detail below, the row decoder / word line driver 508 is configured to perform a programming operation on the memory cell 306 coupled to the (one or more) selected word lines 318. The voltage generator 510 may be configured to be controlled by the control logic 512 and generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a channel boosting voltage, a verification voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory cell array 301.

[0135] In some specific embodiments, the programming operation may include multiple stages. For example, the programming operation may include a channel precharge stage, a channel boosting stage, a programming pulse stage, and a recovery stage. In the channel precharge stage, the voltage generator may generate the voltage required for the next stage, such as the voltage applied to each gate, the channel boosting voltage, etc.; in the channel boosting stage, the channel boosting voltage may be applied to the selected word line; in the programming pulse stage, the target voltage for each programming may be applied to the selected word line. In the recovery stage, the voltage of both the unselected word line and the selected word line may be reduced to the corresponding voltage, such as Vcc, Vdd. In the recovery stage, the voltage may be reduced to the corresponding voltage by one or more step-by-step steps, such as first reducing the voltage to an intermediate voltage, and maintaining the intermediate voltage for a period of time, and then reducing the voltage to the corresponding voltage.

[0136] The control logic 512 may be coupled to each peripheral circuit described above and configured to control the operation of each peripheral circuit. The register 514 may be coupled to the control logic 512 and include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. The interface 516 may be coupled to the control logic 512 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic 512, as well as buffer status information received from the control logic 512 and relay them to the host. The interface 516 may also be coupled to the column decoder / bit line driver 506 via a data bus 518 and act as a data I / O interface and a data buffer to buffer data and relay them to the memory cell array 301 or relay or buffer data from the memory cell array 301.

[0137] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A package structure, It is characterized in that include: A first packaging substrate having a first surface and a second surface arranged opposite to each other; The first packaging substrate includes a first corner; A semiconductor device, located on the first surface of the first packaging substrate and coupled to the first packaging substrate; the semiconductor device includes a second corner; wherein the first corner is aligned with the second corner along a first direction perpendicular to the first packaging substrate; An area of ​​the first packaging substrate is larger than an area of ​​the semiconductor device.

2. The package structure according to claim 1, It is characterized in that The first corner is aligned with a third corner of a positioning mark on the printed circuit board.

3. The package structure according to claim 1, It is characterized in that The orthographic projection of the first corner on the plane where the first surface is located coincides with the orthographic projection of the second corner on the plane; or, the orthographic projection of the first corner on the plane where the first surface is located falls within the orthographic projection of the second corner on the plane.

4. The package structure according to claim 1, It is characterized in that An orthographic projection of the semiconductor device on the plane where the first surface is located falls within the first surface.

5. The package structure according to claim 1, It is characterized in that The first packaging substrate includes two first corners, and the semiconductor device includes two second corners; each of the first corners is aligned with the second corner in the first direction.

6. The package structure according to claim 5, It is characterized in that The two first corners are arranged diagonally.

7. The package structure according to claim 1, It is characterized in that The first surface is a closed polygon surrounded by a plurality of straight line segments, and the first corner comprises a right angle.

8. The package structure according to claim 6, It is characterized in that The orthographic projection of the semiconductor device on the plane where the first surface is located is a closed polygon surrounded by a plurality of straight line segments, and the second corner includes a right angle.

9. The package structure according to claim 1, It is characterized in that The semiconductor device further includes a first conductive channel, which passes through the semiconductor device and is coupled to the first packaging substrate.

10. The package structure according to claim 1, It is characterized in that The package structure further includes: The conductive ball is located on the second surface and coupled to the first packaging substrate.

11. A package system, It is characterized in that include: A first packaging substrate having a first surface and a second surface arranged opposite to each other; the first packaging substrate comprises a first corner; a semiconductor device, located on the first surface of the first packaging substrate and coupled to the first packaging substrate; A second packaging substrate is located on one side of the second surface and coupled to the first packaging substrate; a positioning mark is provided on the second packaging substrate, and the positioning mark includes a third corner; The first corner is aligned with the third corner along a first direction perpendicular to the second packaging substrate; and an area of ​​the first packaging substrate is larger than an area of ​​the positioning mark.

12. The package system according to claim 11, It is characterized in that The second packaging substrate includes a printed circuit board.

13. The package system according to claim 11, It is characterized in that The orthographic projection of the first corner on the plane where the first surface is located coincides with the orthographic projection of the third corner on the plane; or, the orthographic projection of the first corner on the plane where the first surface is located falls within the orthographic projection of the third corner on the plane.

14. The package system according to claim 11, It is characterized in that The first packaging substrate includes two first corners, and the second packaging substrate includes two third corners; each of the first corners is aligned with each of the third corners along the first direction.

15. The package system according to claim 14, It is characterized in that The two first corners are arranged diagonally.

16. The package system according to claim 11, It is characterized in that The first surface is a closed polygon surrounded by a plurality of straight line segments, and the first corner comprises a right angle.

17. The package system according to claim 16, It is characterized in that The positioning mark is a closed polygon surrounded by a plurality of straight line segments, and the third corner comprises a right angle.

18. The package system according to claim 11, It is characterized in that The orthographic projection of the positioning mark on the plane where the first surface is located falls within the first surface.

19. The package system according to claim 11, It is characterized in that The package system further comprises: A conductive ball is located between the first packaging substrate and the second packaging substrate; one side of the conductive ball is coupled to the second surface of the first packaging substrate, and the other side of the conductive ball is coupled to the second packaging substrate.

20. The package system according to claim 11, It is characterized in that The orthographic projection of the semiconductor device on the plane where the first surface is located coincides with the orthographic projection of the positioning mark on the plane; Alternatively, the orthographic projection of the semiconductor device on the plane where the first surface is located falls within the orthographic projection of the positioning mark on the plane.

21. A memory system, It is characterized in that The package structure comprises the package structure according to any one of claims 1 to 10, wherein the semiconductor device in the package structure comprises a memory device and / or a memory controller, wherein the memory controller is coupled to the memory device and configured to control the memory device.

22. A method for manufacturing a package system, It is characterized in that include: A package structure is provided, comprising a first package substrate having a first surface and a second surface arranged opposite to each other, and a semiconductor device located on the first surface; The semiconductor device is coupled to the first packaging substrate, and the first packaging substrate includes a first corner; providing a second packaging substrate; The packaging substrate includes a positioning mark, and the positioning mark includes a third corner; The first corner is aligned with the third corner along a first direction perpendicular to the second packaging substrate, and the second surface of the first packaging substrate and the second packaging substrate are coupled.

23. The method according to claim 22, It is characterized in that The step of aligning the first corner with the third corner to couple the second surface of the first packaging substrate and the second packaging substrate comprises: Conductive balls are formed on the second surface of the first packaging substrate, aligned with the first corner and the third corner, and the first packaging substrate is fixed to the second packaging substrate through the conductive balls to achieve coupling.

24. The method according to claim 22, It is characterized in that The orthographic projection of the first corner on the plane where the first surface is located coincides with the orthographic projection of the third corner on the plane; or, the orthographic projection of the first corner on the plane where the first surface is located falls within the orthographic projection of the third corner on the plane.

25. The method according to claim 22, It is characterized in that The first packaging substrate includes two first corners, and the second packaging substrate includes two third corners; each of the first corners is aligned with each of the third corners along the first direction.

26. The method according to claim 25, It is characterized in that The two first corners are arranged diagonally.

27. The method according to claim 22, It is characterized in that The orthographic projection of the positioning mark on the plane where the first surface is located falls within the first surface.

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