Electronic structure and manufacturing method thereof, and electronic package and manufacturing method thereof

Abstract

An electronic structure and a method of fabricating the same, and an electronic package and a method of fabricating the same, the electronic structure including: an electronic body having a first surface and a second surface opposite to each other; a plurality of conductive bumps disposed on the first surface of the electronic body; a protective layer disposed on the first surface of the electronic body and covering the plurality of conductive bumps; and a plurality of grooves formed in the protective layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, in particular to an electronic structure and an electronic package and a manufacturing method thereof. Background Art

[0002] In order to ensure the continued miniaturization and multi-functionality of electronic products and communication equipment, semiconductor packaging needs to develop towards miniaturization to facilitate multi-pin connection. To this end, the industry has developed many advanced process packaging technologies. For example, in advanced process packaging, commonly used packaging types include 2.5D packaging process, fan-out wiring combined with embedded bridge component process (abbreviated as FO-EB), etc.

[0003] Figure 1 FIG. 1 is a cross-sectional schematic diagram of a method for manufacturing a conventional semiconductor package 1. Figure 1 As shown, a wiring structure 14 on a carrier board 1b is provided with an electronic structure 1a and a plurality of conductive pillars 13, wherein the electronic structure 1a comprises an electronic body 11, a plurality of conductive bumps 111, a circuit portion 12, a plurality of external bumps 122 and a protective layer 19. A plurality of conductive through-holes 110 are formed in the electronic body 11 to connect the first surface 11a and the second surface 11b thereof. A plurality of conductive bumps 111 are formed on the first surface 11a of the electronic body 11 and electrically connect the plurality of conductive through-holes 110. The circuit portion 12 is provided on the second surface 11b of the electronic body 11 and comprises at least one insulating layer 120 and a conductive trace 121 combined with the insulating layer 120. A plurality of external bumps 122 are formed on the circuit portion 12 and electrically connect the plurality of conductive through-holes 110 via the conductive trace 121. The protective layer 19 is formed on the first surface 11a of the electronic body 11 and covers the plurality of conductive bumps 111.

[0004] The electronic structure 1a is disposed on the wiring structure 14 via a plurality of external bumps 122. However, when the electronic structure 1a is disposed on the wiring structure 14 during the die bonding process, the electronic body 11 is very thin, and a protective layer 19 is formed on the first surface 11a of the electronic body 11. The difference in the coefficient of thermal expansion (CTE) between the protective layer 19 and the electronic body 11 is too large, which may easily cause the electronic structure 1a to warp. This warping may easily cause the plurality of external bumps 122 to separate from the wiring structure 14, resulting in non-wetting, which may lead to quality reliability problems in subsequent products and a decrease in product yield.

[0005] Therefore, how to overcome the above-mentioned problems of the prior art has become a topic that needs to be solved urgently. Summary of the invention

[0006] In view of the various deficiencies of the above-mentioned prior art, the present invention provides an electronic structure, including: an electronic body, having a first surface and a second surface relative to each other; a plurality of conductive bumps, arranged on the first surface of the electronic body; a protective layer, arranged on the first surface of the electronic body and covering the plurality of conductive bumps, and defining the area outside the plurality of conductive bumps as an open area; and a plurality of grooves, formed in the protective layer and located in the open area.

[0007] As in the aforementioned electronic structure, the plurality of grooves do not penetrate the protection layer.

[0008] As in the aforementioned electronic structure, parts of the plurality of grooves are exposed on the side surface of the protection layer.

[0009] As in the aforementioned electronic structure, the extension direction of the plurality of grooves is a single direction.

[0010] As in the aforementioned electronic structure, the extension directions of the plurality of grooves are respectively in the horizontal direction and the vertical direction which are perpendicular to each other, so that the plurality of grooves are in a grid shape.

[0011] As in the aforementioned electronic structure, the extension directions of the plurality of grooves are irregularly arranged.

[0012] The present invention provides an electronic package, comprising: a circuit structure having a first side and a second side opposite to each other; an electronic structure as described above, with the first surface of the electronic body being arranged on the first side of the circuit structure; and a plurality of electronic components being arranged on the second side of the circuit structure to electrically connect the circuit structure, wherein the electronic structure is electrically connected to the circuit structure through the plurality of conductive bumps to electrically connect at least two of the plurality of electronic components.

[0013] As in the aforementioned electronic package, it also includes a coating layer coating the electronic structure.

[0014] The aforementioned electronic package further includes a packaging layer covering the plurality of electronic components.

[0015] As mentioned above, the electronic package also includes a supporting structure for supporting the electronic structure, so that the electronic structure is placed on the supporting structure through a plurality of external bumps with the second surface of the electronic body, so that the electronic structure is electrically connected to the supporting structure.

[0016] As in the aforementioned electronic package, it also includes a plurality of conductive pillars disposed on the supporting structure and surrounding the electronic structure to electrically connect the supporting structure.

[0017] The present invention also provides a method for manufacturing an electronic structure, including: providing an electronic body having a first surface and a second surface relative to each other; forming a plurality of conductive bumps on the first surface of the electronic body; forming a protective layer on the first surface of the electronic body to cover the plurality of conductive bumps, wherein the protective layer defines an area outside the plurality of conductive bumps as an open area; and forming a plurality of grooves in the protective layer, wherein the plurality of grooves are located in the open area.

[0018] As in the aforementioned method for manufacturing the electronic structure, the plurality of grooves do not penetrate the protection layer.

[0019] As in the aforementioned method for manufacturing the electronic structure, the portion of the plurality of grooves is exposed on the side surface of the protective layer.

[0020] As in the aforementioned method for manufacturing the electronic structure, the extension direction of the plurality of grooves is a single direction.

[0021] As in the aforementioned method for manufacturing the electronic structure, the extension directions of the plurality of grooves are respectively in the horizontal direction and the vertical direction which are perpendicular to each other, so that the plurality of grooves are in a grid shape.

[0022] As in the aforementioned method for manufacturing the electronic structure, the extension directions of the plurality of grooves are irregularly arranged.

[0023] The present invention further provides a method for manufacturing an electronic package, comprising: providing a circuit structure and at least one electronic structure as described above, wherein the circuit structure has a first side and a second side relative to each other; arranging the electronic structure corresponding to the first surface of the electronic body on the first side of the circuit structure; and arranging a plurality of electronic components on the second side of the circuit structure so that the plurality of electronic components are electrically connected to the circuit structure, wherein the electronic structure is electrically connected to the circuit structure through the plurality of conductive bumps so as to electrically connect at least two of the plurality of electronic components.

[0024] The method for manufacturing the electronic package as mentioned above further includes forming a coating layer that covers the electronic structure.

[0025] The method for manufacturing the electronic package as mentioned above further includes forming a packaging layer covering the plurality of electronic components.

[0026] The method for manufacturing the electronic package as mentioned above further includes placing the electronic structure on a supporting structure through a plurality of external bumps with the second surface of the electronic body, so that the electronic structure is electrically connected to the supporting structure.

[0027] The method for manufacturing the electronic package as mentioned above further includes forming a plurality of conductive pillars on the supporting structure, so that the plurality of conductive pillars surround the electronic structure and are electrically connected to the supporting structure.

[0028] In summary, through the electronic structure and electronic package and the manufacturing method thereof of the present invention, a plurality of grooves are mainly formed in the protective layer of the electronic structure to effectively release stress and prevent the electronic structure from warping, and to prevent the external bump from soldering non-wetting in the subsequent manufacturing process. In addition, the electronic structure and electronic package and the manufacturing method thereof of the present invention can be completed with existing manufacturing processes and equipment without a large amount of additional cost expenditure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a cross-sectional schematic diagram of a conventional semiconductor package.

[0030] FIG. 2A to FIG. 2B It is a cross-sectional schematic diagram of the method for preparing the electronic structure of the present invention.

[0031] Figure 2B-1 FIG. 4 is a cross-sectional schematic diagram of another embodiment of the electronic structure of the present invention.

[0032] Figure 2C-1 to Figure 2C-4 Schematic top views of different embodiments of the electronic structure of the present invention.

[0033] Figure 2C-1 'for Figure 2C-1 A top plan view of another embodiment of the present invention is shown in FIG.

[0034] FIG. 3A to FIG. 3C It is a cross-sectional schematic diagram of the method for manufacturing the electronic package of the present invention.

[0035] Description of Reference Numerals

[0036] 1 Semiconductor Package

[0037] 1a,2a electronic structure

[0038] 1b Loading plate

[0039] 11,21 Electronic Host

[0040] 11a, 21a First surface

[0041] 11b, 21b Second surface

[0042] 110,210 Conductive perforation

[0043] 111,211,261 conductive bumps

[0044] 12,22 Line Department

[0045] 120,220 Insulation layer

[0046] 121,221 Conductive traces

[0047] 122,222 External bump

[0048] 13,23 Conductive column

[0049] 14 Wiring Structure

[0050] 19,29 Protective layer

[0051] 2 Electronic packaging

[0052] 20 Line structure

[0053] 20a First side

[0054] 20b Second side

[0055] 200 Insulation

[0056] 201 Line redistribution layer

[0057] 202 Electrical contact pad

[0058] 24 Load-bearing structure

[0059] 240 Dielectric layer

[0060] 241 Line Layer

[0061] 25 Coating

[0062] 26 Electronic components

[0063] 260,271 Solder materials

[0064] 262 Primer

[0065] 27 Conductive element

[0066] 270 metal bumps

[0067] 272 Under Bump Metal

[0068] 28 Encapsulation layer

[0069] 291 Grooves

[0070] 9 Bearing

[0071] 90 Release layer

[0072] 91 Metal Layer

[0073] A. Open area

[0074] X Long side direction. DETAILED DESCRIPTION

[0075] The following describes the implementation of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0076] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings attached to this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of the present invention, so they have no substantial technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size, without affecting the effects and purposes that can be achieved by the present invention, should still fall within the scope of the technical contents disclosed by the present invention. At the same time, the terms such as "on", "first", "second", "one", etc. cited in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of the present invention without substantially changing the technical contents.

[0077] FIG. 2A to FIG. 2B It is a schematic cross-sectional view of a method for manufacturing the electronic structure 2a of the present invention.

[0078] like Figure 2A As shown, a semiconductor substrate is provided as an electronic body 21. The electronic body 21 has a first surface 21a and a second surface 21b opposite to each other. A plurality of conductive bumps 211 are formed on the first surface 21a of the electronic body 21, and a plurality of external bumps 222 are formed on the second surface 21b of the electronic body 21. Next, a protective layer 29 is formed on the first surface 21a of the electronic body 21, so that the protective layer 29 covers the plurality of conductive bumps 211.

[0079] In the present embodiment, the electronic body 21 is a semiconductor chip, in which a plurality of conductive through-holes 210 are formed to connect the first surface 21a and the second surface 21b, so that the conductive through-holes 210 are electrically connected to a plurality of conductive bumps 211. For example, the conductive through-holes 210 are conductive through-silicon vias (TSVs), and a circuit portion 22 may be formed on the second surface 21b of the electronic body 21 as required. The circuit portion 22 includes at least one insulating layer 220 and a conductive trace 221 combined with the insulating layer 220, so that the conductive trace 221 is electrically connected to the conductive through-holes 210 and the external bumps 222. It should be understood that there are many embodiments of semiconductor devices having conductive through-holes 210, and there is no particular limitation.

[0080] Furthermore, the conductive bump 211 is, for example, a metal pillar of a copper pillar, so that the protection layer 29 covers the side and top surfaces of the conductive bump 211. It should be understood that a portion of the protection layer 29 can be removed through a flattening process as required to expose the top surface of the conductive bump 211 to the protection layer 29, that is, the top surface of the conductive bump 211 is flush with the top surface of the protection layer 29.

[0081] In addition, the external bumps 222 are, for example, copper bumps or solder (ball) materials, and can be coated by a coating layer in a subsequent process. It should be understood that a non-conductive film (NCF) can be used as a bonding layer to coat the external bumps 222 as required, and a primer can also be used to coat the external bumps 222. There are many embodiments of the external bumps 222, and they are not limited to the above.

[0082] In addition, the protection layer 29 may be, for example, polybenzoxazole (PBO), polyimide (PI), prepreg (PP), epoxy resin or other dielectric materials.

[0083] like Figure 2B As shown, the area outside the plurality of conductive bumps 211 in the protection layer 29 is defined as an open area A, and a plurality of grooves 291 are formed in the open area A of the protection layer 29 by laser processing to obtain the electronic structure 2a of the present invention.

[0084] In this embodiment, the multiple grooves 291 do not penetrate the protective layer 29, that is, the multiple grooves 291 do not expose the first surface 21a of the electronic body 21, the depth of the grooves 291 is less than the thickness of the protective layer 29, and the multiple grooves 291 are not exposed on the side of the protective layer 29, that is, the grooves 291 do not extend to the edge of the electronic body 21.

[0085] In one embodiment, if Figure 2B-1 As shown, the plurality of grooves 291 are partially exposed on the side surface of the protection layer 29 , that is, the grooves 291 extend to the edge of the electronic body 21 .

[0086] In one embodiment, if Figure 2C-1 As shown in FIG. 1 , when the electronic body 21 is long, the direction of the warping is the long side direction X of the electronic body 21. At this time, the extension direction of the plurality of grooves 291 is a single direction and is perpendicular to the long side direction X of the electronic body 21. Each groove 291 extends to the edge of the electronic body 21. It should be understood that each groove 291 may not extend to the edge of the electronic body 21. Figure 2C-1 'shown.

[0087] In one embodiment, if Figure 2C-2As shown, when the electronic body 21 is a square, the direction of warping may be irregular. At this time, the extension directions of the multiple grooves 291 are respectively perpendicular to each other in the horizontal and vertical directions, that is, the multiple grooves 291 are respectively parallel and perpendicular to the long side direction X, so that the multiple grooves 291 are in a grid shape.

[0088] In one embodiment, the direction of the grooves 291 can be designed according to different stress release requirements caused by the shape of the electronic body 21, so that the extension directions of the grooves 291 are irregularly arranged, such as Figure 2C-3 The grooves 291 shown are perpendicular to the long side direction X but are staggered with each other, or as shown in FIG. Figure 2C-4 The groove 291 shown has a plurality of bending points, etc. It should be understood that the present invention does not impose any limitation on the number, extension direction, arrangement of the grooves 291, or whether they are exposed on the side of the protective layer 29, as long as the grooves 291 are located in the open area A and can effectively release stress.

[0089] FIG. 3A to FIG. 3C FIG. 2 is a cross-sectional schematic diagram of a method for manufacturing an electronic package 2 of the present invention. Figure 2B The electronic structure shown is 2a.

[0090] like Figure 3A As shown, a carrier 9 is provided, and at least one electronic structure 2 a and a plurality of conductive pillars 23 are disposed on the carrier 9 .

[0091] The carrier 9 is, for example, a plate of a semiconductor material (such as silicon or glass), on which a release layer 90 and a metal layer 91 such as titanium / copper are sequentially formed by, for example, coating, so that a carrier structure 24 is formed on the metal layer 91, wherein the electronic structure 2a is connected to the carrier structure 24 with the second surface 21b of its electronic body 21 facing the carrier 9.

[0092] In the present embodiment, the supporting structure 24 includes at least one dielectric layer 240 and a circuit layer 241 combined with the dielectric layer 240. For example, the material forming the dielectric layer 240 is polybenzoxazole (PBO), polyimide (PI), prepreg (PP) or other dielectric materials, and the circuit layer 241 and the dielectric layer 240 can be formed by a redistribution layer (RDL) process.

[0093] The electronic structure 2 a is connected to the circuit layer 241 of the supporting structure 24 through a plurality of external bumps 222 via the second surface 21 b of the electronic body 21 .

[0094] In this embodiment, since a plurality of grooves 291 are formed in the protective layer 29, warping of the electronic structure 2a can be avoided, and a plurality of external bumps 222 can be effectively placed on the circuit layer 241. Subsequently, by reflow soldering these external bumps 222, the electronic structure 2a can be fixed to the carrier structure 24, avoiding the problem of non-wetting of the solder.

[0095] The conductive posts 23 are disposed on the carrier structure 24 and electrically connected to the circuit layer 241.

[0096] In this embodiment, the material for forming the conductive posts 23 can be, for example, a metal material such as copper or a solder material. For example, by means of exposure and development, these conductive posts 23 are electroplated on the circuit layer 241.

[0097] As Figure 3B shown, a coating layer 25 is formed on the carrier structure 24 to cover the electronic structure 2a and these conductive posts 23. It should be understood that by means of a planarization process, the top surface of the protective layer 29, the end surface of the conductive bumps 211, the grooves 291, and the end surface of the conductive posts 23 are exposed and flush with the surface of the coating layer 25. For example, this planarization process is carried out by grinding to remove part of the material of the protective layer 29, part of the material of the conductive posts 23, part of the material of the conductive bumps 211, and part of the material of the coating layer 25.

[0098] In this embodiment, the coating layer 25 is an insulating material, such as polyimide (PI for short), dry film, an encapsulation colloid such as epoxy resin, or a molding compound. For example, the process for forming the coating layer 25 can be selected from methods such as liquid compound, lamination, or compression molding to be formed on the carrier structure 24.

[0099] Next, a circuit structure 20 is formed on the coating layer 25 to electrically connect a plurality of conductive posts 23 and a plurality of conductive bumps 211. Among them, the circuit structure 20 has opposite first side 20a and second side 20b, so that the electronic structure 2a is bonded to the first side 20a of the circuit structure 20 with the first surface 21a side of its electronic body 21.

[0100] In this embodiment, the circuit structure 20 includes at least one insulating layer 200 and a redistribution layer (RDL) 201 disposed on the insulating layer 200, so that the redistribution layer 201 electrically connects multiple conductive pillars 23 and multiple conductive bumps 211, wherein the outermost insulating layer 200 can be used as a solder mask, and the outermost redistribution layer 201 is exposed to the outside of the solder mask to serve as an electrical contact pad 202, such as a micro pad (commonly known as μ-pad).

[0101] Furthermore, the material forming the circuit redistribution layer 201 is copper, and the material forming the insulating layer 200 can be, for example, dielectric materials such as polybenzoxazole (PBO), polyimide (PI), prepreg (PP), or solder mask materials such as green paint and ink.

[0102] Afterwards, a plurality of electronic components 26 are disposed on the second side 20 b of the circuit structure 20 , and then a packaging layer 28 is used to cover the electronic components 26 .

[0103] In this embodiment, the electronic component 26 is an active component, a passive component or a combination of the two, and the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor and an inductor. In one embodiment, the electronic component 26 is, for example, a semiconductor chip such as a graphics processing unit (GPU), a high bandwidth memory (HBM), and the electronic structure 2a is used as a bridge element (Bridge Die), which is electrically connected to the circuit structure 20 through the conductive bumps 211, thereby electrically bridging at least two electronic components 26.

[0104] Furthermore, the electronic component 26 has a plurality of conductive bumps 261 such as copper pillars to electrically connect the electrical contact pads 202 through a plurality of solder materials 260 such as solder bumps. In this embodiment, an under bump metallurgy (UBM) (not shown) may be formed on the electrical contact pads 202 or the electronic component 26 to facilitate the bonding of the solder material 260 or the conductive bumps 261.

[0105] In addition, the packaging layer 28 is an insulating material, such as polyimide (PI), dry film, packaging colloid such as epoxy, or molding compound, which can be formed on the circuit structure 20 by lamination or molding. It should be understood that the material forming the packaging layer 28 can be the same as or different from the material of the covering layer 25.

[0106] In addition, the primer 262 may be formed between the electronic components 26 and the circuit structure 20 to cover the conductive bumps 261 and the solder material 260, and then the packaging layer 28 may be formed to cover the primer 262 and the electronic components 26. Alternatively, in other embodiments, the packaging layer 28 may cover the electronic components 26 and the conductive bumps 261 at the same time without forming the primer 262.

[0107] like Figure 3C As shown, the carrier 9 and the release layer 90 thereon are removed, and then the metal layer 91 is removed to expose the carrier structure 24 .

[0108] In this embodiment, when peeling off the release layer 90, the metal layer 91 is used as a barrier (it can also be used as an electroplated circuit layer 241) to avoid damaging the supporting structure 24. After removing the supporting member 9 and the release layer 90 thereon, the metal layer 91 is removed by etching to expose the circuit layer 241.

[0109] Next, a singulation process is performed to form a plurality of conductive elements 27 on the supporting structure 24 , and the conductive elements 27 are electrically connected to the circuit layer 241 , so as to obtain the electronic package 2 .

[0110] In this embodiment, the conductive element 27 includes a metal bump 270 such as copper and a solder material 271 formed on the metal bump 270. For example, an under bump metallization (UBM) 272 may be formed on the circuit layer 241 to facilitate the combination of the metal bump 270. It should be understood that when the number of contacts (IOs) is insufficient, a layer increase operation can still be performed through the RDL process to reconfigure the number and position of the IOs of the supporting structure 24.

[0111] In one embodiment, a flattening process such as grinding can be used to remove part of the material of the packaging layer 28 as required, so that the upper surface of the packaging layer 28 is flush with the inactive surface of the electronic component 26, so that the electronic component 26 is exposed outside the packaging layer 28 (not shown).

[0112] In addition, the electronic package 2 can be disposed on an electronic device (not shown) such as a package substrate or a circuit board through the conductive elements 27 .

[0113] Therefore, the manufacturing method of the present invention mainly forms a plurality of grooves 291 in the protection layer 29 of the electronic structure 2a to effectively release stress and prevent the electronic structure 2a from warping, thereby preventing the external bump 222 from having a non-wetting problem in subsequent manufacturing processes.

[0114] The present invention provides an electronic structure 2 a including an electronic body 21 , a plurality of conductive bumps 211 , a plurality of external bumps 222 , a protective layer 29 and a plurality of grooves 291 .

[0115] The electronic body 21 has a first surface 21 a and a second surface 21 b opposite to each other, and a plurality of conductive through holes 210 are formed therein to connect the first surface 21 a and the second surface 21 b.

[0116] The conductive bumps 211 are formed on the first surface 21 a of the electronic body 21 to electrically connect the plurality of conductive through-holes 210 .

[0117] The external bumps 222 are formed on the second surface 21 b of the electronic body 21 .

[0118] The protection layer 29 is formed on the first surface 21 a of the electronic body 21 to cover the plurality of conductive bumps 211 , and the area outside the plurality of conductive bumps 211 in the protection layer 29 is defined as an open area A.

[0119] In one embodiment, a circuit portion 22 and a plurality of external bumps 222 may be formed on the second surface 21 b of the electronic body 21 as required. The circuit portion 22 includes at least one insulating layer 220 and a conductive trace 221 combined with the insulating layer 220 , so that the conductive trace 221 electrically connects the conductive through hole 210 and the external bump 222 .

[0120] The grooves 291 are formed in the open area A of the protective layer 29 by laser processing. In this embodiment, the grooves 291 do not penetrate the protective layer 29, that is, the grooves 291 do not expose the first surface 21a of the electronic body 21, and the depth of the grooves 291 is less than the thickness of the protective layer 29.

[0121] In one embodiment, the grooves 291 are not exposed on the side of the protective layer 29, that is, the grooves 291 do not extend to the edge of the electronic body 21. In another embodiment, part of the grooves 291 are exposed on the side of the protective layer 29, that is, the grooves 291 extend to the edge of the electronic body 21.

[0122] In one embodiment, when the electronic body 21 is long, the direction of the warping is the long side direction X of the electronic body 21 . At this time, the extension directions of the plurality of grooves 291 are in a single direction and are perpendicular to the long side direction X of the electronic body 21 .

[0123] In one embodiment, when the electronic body 21 is a square, the direction of warping may be irregular. In this case, the extension directions of the plurality of grooves 291 are respectively perpendicular to each other in the horizontal direction and the longitudinal direction, that is, the plurality of grooves 291 are respectively parallel to and perpendicular to the long side direction X, so that the plurality of grooves 291 are in a grid shape. In another embodiment, the direction of the grooves 291 can be designed according to different situations where the stress release requirements caused by the shape of the electronic body 21 are different, so that the extension directions of the grooves 291 are arranged irregularly, for example, the grooves 291 are perpendicular to the long side direction X but have intersections with each other, or the grooves 291 have multiple bending points, etc.

[0124] The present invention further provides an electronic package 2 , comprising the aforementioned electronic structure 2 a , a supporting structure 24 , a circuit structure 20 , a plurality of conductive pillars 23 , a coating layer 25 , a plurality of electronic components 26 , a plurality of conductive components 27 and a packaging layer 28 .

[0125] The supporting structure 24 includes at least one dielectric layer 240 and a circuit layer 241 combined with the dielectric layer 240. The electronic structure 2a is connected to the circuit layer 241 of the supporting structure 24 through a plurality of external bumps 222 via the second surface 21b of the electronic body 21.

[0126] The conductive pillars 23 are disposed on the supporting structure 24 and electrically connected to the circuit layer 241 .

[0127] The cladding layer 25 is formed on the supporting structure 24 and covers the electronic structure 2 a and the conductive pillars 23 , and the top surface of the protection layer 29 , the end surface of the conductive bump 211 , the groove 291 and the end surface of the conductive pillar 23 are exposed and flush with the surface of the cladding layer 25 .

[0128] The circuit structure 20 is formed on the cladding layer 25 and has a first side 20 a and a second side 20 b opposite to each other. The electronic structure 2 a is disposed on the first side 20 a of the circuit structure 20 with a first surface 21 a of an electronic body 21 .

[0129] In this embodiment, the circuit structure 20 includes at least one insulating layer 200 and a circuit redistribution layer 201 disposed on the insulating layer 200, so that the circuit redistribution layer 201 electrically connects multiple conductive columns 23 and multiple conductive bumps 211, wherein the outermost insulating layer 200 can be used as a solder mask, and the outermost circuit redistribution layer 201 is exposed to the outside of the solder mask to serve as an electrical contact pad 202, such as a micro pad (commonly known as μ-pad).

[0130] The electronic component 26 is disposed on the second side 20b of the circuit structure 20, and the packaging layer 28 is disposed on the second side 20b of the circuit structure 20 and covers the electronic component 26, wherein the electronic component 26 has a plurality of conductive bumps 261 such as copper pillars, which are electrically connected to the electrical contact pad 202 through a plurality of solder materials 260 such as solder bumps. The electronic structure 2a serves as a connecting element (Bridge Die), which is electrically connected to the circuit structure 20 through the conductive bumps 211, thereby electrically connecting at least two electronic components 26.

[0131] In one embodiment, the underfill 262 may be formed between the electronic components 26 and the circuit structure 20 to cover the conductive bumps 261 and the solder material 260. Alternatively, in other embodiments, the packaging layer 28 may cover the electronic components 26 and the conductive bumps 261 simultaneously without forming the underfill 262.

[0132] The conductive element 27 is formed on the supporting structure 24 and electrically connected to the circuit layer 241, wherein the conductive element 27 includes a metal bump 270 such as copper and a solder material 271 formed on the metal bump 270, and an under-bump metal layer 272 can be formed on the circuit layer 241 to facilitate the combination of the metal bump 270.

[0133] In summary, through the electronic structure and electronic package and the manufacturing method thereof of the present invention, a plurality of grooves are mainly formed in the protective layer of the electronic structure to effectively release stress and prevent the electronic structure from warping, and to prevent the external bump from soldering non-wetting in the subsequent manufacturing process. In addition, the electronic structure and electronic package and the manufacturing method thereof of the present invention can be completed with existing manufacturing processes and equipment without a large amount of additional cost expenditure.

[0134] The above embodiments are only used to illustrate the principles and effects of the present invention, and are not used to limit the present invention. Any person skilled in the art may modify the above embodiments without violating the inventive concept and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the claims.

Claims

1. An electronic structure, include: An electronic body having a first surface and a second surface opposite to each other; A plurality of conductive bumps are disposed on the first surface of the electronic body; A protective layer is disposed on the first surface of the electronic body and covers the plurality of conductive bumps, and defines an area outside the plurality of conductive bumps as an open area; and A plurality of grooves are formed in the protection layer and located in the open area.

2. The electronic structure according to claim 1, in, The plurality of grooves do not penetrate through the protection layer.

3. The electronic structure according to claim 1, in, Parts of the grooves are exposed on the side surface of the protection layer.

4. The electronic structure according to claim 1, in, The plurality of grooves extend in a single direction.

5. The electronic structure according to claim 1, in, The extension directions of the plurality of grooves are respectively perpendicular to each other in the horizontal direction and the vertical direction, so that the plurality of grooves are in a grid shape.

6. The electronic structure according to claim 1, in, The extension directions of the plurality of grooves are irregularly arranged.

7. An electronic package, include: A circuit structure having a first side and a second side opposite to each other; The electronic structure according to any one of claims 1 to 6, wherein the first surface of the electronic body is disposed on the first side of the circuit structure; as well as A plurality of electronic components are disposed on the second side of the circuit structure to electrically connect the circuit structure, wherein the electronic structure is electrically connected to the circuit structure through the plurality of conductive bumps to electrically connect at least two of the plurality of electronic components.

8. The electronic package as claimed in claim 7, in, The electronic package also includes a covering layer covering the electronic structure.

9. The electronic package as claimed in claim 7, in, The electronic package also includes a packaging layer covering the plurality of electronic components.

10. The electronic package according to claim 7, in, The electronic package also includes a supporting structure for supporting the electronic structure, so that the electronic structure is connected to the supporting structure through a plurality of external bumps with the second surface of the electronic body, so that the electronic structure is electrically connected to the supporting structure.

11. The electronic package according to claim 10, in, The electronic package also includes a plurality of conductive posts which are arranged on the supporting structure and surround the electronic structure to be electrically connected to the supporting structure.

12. A method for preparing an electronic structure, include: Providing an electronic body having a first surface and a second surface opposite to each other; forming a plurality of conductive bumps on the first surface of the electronic body; forming a protection layer on the first surface of the electronic body to cover the plurality of conductive bumps, wherein the protection layer defines an area outside the plurality of conductive bumps as an open area; and A plurality of grooves are formed in the protection layer, wherein the plurality of grooves are located in the open area.

13. The method for making an electronic structure according to claim 12, in, The plurality of grooves do not penetrate through the protection layer.

14. The method for making an electronic structure according to claim 12, in, Parts of the grooves are exposed on the side surface of the protection layer.

15. The method for making an electronic structure according to claim 12, in, The plurality of grooves extend in a single direction.

16. The method for making an electronic structure according to claim 12, in, The extension directions of the plurality of grooves are respectively perpendicular to each other in the horizontal direction and the vertical direction, so that the plurality of grooves are in a grid shape.

17. The method for making an electronic structure according to claim 12, in, The extension directions of the plurality of grooves are irregularly arranged.

18. A method for manufacturing an electronic package, include: A circuit structure and at least one electronic structure as claimed in any one of claims 1 to 6 are provided, wherein the circuit structure has a first side and a second side opposite to each other; Disposing the electronic structure corresponding to the first surface of the electronic body on the first side of the circuit structure; and A plurality of electronic components are disposed on the second side of the circuit structure to electrically connect the plurality of electronic components to the circuit structure, wherein the electronic structure is electrically connected to the circuit structure through the plurality of conductive bumps to electrically connect at least two of the plurality of electronic components.

19. The method for manufacturing an electronic package as claimed in claim 18, in, The method further comprises forming a coating layer covering the electronic structure.

20. The method for manufacturing an electronic package as claimed in claim 18, in, The manufacturing method further comprises forming a packaging layer covering the plurality of electronic components.

21. The method for manufacturing an electronic package as claimed in claim 18, in, The manufacturing method also includes placing the electronic structure on a supporting structure through a plurality of external bumps with the second surface of the electronic body, so that the electronic structure is electrically connected to the supporting structure.

22. The method for manufacturing an electronic package as claimed in claim 21, in, The manufacturing method also includes forming a plurality of conductive pillars on the supporting structure, so that the plurality of conductive pillars surround the electronic structure and are electrically connected to the supporting structure.

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