Packaging structure and packaging method of flip chip

Abstract

The invention discloses a packaging structure of a flip chip and a packaging method thereof. The packaging structure comprises a circuit layer, a flip chip, a metal heat dissipation layer and a packaging layer, the flip chip is electroplated on the circuit layer; the metal heat dissipation layer is arranged on the flip chip; the packaging layer is used for wrapping and packaging the flip chip, but the side face, away from the flip chip, of the metal heat dissipation layer is exposed. Wherein the flip chip performs double-sided heat dissipation by using the metal heat dissipation layer and the circuit layer. The flip chip can dissipate heat through the bonding pad surface on the circuit layer, and can also dissipate heat through the metal heat dissipation layer, so that the flip chip is prevented from being corroded by an external environment and being influenced by mechanical stress; meanwhile, the flip chip does not need to process a copper column in advance, the chip processing period is shortened, the surface mounting mode is front surface mounting, and the packaging preparation complexity is reduced.

Description

Technical Field

[0001] The present application relates to the field of chip packaging technology, and in particular to a flip chip packaging structure and a packaging method thereof. Background Art

[0002] As the performance and power consumption of electronic devices continue to improve, semiconductor devices have put forward higher requirements on the heat dissipation performance of the packaging structure. However, the heat dissipation performance of the existing flip chip packaging structure is poor. The thermal conductivity of the traditional epoxy molding compound is usually between 0.15-1.5W / (m·K). The low thermal conductivity of this material directly leads to a large thermal resistance (θJC) between the chip and the packaging shell, which limits the effective dissipation of heat and affects the stability and life of the chip.

[0003] To solve the above problems, a double-sided heat dissipation flip chip packaging structure has been introduced into the market. This structure exposes the silicon surface of the chip during the packaging process, forming a 5-sided encapsulation packaging form. However, the 5-sided encapsulation design lacks protection for the silicon surface of the chip, which is easily corroded by the external environment and affected by mechanical stress, thereby reducing the reliability of the product; at the same time, the packaging process of exposing the silicon surface is complicated, which increases the difficulty and cost of packaging preparation. Summary of the invention

[0004] The main technical problem solved by the present application is to provide a flip chip packaging structure and a packaging method thereof, which can improve the reliability of the flip chip packaging structure and reduce the complexity of packaging preparation.

[0005] In order to solve the above technical problems, a technical solution adopted by the present application is: to provide a flip chip packaging structure, the packaging structure comprising: a circuit layer, a flip chip, a metal heat dissipation layer, and a packaging layer;

[0006] The flip chip is electroplated on the circuit layer;

[0007] The metal heat dissipation layer is disposed on the flip chip;

[0008] The packaging layer is used to wrap and package the flip chip, but exposes a side of the metal heat dissipation layer away from the flip chip;

[0009] Wherein, the flip chip utilizes the metal heat dissipation layer and the circuit layer to perform double-sided heat dissipation.

[0010] In some embodiments, the metal heat dissipation layer is used to fix the flip chip;

[0011] The metal heat dissipation layer includes a base island region and connecting ribs, and the base island region and the connecting ribs are alternately arranged; wherein the base island region is arranged on the flip chip by patch adhesive.

[0012] In some embodiments, the thickness of the connecting rib is smaller than the thickness of the base island region.

[0013] In some embodiments, the packaging structure further includes a frame, which is disposed at both ends of the flip chip and is used to fix the flip chip.

[0014] In some embodiments, the circuit layer includes at least two circuit layers; an insulating buffer layer is laminated between adjacent circuit layers.

[0015] In order to solve the above technical problems, another technical solution adopted by the present application is: to provide a flip chip packaging method, the flip chip packaging method comprising:

[0016] Provide metal materials;

[0017] Etching the metal material to form a frame including a mounting area, and mounting the flip chip in the mounting area by using a face-mounting method;

[0018] Disposing a packaging layer on a side surface of the frame close to the flip chip to wrap and package the flip chip;

[0019] The packaging layer is processed to form a metal heat dissipation layer connected to one side of the flip chip, and a circuit layer connected to the other side of the flip chip, so that the flip chip can dissipate heat on both sides through the metal heat dissipation layer and the circuit layer; wherein the processing includes at least one of electroplating, circuit pattern processing, and surface treatment.

[0020] In some embodiments, etching the metal material to form a frame including a mounting area, and mounting the flip chip in the mounting area using a face-up method, includes:

[0021] Etching the metal material to form a base island area and connecting ribs, and half-etching the connecting ribs, using the base island area as the mounting area to form the frame;

[0022] The flip chip is mounted on one side of the base island region using the face-up method.

[0023] In some embodiments, the circuit layer includes a first circuit layer and a second circuit layer, and the packaging layer is processed to form a metal heat dissipation layer connected to one side of the flip chip, and a circuit layer connected to the other side of the flip chip, including:

[0024] The packaging layer on one side of the flip chip is sequentially subjected to laser drilling, metal electroplating, and pattern etching to form the first circuit layer;

[0025] Disposing an insulating layer on the first circuit layer and pressing it;

[0026] Performing laser drilling, metal electroplating, and pattern etching on the insulating layer in sequence to form the second circuit layer;

[0027] The surface below the base island region is treated to form the metal heat dissipation layer.

[0028] In some embodiments, etching the metal material to form a frame including a mounting area, and mounting the flip chip in the mounting area using a face-up method, includes:

[0029] Etching the metal material to form a hollowed-out mounting area to form the frame;

[0030] The flip chip is mounted on the mounting area in a face-up manner.

[0031] In some embodiments, the circuit layer includes a first circuit layer and a second circuit layer, etching the metal material to form a frame including a mounting area, and mounting the flip chip in the mounting area using a face-up method, including:

[0032] The packaging layer on one side of the flip chip is subjected to laser drilling, metal electroplating, and pattern etching in sequence to form the first circuit layer, and the side below the flip chip is subjected to metal electroplating to form an initial heat dissipation metal layer;

[0033] Disposing an insulating layer on the first circuit layer and pressing it;

[0034] Laser drilling, metal electroplating, and pattern etching are sequentially performed on the insulating layer to form the second circuit layer, and metal electroplating is performed on the initial heat dissipation metal layer to form the heat dissipation metal layer.

[0035] The embodiment of the present application provides a packaging structure of a flip chip, the packaging structure of the flip chip includes: a circuit layer, a flip chip, a metal heat dissipation layer, and a packaging layer; the flip chip is electroplated on the circuit layer; the metal heat dissipation layer is arranged on the flip chip; the packaging layer is used to wrap and package the flip chip, but exposes a side of the metal heat dissipation layer away from the flip chip; wherein the flip chip uses the metal heat dissipation layer and the circuit layer for double-sided heat dissipation. In addition to heat dissipation through the pad surface on the circuit layer, the flip chip can also dissipate heat through the metal heat dissipation layer to avoid erosion and mechanical stress from the external environment; at the same time, the flip chip does not need to pre-process the copper column, which shortens the chip processing cycle, and the mounting method is front mounting, which reduces the complexity of packaging preparation. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 It is a structural schematic diagram of a first embodiment of a flip chip packaging structure of the present application;

[0037] Figure 2 It is a structural schematic diagram of a second embodiment of the flip chip packaging structure of the present application;

[0038] Figure 3 It is a flow chart of an exemplary embodiment of a flip chip packaging method of the present application;

[0039] Figure 4a to Figure 4n It is a schematic diagram of an exemplary process flow of the flip chip packaging method of the present application;

[0040] Figure 5a to Figure 5n It is another exemplary process flow diagram of the flip chip packaging method of the present application. DETAILED DESCRIPTION

[0041] The present application is described in detail below with reference to the accompanying drawings and implementation methods.

[0042] See also Figure 1 , Figure 1 1 is a schematic diagram of the structure of the first embodiment of the flip chip packaging structure of the present application. Figure 1 As shown, the packaging structure of the flip chip includes: a circuit layer 101; a flip chip 102; a metal heat dissipation layer 103, and a packaging layer 104; the flip chip 102 is electroplated on the circuit layer 101; the metal heat dissipation layer 103 is arranged on the flip chip 102; the packaging layer 104 is used to wrap and package the flip chip 102, but exposes a side of the metal heat dissipation layer 103 away from the flip chip 102; wherein the flip chip 102 uses the metal heat dissipation layer 103 and the circuit layer 101 for double-sided heat dissipation.

[0043] Specifically, in the traditional packaging structure, it is generally necessary to first process the copper pillars as the connection points of the flip chip 102, and then solder the flip chip 102 to the substrate. This packaging method not only increases the processing steps and time, but also increases the amount of material used. However, by optimizing the packaging structure, the present embodiment connects one side of the flip chip 102 to the metal heat dissipation layer 103 using patch adhesive, and the other side is connected to the circuit layer 101 by electroplating, so that there is no need to process the copper pillars additionally, thereby reducing the processing cycle of the flip chip 102.

[0044] Specifically, the packaging layer 104 can be used to encapsulate the flip chip 102 to protect the flip chip 102 from external environmental influences, such as humidity and mechanical stress. It can also be used to encapsulate part of the metal heat dissipation layer 103 and control the exposure of the side of the metal heat dissipation layer 103 away from the flip chip 102, so that the flip chip 102 can dissipate heat through the exposed side of the metal heat dissipation layer 103.

[0045] Specifically, the side of the metal heat dissipation layer 103 away from the flip chip 102 can be the side of the metal heat dissipation layer 103 facing upward, which is exposed to the outside of the packaging layer 104, and the rest can be packaged by the packaging layer 104. The packaged part of the metal heat dissipation layer 103 can enhance the structural stability by being wrapped by the packaging layer 104.

[0046] Among them, the flip chip 102 can transfer heat to the pad surface through the circuit layer 101 below, and the metal heat dissipation layer 103 above the flip chip 102 can diffuse the heat to the copper surface of the package surface. The double-sided heat dissipation design improves the heat dissipation efficiency and allows the heat to quickly diffuse to the entire package surface.

[0047] In some embodiments, a dam frame is a commonly used structure in traditional package design, which is used to protect the area around the package and ensure a stable connection between the flip chip 102 and the substrate. However, this structure requires the pad to be set on the dam structure, resulting in a decrease in the panel utilization rate, that is, reducing the number of flip chips 102 that can be packaged on the same substrate.

[0048] Therefore, this embodiment proposes a dam-free frame structure, which improves the utilization rate of the panel by removing the dam frame and avoiding the connection between the frame and the pad of the flip chip 102. Compared with the traditional packaging design that requires additional heat sinks or heat pipes to manage heat, the packaging structure in this embodiment realizes the heat dissipation function through the frame itself, so that the heat generated by the flip chip 102 can be effectively discharged, and the flip chip 102 can be kept working within an ideal temperature range.

[0049] Among them, the metal heat dissipation layer 103 can serve as a frame of the flip chip 102, used to fix the flip chip 102; the metal heat dissipation layer 103 includes a base island area and connecting ribs, and the base island area and the connecting ribs are alternately arranged; wherein the base island area is arranged on the flip chip 102 by patch glue.

[0050] Specifically, the base island area of ​​the metal heat dissipation layer 103 can cover one side above the flip chip 102, and conduct the heat of the flip chip 102 to the outside of the packaging structure through its high thermal conductivity material, such as copper or aluminum material. That is, the frame of the structure acts as a heat sink, which has a better heat dissipation effect, especially for the power management type flip chip 102 with high heat generation.

[0051] The base island area and the connecting ribs of the metal heat dissipation layer 103 work together to fix the flip chip 102 to provide mechanical strength for the flip chip 102. The base island area can fix the flip chip 102 by using a patch adhesive. Since the pad is not on the frame, the size of the base island area is larger, and the flip chip 102 that can be mounted is also larger.

[0052] In some embodiments, considering that the connecting ribs of conventional packaging frames are usually relatively thick, they not only increase the wear of cutting tools during the production process, but may also cause poor appearance during cutting, such as scratches or breakage.

[0053] Therefore, this embodiment proposes a half-etched design of the frame, which reduces the space occupied by the connecting ribs by optimizing the thickness and shape of the connecting ribs. This not only reduces damage to the tool during the cutting process, but also effectively improves cutting accuracy and product appearance quality.

[0054] Wherein, the thickness of the connecting rib is less than the thickness of the base island region. Further, the thickness of the connecting rib may be half of the thickness of the base island region.

[0055] In some embodiments, the heat dissipation metal layer can adjust its shape and size according to the package size and application requirements, providing customized heat dissipation solutions for different scenarios and improving flexibility.

[0056] In some embodiments, considering that the stress generated during the welding process will be directly transmitted to the active area of ​​the flip chip 102, which may cause performance degradation or damage, the packaging structure of this embodiment can adopt a two-stage routing design with an insulating buffer layer in the middle to effectively isolate the welding stress, so that the stress cannot be directly transmitted to the active part of the flip chip 102, thereby reducing the risk of damage.

[0057] The circuit layer 101 includes at least two circuit layers 101 ; an insulating buffer layer is laminated between adjacent circuit layers 101 , which can effectively solve the problem of stress-sensitive analog flip chip 102 .

[0058] See also Figure 2 , Figure 2 1 is a schematic diagram of the structure of the second embodiment of the flip chip packaging structure of the present application. Figure 2As shown, the packaging structure of the flip chip includes: a circuit layer 201; a flip chip 202; a metal heat dissipation layer 203, and a packaging layer 204; the flip chip 202 is electroplated on the circuit layer 201; the metal heat dissipation layer 203 is arranged on the flip chip 202; the packaging layer 204 is used to wrap and package the flip chip 202, but expose a side of the metal heat dissipation layer 203 away from the flip chip 202; wherein the flip chip 202 uses the metal heat dissipation layer 203 and the circuit layer 201 for double-sided heat dissipation.

[0059] In some embodiments, the circuit layer 201 includes at least two circuit layers 201 ; an insulating buffer layer is laminated between adjacent circuit layers 201 .

[0060] Specifically, the connection method and beneficial effects of the circuit layer 201, the flip chip 202, and the packaging layer 204 in this embodiment can be the same as those in the first embodiment mentioned above; compared with the packaging structure in the first embodiment, the flip chip 202 of the metal heat dissipation layer 203 in this embodiment can be directly connected to the heat dissipation metal layer, that is, the flip chip 202 and the heat dissipation metal layer do not need to be connected using patch adhesive, which can further improve the heat dissipation effect.

[0061] In some embodiments, compared with the dam structure in traditional packaging design, the packaging structure in this embodiment also includes a frame 205, and the frame 205 is arranged at both ends of the flip chip 202 to fix the flip chip 202, and also realizes a dam-free frame 205 structure, so that the panel utilization rate is higher and the unit cost is lower.

[0062] The above scheme provides a packaging structure of a flip chip, and the packaging structure of the flip chip includes: a circuit layer, a flip chip, a metal heat dissipation layer, and a packaging layer; the flip chip is electroplated on the circuit layer; the metal heat dissipation layer is arranged on the flip chip; the packaging layer is used to wrap and package the flip chip, but exposes a side of the metal heat dissipation layer away from the flip chip; wherein the flip chip uses the metal heat dissipation layer and the circuit layer for double-sided heat dissipation. In addition to heat dissipation through the pad surface on the circuit layer, the flip chip can also dissipate heat through the metal heat dissipation layer to avoid erosion and mechanical stress from the external environment; at the same time, the flip chip does not need to pre-process the copper column, which shortens the chip processing cycle, and the mounting method is front mounting, which reduces the complexity of packaging preparation.

[0063] See also Figure 3 , Figure 3 FIG. 1 is a flow chart of an exemplary embodiment of a flip chip packaging method of the present application. It should be noted that if there is substantially the same result, the method of the present application is not limited to the method of the present application. Figure 3 The process sequence shown is limited. Figure 3 As shown, the flip chip packaging method includes:

[0064] Step S301, providing metal material;

[0065] As an illustrative example, the metal material can be used to form a frame of a flip chip and can also be used to form a metal heat dissipation layer.

[0066] Step S302, etching the metal material to form a frame including a mounting area, and mounting the flip chip in the mounting area by a face-mounting method;

[0067] As an illustrative example, the mounting area may be used to mount a flip chip. The metal material is etched through an etching process to form a frame including the mounting area, and the flip chip is mounted on the mounting area of ​​the frame in a positive manner, which can improve the performance of the flip chip, such as the connection between the electrode and the sensor area and the packaging layer and the metal heat dissipation layer, thereby improving the heat dissipation efficiency and electrical performance.

[0068] Step S303, disposing a packaging layer on a side surface of the frame close to the flip chip to wrap and package the flip chip;

[0069] As an illustrative example, a packaging layer can be placed on the frame and wrap the flip chip to form a flip chip protection structure. The packaging layer can protect the flip chip from environmental factors and extend the life of the flip chip.

[0070] Step S304, processing the packaging layer to form a metal heat dissipation layer connected to one side of the flip chip, and a circuit layer connected to the other side of the flip chip, so that the flip chip can dissipate heat on both sides through the metal heat dissipation layer and the circuit layer; wherein the processing includes at least one of electroplating, circuit pattern processing, and surface treatment.

[0071] In some embodiments, etching the metal material to form a frame including a mounting area, and mounting the flip chip in the mounting area using a face-up method, includes:

[0072] The metal material is etched to form a base island area and connecting ribs, and the connecting ribs are half-etched, and the base island area is used as the mounting area to form the frame; on one side of the base island area, the flip chip is mounted using the face-up method.

[0073] As an illustrative example, electroplating, graphic circuit processing and surface treatment can be performed above the packaging layer to form a circuit layer that is electrically connected to one side of the flip chip; at the same time, surface treatment is performed on the surface of the mounting area below the packaging layer to form a metal heat dissipation layer connected to the other side of the flip chip.

[0074] Among them, part of the material can be removed from the surface of the metal material by etching to form a frame with a specific shape and function. This frame includes a mounting area and connecting ribs. The mounting area is used to install the flip chip area, and the connecting ribs are used to connect and support the thin strip structure of the frame. Then, the flip chip is placed face up and mounted above the base island area. Among them, by partially removing the thickness of the connecting ribs and making them thinner, the overall design of the frame can be made more compact and the space utilization rate can be improved. This lightweight design is especially suitable for portable or high-performance devices.

[0075] The circuit layer includes a first circuit layer and a second circuit layer, and the packaging layer is processed to form a metal heat dissipation layer connected to one side of the flip chip and a circuit layer connected to the other side of the flip chip, including:

[0076] The packaging layer on one side of the flip chip is subjected to laser drilling, metal electroplating, and pattern etching in sequence to form the first circuit layer; an insulating layer is provided on the first circuit layer and pressed together; laser drilling, metal electroplating, and pattern etching are performed in sequence on the insulating layer to form the second circuit layer; and surface treatment is performed below the base island area to form the metal heat dissipation layer.

[0077] Specifically, through the layered design of the first circuit layer and the second circuit layer, the insulating buffer layer in the middle effectively reduces the conduction of welding stress to the active surface of the flip chip, effectively solving the problem of stress-sensitive analog flip chips.

[0078] As an exemplary specific implementation process, please refer to Figure 4a to Figure 4n .

[0079] First, if Figure 4a As shown, a copper material 401 of a certain thickness is provided, for example, the thickness may be 100um to 210um;

[0080] Then, if Figure 4b As shown, a copper material 401 of a certain thickness is etched into a frame, and the frame includes a base island area 402 and a connecting rib 403, wherein the area of ​​the connecting rib 403 can be half-etched;

[0081] Then, if Figure 4c It is shown that the flip chip 404 is mounted in a positive mounting manner, and the flip chip is mounted to the position specified by the base island area 402 through the patch adhesive 405;

[0082] Then, if Figure 4d As shown, the mounted flip chip 404 and the frame are plastic-encapsulated to form a packaging layer 406;

[0083] Then, if Figure 4e As shown, laser drilling is performed on the surface of the packaging layer 406 to form a first layer of laser holes 407, and the bottom of the laser holes 407 is connected to the I / O of the active surface of the flip chip 404;

[0084] Then, if Figure 4f It is shown that a first conductive seed layer 408 is attached to the surface of the encapsulation layer 406 and inside the laser hole 407 by sputtering or chemical deposition;

[0085] Then, if Figure 4g As shown, copper is electroplated on the first conductive seed layer 408 to a certain thickness to form a first electroplated layer 409;

[0086] Then, if Figure 4h As shown, the first electroplating layer 409 is processed with circuit patterns by photolithography-development-etching to form a first circuit layer 410;

[0087] Then, if Figure 4i It is shown that the first circuit layer 410 is pressed with an insulating buffer material to form an insulating buffer layer 411, which increases the structural rigidity of the product and buffers the welding stress, wherein the insulating buffer material can be FR4, PP, PI, etc.;

[0088] Then, if Figure 4j As shown, laser drilling is performed on the surface of the insulating buffer layer 411 to form a second layer of laser holes 412;

[0089] Then, if Figure 4k It is shown that a second conductive seed layer 413 is attached to the insulating buffer layer 411 and the second laser hole 412 by sputtering or chemical deposition;

[0090] Then, if Figure 4l As shown, copper is electroplated on the second conductive seed layer 413 to a certain thickness to form a second electroplated layer 414;

[0091] Then, if Figure 4m As shown, the second electroplating layer 414 is processed with circuit patterns by photolithography-development-etching to form a second circuit layer 415;

[0092] Finally, if Figure 4nAs shown, the surface of the structure is treated to form the packaging structure of the flip chip 404 in this embodiment. The surface treatment material may include but is not limited to chemical tin plating, chemical gold plating, chemical silver plating, etc., to prevent oxidation of the pad and provide solderability. In this embodiment, double-sided mounting and packaging can be performed, that is, two or more multi-chip packaging structures are manufactured at one time to obtain two finished multi-chip packaging structures. Therefore, after the surface treatment, the finished product can be cut and cut out by a cutting machine.

[0093] The frame of this structure acts as a heat sink, which has better heat dissipation effect and is very suitable for flip chips with high heat generation in power management. The connecting ribs are semi-etched and 50% thinner than traditional frame connecting ribs, which is conducive to extending the service life of the finished cutting tool and reducing the appearance problems caused by the connecting ribs in the finished product cutting.

[0094] In other embodiments, the metal material is etched to form a frame including a mounting area, and a flip chip is mounted in the mounting area using a face-up method, including: etching the metal material to form a hollow mounting area to form the frame; and mounting the flip chip in the mounting area using a face-up method.

[0095] As an illustrative example, as another illustrative example, electroplating, graphic circuit processing and surface treatment can be performed above the packaging layer to form a circuit layer that is electrically connected to one side of the flip chip; at the same time, electroplating and surface treatment are performed below the packaging layer to form a metal heat dissipation layer connected to the other side of the flip chip.

[0096] The mounting area is hollowed out, and the two ends of the mounting area are frames, which can reduce the cost of frame materials. In this embodiment, the frame can be a metal support part left after etching, and the mounting area is between adjacent support parts, which can be used to support and protect the flip chip.

[0097] The existing flip chip mounting is a process of fixing the flip chip to the frame, which is usually completed by welding, bonding, etc. However, in this embodiment, by placing the flip chip in the hollow mounting area, there is no need to further fix the flip chip to the frame by welding or bonding.

[0098] The circuit layer includes a first circuit layer and a second circuit layer, the metal material is etched to form a frame including a mounting area, and a flip chip is mounted in the mounting area by a face-mounting method, including:

[0099] The packaging layer on one side of the flip chip is subjected to laser drilling, metal electroplating, and pattern etching in sequence to form the first circuit layer, and the side below the flip chip is subjected to metal electroplating to form an initial heat dissipation metal layer; an insulating layer is provided on the first circuit layer and pressed together; laser drilling, metal electroplating, and pattern etching are performed in sequence on the insulating layer to form the second circuit layer, and the initial heat dissipation metal layer is subjected to metal electroplating to form the heat dissipation metal layer.

[0100] As an illustrative example, metal electroplating is performed on one side below the flip chip in order to form a heat dissipation metal layer, thereby allowing the flip chip to be in direct contact with the heat dissipation metal layer, i.e., there is no patch glue or welding metal between the flip chip and the heat dissipation metal layer, so that the packaging structure can more effectively improve the heat dissipation effect of the flip chip.

[0101] At the same time, through the layered design of the first circuit layer and the second circuit layer, the insulating buffer layer in the middle effectively reduces the conduction of welding stress to the active surface of the flip chip, effectively solving the problem of stress-sensitive analog flip chips.

[0102] As an exemplary specific implementation process, please refer to Figure 5a to Figure 5n .

[0103] First, if Figure 5a As shown, a copper material 501 of a certain thickness is provided, for example, the thickness may be 100um to 210um;

[0104] Then, if Figure 5b As shown, a copper material 501 of a certain thickness is etched into a frame 502, wherein the area where the flip chip is mounted is etched to form a hollow mounting area 503;

[0105] Then, if Figure 5c It is shown that the flip chip 504 is placed in the mounting area 503 by using the face-up method;

[0106] Then, if Figure 5d As shown, the mounted flip chip 504 and the frame 502 are plastic-encapsulated to form a packaging layer 506;

[0107] Then, if Figure 5e As shown, laser drilling is performed on the surface of the packaging layer 506 to form a first layer of laser holes 507, and the bottom of the laser holes 507 is connected to the I / O of the active surface of the flip chip 504;

[0108] Then, if Figure 5f It is shown that a first conductive seed layer 508 is attached to the surface of the encapsulation layer 506 and inside the laser hole 507 by sputtering or chemical deposition;

[0109] Then, if Figure 5g As shown, copper is electroplated on the first conductive seed layer 508 to a certain thickness to form a first electroplated layer 509;

[0110] Then, if Figure 5h As shown, the first electroplating layer 509 is processed with circuit patterns by photolithography-development-etching to form a first circuit layer 510;

[0111] Then, if Figure 5i It is shown that the first circuit layer 510 is pressed with an insulating buffer material to form an insulating buffer layer 511, which increases the structural rigidity of the product and buffers welding stress, wherein the insulating buffer material can be FR4, PP, PI, etc.;

[0112] Then, if Figure 5j As shown, laser drilling is performed on the surface of the insulating buffer layer 511 to form a second layer of laser holes 512;

[0113] Then, if Figure 5k It is shown that a second conductive seed layer 513 is attached to the insulating buffer layer 511 and the second laser hole 512 by sputtering or chemical deposition;

[0114] Then, if Figure 5l As shown, copper is electroplated on the second conductive seed layer 513 to a certain thickness to form a second electroplated layer 514;

[0115] Then, if Figure 5m It is shown that the second electroplating layer 514 is processed with circuit patterns by photolithography-development-etching to form a second circuit layer 515;

[0116] Finally, if Figure 5n As shown, the surface of the structure is treated to form the flip chip packaging structure in this embodiment. The surface treatment material may include but is not limited to chemical tin plating, chemical gold plating, chemical silver plating, etc., to prevent oxidation of the pad and provide solderability. In this embodiment, double-sided mounting and packaging can be performed, that is, two or more multi-chip packaging structures are manufactured at one time to obtain two finished multi-chip packaging structures. Therefore, after the surface treatment, the finished product can be cut and cut out by a cutting machine.

[0117] In this embodiment, the structure is suitable for flip-chip packaging, and there is no need to pre-process the copper pillars, which shortens the processing cycle of the flip chip; the frame structure without dams has a higher utilization rate of the panels and a lower unit cost. Since the pads are not on the frame, the base island size is larger, and the flip chip that can be mounted is also larger. The two-stage routing on the surface of the flip chip, and the insulating buffer layer in the middle effectively reduce the conduction of the welding stress to the active surface of the flip chip, which effectively solves the problem of stress-sensitive analog flip chips.

[0118] In the several embodiments provided in the present application, it should be understood that the disclosed packaging structure and method can be implemented in other ways. For example, the packaging structure implementation described above is only schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0119] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0120] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0121] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) or a processor (processor) to perform all or part of the steps of the flip chip packaging method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.

[0122] The above description is only an implementation method of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A flip chip packaging structure, characterized in that: The packaging structure includes: Circuit layer; A flip chip, wherein the flip chip is electroplated on the circuit layer; A metal heat dissipation layer, the metal heat dissipation layer is arranged on the flip chip; A packaging layer, the packaging layer is used to wrap and package the flip chip, but expose a side of the metal heat dissipation layer away from the flip chip; Wherein, the flip chip utilizes the metal heat dissipation layer and the circuit layer to perform double-sided heat dissipation.

2. The packaging structure according to claim 1, characterized in that: The metal heat dissipation layer is used to fix the flip chip; The metal heat dissipation layer includes a base island region and connecting ribs, and the base island region and the connecting ribs are alternately arranged; wherein the base island region is arranged on the flip chip by patch adhesive.

3. The packaging structure according to claim 2, characterized in that: The thickness of the connecting rib is smaller than the thickness of the base island region.

4. The packaging structure according to claim 1, characterized in that: The packaging structure also includes a frame, which is arranged at both ends of the flip chip and is used to fix the flip chip.

5. The packaging structure according to claim 1, characterized in that: The circuit layer comprises at least two circuit layers; an insulating buffer layer is laminated between adjacent circuit layers.

6. A flip chip packaging method, characterized in that: The flip chip packaging method comprises: Provide metal materials; Etching the metal material to form a frame including a mounting area, and mounting the flip chip in the mounting area by using a face-mounting method; Disposing a packaging layer on a side surface of the frame close to the flip chip to wrap and package the flip chip; The packaging layer is processed to form a metal heat dissipation layer connected to one side of the flip chip, and a circuit layer connected to the other side of the flip chip, so that the flip chip can dissipate heat on both sides through the metal heat dissipation layer and the circuit layer; wherein the processing includes at least one of electroplating, circuit pattern processing, and surface treatment.

7. The flip chip packaging method according to claim 6, characterized in that: The step of etching the metal material to form a frame including a mounting area, and mounting the flip chip in the mounting area by a face-mounting method includes: Etching the metal material to form a base island area and connecting ribs, and half-etching the connecting ribs, using the base island area as the mounting area to form the frame; The flip chip is mounted on one side of the base island region using the face-up method.

8. The flip chip packaging method according to claim 7, characterized in that: The circuit layer includes a first circuit layer and a second circuit layer, and the packaging layer is processed to form a metal heat dissipation layer connected to one side of the flip chip and a circuit layer connected to the other side of the flip chip, including: The packaging layer on one side of the flip chip is sequentially subjected to laser drilling, metal electroplating, and pattern etching to form the first circuit layer; Disposing an insulating layer on the first circuit layer and pressing it; Performing laser drilling, metal electroplating, and pattern etching on the insulating layer in sequence to form the second circuit layer; The surface below the base island region is treated to form the metal heat dissipation layer.

9. The flip chip packaging method according to claim 6, characterized in that: The step of etching the metal material to form a frame including a mounting area, and mounting the flip chip in the mounting area by a face-mounting method includes: Etching the metal material to form a hollowed-out mounting area to form the frame; The flip chip is mounted on the mounting area in a face-up manner.

10. The flip chip packaging method according to claim 9, characterized in that: The circuit layer includes a first circuit layer and a second circuit layer, the metal material is etched to form a frame including a mounting area, and a flip chip is mounted in the mounting area by a face-mounting method, including: The packaging layer on one side of the flip chip is subjected to laser drilling, metal electroplating, and pattern etching in sequence to form the first circuit layer, and the side below the flip chip is subjected to metal electroplating to form an initial heat dissipation metal layer; Disposing an insulating layer on the first circuit layer and pressing it; Laser drilling, metal electroplating, and pattern etching are sequentially performed on the insulating layer to form the second circuit layer, and metal electroplating is performed on the initial heat dissipation metal layer to form the heat dissipation metal layer.

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