Integrated substrate and manufacturing method thereof
By using plastic encapsulation materials such as epoxy resin or polyimide as the support layer of the integrated substrate, combined with the design of the conductive layer and the inter-dielectric layer, the problem of cracking of the wafer after filling of glass through holes or silicon through holes is solved, and higher flexibility and deformation capabilities are achieved, and the process flow is simplified.
Patent Information
- Application Number
- CN202311576360.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-23
- Publication Date
- 2025-05-23
AI Technical Summary
In the prior art, glass through holes or silicon through holes are easily cracked after filling, and the material has a large difference in thermal conductivity and thermal expansion coefficient, which leads to the impact of structural reliability and cannot meet the large deformation needs.
Plastic encapsulation materials such as epoxy resin or polyimide are used as support layers for the integrated substrate. By forming connection vias and connection electrodes that penetrate in the thickness direction, electrical connection between conductive layers is realized, and inductive and capacitive structures are constructed through multi-layer dielectric layers and adapter structures.
The problem of cracking of the wafer after filling of glass through holes or silicon through holes is solved, the flexibility and deformation ability of the material are improved, and the demand for large deformation is adapted, while reducing the difficulty of the electroplating filling process and simplifying the process flow.
Smart Images
Figure CN120033170A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of electronic technology, and particularly relates to an integrated substrate and a manufacturing method thereof. Background Art
[0002] With the development of communication technology, the frequency used in mobile communications is getting higher and higher, from hundreds of megahertz in 2G technology to 3.5 GHz and millimeter wave in 5G technology. The current market demand for the miniaturization of electronic products is getting higher and higher. At present, passive devices such as capacitors, inductors, and resistors account for about 70% of the area on PCB (Printed Circuit Board). IPD (Integrated Passive Devices) technology can reduce the area of passive devices by more than 80%, and the market prospects are broad. Based on the different integrated substrates, integrated substrate technology can be divided into silicon-based, LTCC-based (Low Temperature Co-fired Ceramic), glass-based and other technical routes. As the main energy-consuming component in electronic products, the RF front end requires a significant reduction in device electromagnetic loss. Due to the advantages of glass-based materials in dielectric loss and cost, glass-based integrated substrates have gradually become the mainstream route.
[0003] TGV (Through Glass Vias) and TSV (Through Silicon Vias) three-dimensional interconnection technologies can realize chip interconnection in the horizontal and vertical directions. They have the advantages of excellent electrical and optical properties, good mechanical stability and low cost. They have broad application prospects in three-dimensional packaging, integrated substrates, MEMS (Micro-Electro-Mechanical System) sensor devices and optoelectronic devices.
[0004] Metal and glass (or silicon) have large differences in thermal conductivity and thermal expansion coefficient. The metal in TGV and TSV is a good thermal conductor. In the process, high temperature is required for the curing of polyimide materials and ball reflow. On the one hand, due to the different thermal parameters of the metal and glass (or silicon) materials in TGV and TSV, different degrees of stress and strain will be generated inside. When the stress reaches a certain level, the material will break or suffer fatigue damage, which will affect the reliability of the structure. On the other hand, because glass (or silicon) is a brittle material, it cannot meet the large deformation required by some IPDs. Summary of the invention
[0005] The present disclosure aims to solve at least one of the technical problems existing in the prior art, and to provide an integrated substrate that can be used to solve problems such as wafer cracking caused by filling of existing through glass vias or through silicon vias, while having a flexible supporting material that can adapt to larger deformations.
[0006] In a first aspect, the present disclosure provides an integrated substrate, comprising:
[0007] A supporting layer, wherein the supporting layer has a first connecting via hole penetrating along a thickness direction thereof;
[0008] The first conductive layer and the second conductive layer are respectively arranged on two opposite side surfaces of the support layer along the thickness direction thereof;
[0009] The first connecting electrode is disposed in the first connecting via hole, and the first conductive layer is electrically connected to the second conductive layer through the first connecting electrode.
[0010] Preferably, the integrated substrate further includes a first protective layer covering the first conductive layer; the first conductive layer includes a first conductive structure; the first protective layer has a first concave pattern, and the first conductive structure is filled in the first concave pattern.
[0011] Preferably, the second conductive layer includes a second conductive structure, and the first conductive structure and the second conductive structure are connected via the first connecting electrode to form an inductor coil structure; and a first interlayer dielectric layer is provided on a side of the support layer away from the first conductive layer.
[0012] Preferably, the second conductive layer includes a first plate of a capacitor; a second interlayer dielectric layer and a third conductive layer are sequentially arranged on a side of the second conductive layer away from the support layer; and the third conductive layer includes a second plate of a capacitor.
[0013] Preferably, the integrated substrate further comprises a third interlayer dielectric layer located on a side of the second conductive layer away from the support layer, a first transfer structure located on a side of the second conductive structure away from the second conductive layer, and a second transfer structure located on a side of the second plate of the capacitor away from the second conductive layer; wherein,
[0014] The first transfer structure is electrically connected to the second conductive structure through a via hole penetrating the third interlayer dielectric layer, and the second transfer structure is electrically connected to the second plate of the capacitor through a via hole penetrating the third interlayer dielectric layer.
[0015] Preferably, the integrated substrate further comprises a fourth interlayer dielectric layer disposed on a side of the first transfer structure and the second transfer structure away from the third interlayer dielectric layer, and a connection structure disposed on a side of the fourth interlayer dielectric layer away from the first transfer structure; wherein,
[0016] The connection structure is connected to the first transfer structure through a via hole penetrating the fourth interlayer dielectric layer.
[0017] Preferably, the material of the support layer includes epoxy resin or polyimide.
[0018] In a second aspect, the present disclosure provides a method for preparing an integrated substrate, comprising:
[0019] forming a first conductive layer;
[0020] forming a first connecting electrode on the first conductive layer;
[0021] forming a supporting layer on the first conductive layer, wherein the supporting layer has a first connecting via hole penetrating along a thickness direction thereof, and the first connecting electrode is disposed in the first connecting via hole;
[0022] A second conductive layer is formed on a side of the support layer away from the first conductive layer; the first conductive layer is electrically connected to the second conductive layer through the first connecting electrode.
[0023] Preferably, before forming the first conductive layer, the method further comprises:
[0024] providing a substrate;
[0025] forming a first adhesive layer on the substrate;
[0026] forming a first sub-protective layer on a side of the first adhesive layer facing away from the substrate;
[0027] A second sub-protective layer is formed on a side of the first sub-protective layer facing away from the substrate, the second sub-protective layer includes a first opening penetrating along a thickness direction thereof, the first opening and the first sub-protective layer define a first concave pattern, and the first sub-protective layer and the second sub-protective layer constitute a first protective layer; the first conductive structure of the first conductive layer is filled in the first concave pattern;
[0028] After forming the second conductive layer, the method further includes removing the first adhesive layer and the substrate.
[0029] Preferably, the step of forming the first conductive layer includes:
[0030] forming a first conductive film on a side of the second sub-protection layer facing away from the substrate as a first seed layer, and electroplating the first seed layer to form a first conductive film layer;
[0031] The first conductive film layer is processed by a chemical mechanical polishing process, and only the first conductive film layer portion filled in the first concave pattern remains, thereby forming the first conductive structure.
[0032] Preferably, before forming the first conductive layer, the method further comprises:
[0033] providing a substrate;
[0034] forming a first adhesive layer on the substrate;
[0035] forming a first protective layer on a side of the first adhesive layer away from the substrate; the first conductive structure is located on a side of the first protective layer away from the substrate;
[0036] After forming the second conductive layer, the method further includes removing the first adhesive layer and the substrate.
[0037] Preferably, the support layer is formed by using a lamination technique after the first connecting electrode is formed.
[0038] Preferably, the step of forming the support layer comprises:
[0039] forming a support material layer on the first conductive layer, and processing the support material layer to form a first connecting via hole penetrating along the thickness direction of the support material layer;
[0040] The first connection electrode is formed after the support layer is formed, and the first connection electrode passes through the first connection via hole.
[0041] Preferably, the material of the support layer includes epoxy resin or polyimide.
[0042] In a third aspect, the present disclosure provides an electronic device, which includes the above-mentioned integrated substrate. BRIEF DESCRIPTION OF THE DRAWINGS
[0043] Figure 1 A schematic diagram of the structure of an integrated substrate provided by the present disclosure;
[0044] Figure 2 A schematic structural diagram of another integrated substrate provided by the present disclosure;
[0045] Figure 3 A schematic structural diagram of another integrated substrate provided by the present disclosure;
[0046] Figure 4a A schematic diagram of an intermediate product of step S11 of a method for preparing an integrated substrate provided by the present disclosure;
[0047] Figure 4b A schematic diagram of an intermediate product of step S12 of a method for preparing an integrated substrate provided by the present disclosure;
[0048] Figure 4cA schematic diagram of an intermediate product of step S13 of a method for preparing an integrated substrate provided by the present disclosure;
[0049] Figure 4d A schematic diagram of an intermediate product of step S14 of a method for preparing an integrated substrate provided by the present disclosure;
[0050] Figure 4e A schematic diagram of an intermediate product of step S15 of a method for preparing an integrated substrate provided by the present disclosure;
[0051] Figure 4f A schematic diagram of an intermediate product of step S16 of a method for preparing an integrated substrate provided by the present disclosure;
[0052] Figure 4g A schematic diagram of an intermediate product of step S17 of a method for preparing an integrated substrate provided by the present disclosure;
[0053] Figure 5a A schematic diagram of an intermediate product of step S21 of another method for preparing an integrated substrate provided by the present disclosure;
[0054] Figure 5b A schematic diagram of an intermediate product of step S22 of another method for preparing an integrated substrate provided by the present disclosure;
[0055] Figure 5c A schematic diagram of an intermediate product of step S23 of another method for preparing an integrated substrate provided by the present disclosure;
[0056] Figure 5d A schematic diagram of an intermediate product of step S24 of another method for preparing an integrated substrate provided by the present disclosure;
[0057] Figure 5e A schematic diagram of an intermediate product of step S25 of another method for preparing an integrated substrate provided by the present disclosure;
[0058] Figure 5f A schematic diagram of an intermediate product of step S26 of another method for preparing an integrated substrate provided by the present disclosure;
[0059] Figure 5g A schematic diagram of an intermediate product of step S27 of another method for preparing an integrated substrate provided by the present disclosure;
[0060] Figure 6a A schematic diagram of an intermediate product of step S31 of another method for preparing an integrated substrate provided by the present disclosure;
[0061] Figure 6b A schematic diagram of an intermediate product of step S32 of another method for preparing an integrated substrate provided by the present disclosure;
[0062] Figure 6c A schematic diagram of an intermediate product of step S33 of another method for preparing an integrated substrate provided by the present disclosure;
[0063] Figure 6d A schematic diagram of an intermediate product of step S34 of another method for preparing an integrated substrate provided by the present disclosure;
[0064] Figure 6e A schematic diagram of an intermediate product of step S35 of another method for preparing an integrated substrate provided by the present disclosure;
[0065] Figure 6f A schematic diagram of an intermediate product of step S36 of another method for preparing an integrated substrate provided by the present disclosure;
[0066] Figure 6g This is a schematic diagram of an intermediate product of step S37 of another method for preparing an integrated substrate provided by the present disclosure. DETAILED DESCRIPTION
[0067] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. The components of the embodiments of the present disclosure generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the scope of the present disclosure for protection, but merely represents the selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present disclosure.
[0068] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.
[0069] The "multiple or several" mentioned in this disclosure refers to two or more. "And / or" describes the association relationship of the associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.
[0070] In a first aspect, the present disclosure provides an integrated substrate, such as Figure 1 As shown, the integrated substrate includes: a support layer 10, a first conductive layer 100 and a second conductive layer 200. The support layer 10 has a first connecting via 11 penetrating along the thickness direction thereof, and a first connecting electrode 12 arranged in the first connecting via 11. The first conductive layer 100 and the second conductive layer 200 are respectively arranged on two side surfaces of the support layer 10 that are oppositely arranged along the thickness direction thereof; the first conductive layer 100 is electrically connected to the second conductive layer 200 through the first connecting electrode 12.
[0071] It should be noted that the integrated substrate in the embodiment of the present disclosure may include passive devices such as inductors, capacitors, resistors, etc. integrated on the support layer 10. Among them, the first conductive layer 100 may include a first conductive structure 101, and the second conductive layer 200 may include a second conductive structure 201. The first conductive structure 101 is connected to the second conductive structure 201 through the first connecting electrode 12 to form a coil structure of the inductor. In this case, the inductor formed is a 3D stereoscopic inductor. Of course, the second conductive layer 200 may also include structures such as the first plate 202 of the capacitor, which will be specifically described in the following examples.
[0072] In some examples, the material of the support layer includes, but is not limited to, epoxy or polyimide.
[0073] The integrated substrate in the disclosed embodiment uses a plastic encapsulation material including epoxy resin or polyimide to replace the silicon or glass materials commonly used in the prior art as the supporting layer of the integrated substrate, which can solve the problem of wafer cracking caused by filling of glass through vias or silicon through vias due to the large differences in thermal conductivity and thermal expansion coefficient between metal and glass / silicon materials in the prior art. At the same time, the plastic encapsulation material is an insulator, the substrate loss is low, the process is simple, and the flexibility is high to adapt to larger deformations.
[0074] Exemplarily, the integrated substrate includes not only the support layer 10, the first conductive layer 100 and the second conductive layer 200, but also includes a first protective layer 30 covering the first conductive layer 100. The first conductive layer 100 includes a first conductive structure 101, the first protective layer 30 has a first concave pattern, and the first conductive structure 101 is filled in the first concave pattern. The first protective layer 30 can protect the first conductive structure 101 from being corroded by water and oxygen, and prevent harmful gases such as water and oxygen from penetrating into the integrated substrate, thereby causing damage to the device.
[0075] Exemplarily, the second conductive layer 200 includes a second conductive structure 201, and the first conductive structure 101 and the second conductive structure 201 are connected to form an inductor coil structure through a first connecting electrode 12; a first interlayer dielectric layer 5 is disposed on the side of the support layer away from the first conductive layer 100. The first interlayer dielectric layer 5 can serve as a cutoff layer of the second conductive layer 200, and plays a role in limiting the height of the second conductive layer 200.
[0076] Exemplarily, the second conductive layer 200 includes a first plate 202 of a capacitor, and a second interlayer dielectric layer 4 and a third conductive layer 300 are sequentially arranged on a side of the second conductive layer 200 away from the support layer, and the third conductive layer includes a second plate 301 of the capacitor.
[0077] In some examples, the integrated substrate includes a third interlayer dielectric layer 6 located on the side of the second conductive layer 200 away from the support layer, a first transfer structure 7 located on the side of the second conductive structure 201 away from the second conductive layer 200, and a second transfer structure 8 located on the side of the second plate of the capacitor away from the second conductive layer 200. The first transfer structure 7 is electrically connected to the second conductive structure 201 through a via penetrating the third interlayer dielectric layer 6, and the second transfer structure 8 is electrically connected to the second plate of the capacitor through a via penetrating the third interlayer dielectric layer 6. The first transfer structure 7 and the second transfer structure 8 can electrically connect the coil structure formed by connecting the first conductive structure 101 and the second conductive structure 201 through the first connecting electrode 12 to the connecting structure 20.
[0078] Exemplarily, the integrated substrate includes a fourth interlayer dielectric layer 9 disposed on the side of the first transfer structure 7 and the second transfer structure 8 away from the third interlayer dielectric layer 6, and a connection structure 20 disposed on the side of the fourth interlayer dielectric layer 9 away from the first transfer structure 7; wherein the connection structure 20 is connected to the first transfer structure 7 through a via hole penetrating the fourth interlayer dielectric layer 9. The connection structure 20 can realize electrical connection between the coil structure and the outside world.
[0079] In some examples, connection structures 20 include, but are not limited to, solder balls or copper pillars.
[0080] In a second aspect, the present disclosure also provides a method for preparing an integrated substrate, which can be used to prepare any of the above-mentioned integrated substrates. The method may include:
[0081] forming a first conductive layer 100;
[0082] forming a first connection electrode 12 on the first conductive layer 100;
[0083] A support layer 10 is formed on the first conductive layer 100 , wherein the support layer 10 has a first connection via hole 11 penetrating along a thickness direction thereof, and a first connection electrode 12 is disposed in the first connection via hole 11 ;
[0084] The second conductive layer 200 is formed on the side of the support layer 10 facing away from the first conductive layer 100 ; the first conductive layer 100 is electrically connected to the second conductive layer 200 via the first connection electrode 12 .
[0085] In the preparation method of the disclosed embodiment, a plastic encapsulation material including epoxy resin or polyimide is used to replace the silicon or glass material commonly used in the prior art as the support layer of the integrated substrate, which can solve the problem of wafer cracking caused by filling of glass through holes or silicon through holes due to the large difference in thermal conductivity and thermal expansion coefficient between metal and glass / silicon materials in the prior art. At the same time, the plastic encapsulation material is an insulator, the substrate loss is low, the process is simple, and the flexibility is high to adapt to large deformation. In addition, the process of plastic encapsulation through hole is relatively simple, and the first connection via with a high aspect ratio can be filled in multiple times, which reduces the difficulty of the electroplating filling process to a certain extent.
[0086] In order to make the preparation method of the embodiment of the present disclosure clearer, the following three examples are combined for explanation.
[0087] The first example: This example provides a preparation Figure 1 The method for preparing the integrated substrate shown in the figure may include the following steps:
[0088] S11, such as Figure 4aAs shown, a substrate 1 is provided, a first adhesive layer 2 is formed on the substrate 1, a first sub-protective layer 31 is formed on the side of the first adhesive layer 2 facing away from the substrate 1, a second sub-protective layer 32 is formed on the side of the first sub-protective layer 31 facing away from the substrate, the second sub-protective layer 32 includes a first opening penetrating along the thickness direction thereof, the first opening and the first sub-protective layer 31 define a first concave pattern, and the first sub-protective layer 31 and the second sub-protective layer 32 constitute a first protective layer 30. The first protective layer 30 can protect the first conductive structure 101 from being corroded by water and oxygen, and prevent harmful gases such as water and oxygen from penetrating into the integrated substrate to cause device damage.
[0089] S12, such as Figure 4b As shown, a first conductive layer 100 is formed, wherein the first conductive layer 100 includes a first conductive structure 101 .
[0090] In some examples, step S12 may specifically include:
[0091] S121 . Form a first conductive film as a first seed layer on a side of the second sub-protective layer 32 facing away from the substrate 1 . Electroplate the first seed layer to form a first conductive film layer.
[0092] S122 , processing the first conductive film layer by using a chemical mechanical polishing process, leaving only a portion of the first conductive film layer filled in the first concave pattern, to form a first conductive structure 101 .
[0093] Optionally, step S121 may specifically include:
[0094] A first conductive film is formed on the second sub-protection layer 32 by physical vapor deposition (PVD) as a first seed layer. The first seed layer is thickened by electroplating technology to form a first conductive film layer.
[0095] S13, such as Figure 4c As shown, the first connection electrode 12 is formed on the first conductive layer 100 .
[0096] Optionally, step S13 may specifically include:
[0097] A second conductive film is formed on the first conductive layer 100 by physical vapor deposition (PVD) as a second seed layer. A plating pattern is made by photolithography, and the second seed layer is thickened by electroplating to form the first connecting electrode 12. The second seed layer is removed by etching.
[0098] S14, such as Figure 4d As shown, a support layer 10 is formed on the first conductive layer 100 , and the support layer 10 has a first connection via hole 11 penetrating along the thickness direction thereof, and a first connection electrode 12 is disposed in the first connection via hole 11 .
[0099] Optionally, step S14 may specifically include:
[0100] The support layer 10 is obtained by using a lamination technique, and the support layer 10 is thinned by using a grinding technique to expose the first connection electrode 12 and then polished.
[0101] In some examples, the material of the support layer 10 includes epoxy resin or polyimide.
[0102] Using plastic encapsulation materials such as epoxy resin or polyimide instead of silicon or glass as the support layer of the integrated substrate can solve the problems of wafer cracking caused by filling of existing glass through vias or silicon through vias. At the same time, the plastic encapsulation material is an insulator, has low substrate loss, simple process, high flexibility and can adapt to larger deformation.
[0103] S15, such as Figure 4e As shown, the second conductive layer 200 is formed on the side of the support layer 10 facing away from the first conductive layer 100 ; the first conductive layer 100 is electrically connected to the second conductive layer 200 via the first connecting electrode 12 .
[0104] In some examples, step S15 may specifically include:
[0105] S151. Form a first interlayer dielectric layer 5 having a second opening on the side of the support layer 10 away from the first conductive layer 100 by means of photolithography technology. The second opening and the support layer 10 define a second concave pattern. Form a third conductive film as a third seed layer on the side of the first interlayer dielectric layer 5 away from the first conductive layer 100. Electroplate the third seed layer to form a third conductive film layer.
[0106] S152, the third conductive film layer is processed by chemical mechanical polishing process, leaving only the third conductive film layer portion filled in the second concave pattern, to form a second conductive structure 201 and a first electrode 202 of the capacitor; the second conductive structure 201 is electrically connected to the first connection electrode 12 through the first connection via 11.
[0107] Optionally, step S151 may specifically include:
[0108] A third conductive film is formed on the side of the first interlayer dielectric layer 5 away from the first conductive layer 100 by physical vapor deposition (PVD) as a third seed layer. The third seed layer is thickened by electroplating technology to form a third conductive film layer.
[0109] S16, such as Figure 4f As shown, a second interlayer dielectric layer 4 and a third conductive layer are formed on the side of the first electrode plate 202 of the capacitor away from the support layer 10 , and the third conductive layer includes the second electrode plate 301 of the capacitor.
[0110] Optionally, step S16 may specifically include:
[0111] A second interlayer dielectric layer 4 is formed on the side of the second conductive layer 200 away from the support layer 10 by physical vapor deposition (PVD) and chemical vapor deposition (CVD), and a third conductive layer is formed on the second interlayer dielectric layer 4 by physical vapor deposition (PVD).
[0112] S17, such as Figure 4g As shown, a third interlayer dielectric layer 6 having a third opening is formed on the side of the second conductive layer 200 away from the support layer 10 by using photolithography technology, and a first transfer structure 7 located on the side of the second conductive structure 201 away from the second conductive layer 200 and a second transfer structure 8 located on the side of the second plate 301 of the capacitor away from the second conductive layer 200 are formed. The first transfer structure 7 and the second transfer structure 8 can electrically connect the coil structure formed by connecting the first conductive structure 101 and the second conductive structure 201 through the first connecting electrode 12 to form an inductor with other structures.
[0113] Optionally, step S17 may specifically include:
[0114] A fourth conductive film is formed on the second conductive layer 200 and the third conductive layer by physical vapor deposition (PVD) as a fourth seed layer. A plating pattern is made by photolithography, and the fourth seed layer is thickened by electroplating to form a first transfer structure 7 and a second transfer structure 8. The fourth seed layer is removed by degumming and cleaning by etching.
[0115] S18, such as Figure 1 As shown, a fourth interlayer dielectric layer 9 having a fourth opening is formed on the side of the third interlayer dielectric layer 6 away from the support layer 10 by using photolithography technology. The first adhesive layer 2 and the substrate 1 are removed. A connection structure 20 is formed in the fourth opening. The connection structure 20 can realize electrical connection between the coil structure and the outside world.
[0116] In some examples, connection structures 20 include, but are not limited to, solder balls or copper pillars.
[0117] The second example: This example provides a preparation Figure 2 The method for preparing the integrated substrate shown in the figure may include the following steps:
[0118] S21, such as Figure 5a As shown, a substrate 1 is provided, a first adhesive layer 2 is formed on the substrate 1, and a first protective layer 30 is formed on the side of the first adhesive layer 2 facing away from the substrate 1. The first protective layer 30 can protect the first conductive structure 101 from being corroded by water and oxygen, and prevent harmful gases such as water and oxygen from penetrating into the integrated substrate to cause device damage.
[0119] S22, such as Figure 5bAs shown, a first conductive layer 100 is formed, wherein the first conductive layer 100 includes a first conductive structure 101 .
[0120] Optionally, step S22 may specifically include:
[0121] A fifth conductive film is formed on the first protective layer 30 by physical vapor deposition (PVD) as a fifth seed layer. A plating pattern is made by photolithography, and the fifth seed layer is thickened by electroplating to form the first conductive structure 101. The fifth seed layer is removed by etching.
[0122] S23, such as Figure 5c As shown, the first connection electrode 12 is formed on the first conductive layer 100 .
[0123] Optionally, step S23 may specifically include:
[0124] A sixth conductive film is formed on the first conductive layer 100 by physical vapor deposition (PVD) as a sixth seed layer. A plating pattern is made by photolithography, and the sixth seed layer is thickened by electroplating to form the first connection electrode 12. The sixth seed layer is removed by etching and cleaning.
[0125] S24, such as Figure 5d As shown, a support layer 10 is formed on the first conductive layer 100 , and the support layer 10 has a first connection via hole 11 penetrating along the thickness direction thereof, and a first connection electrode 12 is disposed in the first connection via hole 11 .
[0126] Optionally, step S24 may specifically include:
[0127] The support layer 10 is obtained by using a lamination technique, and the support layer 10 is thinned by using a grinding technique to expose the first connection electrode 12 and then polish it.
[0128] In some examples, the material of the support layer includes epoxy or polyimide.
[0129] Using plastic encapsulation materials such as epoxy resin or polyimide instead of silicon or glass as the support layer of the integrated substrate can solve the problems of wafer cracking caused by filling of existing glass through vias or silicon through vias. At the same time, the plastic encapsulation material is an insulator, has low substrate loss, simple process, high flexibility and can adapt to larger deformation.
[0130] S25, such as Figure 5e As shown, the second conductive layer 200 is formed on the side of the support layer 10 facing away from the first conductive layer 100 ; the first conductive layer 100 is electrically connected to the second conductive layer 200 via the first connecting electrode 12 .
[0131] In some examples, step S15 may specifically include:
[0132] S251. A first interlayer dielectric layer 5 having a fourth opening is formed on the side of the support layer 10 away from the first conductive layer 100 by using photolithography technology. The fifth opening and the support layer 10 define a third concave pattern. A seventh conductive film is formed on the side of the first interlayer dielectric layer 5 away from the first conductive layer 100 as a seventh seed layer. The seventh seed layer is electroplated to form a seventh conductive film layer.
[0133] S252, the seventh conductive film layer is processed by chemical mechanical polishing process, leaving only the seventh conductive film layer portion filled in the third concave pattern, to form a second conductive structure 201 and a first electrode 202 of the capacitor; the second conductive structure 201 is electrically connected to the first connection electrode 12 through the first connection via 11.
[0134] Optionally, step S251 may specifically include:
[0135] A seventh conductive film is formed on the side of the first interlayer dielectric layer 5 away from the first conductive layer 100 by physical vapor deposition (PVD) as a seventh seed layer. The seventh seed layer is thickened by electroplating technology to form a seventh conductive film layer.
[0136] S26, such as Figure 5f As shown, a second interlayer dielectric layer 4 and a third conductive layer are formed on the side of the first electrode plate 202 of the capacitor away from the support layer 10 , and the third conductive layer includes the second electrode plate 301 of the capacitor.
[0137] Optionally, step S16 may specifically include:
[0138] A second interlayer dielectric layer 4 is formed on the side of the second conductive layer 200 away from the support layer 10 by physical vapor deposition (PVD) and chemical vapor deposition (CVD), and a third conductive layer is formed on the second interlayer dielectric layer 4 by physical vapor deposition (PVD).
[0139] S27, such as Figure 5g As shown, a third interlayer dielectric layer 6 having a sixth opening is formed on the side of the second conductive layer 200 away from the support layer 10 by using photolithography technology, and a first transfer structure 7 located on the side of the second conductive structure 201 away from the second conductive layer 200 and a second transfer structure 8 located on the side of the second plate 301 of the capacitor away from the second conductive layer 200 are formed. The first transfer structure 7 and the second transfer structure 8 can electrically connect the coil structure formed by connecting the first conductive structure 101 and the second conductive structure 201 through the first connecting electrode 12 to form an inductor with other structures.
[0140] Optionally, step S27 may specifically include:
[0141] An eighth conductive film is formed on the second conductive layer 200 and the third conductive layer by physical vapor deposition (PVD) as an eighth seed layer. An electroplating pattern is made by photolithography, and the eighth seed layer is thickened by electroplating to form the first transfer structure 7 and the second transfer structure 8. The eighth seed layer is removed by degumming and cleaning by etching.
[0142] S28, such as Figure 2 As shown, a fourth interlayer dielectric layer 9 having a seventh opening is formed on the side of the third interlayer dielectric layer 6 away from the support layer 10 by using photolithography technology. The first adhesive layer 2 and the substrate 1 are removed. A connection structure 20 is formed in the seventh opening. The connection structure 20 can realize electrical connection between the coil structure and the outside world.
[0143] In some examples, connection structures 20 include, but are not limited to, solder balls or copper pillars.
[0144] The difference between the second example and the first example is that in the second example, the first conductive structure 101 is directly formed on the first protective layer 30 without forming the second sub-protective layer 32 , which can reduce the process steps and save the process cost.
[0145] The third example: This example provides a preparation Figure 3 The method for preparing the integrated substrate shown in the figure may include the following steps:
[0146] S31, such as Figure 6a As shown, a substrate 1 is provided, a first adhesive layer 2 is formed on the substrate 1, a first sub-protective layer 31 is formed on the side of the first adhesive layer 2 facing away from the substrate 1, a second sub-protective layer 32 is formed on the side of the first sub-protective layer 31 facing away from the substrate, the second sub-protective layer 32 includes a first opening penetrating along the thickness direction thereof, the first opening and the first sub-protective layer 31 define a first concave pattern, and the first sub-protective layer 31 and the second sub-protective layer 32 constitute a first protective layer 30. The first protective layer 30 can protect the first conductive structure 101 from being corroded by water and oxygen, and prevent harmful gases such as water and oxygen from penetrating into the integrated substrate to cause device damage.
[0147] S32, such as Figure 6b As shown, a first conductive layer 100 is formed, wherein the first conductive layer 100 includes a first conductive structure 101 .
[0148] In some examples, step S12 may specifically include:
[0149] S321 , forming a ninth conductive film as a ninth seed layer on the side of the second sub-protective layer 32 facing away from the substrate 1 , and electroplating the ninth seed layer to form a ninth conductive film layer.
[0150] S322 , the ninth conductive film layer is processed by a chemical mechanical polishing process, and only a portion of the ninth conductive film layer filled in the first concave pattern remains, thereby forming a first conductive structure 101 .
[0151] Optionally, step S321 may specifically include:
[0152] A ninth conductive film is formed on the second protective sublayer 32 by physical vapor deposition (PVD) as a ninth seed layer, and the ninth seed layer is thickened by electroplating technology to form a ninth conductive film layer.
[0153] S33, such as Figure 6c As shown, a support layer 10 is formed on the first conductive layer 100 , and the support layer 10 has a first connecting via 11 penetrating along a thickness direction thereof.
[0154] Optionally, step S33 may specifically include:
[0155] The support layer 10 is obtained by using a lamination technique, and a hole is opened on the support layer 10 by using a photolithography technique and an etching technique to obtain a first connecting via hole 11 .
[0156] In some examples, the material of the support layer includes epoxy or polyimide.
[0157] Using plastic encapsulation materials such as epoxy resin or polyimide instead of silicon or glass as the support layer of the integrated substrate can solve the problems of wafer cracking caused by filling of existing glass through vias or silicon through vias. At the same time, the plastic encapsulation material is an insulator, has low substrate loss, simple process, high flexibility and can adapt to larger deformation.
[0158] S34, such as Figure 6d As shown, a first connection electrode 12 is formed in the first connection via hole 11 of the support layer 10 .
[0159] Optionally, step S34 may specifically include:
[0160] A tenth conductive film is formed in the first connection via 11 by physical vapor deposition (PVD) as a tenth seed layer. A plating pattern is made by photolithography, and the tenth seed layer is thickened by electroplating to form the first connection electrode 12. The tenth seed layer is removed by etching and cleaning.
[0161] S35, such as Figure 6e As shown, the second conductive layer 200 is formed on the side of the support layer 10 facing away from the first conductive layer 100 ; the first conductive layer 100 is electrically connected to the second conductive layer 200 via the first connecting electrode 12 .
[0162] In some examples, step S15 may specifically include:
[0163] S351. Form a first interlayer dielectric layer 5 having an eighth opening on the side of the support layer 10 away from the first conductive layer 100 by means of photolithography technology, wherein the eighth opening and the support layer 10 define a fourth concave pattern; form an eleventh conductive film on the side of the first interlayer dielectric layer 5 away from the first conductive layer 100 as an eleventh sub-layer, and electroplate the eleventh sub-layer to form an eleventh conductive film layer.
[0164] S352, the eleventh conductive film layer is processed by chemical mechanical polishing process, leaving only the portion of the eleventh conductive film layer filled in the fourth concave pattern, forming a second conductive structure 201 and a first electrode 202 of the capacitor; the second conductive structure 201 is electrically connected to the first connection electrode 12 through the first connection via 11.
[0165] Optionally, step S351 may specifically include:
[0166] An eleventh conductive film is formed on the side of the first interlayer dielectric layer 5 away from the first conductive layer 100 by physical vapor deposition (PVD) as the eleventh sub-layer. The eleventh sub-layer is thickened by electroplating technology to form the eleventh conductive film layer.
[0167] S36, such as Figure 6f As shown, a second interlayer dielectric layer 4 and a third conductive layer are formed on the side of the first electrode plate 202 of the capacitor away from the support layer 10 , and the third conductive layer includes the second electrode plate 301 of the capacitor.
[0168] Optionally, step S36 may specifically include:
[0169] A second interlayer dielectric layer 4 is formed on the side of the second conductive layer 200 away from the support layer 10 by physical vapor deposition (PVD) and chemical vapor deposition (CVD), and a third conductive layer is formed on the second interlayer dielectric layer 4 by physical vapor deposition (PVD).
[0170] S37, such as Figure 6g As shown, a third interlayer dielectric layer 6 having a ninth opening is formed on the side of the second conductive layer 200 away from the support layer 10 by using photolithography technology, and a first transfer structure 7 located on the side of the second conductive structure 201 away from the second conductive layer 200 and a second transfer structure 8 located on the side of the second plate 301 of the capacitor away from the second conductive layer 200 are formed. The first transfer structure 7 and the second transfer structure 8 can electrically connect the coil structure formed by connecting the first conductive structure 101 and the second conductive structure 201 through the first connecting electrode 12 to form an inductor with other structures.
[0171] Optionally, step S37 may specifically include:
[0172] A twelfth conductive film is formed on the second conductive layer 200 and the third conductive layer by physical vapor deposition (PVD) as a twelfth seed layer. An electroplating pattern is made by photolithography, and the twelfth seed layer is thickened by electroplating to form a first transfer structure 7 and a second transfer structure 8. The twelfth seed layer is removed by etching and cleaning.
[0173] S38, such as Figure 3 As shown, a fourth interlayer dielectric layer 9 having a tenth opening is formed on the side of the third interlayer dielectric layer 6 away from the support layer 10 by using photolithography technology. The first adhesive layer 2 and the substrate 1 are removed. A connection structure 20 is formed in the tenth opening. The connection structure 20 can realize electrical connection between the coil structure and the outside world.
[0174] In some examples, connection structures 20 include, but are not limited to, solder balls or copper pillars.
[0175] The difference between the third example and the first example is that in the third example, a support material layer is formed on the first conductive layer 100, and the support material layer is processed to form a first connection via 11 that penetrates along the thickness direction thereof. The first connection electrode 12 is formed after the support layer 10 is formed, and the first connection electrode 12 penetrates the first connection via 11.
[0176] In a third aspect, an embodiment of the present disclosure provides an electronic device, which includes the integrated substrate in the above embodiment.
[0177] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and substance of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the present disclosure.
Claims
1. An integrated substrate, It is characterized in that include: A supporting layer, wherein the supporting layer has a first connecting via hole penetrating along a thickness direction thereof; The first conductive layer and the second conductive layer are respectively arranged on two opposite side surfaces of the support layer along the thickness direction thereof; The first connecting electrode is disposed in the first connecting via hole, and the first conductive layer is electrically connected to the second conductive layer through the first connecting electrode.
2. The integrated substrate according to claim 1, It is characterized in that The integrated substrate further includes a first protection layer covering the first conductive layer; the first conductive layer includes a first conductive structure; the first protection layer has a first concave pattern, and the first conductive structure is filled in the first concave pattern.
3. The integrated substrate according to claim 1, It is characterized in that The second conductive layer includes a second conductive structure, and the first conductive structure and the second conductive structure are connected via the first connecting electrode to form an inductor coil structure; a first interlayer dielectric layer is disposed on a side of the support layer away from the first conductive layer.
4. The integrated substrate according to claim 3, It is characterized in that The second conductive layer includes a first plate of the capacitor; a second interlayer dielectric layer and a third conductive layer are sequentially arranged on a side of the second conductive layer away from the support layer; and the third conductive layer includes a second plate of the capacitor.
5. The integrated substrate according to claim 4, It is characterized in that The integrated substrate further includes a third interlayer dielectric layer located on a side of the second conductive layer away from the support layer, a first transfer structure located on a side of the second conductive structure away from the second conductive layer, and a second transfer structure located on a side of the second plate of the capacitor away from the second conductive layer; wherein, The first transfer structure is electrically connected to the second conductive structure through a via hole penetrating the third interlayer dielectric layer, and the second transfer structure is electrically connected to the second plate of the capacitor through a via hole penetrating the third interlayer dielectric layer.
6. The integrated substrate according to claim 5, It is characterized in that It also includes a fourth interlayer dielectric layer disposed on a side of the first transfer structure and the second transfer structure away from the third interlayer dielectric layer, and a connection structure disposed on a side of the fourth interlayer dielectric layer away from the first transfer structure; wherein, The connection structure is connected to the first transfer structure through a via hole penetrating the fourth interlayer dielectric layer.
7. The integrated substrate according to claim 1, It is characterized in that The material of the support layer includes epoxy resin or polyimide.
8. A method for preparing an integrated substrate, include: forming a first conductive layer; forming a first connecting electrode on the first conductive layer; forming a supporting layer on the first conductive layer, wherein the supporting layer has a first connecting via hole penetrating along a thickness direction thereof, and the first connecting electrode is disposed in the first connecting via hole; A second conductive layer is formed on a side of the support layer away from the first conductive layer; the first conductive layer is electrically connected to the second conductive layer through the first connecting electrode.
9. The method for preparing an integrated substrate according to claim 8, It is characterized in that Before forming the first conductive layer, the method further comprises: providing a substrate; forming a first adhesive layer on the substrate; forming a first sub-protective layer on a side of the first adhesive layer facing away from the substrate; A second sub-protective layer is formed on a side of the first sub-protective layer facing away from the substrate, the second sub-protective layer includes a first opening penetrating along a thickness direction thereof, the first opening and the first sub-protective layer define a first concave pattern, and the first sub-protective layer and the second sub-protective layer constitute a first protective layer; the first conductive structure of the first conductive layer is filled in the first concave pattern; After forming the second conductive layer, the method further includes removing the first adhesive layer and the substrate.
10. The method for preparing an integrated substrate according to claim 9, It is characterized in that The step of forming the first conductive layer comprises: forming a first conductive film on a side of the second sub-protection layer facing away from the substrate as a first seed layer, and electroplating the first seed layer to form a first conductive film layer; The first conductive film layer is processed by a chemical mechanical polishing process, and only the first conductive film layer portion filled in the first concave pattern remains, thereby forming the first conductive structure.
11. The method for preparing an integrated substrate according to claim 8, It is characterized in that Before forming the first conductive layer, the method further comprises: providing a substrate; forming a first adhesive layer on the substrate; forming a first protective layer on a side of the first adhesive layer away from the substrate; the first conductive structure is located on a side of the first protective layer away from the substrate; After forming the second conductive layer, the method further includes removing the first adhesive layer and the substrate.
12. The method for preparing an integrated substrate according to claim 8, It is characterized in that The support layer is formed by using a lamination technique after the first connecting electrode is formed.
13. The method for preparing an integrated substrate according to claim 8, It is characterized in that The steps of forming the support layer include: forming a support material layer on the first conductive layer, and processing the support material layer to form a first connecting via hole penetrating along the thickness direction of the support material layer; The first connection electrode is formed after the support layer is formed, and the first connection electrode passes through the first connection via hole.
14. The method for preparing an integrated substrate according to claim 8, It is characterized in that The material of the support layer includes epoxy resin or polyimide.
15. An electronic device, in, Comprising the integrated substrate as claimed in any one of claims 1 to 7.