Stacked electronic package

Abstract

The invention relates to a stacked electronic package. An electronic device package including cavities that may be inflated, evacuated, or filled with another material may be formed by stacking a plurality of circuit substrates ("carriers") bonded together by interposers disposed between pairs of circuit substrates such that one or more cavities are formed between adjacent carriers. The interposer may include interconnects that may electrically couple devices or other structures on or within a first carrier to devices or structures on or within another carrier, including contacts formed on an outer surface of the package.

Description

Technical Field

[0001] Embodiments of the subject matter described herein relate to packaging for electronic devices that include multiple circuit boards or other substrates. Background Art

[0002] Electronic devices such as integrated circuits are often packaged in polymer or ceramic housings that can be designed to protect the device from damage, help dissipate heat, and provide macroscopic contacts that allow the device to be coupled to other devices on printed circuit boards and other substrates. In some applications, it is desirable to provide a hollow or air-filled cavity within the package to accommodate high-frequency components. Summary of the invention

[0003] According to a first aspect of the present invention, there is provided an assembly comprising:

[0004] a first circuit substrate having a top surface and a bottom surface;

[0005] a second circuit substrate having a top surface and a bottom surface, wherein the second circuit substrate is disposed above the first circuit substrate and the bottom surface of the second circuit substrate faces the top surface of the first circuit substrate;

[0006] a first interposer substrate disposed between the first circuit substrate and the second circuit substrate to mechanically couple the first circuit substrate to the second circuit substrate;

[0007] wherein a first electronic component is mechanically bonded and electrically coupled to the top surface of the first circuit substrate or the bottom surface of the second circuit substrate; and

[0008] Wherein the first interposer substrate, the top surface of the first circuit substrate, and the bottom surface of the second circuit substrate jointly define a cavity between the first circuit substrate and the second circuit substrate.

[0009] In one or more embodiments, the first interposer substrate includes an electrical interconnect that electrically couples the first circuit substrate to the second circuit substrate.

[0010] In one or more embodiments, the assembly further comprises:

[0011] a conductive shielding structure configured to shield the first electronic component from electromagnetic interference, or to shield components outside the conductive shielding structure from electromagnetic interference generated within the shielding structure;

[0012] wherein the shielding structure is at least partially formed by a first portion disposed on or within the first circuit substrate and a second portion disposed on or within the second circuit substrate; and

[0013] Wherein the first portion of the shield structure is directly electrically coupled to the second portion of the shield structure through the electrical interconnect of the first interposer substrate.

[0014] In one or more embodiments, the assembly further comprises:

[0015] a third circuit substrate having a top surface and a bottom surface, wherein the third circuit substrate is disposed above the second circuit substrate and the bottom surface of the third circuit substrate faces the top surface of the second circuit substrate; and

[0016] a second interposer substrate disposed between the second circuit substrate and the third circuit substrate to mechanically couple the third circuit substrate to the second circuit substrate;

[0017] wherein the first interposer substrate includes an electrical interconnect coupling the first circuit substrate to the second circuit substrate;

[0018] wherein the second interposer substrate includes an electrical interconnect coupling the second circuit substrate to the third circuit substrate; and

[0019] The first circuit substrate is electrically coupled to the third circuit substrate via the electrical interconnections of the first interposer substrate and the second interposer substrate.

[0020] In one or more embodiments, the assembly further comprises:

[0021] a thermally conductive heat sink formed within the first circuit substrate, the thermally conductive heat sink extending from the top surface of the first circuit substrate to the bottom surface of the first circuit substrate;

[0022] Wherein the first electronic component disposed on the top surface of the first circuit substrate or a different electronic component disposed on the top surface of the first circuit substrate is directly thermally coupled to the heat sink at the top surface of the first circuit substrate.

[0023] In one or more embodiments, the assembly further comprises:

[0024] a first set of electrical contacts disposed on a circuit substrate spaced apart from the first circuit substrate;

[0025] Wherein the first set of electrical contacts includes electrical contacts coupled to one or more electronic components within the assembly.

[0026] In one or more embodiments, the first circuit substrate is coupled to the first interposer substrate via metal pins that mate with corresponding sockets;

[0027] The metal pins protrude from a surface of the first interposer substrate, and the corresponding sockets are recessed sockets formed in the first circuit substrate; or

[0028] The metal pins protrude from a surface of the first circuit substrate, and the corresponding sockets are recessed sockets formed in the first interposer substrate.

[0029] In one or more embodiments, the first electronic component is mechanically bonded and electrically coupled to the top surface of the first circuit substrate;

[0030] And a second electronic component is mechanically bonded and electrically coupled to the bottom surface of the second circuit substrate.

[0031] In one or more embodiments, the cavity is filled with a volume of polymeric molding material.

[0032] In one or more embodiments, the outer edge of the assembly is encapsulated within a volume of polymeric molding material.

[0033] According to a second aspect of the present invention, there is provided a method of forming an assembly, the method comprising:

[0034] receiving a first circuit substrate having a top surface and a bottom surface;

[0035] receiving a second circuit substrate having a top surface and a bottom surface; and

[0036] coupling the first circuit substrate to the second circuit substrate by coupling a first interposer substrate between the first circuit substrate and the second circuit substrate, the first interposer substrate mechanically coupling the first circuit substrate to the second circuit substrate;

[0037] wherein the second circuit substrate is disposed above and coupled to the first circuit substrate, and the bottom surface of the second circuit substrate faces the top surface of the first circuit substrate;

[0038] wherein a first electronic component is mechanically bonded and electrically coupled to the top surface of the first circuit substrate or the bottom surface of the second circuit substrate; and

[0039] Wherein the first interposer substrate, the top surface of the first circuit substrate, and the bottom surface of the second circuit substrate jointly define a cavity between the first circuit substrate and the second circuit substrate.

[0040] In one or more embodiments, the first interposer substrate includes an electrical interconnect that electrically couples the first circuit substrate to the second circuit substrate.

[0041] In one or more embodiments, the method further comprises:

[0042] forming a conductive shielding structure configured to shield the first electronic component from electromagnetic interference, or to shield components external to the conductive shielding structure from electromagnetic interference generated within the shielding structure;

[0043] wherein the shielding structure is at least partially formed by a first portion disposed on or within the first circuit substrate and a second portion disposed on or within the second circuit substrate; and

[0044] Wherein the first portion of the shield structure is directly electrically coupled to the second portion of the shield structure through the electrical interconnect of the first interposer substrate.

[0045] In one or more embodiments, the method further comprises:

[0046] placing a third circuit substrate over the second circuit substrate, the third circuit substrate having a top surface and a bottom surface, wherein the bottom surface of the third circuit substrate faces the top surface of the second circuit substrate; and

[0047] placing a second interposer substrate between the second circuit substrate and the third circuit substrate, the second interposer substrate mechanically coupling the third circuit substrate to the second circuit substrate;

[0048] wherein the first interposer substrate includes an electrical interconnect coupling the first circuit substrate to the second circuit substrate;

[0049] wherein the second interposer substrate includes an electrical interconnect coupling the second circuit substrate to the third circuit substrate; and

[0050] The first circuit substrate is electrically coupled to the third circuit substrate via the electrical interconnections of the first interposer substrate and the second interposer substrate.

[0051] In one or more embodiments, the first circuit substrate includes a thermally conductive heat sink formed within the first circuit substrate, the thermally conductive heat sink extending from the top surface of the first circuit substrate to the bottom surface of the first circuit substrate; and

[0052] The first electronic component disposed on the top surface of the first circuit substrate or a different electronic component disposed on the top surface of the first circuit substrate is directly thermally coupled to the heat sink at the top surface of the first circuit substrate.

[0053] In one or more embodiments, the method further comprises:

[0054] A first set of electrical contacts is disposed on a circuit substrate spaced apart from the first circuit substrate; and

[0055] The first set of electrical contacts includes electrical contacts that couple to one or more electronic components within the assembly.

[0056] In one or more embodiments, the first circuit substrate is coupled to the first interposer substrate via metal pins that mate with corresponding sockets;

[0057] The metal pins protrude from a surface of the first interposer substrate, and the corresponding sockets are recessed sockets formed in the first circuit substrate; or

[0058] The metal pins protrude from a surface of the first circuit substrate, and the corresponding sockets are recessed sockets formed in the first interposer substrate.

[0059] In one or more embodiments, the first electronic component is mechanically bonded and electrically coupled to the top surface of the first circuit substrate;

[0060] And a second electronic component is mechanically bonded and electrically coupled to the bottom surface of the second circuit substrate.

[0061] In one or more embodiments, the cavity is filled with a volume of polymeric molding material.

[0062] In one or more embodiments, the outer edge of the assembly is encapsulated within a volume of polymeric molding material.

[0063] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] The present disclosure is illustrated by way of examples, embodiments, etc. and is not limited by the accompanying drawings, in which the same reference numerals indicate similar elements. For simplicity and clarity, the elements in the drawings are shown and are not necessarily drawn to scale. The drawings are incorporated with the detailed description and form a part of the specification and are used to further illustrate the examples, embodiments, etc., and to explain various principles and advantages according to the present disclosure, wherein:

[0065] Figure 1is a partially exploded cross-sectional view of a multi-level circuit assembly according to one or more embodiments.

[0066] Figure 2 After the individual circuit carrier substrates ("carriers") have been coupled to each other via an interposer substrate ("interposer") Figure 1 Cross-sectional view of the assembly.

[0067] Figure 3 is a partially exploded cross-section of another example assembly illustrating an embodiment in which carriers engage one another via an interposer via a system of mating pins and sockets.

[0068] Figure 4 is a cross-sectional view of another example assembly illustrating features of one or more embodiments.

[0069] Figure 5 is a cross-sectional view of another example assembly illustrating features of one or more embodiments.

[0070] Figure 6 is a partial cross-sectional view illustrating features of one or more embodiments. DETAILED DESCRIPTION

[0071] The following detailed description provides examples for the purpose of understanding and is not intended to limit the invention or the application and use of the invention. In addition, it is not intended to be bound by any express or implied theory presented in the foregoing technical field, background technology or the following detailed description.

[0072] For simplicity and clarity of explanation, the drawings show the general construction mode, and the description and details of well-known features and technologies may be omitted so as not to unnecessarily obscure the present invention. In addition, the elements in the drawings are not necessarily drawn to scale. For example, the sizes of some elements or regions in the drawings may be exaggerated relative to other elements or regions to help improve the understanding of the embodiments of the present invention.

[0073] The terms "first", "second", "third", "fourth", etc. (if any) in the description and claims may be used to distinguish similar elements and are not necessarily used to describe a specific sequence or time order. It should be understood that the terms used in this way are interchangeable in appropriate circumstances, so that the embodiments of the present invention described herein can, for example, operate in a sequence other than that shown or otherwise described herein. In addition, the terms "including", "having" and any variants thereof are intended to cover non-exclusive inclusions, so that a process, method, article or device including a series of elements is not necessarily limited to those elements, but may include other elements that are not explicitly listed or inherent to such processes, methods, articles or devices. The term "coupled" as used herein is defined as being connected directly or indirectly in an electrical or non-electrical manner. As used herein, the terms "substantially" and "substantially" mean sufficient to achieve the stated purpose in a practicable manner, and minor defects (if any) are not important for the stated purpose.

[0074] Unless otherwise stated, directional references such as “top”, “bottom”, “left”, “right”, “above”, “below”, etc. are not intended to require any preferred orientation, but are made for illustrative purposes with reference to the orientation of the corresponding figure or figures.

[0075] Unless expressly stated otherwise, the use of the terms "substantially," "generally," and similar terms with respect to the size, relative positioning, or orientation of various features indicates that the size, positioning, or orientation of those features is subject to tolerances of the equipment and processes selected to form the described features and / or expected process variations. Unless expressly stated otherwise, the use of the terms "substantially," "substantially," and similar terms with respect to measurable values ​​or characteristics is subject to the expected measurement accuracy of the equipment and methods used to measure those values ​​or characteristics and / or is within tolerance limits specified by technical standards applicable to the technology being described.

[0076] It should be understood that the steps of the various processes described herein are non-limiting examples of suitable processes according to embodiments and are for illustrative purposes. The embodiments herein may use any suitable process, including processes that omit the steps described herein, perform those steps in a different order, and similar steps, etc. It should also be understood that well-known features and techniques may be omitted for clarity.

[0077] Conventional techniques for packaging and encapsulating electronic devices include methods where components are stacked on top of each other or otherwise occupy multiple levels. However, such methods typically involve bonding one or more discrete monolithic devices or packaged devices to a substrate or directly to another monolithic device or packaged device, which can have disadvantages. As an example, when radio frequency (RF), microwave (MW), and millimeter wave (mmWave) devices and / or associated components coupled to these devices are surrounded by dielectric materials such as polymer molding materials, the performance of these devices may be impaired due to signal losses caused by attenuation of high frequency signals due to absorption within the dielectric.

[0078] Thus, benefits of embodiments herein may include the realization of a multi-level electronic device assembly with a gas-filled or vacuum-evacuated cavity above a sensitive component. A stacked assembly according to one or more embodiments may have any suitable number of levels, and devices on different levels may be isolated or interconnected as desired with the aid of an interposer substrate, which may include interconnects between layers and may also form part of a metal shielding structure suitable for isolating selected layers or devices from electromagnetic interference.

[0079] Along these lines, Figure 1 1 is a partially exploded cross-sectional view of an example assembly 100 according to one or more embodiments. Assembly 100 is formed of three discrete circuit carrier substrates, which may also be referred to as circuit substrates and / or carriers (carriers 120; e.g., polymer-based printed circuit boards, ceramic-based circuit boards, etc., represented by carriers 120A, 120B, and 120C as non-limiting examples). It should be appreciated that assembly 100 is a non-limiting example, and embodiments herein may include any suitable number of carriers and be made of any suitable material and include any number and type of suitable devices. Each carrier 120 has a bottom surface 121 (e.g., bottom surfaces 121A, 121B, and 121C of respective carriers 120A, 120B, and 120C) and a top surface 122 (e.g., top surfaces 122A, 122B, and 122C of respective carriers 120A, 120B, and 120C).

[0080] Each carrier 120 may include active and passive electronic devices on its bottom surface 121, its top surface 122, or both surfaces. Each carrier 120 may include conductive interconnects 115 disposed within the carrier and on its top and bottom surfaces. As shown, the interconnects 115 may include metallized pads on the bottom surface 121 and / or the top surface 122 of the carrier 120, and the electronic devices (which may include active devices, passive devices, or both in any suitable arrangement) may be coupled to such pads to the interconnects 115 using any suitable method. As an example, the electronic devices 102 (e.g., semiconductor device dies) are shown as being wire-bonded to the interconnects 115 at the top surface 122A of the carrier 120A and to the interconnects 115 at the bottom surface 121B of the carrier 120B. As another example, passive components 106 (e.g., discrete resistors, capacitors, inductors, etc.) are shown as metal contacts having interconnects bonded to top surface 122A of carrier 120A, bottom surface 121B of carrier 120B, and bottom surface 121C of carrier 120C. As another example, electronic device 107 is depicted as metal pillars having interconnects 115 bonded to top surface 122B of carrier 120B and bottom surface 121C of carrier 120C.

[0081] The carriers 120 are mechanically coupled to each other in a stacked arrangement by means of interposer substrates or "interposers" (e.g., interposer 150A and interposer 150B). The interposer substrate 150 may include electrical interconnects 155 and bond or otherwise mechanically couple between adjacent carriers 120. The interposer 150 may be bonded to the carriers 120 via solder bump bonding to contact pads (i.e., interconnects 115 at the surface of the carriers 120), solder reflow, epoxy bonding, and / or any other suitable method. In one or more embodiments, a first carrier (e.g., one of the carriers 120) is also electrically coupled to one or more other such carriers in an assembly (e.g., assembly 100) via interconnects (e.g., interconnects 155) within an interposer (e.g., interposer 150). In other words, an interconnect (e.g., interconnect 115), an electronic component (e.g., component or electronic device 102, 106, or 107), or other features on or within a first carrier are electrically coupled to one or more interconnects, electronic components, or other features on or within other carriers.

[0082] It should be understood that when two or more carriers (e.g., carrier 120) are mechanically coupled to each other via an interposer (e.g., interposer 150), a connection may be formed between the two carriers (e.g., between carrier 120A and carrier 120B, or between carrier 120B and carrier 120C; see Figure 2The cavity 295A and cavity 295B in the carrier 120 form a cavity. In one or more embodiments, this cavity is hollow or inflated (e.g., filled with air or an inert gas). This hollow or inflated cavity may be desirable for certain applications. For example, compared to other packaging methods that fill the space between adjacent stacked circuit layers with polymer materials, etc., if radio frequency (RF), microwave (MW), millimeter wave (mmWave) or other high-frequency electrical signals propagate in the cavity or along a surface surrounded by the cavity (e.g., along a waveguide formed on the surface of the carrier 120), signal attenuation can be minimized. In addition, compared to other methods of sealing a single circuit substrate in a capped package to produce a hollow or inflated cavity, the embodiments of the present invention allow such cavities to be incorporated into a high-density package with multiple circuit layers (e.g., multiple carriers 120). In addition, assemblies such as assembly 100 may include multiple hollow or inflated cavities.

[0083] It should be understood that Figure 1 The assembly 100 depicted and other assemblies depicted herein are for illustrative purposes and may show elements omitted in certain embodiments, or show elements not present, and may add or omit elements simply to provide illustrative examples. Along these lines, in the embodiments described herein, the interconnects (e.g., interconnects 115 and interconnects 155) may be arranged in any suitable manner. For example, Figure 1 As shown, interconnects 115 can be arranged on the surface of a carrier and within the carrier to connect electronic devices to other devices on the same surface, or to devices or external contact pads on the opposite surface of the same carrier. Interconnects within the interposer (e.g., interconnects 155 within interposer 150) can be used to form electrical connections between different carriers. For example, in Figure 1 , various interconnects 115 and 155 are coupled to each other so that there is a continuous conductive path from discrete carrier 120A to one of solder bumps 195 on top surface 122C of carrier 120C. Alternatively, some connections between the carrier substrate and the interposer may serve only as mechanical connections.

[0084] like Figure 1 As shown, the carrier may include additional structures, such as a heat sink (e.g., a thermally conductive heat sink 135 forming part of the carrier 120A, which may be referred to as a "bump"). The assembly 100 also includes a set of external contacts (depicted as solder bumps 195 on the top surface 122C of the carrier 120C). It will be appreciated that these features allow the assembly 100 to be mounted to a circuit board or other substrate via the solder bumps 195, and also coupled to another heat sink assembly (such as a heat sink assembly) via the heat sink 135 in a so-called top-side cooling arrangement. Figure 2 depicted).

[0085] It should be understood that for illustrative purposes, the interposer 150 and similar interposers described herein may be described as a single-piece substrate, but other arrangements are possible. Thus, in one or more embodiments, one or more interposers (e.g., one or more interposers 150) are composed of a substrate having a plurality of substrates as described above. Figure 1 and / or in combination with other related interposers described herein. Also, in one or more embodiments, one or more interposers are formed of individual segments that are not mechanically connected to each other or joined together by another material, such as a polymer, prior to being incorporated into an assembly, such as assembly 100. As a non-limiting example, an interposer, such as interposer 150, may include a plurality of discrete "bricks" that are bonded to a carrier, such as carrier 120, at different locations (e.g., around the outer perimeter of the carrier).

[0086] Figure 2 is a cross-sectional view of the assembly 100 after the carriers 120 have been coupled to each other via the interposer 150. It should be understood that the combination Figure 1 The elements described and similar elements may not be combined Figure 2 Individually label or describe. Figure 2 As shown in , the interposer (e.g., interposer 150) and the carrier (e.g., discrete carrier 120) according to embodiments herein may be configured such that one or more completely enclosed cavities (e.g., cavity 295A between carrier 120A and carrier 120B, or cavity 295B between carrier 120B and carrier 120C) are formed. Figure 2 As shown, when the example assembly 100 is relative to its Figure 1 When the orientation is “flipped” in FIG. 1 , the example assembly 100 can be coupled to a larger circuit board or other substrate (eg, substrate 298) via solder bumps 195 on the top surface 122C of the carrier 120C. Figure 2 In the depicted arrangement, heat sink 135 may be coupled to another heat sink (eg, heat sink 299).

[0087] like Figure 2 As shown, in one or more embodiments, an assembly such as assembly 100 has one or more outer edges encapsulated within a polymeric material such as molding material 275 as shown. It should be understood that in such embodiments, any suitable arrangement of such molding material may be used. For example, in one or more embodiments, molding material is present at the edges of one or more interposers (e.g., one or more interposers 150), but not at the edges of one or more other interposers. Similarly, in one or more embodiments, molding material is present at the edges of one or more carriers (e.g., one or more interposers 120), but not at the edges of one or more other carriers.

[0088] Figure 3 is a partially exploded cross-section of another example assembly to illustrate an embodiment in which carriers engage each other via an interposer via a system of mating pins and sockets. It should be understood that elements and similar elements described in connection with the previous figures may not be combined Figure 3 Individually labeled or described. Assembly 300 includes carrier 320A and carrier 350B joined by interposer 350. In this example, carrier 320A includes a metallized socket 326 extending into carrier 320A at top surface 322A. Socket 326 is configured to receive a corresponding metallized pin. Interposer 350 includes interconnect 355 (related to interconnect 155 of interposer 150), which has pins 357 disposed on one surface, which are configured to mate with corresponding sockets (e.g., socket 326 of carrier 320A). Interconnect 355 also includes a metallized socket 356 configured to mate with a corresponding pin on an opposing surface of interposer 350. In this example, carrier 320B includes pins 327 on its bottom surface 321B (optionally coupled to interconnects 315 on and / or within carrier 320B) that are configured to mate with sockets 356 of interposer 350. It should be appreciated that in one or more embodiments, sockets such as sockets 326 or 356 are configured only as mechanical connection points, while in one or more other embodiments, such sockets are configured to serve as both mechanical and electrical connection points. In some embodiments, pins and / or sockets that do not make electrical connections may not be metallized.

[0089] It should be appreciated that in embodiments including an interposer such as interposer 350 or a related interposer, the pins and sockets may be arranged in any suitable manner. For example, an interposer may have sockets on only two surfaces, and the corresponding pins may be disposed on a carrier. Alternatively, a carrier (e.g., carrier 320) and / or an interposer (e.g., interposer 350) may have both sockets (e.g., sockets 326 or 356) and pins (e.g., pins 327 or 357) distributed in any suitable arrangement on one or both of the top and bottom surfaces.

[0090] Figure 4 is a cross-sectional view of another example assembly showing features of one or more embodiments. It should be understood that elements described in conjunction with the previous figures may not be combined Figure 4Individually labeled or described. Assembly 400 includes a first carrier 420A that is mechanically and electrically coupled to a second carrier 420B via an interposer 450. Similar to carrier 120A of example assembly 100, carrier 420A includes a thermally conductive heat sink 432 (e.g., a "coin block" or heat sink 135). Heat sink 435 is also conductive (i.e., metallic) and is coupled to interconnects 415 within carrier 420A that span the width of carrier 420A to either side of heat sink 435. These interconnects 415, in turn, are electrically coupled to one or more interconnects 415 within carrier 420B via interconnects 455 of interposer 450 and form a continuous conductive path that surrounds cavity 495 formed between carrier 420A and carrier 420B. The interconnect 415 and the heat sink 435 may extend through the thickness of the carriers 420A, 420B and the interposer 450 (ie, along a direction perpendicular to the Figure 4 The conductive enclosure may be formed in a direction of the cross-sectional plane depicted) to create a continuous conductive enclosure that may shield components within cavity 495 (and / or components within carrier 420A, carrier 420B, components on top surface 422A of carrier 420A, and / or components on bottom surface 421B of carrier 420B) from electromagnetic interference. Similarly, devices outside cavity 495 may be shielded from electromagnetic interference originating from devices within cavity 495. It should be appreciated that an electromagnetic shielding cavity such as cavity 495 may be formed between any two carriers in a stacked assembly of two or more carriers (e.g., carriers 120, 320, or 420).

[0091] Figure 5 is a cross-sectional view of another example assembly showing features of one or more embodiments. It should be understood that elements and similar elements described in conjunction with the previous figures may not be combined Figure 5 Individually labeled or described. Assembly 500 includes a first carrier 520A, a second carrier 520B, and a third carrier 520C. Carrier 520A is bonded to carrier 520B through interposer 550A, thereby forming cavity 595A, and carrier 520B is bonded to carrier 520C through interposer 550B, thereby forming cavity 595B. In one or more embodiments, as shown in assembly 500, the cavity between two carriers (e.g., cavity 595B as shown, cavity 595A, or similar cavity) is filled with a certain volume of polymeric molding material. It should be understood that it is not intended herein to require that a specific cavity between two carriers be filled with molding material, or to require that any specific number of cavities in an assembly of two or more carriers be filled with molding material, and according to embodiments of the present invention, any number of cavities may be filled or unfilled with molding material.

[0092] Figure 6It is a partial cross-sectional view showing features of one or more embodiments. It should be understood that elements and similar elements described in conjunction with previous figures may not be combined Figure 6 Individually label or describe. Figure 6 As shown in , assemblies according to embodiments herein can be manufactured using known techniques for large-scale manufacturing and assembly of devices that employ circuit carrier substrates associated with the carriers described herein. Such techniques include so-called panel-level manufacturing techniques, in which many carriers are manufactured simultaneously as part of a larger "panel" substrate. After manufacturing, the panel can be singulated into individual carriers either before or after filling the carriers with devices (e.g., via solder reflow or other suitable techniques).

[0093] like Figure 6 As shown, three panels can be assembled and then singulated to form two identical assemblies: assembly 600(1) and assembly 600(2). Panel 620A includes carrier 620A(1) and carrier 620A(2). The two carriers of panel 620A are identical, but it should be understood that all carriers (or other structures) that form part of a single panel are not required to be identical. Similarly, panel 620B includes two identical carriers 620B(1) and 620B(2). Panels 620A and 620B can be joined as indicated by panel 650A including two identical interposers 650A(1) and 650A(2) to form panel assembly 600 including two identical assemblies 600(1) and 600(2). It should be understood that although panel assembly 600 includes two panels, panel assemblies according to embodiments herein and assemblies according to embodiments herein can be formed using panels of any suitable size and arrangement of carriers and / or interposers.

[0094] In an example assembly process, each panel may be populated with a device prior to assembling a panel assembly such as panel assembly 600 as indicated. The panels may also be populated in any suitable order. For example, a bottom surface 621B of a panel such as panel 620B may be populated, followed by a top surface of the panel (e.g., top surface 622B of panel 620B) before or after the panel is joined to another panel such as panel 620A via an interposer panel such as panel 650A.

[0095] It should be appreciated that the stacked carrier architecture described herein can have various advantages when combined with a panel level manufacturing method. As an example, a panel level assembly including a metal shield structure (e.g., as combined with Figure 4The assembly 400 of FIG. 400 may be manufactured and assembled in large quantities and then singulated into individual assemblies including both electromagnetic shielding cavities and hollow cavities (e.g., cavity 495), whereas such large-scale assemblies may be economically unattractive for metal packages that include metallized cavities and require a metal cover to be bonded to each cavity. In addition, devices requiring such shielding and / or hollow or gas-filled cavities may be more easily interconnected and stacked than conventional methods of assembling devices into individual shielding and / or hollow packages.

[0096] Various examples

[0097] Features of the embodiments may be understood with the aid of one or more of the following examples:

[0098] Example 1: An apparatus or method includes: a first circuit substrate having a top surface and a bottom surface; a second circuit substrate having a top surface and a bottom surface; and a first interposer substrate disposed between the first circuit substrate and the second circuit substrate. The second circuit substrate is disposed above the first circuit substrate, and the bottom surface of the second circuit substrate faces the top surface of the first circuit substrate. The first interposer substrate is disposed between the first circuit substrate and the second circuit substrate, mechanically coupling the first circuit substrate to the second circuit substrate. A first electronic component is mechanically bonded and electrically coupled to the top surface of the first circuit substrate or the bottom surface of the second circuit substrate. The interposer substrate, the top surface of the first circuit substrate, and the bottom surface of the second circuit substrate jointly define a cavity between the first circuit substrate and the second circuit substrate.

[0099] Example 2: The apparatus or method of Example 1, wherein the first interposer substrate includes an electrical interconnect electrically coupling the first circuit substrate to the second circuit substrate.

[0100] Example 3: The device or method according to Example 1 or Example 2 further includes a conductive shielding structure. The shielding structure is configured to shield the first electronic component from electromagnetic interference, or to shield components outside the conductive shielding structure from electromagnetic interference generated within the shielding structure. The shielding structure is at least partially formed by a first portion disposed on or in the first circuit substrate and a second portion disposed on or in the second circuit substrate. The first portion of the shielding structure is directly electrically coupled to the second portion of the shielding structure through the electrical interconnect of the first interposer substrate.

[0101] Example 4: The device or method according to any one of Examples 1 to 3, further comprising a third circuit substrate having a top surface and a bottom surface; and a second interposer substrate disposed between the second circuit substrate and the third circuit substrate. The third circuit substrate is disposed above the second circuit substrate, and the bottom surface of the third circuit substrate faces the top surface of the second circuit substrate. The second interposer substrate is disposed between the second circuit substrate and the third circuit substrate, and mechanically couples the third circuit substrate to the second circuit substrate. The first interposer substrate includes an electrical interconnect that couples the first circuit substrate to the second circuit substrate. The second interposer substrate includes an electrical interconnect that couples the second circuit substrate to the third circuit substrate. The first circuit substrate is electrically coupled to the third circuit substrate via the electrical interconnects of the first interposer substrate and the second interposer substrate.

[0102] Example 5: The device or method according to any one of Examples 1 to 4, further comprising a heat conductive heat sink formed in the first circuit substrate, extending from the top surface of the first circuit substrate to the bottom surface of the first circuit substrate. The first electronic component disposed on the top surface of the first circuit substrate or a different electronic component disposed on the top surface of the first circuit substrate is directly thermally coupled to the heat sink at the top surface of the first circuit substrate.

[0103] Example 6: The device or method of any one of Examples 1 to 5, further comprising a first set of electrical contacts disposed on a circuit substrate spaced apart from the first circuit substrate. The first set of electrical contacts includes electrical contacts coupled to one or more electronic components within the assembly.

[0104] Example 7: The device or method of any one of Examples 1 to 6, wherein the first circuit substrate is coupled to the first interposer substrate via a metal pin that mates with a corresponding socket. The metal pin protrudes from a surface of the first interposer substrate, and the corresponding socket is a recessed socket formed in the first circuit substrate. The metal pin protrudes from a surface of the first circuit substrate, and the corresponding socket is a recessed socket formed in the first interposer substrate.

[0105] Example 8: An apparatus or method according to any one of Examples 1 to 7, wherein the first electronic component is mechanically bonded and electrically coupled to the top surface of the first circuit substrate; and the second electronic component is mechanically bonded and electrically coupled to the bottom surface of the second circuit substrate.

[0106] Example 9: The device or method of any one of Examples 1 to 8, wherein the cavity is filled with a volume of polymeric molding material.

[0107] Example 10: The device or method of any of Examples 1 to 9, wherein an outer edge of the device is encapsulated within a volume of polymeric molding material.

[0108] The foregoing detailed description and examples are merely illustrative in nature and are not intended to limit the embodiments of the subject matter or the application and use of such embodiments. As used herein, the word "exemplary" means "serving as an example, instance, or illustration". Any embodiment described herein as exemplary is not necessarily to be construed as being preferred or advantageous over other embodiments. In addition, it is not intended to be bound by any express or implied theory presented in the foregoing technical field, background technology, or detailed description.

[0109] It should be understood that the application of the present invention is not limited to the details of the construction and arrangement of the components set forth in the foregoing description or shown in the accompanying drawings. The present invention can have other embodiments and can be practiced or implemented in various ways. In addition, it should be understood that the words and terms used herein are for the purpose of description and should not be considered as restrictive. The use of "including" or "having" and its variations herein is intended to cover the items listed thereafter and their equivalents and other items. Unless otherwise specified or limited, the terms "install", "connect", "support" and "couple" and their variations are used in a broad sense and cover direct and indirect installation, connection, support and coupling. In addition, "connect" and "couple" are not limited to physical or mechanical connections or couplings.

[0110] The previous discussion is presented to enable those skilled in the art to make and use embodiments of the present invention. Various modifications to the illustrated embodiments will be apparent to those skilled in the art, and the general principles herein may be applied to other embodiments and applications without departing from embodiments of the present invention. Therefore, embodiments of the present invention are not intended to be limited to the embodiments shown, but should be given the widest scope consistent with the principles and features disclosed herein. The previous detailed description should be read with reference to the drawings, in which similar elements in different figures have similar reference numerals. The drawings are not necessarily drawn to scale, and the drawings depict selected embodiments, and do not wish to limit the scope of embodiments of the present invention. It will be appreciated by those skilled in the art that the examples provided herein have many useful alternatives and fall within the scope of embodiments of the present invention.

[0111] The connecting lines shown in the various figures contained herein are intended to represent exemplary functional relationships and / or physical couplings between the various elements. It should be noted that many alternative or additional functional relationships or physical connections may be present in one or more embodiments of the subject matter. In addition, certain terms may also be used herein for reference purposes only, and therefore do not wish to be restrictive, and unless the context clearly indicates, the terms "first", "second" and other such numerical terms referring to structures do not imply a certain sequence or order.

[0112] The above description refers to elements or nodes or features being "connected" or "coupled" together. As used herein, unless otherwise expressly stated, "connected" means that one element is directly joined to another element (or is directly communicated with another element), and not necessarily mechanically. Similarly, unless otherwise expressly stated, "coupled" means that one element is directly or indirectly joined to another element (or is directly or indirectly electrically communicated with another element or otherwise communicated), and not necessarily mechanically. Therefore, although the schematic diagrams shown in the figures depict an exemplary arrangement of elements, additional intermediate elements, devices, features, or components may be present in one or more embodiments of the depicted subject matter.

Claims

1. An assembly, characterized in that: include: a first circuit substrate having a top surface and a bottom surface; a second circuit substrate having a top surface and a bottom surface, wherein the second circuit substrate is disposed above the first circuit substrate and the bottom surface of the second circuit substrate faces the top surface of the first circuit substrate; a first interposer substrate disposed between the first circuit substrate and the second circuit substrate to mechanically couple the first circuit substrate to the second circuit substrate; wherein a first electronic component is mechanically bonded and electrically coupled to the top surface of the first circuit substrate or the bottom surface of the second circuit substrate; and Wherein the first interposer substrate, the top surface of the first circuit substrate, and the bottom surface of the second circuit substrate jointly define a cavity between the first circuit substrate and the second circuit substrate.

2. The assembly according to claim 1, characterized in that The first interposer substrate includes electrical interconnects that electrically couple the first circuit substrate to the second circuit substrate.

3. The assembly according to claim 2, characterized in that Also includes: a conductive shielding structure configured to shield the first electronic component from electromagnetic interference, or to shield components outside the conductive shielding structure from electromagnetic interference generated within the shielding structure; wherein the shielding structure is at least partially formed by a first portion disposed on or within the first circuit substrate and a second portion disposed on or within the second circuit substrate; and Wherein the first portion of the shield structure is directly electrically coupled to the second portion of the shield structure through the electrical interconnect of the first interposer substrate.

4. The assembly according to claim 1, characterized in that Also includes: a third circuit substrate having a top surface and a bottom surface, wherein the third circuit substrate is disposed above the second circuit substrate and the bottom surface of the third circuit substrate faces the top surface of the second circuit substrate; as well as a second interposer substrate disposed between the second circuit substrate and the third circuit substrate to mechanically couple the third circuit substrate to the second circuit substrate; wherein the first interposer substrate includes an electrical interconnect coupling the first circuit substrate to the second circuit substrate; wherein the second interposer substrate includes electrical interconnects coupling the second circuit substrate to the third circuit substrate; and The first circuit substrate is electrically coupled to the third circuit substrate via the electrical interconnections of the first interposer substrate and the second interposer substrate.

5. The assembly according to claim 1, characterized in that Also includes: a thermally conductive heat sink formed within the first circuit substrate, the thermally conductive heat sink extending from the top surface of the first circuit substrate to the bottom surface of the first circuit substrate; Wherein the first electronic component disposed on the top surface of the first circuit substrate or a different electronic component disposed on the top surface of the first circuit substrate is directly thermally coupled to the heat sink at the top surface of the first circuit substrate.

6. The assembly according to claim 1, characterized in that The first circuit substrate is coupled to the first interposer substrate via metal pins that mate with corresponding sockets; The metal pins protrude from a surface of the first interposer substrate, and the corresponding sockets are recessed sockets formed in the first circuit substrate; or The metal pins protrude from a surface of the first circuit substrate, and the corresponding sockets are recessed sockets formed in the first interposer substrate.

7. The assembly according to claim 1, characterized in that the first electronic component being mechanically bonded and electrically coupled to the top surface of the first circuit substrate; And a second electronic component is mechanically bonded and electrically coupled to the bottom surface of the second circuit substrate.

8. The assembly according to claim 1, characterized in that The cavity is filled with a volume of polymeric molding material.

9. The assembly according to claim 1, characterized in that The outer edges of the assembly are encapsulated within a volume of polymeric molding material.

10. A method of forming an assembly, characterized in that The method comprises: receiving a first circuit substrate having a top surface and a bottom surface; receiving a second circuit substrate having a top surface and a bottom surface; and coupling the first circuit substrate to the second circuit substrate by coupling a first interposer substrate between the first circuit substrate and the second circuit substrate, the first interposer substrate mechanically coupling the first circuit substrate to the second circuit substrate; wherein the second circuit substrate is disposed above and coupled to the first circuit substrate, and the bottom surface of the second circuit substrate faces the top surface of the first circuit substrate; wherein a first electronic component is mechanically bonded and electrically coupled to the top surface of the first circuit substrate or the bottom surface of the second circuit substrate; and Wherein the first interposer substrate, the top surface of the first circuit substrate, and the bottom surface of the second circuit substrate jointly define a cavity between the first circuit substrate and the second circuit substrate.

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