Stacked film and prepreg substrate in isolation package

Abstract

The invention relates to a build-up film and a prepreg substrate in an isolation package. In an example, a semiconductor package (100) includes a substrate (102) including a build-up film isolation layer (122) and a first prepreg layer (118) and a second prepreg layer (120) contacting opposing lateral sides of the build-up film isolation layer, the first prepreg layer including a first metallization (124), the second prepreg layer including a second metallization (124), and the first prepreg layer including a second metallization (124). And the second prepreg layer comprises a second metallization (128) that is not in physical contact with the first metallization. The package also includes solder mask layers (152, 154) on top and bottom surfaces of the substrate, a first semiconductor die (104) coupled to the first metallization, and a second semiconductor die (106) coupled to the second metallization, the first semiconductor die and the second semiconductor die are configured to operate in separate voltage domains. The package also includes a molding compound (116) covering the substrate and the first semiconductor die and the second semiconductor die.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 601,702, filed on November 21, 2023, entitled “HYBRIDABF-PREPREG ISO-ETS,” and is hereby incorporated by reference in its entirety. Technical Field

[0003] The present disclosure relates to the field of semiconductors. Background Art

[0004] A semiconductor wafer is a circular piece of semiconductor material, such as silicon, used to make semiconductor chips. In general, complex manufacturing processes are used to form many integrated circuits on a single wafer. Forming such circuits on a wafer is called manufacturing. After wafer manufacturing, the wafer is cut into multiple pieces, called semiconductor dies, where each die contains one of the circuits. Cutting or sawing the wafer into individual dies is called singulation. Subsequently, the individual dies can be coupled to a substrate or die pad. Subsequently, the resulting structure is covered with a molding compound to produce a package. Summary of the invention

[0005] In an example, a semiconductor package includes a substrate, the substrate includes a buildup film isolation layer and a first prepreg layer and a second prepreg layer contacting opposite lateral sides of the buildup film isolation layer, the first prepreg layer includes a first metallization, and the second prepreg layer includes a second metallization that is not in physical contact with the first metallization. The package also includes solder mask layers on the top and bottom surfaces of the substrate, a first semiconductor die coupled to the first metallization, and a second semiconductor die coupled to the second metallization, the first semiconductor die and the second semiconductor die being configured to operate in independent voltage domains. The package also includes a molding compound covering the substrate and the first semiconductor die and the second semiconductor die.

[0006] In an example, a method for manufacturing a semiconductor package includes forming two or more layers of a substrate by iteratively performing the following operations: plating a metal layer, applying a buildup film to the metal layer using a first mask, applying a first prepreg to the metal layer on a first lateral side of the buildup film, and applying a second prepreg to the metal layer on a second lateral side of the buildup film, the second lateral side being opposite to the first lateral side. The method includes applying a solder mask layer to the substrate, coupling a first semiconductor die and a second semiconductor die to the substrate, the first semiconductor die and the second semiconductor die being configured to operate in independent voltage domains, and covering the substrate and the first semiconductor die and the second semiconductor die with a molding compound. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A are cross-sectional views of semiconductor packages having a build-up film (BUF) and a prepreg substrate according to various examples.

[0008] Figure 1B is a top view of a semiconductor package with a BUF and a prepreg substrate according to various examples.

[0009] Figure 1C is a perspective view of a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0010] Figure 2 is a flow chart of a method for manufacturing a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0011] Figure 3A Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0012] Figure 3B Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0013] Figure 4A Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0014] Figure 4B Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0015] Figure 5A Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0016] Figure 5B Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0017] Fig. 6A Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0018] Figure 6B Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0019] Fig. 7A Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0020] Figure 7B Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0021] Fig. 8A Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0022] Figure 8B Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0023] Fig. 9A Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0024] Fig. 9B Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0025] Fig. 10A Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0026] Fig. 10B Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0027] Fig.11A Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0028] Fig. 11BDepicts steps in a process flow for manufacturing a semiconductor package with a BUF and a prepreg substrate according to various examples.

[0029] Fig. 12A Depicts steps in a process flow for manufacturing a semiconductor package with a BUF and a prepreg substrate according to various examples.

[0030] Fig. 12B Depicts steps in a process flow for manufacturing a semiconductor package with a BUF and a prepreg substrate according to various examples.

[0031] Fig.13A Depicts steps in a process flow for manufacturing a semiconductor package with a BUF and a prepreg substrate according to various examples.

[0032] Fig. 13B Depicts steps in a process flow for manufacturing a semiconductor package with a BUF and a prepreg substrate according to various examples.

[0033] Fig.14A Depicts steps in a process flow for manufacturing a semiconductor package with a BUF and a prepreg substrate according to various examples.

[0034] Fig. 14B Depicts steps in a process flow for manufacturing a semiconductor package with a BUF and a prepreg substrate according to various examples.

[0035] Fig.15A Depicts steps in a process flow for manufacturing a semiconductor package with a BUF and a prepreg substrate according to various examples.

[0036] Fig. 15B Depicts steps in a process flow for manufacturing a semiconductor package with a BUF and a prepreg substrate according to various examples.

[0037] Fig.16A Depicts steps in a process flow for manufacturing a semiconductor package with a BUF and a prepreg substrate according to various examples.

[0038] Fig. 16B Depicts steps in a process flow for manufacturing a semiconductor package with a BUF and a prepreg substrate according to various examples.

[0039] Fig.17A Depicts steps in a process flow for manufacturing a semiconductor package with a BUF and a prepreg substrate according to various examples.

[0040] Fig. 17B Depicts steps in a process flow for manufacturing a semiconductor package with a BUF and a prepreg substrate according to various examples.

[0041] Fig.18A Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0042] Fig.18B Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0043] Fig.19A Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0044] Fig.19B Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0045] Fig. 20A Depicted are steps in a process flow for fabricating a semiconductor package with a BUF and a prepreg substrate according to various examples.

[0046] Fig. 20B Depicted are steps in a process flow for fabricating a semiconductor package with a BUF and a prepreg substrate according to various examples.

[0047] Fig.21A Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0048] Fig.21B Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0049] Fig.22A Depicted are steps in a process flow for fabricating a semiconductor package with a BUF and a prepreg substrate according to various examples.

[0050] Fig. 22B Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0051] Fig.23A Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0052] Fig. 23B Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0053] Fig.24ADepicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0054] Fig. 24B Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0055] Fig.25A Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0056] Fig.25B Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0057] Fig.26A Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0058] Fig.26B Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0059] Fig.27A Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0060] Fig.27B Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0061] Fig.28A Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0062] Fig.28B Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0063] Fig.29A Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0064] Fig.29B Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0065] Fig. 30A Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0066] Fig. 30B Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0067] Fig.31A Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0068] Fig.31B Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0069] Fig.32A Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0070] Fig.32B Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0071] Fig.33A Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0072] Fig.33B Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0073] Fig.34A Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0074] Fig.34B Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0075] Fig.35A Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0076] Fig.35B Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0077] Fig.36A Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0078] Fig.36BDepicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0079] Fig.37A Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0080] Fig.37B Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0081] Fig.38A Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0082] Fig.38B Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0083] Fig.39A Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0084] Fig.39B Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0085] Fig.40A Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0086] Fig.40B Depicted are steps in a process flow for fabricating a semiconductor package having a BUF and a prepreg substrate according to various examples.

[0087] Fig.41 is a block diagram of an electronic device including a semiconductor package having a BUF and a prepreg substrate according to various examples. DETAILED DESCRIPTION

[0088] The technical challenge of semiconductor packaging substrates containing built-up films (BUFs) such as Ajinomoto built-up films (ABFs) is the risk of mechanical failure, especially cracking and delamination of the BUF layer. This is an important issue for isolation devices built with substrates in which the BUF acts as a dielectric material. The BUF layer is susceptible to mechanical stresses, especially during thermal cycles or high strain conditions typical in semiconductor packaging processes. Over time, these stresses may cause the BUF to crack or separate from the underlying layer, resulting in delamination. This compromises the mechanical integrity of the package, resulting in package reliability issues. In these cases, any cracking or delamination in the dielectric layer will compromise the isolation and structural strength of the package, ultimately affecting the overall performance and durability of the device.

[0089] In contrast, prepreg materials (pre-impregnated composite fibers) used in packaging substrates, such as in embedded trace substrates (ETS), present a different set of problems. Although prepregs are widely used as insulation and bonding materials, the isolation properties of prepregs are not sufficient for certain applications, particularly in high voltage or high frequency devices. Prepregs lack the dielectric properties necessary to provide adequate isolation between conductive layers or traces within a packaging substrate. This is because the glass fiber fabric of the prepreg efficiently transports charge. As a result, devices that rely on prepregs for isolation may suffer from electrical breakdown or leakage, thereby impairing the ability of the device to function in high stress environments. Therefore, the use of prepregs in these substrates requires additional design considerations or complementary materials to meet isolation standards, making them less than ideal for applications where robust electrical isolation is critical.

[0090] This specification presents various examples of semiconductor packages, which alleviate the technical challenges described above by including a package substrate comprising a combined stacked film and a prepreg layer. Specifically, the stacked film layer is positioned in an isolation region between metallizations for two different voltage domains. For example, the isolation region may include a pair of physically separated coils covered by a stacked film layer. The remainder of the substrate, including metallizations for two different voltage domains, is covered by a prepreg layer. The stacked film layer provides excellent isolation properties in the isolation region, where such properties are useful, because the stacked film layer contains non-charge transport polymer particles instead of charge transport glass fiber fabrics of prepregs. In addition, the prepreg layer provides excellent mechanical stability in the non-isolated region of the substrate, where such stability is useful. In this way, the relative strengths of the stacked film and the prepreg are utilized while minimizing the shortcomings of the stacked film and the prepreg. In some examples, the semiconductor package includes a substrate, the substrate including a first metallization, a second metallization, a first coil and a second coil. The first metallization and the first coil are in a first voltage domain, and the second metallization and the second coil are in a second voltage domain. The first metallization is covered by the first prepreg layer, and the second metallization is covered by the second prepreg layer. The first coil and the second coil are covered by the buildup film isolation layer. The example package also includes a first solder mask layer contacting the top surface of the first prepreg layer and the second prepreg layer and the top surface of the buildup film isolation layer, and a second solder mask layer contacting the bottom surface of the first prepreg layer and the second prepreg layer and the bottom surface of the buildup film isolation layer. The example package further includes a first semiconductor die coupled to the first metallization and the first coil, a second semiconductor die coupled to the second metallization and the second coil, and a molding compound contacting the first semiconductor die and the second semiconductor die and the first solder mask.

[0091] Figure 1A is a cross-sectional view of a semiconductor package 100 having a build-up film (BUF) and a prepreg substrate according to various examples. Figure 1B is a top view of a semiconductor package 100 having a BUF and a prepreg substrate according to various examples. Figure 1C is a perspective view of a semiconductor package 100 having a BUF and a prepreg substrate according to various embodiments. Figures 1A-1C. Example semiconductor package 100 includes substrate 102, semiconductor die 104, and semiconductor die 106. Semiconductor die 104 can be coupled to substrate 102 via pillars 108 (e.g., copper pillars) and solder members 110. Semiconductor die 106 can be coupled to substrate 102 via pillars 112 (e.g., copper pillars) and solder members 114. Molding compound 116 covers semiconductor die 104, 106, pillars 108, 112, and various structures within substrate 102. In an example, semiconductor die 104, 106 are configured to operate in independent voltage domains. Therefore, semiconductor package 100 can be referred to as an isolated package or an isolated device.

[0092] Because semiconductor package 100 is an isolation device, substrate 102 that facilitates such isolation between independent voltage domains may be referred to as an isolation substrate. In an example, substrate 102 includes prepreg layer 118, prepreg layer 120, and build-up film (BUF) isolation layer 122 between prepreg layer 118 and prepreg layer 120. Prepreg layer 118 may physically contact a lateral surface of BUF isolation layer 122, and prepreg layer 120 may physically contact a different lateral surface of BUF isolation layer 122 opposite to the surface contacting prepreg layer 118. Prepreg layer 118 may include metallization 124 and prepreg material 126. Prepreg layer 120 may include metallization 128 and prepreg material 130. BUF isolation layer 122 may include metallization 132 and build-up film (BUF) 134.

[0093] In an example, the metallization 124 includes a metal layer 136, a metal layer 138, and a via 140 extending between and coupling the metal layers 136 and 138. In an example, one or more of the metal layers 136, 138, and the via 140 include copper. In an example, one or more of the metal layers 136, 138, and the via 140 are optionally plated with a suitable metal or alloy, such as nickel, gold, tin, and / or palladium. The metallization 128 may include a metal layer 142, a metal layer 144, and a via 146 extending between and coupling the metal layers 142 and 144. In an example, one or more of the metal layers 142, 144, and the via 146 include copper. In an example, one or more of the metal layers 142, 144, and the via 146 are optionally plated with a suitable metal or alloy, such as nickel, gold, tin, and / or palladium.

[0094] In an example, metallization 132 includes coil 148 and coil 150. Coils 148, 150 are physically separated from each other, meaning that coils 148, 150 do not physically contact each other. Coils 148, 150 may include copper or another suitable metal or alloy, and may optionally be plated with a suitable metal or alloy, such as nickel, gold, tin, and / or palladium. Although in Figure 1A148, 150 are shown, but in some examples, three or more coils may be included. For example, a pair of coils may be coupled to each other through one or more vias, and a third coil may be co-located with the pair of coils within the BUF isolation layer 122, but may be physically separated from the pair of coils.

[0095] Prepreg materials 126, 130 can be prepregs of any suitable type that can be used to achieve the specific operational goals described herein. Prepreg materials are useful because of their bonding properties, dielectric properties and mechanical properties. The prepreg materials have low dielectric constants (Dk) and low loss tangents (Df). Prepregs provide bonding strength for the bonding between conductive layers, thereby reducing the possibility of delamination under mechanical stress or thermal stress. Prepreg materials also have considerable mechanical strength due to their glass fiber reinforcement, so that they can withstand bending, warping and other stresses during manufacture and use. The thermal stability of prepreg materials is supported by high glass transition temperatures (Tg) and low coefficient of thermal expansion (CTE), which helps to maintain structural integrity during thermal cycles. In addition, prepreg materials provide moisture resistance, which helps to maintain electrical insulation under humid conditions. In addition, the prepreg thickness can be accurately controlled during lamination, thereby allowing strict tolerances in multi-layer semiconductor packaging. The prepreg materials 126, 130 may include a variety of materials, including resins and glass fibers, which may individually or synergistically provide the various benefits of the prepreg materials described herein. The composition of the prepreg materials 126, 130 is 36%-77% glass fibers by weight, wherein excursions outside of this range are unfavorable because mechanical and electrical properties will be significantly and negatively affected.

[0096] BUF 134 may be any suitable deposited film, such as 134 is a 3D-type laminated film (ABF). BUF 134 has properties that contribute to its electrical isolation capabilities. For example, BUF 134 has a relatively low dielectric constant (Dk), which reduces signal delay and crosstalk between circuit traces, helping to maintain signal integrity. The dielectric constant of BUF 134 is between 3.2 and 3.4 at 5.8 GHz, where excursions outside this range are disadvantageous because mechanical and electrical properties will be significantly and negatively affected. BUF 134 also has a relatively low dissipation factor (Df), which minimizes energy loss as heat, thereby reducing signal attenuation. The thermal stability of BUF 134 enables it to withstand heat generated during operation and manufacturing processes, thereby maintaining the electrical properties of BUF 134 over time. BUF 134 has a coefficient of thermal expansion (CTE) in the range of 20 parts per million per Kelvin (ppm / K) to 39 ppm / K, where excursions outside this range are disadvantageous because mechanical and electrical properties will be significantly and negatively affected. In addition, the high insulation resistance of BUF 134 prevents leakage current, thereby maintaining the separation between the conductive layers. BUF 134 also has anti-hygroscopic properties, which helps maintain consistent electrical performance under different environmental conditions. BUF 134 may include epoxy resin, inorganic filler and curing agent. In the example, BUF 134 does not include glass fiber, because the specific combination of glass fiber and epoxy resin in prepreg material 126, 130 provides excellent mechanical properties for prepreg material 126, 130, but also provides poor isolation capability, and because in the case of BUF 134, excellent isolation capability (relative to prepreg material 126, 130) is critical.

[0097] To achieve adequate isolation, the minimum lateral distance between the third metallization 132 in the BUF isolation layer 122 and the interface between the BUF isolation layer 122 and the closest prepreg layers 118, 120 is at least 100 microns. Lateral distances below this range may result in unacceptably poor isolation.

[0098] One or more of the posts 108 may be coupled to the metal layer 138 via the solder member 110. Similarly, one or more of the posts 108 may be coupled to the coil 150 via the solder member 110. One or more of the posts 112 may be coupled to the metal layer 144 via the solder member 114. Similarly, one or more of the posts 112 may be coupled to the coil 148 via the solder member 114.

[0099] The solder mask layer 152 may cover at least some of the top surfaces of the substrate 102, such as the top surfaces of the prepreg layers 118, 120 and the top surface of the BUF isolation layer 122. Similarly, the solder mask layer 154 may cover at least some of the bottom surfaces of the substrate 102, such as the bottom surfaces of the prepreg layers 118, 120 and the bottom surface of the BUF isolation layer 122. The solder mask layers 152, 154 may provide insulating properties and protective properties (e.g., from solder and residue) that are beneficial to the substrate 102.

[0100] The substrate 102 may be an embedded trace substrate (ETS). An ETS is a multilayer structure in which copper traces are embedded within an insulating layer of the substrate, rather than patterned on the surface. In such examples, during the manufacturing process, the copper traces are buried between layers of insulating material such as epoxy or build-up film. The substrate comprises alternating layers of conductive traces and dielectric materials laminated together. The embedding of the traces allows precise control of the thickness and placement of the wiring, and the entire structure supports fine pitch connections, thereby enabling dense interconnect wiring between different components of a semiconductor device. Perforated vias or laser-drilled microvias connect the embedded traces to the outer layers of the substrate, thereby facilitating electrical connections to other components such as integrated circuits or solder bumps.

[0101] In operation, semiconductor die 104, 106 operate in independent voltage domains. Because semiconductor die 104 is coupled to metallization 124 in prepreg layer 118, prepreg layer 118 and metallization 124 belong to semiconductor die 104 and operate in the same voltage domain as semiconductor die 104. Because semiconductor die 106 is coupled to metallization 128 in prepreg layer 120, prepreg layer 120 and metallization 128 belong to semiconductor die 106 and operate in the same voltage domain as semiconductor die 106. In addition, coil 150 is coupled to semiconductor die 104, so coil 150 operates in the same voltage domain as semiconductor die 104. Similarly, coil 148 is coupled to semiconductor die 106, so coil 148 operates in the same voltage domain as semiconductor die 106. Independent voltage domains can interact with each other through electromagnetic coupling of coils 148, 150. The BUF 134 provides sufficient isolation for the metallization 132 (eg, coils 148 , 150 ), while the remainder of the substrate 102 comprises prepregs (eg, prepregs 126 , 130 ) that provide mechanical stability and mitigate the risks described above, such as delamination, cracking, etc.

[0102] Figure 2 is a flow chart of a method 200 for fabricating a semiconductor package (eg, semiconductor package 100 ) having a BUF and a prepreg substrate according to various examples. Figure 3A-40Bis a process flow for manufacturing a semiconductor package (eg, semiconductor package 100 ) having a BUF and a prepreg substrate according to various examples.

[0103] The method 200 may include patterning 202 a dry film mask. Figure 3A is a cross-sectional view of a carrier core 300. A barrier layer 302 contacts the carrier core 300. A seed layer 304 (eg, copper) contacts the barrier layer 302. Figure 3B yes Figure 3A Top view of the structure. Figure 4A yes Figure 3A 4. A cross-sectional view of the structure of FIG. 4, except that a dry film mask 400 has been applied and patterned on the seed layer 304. Figure 4B yes Figure 4A Top view of the structure.

[0104] The method 200 may include plating 204 a metal layer using a dry film mask. Figure 5A yes Figure 4A , except that a metal layer 500 (eg, copper) has been plated in the gaps of the dry film mask 400. This metal layer 500 may correspond to Figure 1A metal layer 136 , metal layer 142 and coil 148 . Figure 5B yes Figure 5A Top view of the structure.

[0105] The method 200 may include removing (206) the dry film mask and applying (208) the dry film mask over areas not covered by the BUF laminate. Fig. 6A yes Figure 5A A cross-sectional view of the structure, except Figure 5A The dry film mask has been removed, as depicted by numeral 600 . Figure 6B yes Fig. 6A Top view of the structure. Fig. 7A yes Fig. 6A 7 is a cross-sectional view of the structure of FIG. 1 , except that a dry film mask 700 is applied to the areas not covered by the BUF laminate. Figure 7B yes Fig. 7A Top view of the structure.

[0106] The method 200 may include laminating ( 210 ) with BUF, and removing ( 212 ) the dry film mask. Fig. 8A yes Fig. 7A 8, except that BUF 800 has been applied to the areas not covered by dry film mask 700. Figure 8B yes Fig. 8A Top view of the structure. Fig. 9A yes Fig. 8A, except that the dry film mask 700 has been removed, as indicated by numeral 900 . Fig. 9B yes Fig. 9A Top view of the structure.

[0107] The method 200 may include thinning (214) the BUF and applying (216) a dry film mask on areas not covered by the prepreg laminate. Fig. 10A yes Fig. 9A 1000 , except that BUF 800 has been thinned to produce BUF 1000 . For example, BUF 800 may be thinned to the same thickness as metal layer 500 . Fig. 10B yes Fig. 10A Top view of the structure. Fig.11A yes Fig. 10A 1 , except that a dry film mask 1100 has been applied to the areas not covered by the prepreg laminate. Fig. 11B yes Fig.11A Top view of the structure.

[0108] The method 200 may include laminating ( 218 ) with a prepreg, removing ( 220 ) a dry film mask, and thinning ( 222 ) the prepreg layers. Fig. 12A yes Fig.11A 1 is a cross-sectional view of the structure, except that a prepreg layer 1200 is applied. Fig. 12B yes Fig. 12A Top view of the structure. Fig.13A yes Fig. 12A A cross-sectional view of the structure of FIG. 1 , except that the dry film mask 1100 is removed, as indicated by numeral 1300 . Fig. 13B yes Fig.13A Top view of the structure. Fig.14A yes Fig.13A 14 is a cross-sectional view of a structure of BUF 1000, except that prepreg layer 1200 is thinned, as indicated by numeral 1400. For example, prepreg layer 1200 may be thinned to have the same thickness as BUF 1000. Fig. 14B yes Fig.14A Top view of the structure.

[0109] Method 200 may include determining whether to form (224) additional metal layers. If so, steps 202-224 are repeated until all metal layers to be formed have been formed. In the example process flow described, two additional metal layers are formed. Specifically, Fig.15A yes Fig.14A 15. A cross-sectional view of the structure of FIG. 15, except that a dry film mask 1500 is applied and patterned. Fig. 15B yes Fig.15A Top view of the structure. Fig.16A yes Fig.15A140 , 146 , portions of coil 148 , except that metal components 1600 (eg, vias 140 , 146 , portions of coil 148 ) are plated using dry film mask 1500 . Fig. 16B yes Fig.16A Top view of the structure. Fig.17A yes Fig.16A A cross-sectional view of the structure of FIG. 1 , except that the dry film mask 1500 is removed, as indicated by numeral 1700 . Fig. 17B yes Fig.17A Top view of the structure. Fig.18A yes Fig.17A A cross-sectional view of the structure of FIG. 1 , except that a dry film mask 1800 is applied to the areas not covered by the BUF. Fig.18B yes Fig.18A Top view of the structure. Fig.19A yes Fig.18A A cross-sectional view of the structure, except that an additional BUF 1900 is applied to the existing BUF. Fig.19B yes Fig.19A Top view of the structure. Fig. 20A yes Fig.19A A cross-sectional view of the structure of FIG. 1 , except that the dry film mask 1800 is removed, as indicated by numeral 2000 . Fig. 20B yes Fig. 20A Top view of the structure.

[0110] Fig.21A yes Fig. 20A 1900 is thinned to a thickness matching that of metal component 1600 to produce BUF 2100. Fig.21B yes Fig.21A Top view of the structure. Fig.22A yes Fig.21A 2100, except that a dry film mask 2200 is applied to the BUF 2100. Fig. 22B yes Fig.22A Top view of the structure.

[0111] Fig.23A yes Fig.22A A cross-sectional view of the structure of , except that additional prepreg 2300 is applied to the areas not covered by the dry film mask 2200, as shown. Fig. 23B yes Fig.23A Top view of the structure. Fig.24A yes Fig.23A A cross-sectional view of the structure of FIG. 220 , except that the dry film mask 2200 is removed, as indicated by numeral 2400 . Fig. 24B yes Fig.24A Top view of the structure.

[0112] Fig.25A yes Fig.24A 2300 is thinned to the thickness of BUF 2100 to produce prepreg layer 2500. Fig.25B yes Fig.25A Top view of the structure.

[0113] Fig.26A yes Fig.25A A cross-sectional view of the structure of , except that a dry film mask 2600 is applied and patterned. Fig.26B yes Fig.26A Top view of the structure.

[0114] Fig.27A yes Fig.26A , except that a metal layer 2700 is plated using a dry film mask 2600. The metal layer 2700 may correspond to Figure 1A The metal layers 138, 144 and the coil 150 in. Fig.27B yes Fig.27A Top view of the structure.

[0115] Fig.28A yes Fig.27A A cross-sectional view of the structure of FIG. 28 , except that the dry film mask 2600 is removed, as indicated by numeral 2800 . Fig.28B yes Fig.28A Top view of the structure.

[0116] Fig.29A yes Fig.28A A cross-sectional view of the structure of FIG. 2900 is shown, except that a dry film mask 2900 is applied to areas where no additional BUF will be applied. Fig.29B yes Fig.29A Top view of the structure.

[0117] Fig. 30A yes Fig.29A A cross-sectional view of the structure of FIG. 29 , except that additional BUF 3000 is applied on the areas not covered by dry film mask 2900 . Fig. 30B yes Fig. 30A Top view of the structure.

[0118] Fig.31A yes Fig. 30A A cross-sectional view of the structure of , except that the dry film mask 2900 is removed, as indicated by number 3100. Fig.31B yes Fig.31A Top view of the structure.

[0119] Fig.32A yes Fig.31A 124 and / or 128, except that BUF 3000 is thinned to the thickness of metallization 124 and / or 128, as indicated by thinned BUF 3200. Fig.32B yes Fig.32A Top view of the structure.

[0120] Fig.33A yes Fig.32A A cross-sectional view of the structure of , except that a dry film mask 3300 is applied to the areas to be protected from the effects of additional prepreg deposition. Fig.33B yes Fig.33A Top view of the structure.

[0121] Fig.34A yes Fig.33A 3400 is applied to the areas not covered by the dry film mask 3300. Fig.34B yes Fig.34A Top view of the structure.

[0122] Fig.35A yes Fig.34A A cross-sectional view of the structure of , except that the dry film mask 3300 is removed, as indicated by the number 3500. Fig.35B yes Fig.35A Top view of the structure.

[0123] Fig.36A yes Fig.35A A cross-sectional view of the structure of , except that the prepreg 3400 is thinned to the thickness of the BUF 3200 , as indicated by the numeral 3600 . Fig.36B yes Fig.36A Top view of the structure.

[0124] In this manner, steps 202-224 are iteratively performed until all metal layers are formed. Method 200 includes removing (226) the carrier core, and applying (228) a solder mask. Fig.37A yes Fig.36A 3700 , except that the carrier core 300 , the barrier layer 302 , and the seed layer 304 are removed, as indicated by numeral 3700 . Fig.37B yes Fig.37A Top view of the structure. Fig.38A yes Fig.37A A cross-sectional view of the structure, except that solder masks 3800 and 3802 are applied on Fig.37A The solder masks 3800 and 3802 are patterned on the opposite top and bottom surfaces of the structure and are patterned outside. In an example, the solder masks 3800 and 3802 are patterned to expose specific portions of the metallization within the substrate to facilitate soldering (e.g., coupling the substrate to a semiconductor die or to a printed circuit board (PCB)). The result is a finished substrate 3804. Fig.38B yes Fig.38A Top view of the structure.

[0125] The method 200 includes coupling (230) a semiconductor die to a metal layer in a substrate, and covering (232) the semiconductor die and the substrate with a molding compound. Fig.39A yes Fig.38A 3904, except that semiconductor dies 3900 and 3902 are coupled to metallization within substrate 3804 using pillars 3904 and 3906, respectively. Solder members 3908 may be used to couple pillars 3904 to the metallization of substrate 3804, and solder members 3910 may be used to couple pillars 3906 to the metallization of substrate 3804. For example, solder members 3908 and 3910 may be positioned using solder mask 3800, and after pillars 3904, 3906 and semiconductor dies 3900, 3902 are appropriately positioned, solder members 3908 and 3910 may be reflowed to establish connections to the metallization within substrate 3804. Fig.39B yes Fig.39A Top view of the structure.

[0126] Fig.40A yes Fig.39A 4000 , 4002 and substrate 3804 . Fig.40B yes Fig.40A The result is a completed semiconductor package 4002. The semiconductor package 4002 can be used with Figures 1A-1C The semiconductor package 100 is similar or identical to the semiconductor package 100 .

[0127] Fig.41 is a block diagram of an electronic device including a semiconductor package having a BUF and a prepreg substrate according to various examples. Specifically, Fig.41 An electronic device 4100 is shown that includes a PCB 4102 to which a semiconductor package 4104 is coupled. Semiconductor package 4104 may be similar or identical to semiconductor package 100 and / or 4002 described above. Examples of electronic device 4100 include an automobile, an airplane, a boat, a spacecraft, a video game console, an arcade video game unit, a smartphone, an entertainment device, a home appliance, a laptop computer, a desktop computer, a tablet computer, a notebook computer, or any other suitable type of electronic device or system.

[0128] In this specification, the term "coupled" may encompass connections, communications, or signal paths that enable a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B through a direct connection; or (b) in a second instance, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not change the functional relationship between device A and device B, so that device B is controlled by device A through the control signal generated by device A.

[0129] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by a manufacturer, and / or may be configured (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. Configuration may be achieved through firmware and / or software programming of the device, through the construction and / or layout of the device's hardware components and interconnects, or a combination thereof.

[0130] In this specification, unless otherwise stated, "about," "approximately," or "substantially" preceding a parameter means within a + / -10% range of the parameter. Modifications may be made in the described examples, and other examples may be made within the scope of the claims.

[0131] As used herein, the terms "terminal", "node", "interconnect", "pin" and "lead" are used interchangeably. Unless specifically stated otherwise, these terms are generally used to refer to interconnects between device elements, circuit elements, integrated circuits, devices or semiconductor components or their terminals.

Claims

1. A semiconductor package, comprising: a substrate comprising a build-up film barrier layer and a first prepreg layer and a second prepreg layer contacting opposite lateral sides of the build-up film barrier layer, the first prepreg layer comprising a first metallization and the second prepreg layer comprising a second metallization not in physical contact with the first metallization; solder mask layers on the top and bottom surfaces of the substrate; a first semiconductor die coupled to the first metallization; a second semiconductor die coupled to the second metallization, the first semiconductor die and the second semiconductor die being configured to operate in independent voltage domains; as well as A molding compound covers the substrate and the first semiconductor die and the second semiconductor die. 2 . The semiconductor package of claim 1 , wherein a minimum lateral distance between the third metallization in the buildup film isolation layer and an interface between the buildup film isolation layer and the second prepreg layer is at least 100 microns. 3 . The semiconductor package of claim 1 , wherein the buildup film isolation layer comprises a first coil and a second coil that are not in physical contact with each other, the first coil is coupled to the first semiconductor die, and the second coil is coupled to the second semiconductor die. 4 . The semiconductor package according to claim 1 , wherein the build-up film isolation layer comprises an epoxy-based resin, an inorganic filler, and a curing agent, and does not comprise glass fiber. 5 . The semiconductor package according to claim 1 , wherein the deposited film isolation layer has a dielectric constant between 3.2 and 3.4 at 5.8 GHz. 6 . The semiconductor package of claim 1 , wherein the build-up film isolation layer has a coefficient of thermal expansion (CTE) in a range of 20 parts per million per Kelvin (ppm / K) to 39 ppm / K.

7. The semiconductor package of claim 1, wherein the first prepreg layer is 36%-77% glass fiber by weight.

8. A semiconductor package, comprising: a substrate comprising a first metallization, a second metallization, a first coil, and a second coil, the first metallization and the first coil being in a first voltage domain and the second metallization and the second coil being in a second voltage domain, the first metallization being covered by a first prepreg layer, the second metallization being covered by a second prepreg layer, and the first coil and the second coil being covered by a build-up film isolation layer; a first solder mask layer contacting top surfaces of the first and second prepreg layers and a top surface of the build-up film isolation layer; a second solder mask layer contacting bottom surfaces of the first and second prepreg layers and a bottom surface of the build-up film isolation layer; a first semiconductor die coupled to the first metallization and the first coil; a second semiconductor die coupled to the second metallization and the second coil; as well as A molding compound contacts the first semiconductor die and the second semiconductor die and the first solder mask. 9 . The semiconductor package of claim 8 , wherein a minimum lateral distance between the first coil in the buildup film isolation layer and an interface between the buildup film isolation layer and the second prepreg layer is at least 100 microns. 10 . The semiconductor package according to claim 8 , wherein the build-up film isolation layer comprises an epoxy resin, an inorganic filler, and a curing agent, and does not comprise glass fiber.

11. The semiconductor package of claim 8, wherein the deposited film isolation layer has a dielectric constant between 3.2 and 3.4 at 5.8 GHz.

12. The semiconductor package of claim 8, wherein the first prepreg layer is 36%-77% glass fiber by weight. 13 . The semiconductor package of claim 8 , wherein the build-up film isolation layer has a coefficient of thermal expansion (CTE) in a range of 20 parts per million per Kelvin (ppm / K) to 39 ppm / K.

14. A method for manufacturing a semiconductor package, comprising: Two or more layers of a substrate are formed by iteratively performing the following operations: Metal coating; applying a buildup film to the metal layer using a first mask; applying a first prepreg to the metal layer on a first lateral side of the buildup film; as well as applying a second prepreg to the metal layer on a second lateral side of the buildup film, the second lateral side opposite the first lateral side; as well as applying a solder mask layer to the substrate; coupling a first semiconductor die and a second semiconductor die to the substrate, the first semiconductor die and the second semiconductor die being configured to operate in independent voltage domains; as well as The substrate and the first and second semiconductor dies are covered with a molding compound.

15. A method according to claim 14, wherein the forming of the two or more layers of the substrate includes forming a prepreg layer and a build-up film isolation layer including a coil, and wherein the minimum lateral distance between the coil and the interface between the build-up film isolation layer and the prepreg layer is at least 100 microns.

16. The method of claim 15, wherein the forming of the two or more layers of the substrate includes forming the deposited film isolation layer including a second coil, wherein the coil and the second coil are not in physical contact with each other, the coil is coupled to the first semiconductor die, and the second coil is coupled to the second semiconductor die. 17 . The method according to claim 15 , wherein the build-up film isolation layer comprises an epoxy resin, an inorganic filler, and a curing agent, and does not comprise glass fiber.

18. The method of claim 15, wherein the deposited film isolation layer has a dielectric constant between 3.2 and 3.4 at 5.8 GHz.

19. The method of claim 15, wherein the prepreg layer is 36%-77% glass fiber by weight.

20. The method of claim 15, wherein the stacked film isolation layer has a coefficient of thermal expansion (CTE) in a range of 20 parts per million per Kelvin (ppm / K) to 39 ppm / K.

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