Low parasitic inductance power packaging structure suitable for high temperature application

Abstract

The invention belongs to the technical field of electronics, and particularly relates to a low parasitic inductance power packaging structure suitable for high-temperature application, which comprises a middle layer and a chip unit electrically connected with the middle layer, the middle layer is composed of a plurality of conductive layers and insulating ceramic layers, and each conductive layer is arranged between two adjacent insulating ceramic layers; the power supply circuit is arranged in the conducting layers, one end of the power supply circuit is used for being connected with a power supply, and the other end of the power supply circuit is electrically connected with the chip unit; the control circuit is arranged in the conducting layers, one end of the control circuit is electrically connected with the chip unit, and the other end of the control circuit is electrically connected with the control end. By utilizing the characteristics of high temperature resistance, high insulating strength and excellent heat dissipation performance of the insulating ceramic layer, the packaging structure has the characteristics of low parasitic inductance development, high temperature resistance, excellent heat dissipation performance and high insulating strength.

Description

Technical Field

[0001] The present invention belongs to the field of electronic technology, and in particular relates to a low parasitic inductance power packaging structure suitable for high temperature applications. Background Art

[0002] With the development of electric vehicle technology, the performance requirements for power electronic converters are increasing. Especially in high temperature environments, power modules need to have higher power density, lower parasitic inductance and stronger heat dissipation capabilities.

[0003] Silicon carbide (SiC) power devices have become a popular choice for electric vehicle applications due to their excellent electrical properties at high temperatures. However, traditional packaging technology cannot fully meet the performance requirements of SiC devices in high-temperature, high-power density applications.

[0004] In order to meet the high performance requirements of power modules in high-temperature applications of electric vehicles, it is necessary to develop a new packaging structure with low parasitic inductance, high temperature resistance, excellent heat dissipation performance and high insulation strength. Summary of the invention

[0005] The object of the present invention is to provide a low parasitic inductance power packaging structure suitable for high temperature applications to solve the above problems.

[0006] To achieve the above object, the present invention provides the following solutions:

[0007] A low parasitic inductance power packaging structure suitable for high temperature applications, comprising: an intermediate layer, a chip unit electrically connected to the intermediate layer,

[0008] The intermediate layer includes a plurality of conductive layers and insulating ceramic layers, wherein the conductive layer is arranged between two adjacent insulating ceramic layers;

[0009] A power supply circuit is arranged in the plurality of conductive layers, one end of the power supply circuit is used to be connected to a power source, and the other end of the power supply circuit is electrically connected to the chip unit;

[0010] A control circuit is arranged in the plurality of conductive layers, one end of the control circuit is electrically connected to the chip unit, and the other end of the control circuit is electrically connected to the control end.

[0011] Optionally, the chip unit includes a multi-layer ceramic substrate upper layer component and a multi-layer ceramic substrate lower layer component, and the multi-layer ceramic substrate upper layer component and the multi-layer ceramic substrate lower layer component are both electrically connected to the middle layer.

[0012] Optionally, the upper layer components of the multilayer ceramic substrate include a lower bridge arm bare chip and a DC negative electrode substrate;

[0013] The DC negative electrode substrate is a three-layer structure, comprising an insulating heat transfer layer located in the middle, a metal layer fixedly connected above the insulating heat transfer layer, and a DC negative electrode layer fixedly connected below the insulating heat transfer layer, and a second control electrode layer is provided in the middle of the DC negative electrode layer;

[0014] The lower bridge arm bare chip includes a second control terminal, a third switch terminal and a fourth switch terminal, the second control terminal is electrically connected to the second control electrode layer, the third switch terminal is electrically connected to the DC negative electrode layer, the fourth switch terminal is electrically connected to a fourth switch terminal pad, and the fourth switch terminal pad is arranged on the top of the middle layer;

[0015] The lower bridge arm bare chip is arranged between the DC negative electrode layer and the middle layer;

[0016] The DC negative electrode layer is electrically connected to an upper thermal conductive pad, the second control electrode layer is electrically connected to a second control end pad, and both the upper thermal conductive pad and the second control end pad are connected to the top of the middle layer.

[0017] Optionally, the lower layer components of the multilayer ceramic substrate include an upper bridge arm bare chip and a DC positive electrode substrate;

[0018] The DC positive electrode substrate is a three-layer structure, comprising an insulating heat transfer layer located in the middle, a metal layer fixedly connected below the insulating heat transfer layer, and a DC positive electrode layer fixedly connected above the insulating heat transfer layer;

[0019] The upper bridge arm bare chip includes a first control end, a first switch end and a second switch end, the first control end is electrically connected to a first control end pad, the first switch end is electrically connected to a first switch end pad, and the second switch end is electrically connected to the DC positive electrode layer; the first switch end pad and the first control end pad are both located at the bottom of the middle layer;

[0020] The upper bridge arm bare chip is arranged between the DC positive electrode layer and the middle layer; the DC positive electrode layer is electrically connected to a lower thermal conductive pad, and the lower thermal conductive pad is connected to the bottom of the middle layer.

[0021] Optionally, the DC positive electrode layer is electrically connected to one end of a DC positive terminal component, the other end of the DC positive terminal component extends to the outside of the DC positive substrate, and the DC positive terminal component serves as a DC positive electrode lead-out terminal.

[0022] Optionally, the DC negative electrode layer is electrically connected to one end of a DC negative electrode terminal, the other end of the DC negative electrode terminal extends to the outside of the DC negative substrate, and the DC negative electrode terminal serves as a DC negative electrode lead-out terminal.

[0023] Optionally, the fourth switch end pad is electrically connected to the first switch end pad via an AC electrode through-hole, and the AC electrode through-hole is disposed through the middle layer.

[0024] Optionally, the first control terminal pad is electrically connected to one end of the first control terminal conductive trace, and the other end of the first control terminal conductive trace is electrically connected to the first control terminal pad;

[0025] One end of the first control-end conductive trace is electrically connected to a first control-end through hole for connecting to the first control-end pad, the other end of the first control-end conductive trace is electrically connected to a first control terminal through hole for connecting to the first control terminal pad, the first control terminal pad is electrically connected to the first control terminal through hole, and the first control-end pad is electrically connected to the first control-end through hole;

[0026] The first control terminal pad is electrically connected to a first control terminal piece.

[0027] Optionally, the second control terminal pad is electrically connected to one end of a second control terminal conductive trace, and the other end of the second control terminal conductive trace is electrically connected to a second control terminal pad;

[0028] One end of the second control-end conductive trace is electrically connected to a second control-end through hole for connecting to the second control-end pad, the other end of the second control-end conductive trace is electrically connected to a second control terminal through hole for connecting to the second control terminal pad, the second control terminal pad is electrically connected to the second control terminal through hole, and the second control terminal pad is electrically connected to the second control-end through hole;

[0029] The second control terminal pad is electrically connected to a second control terminal piece.

[0030] Optionally, the AC electrode through-hole 110 is electrically connected to an AC terminal pad via an AC electrode conductive trace, the AC terminal pad is electrically connected to an AC terminal through-hole, the AC terminal through-hole is used to install an AC terminal component, and the AC terminal through-hole is electrically connected to the AC terminal component.

[0031] Compared with the prior art, the present invention has the following advantages and technical effects:

[0032] The present invention realizes the miniaturization of the packaging structure by setting the middle layer as a multi-layer structure and setting the power supply circuit and the control circuit on several conductive layers in the middle layer. At the same time, two adjacent conductive layers are connected by an insulating ceramic layer. The insulating ceramic layer has the characteristics of high temperature resistance, high insulation strength and excellent heat dissipation performance, so that the packaging structure of the present invention has the characteristics of low parasitic inductance, high temperature resistance, excellent heat dissipation performance and high insulation strength. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative labor:

[0034] Figure 1 It is an exploded view of the structure of the present invention;

[0035] Figure 2 It is a bottom perspective view of the present invention;

[0036] Figure 3 It is a top perspective view of the present invention;

[0037] Figure 4 It is a bottom view of the present invention;

[0038] Figure 5 A top view of the present invention;

[0039] Figure 6 This is a structural diagram of the DC negative electrode substrate of the present invention;

[0040] Figure 7 This is a structural diagram of the DC positive electrode substrate of the present invention;

[0041] Among them, 1, middle layer; 101, first switch end pad; 102, fourth switch end pad; 103, first control end pad; 104, second control end pad; 105, AC terminal pad; 106, first control terminal pad; 107, second control terminal pad; 108, upper thermal pad; 109, lower thermal pad; 110, AC electrode through hole; 111, first control end through hole; 112, second control end through hole; 113, AC terminal through hole; 114, first control terminal through hole ; 115, second control terminal through hole; 116, AC electrode conductive trace; 117, first control terminal conductive trace; 118, second control terminal conductive trace; 2, DC positive substrate; 201, DC positive electrode layer; 3, DC negative substrate; 301, DC negative electrode layer; 302, second control electrode layer; 4, upper bridge arm bare chip; 5, lower bridge arm bare chip; 6, DC positive terminal component; 7, DC negative electrode terminal component; 8, AC terminal component; 9, first control terminal component; 10, second control terminal component. DETAILED DESCRIPTION

[0042] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0043] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0044] Reference Figures 1 to 7 The present invention discloses a low parasitic inductance power packaging structure suitable for high temperature applications, comprising: an intermediate layer 1, a chip unit electrically connected to the intermediate layer 1,

[0045] The middle layer 1 includes a plurality of conductive layers and insulating ceramic layers, wherein the conductive layer is arranged between two adjacent insulating ceramic layers;

[0046] A power supply circuit is arranged in the plurality of conductive layers, one end of the power supply circuit is used to be connected to a power source, and the other end of the power supply circuit is electrically connected to the chip unit;

[0047] The control circuit is arranged in the plurality of conductive layers, one end of the control circuit is electrically connected to the chip unit, and the other end of the control circuit is electrically connected to the control end.

[0048] The present invention realizes the miniaturization of the packaging structure by setting the middle layer 1 as a multi-layer structure and setting the power supply circuit and the control circuit on several conductive layers in the middle layer. At the same time, two adjacent conductive layers are connected by an insulating ceramic layer. The insulating ceramic layer has the characteristics of high temperature resistance, high insulation strength and excellent heat dissipation performance, so that the packaging structure of the present invention has the characteristics of low parasitic inductance, high temperature resistance, excellent heat dissipation performance and high insulation strength.

[0049] As an optional implementation, the chip unit includes a multi-layer ceramic substrate upper component and a multi-layer ceramic substrate lower component, and both the multi-layer ceramic substrate upper component and the multi-layer ceramic substrate lower component are electrically connected to the middle layer.

[0050] As an optional implementation, the upper component of the multilayer ceramic substrate includes a lower bridge arm bare chip 5 and a DC negative electrode substrate 3;

[0051] The DC negative electrode substrate 3 is a three-layer structure, comprising an insulating heat transfer layer in the middle, a metal layer fixedly connected above the insulating heat transfer layer, and a DC negative electrode layer 301 fixedly connected below the insulating heat transfer layer, and a second control electrode layer 302 is provided in the middle of the DC negative electrode layer 301;

[0052] The lower bridge arm bare chip 5 includes a second control terminal, a third switch terminal and a fourth switch terminal, the second control terminal is electrically connected to the second control electrode layer 302, the third switch terminal is electrically connected to the DC negative electrode layer 301, and the fourth switch terminal is electrically connected to the fourth switch terminal pad 102, and the fourth switch terminal pad 102 is arranged on the top of the middle layer 1;

[0053] The lower bridge arm bare chip 5 is arranged between the DC negative electrode layer 301 and the middle layer 1;

[0054] The DC negative electrode layer 301 is electrically connected to the upper thermal conductive pad 108 , and the second control electrode layer 302 is electrically connected to the second control terminal pad 104 . Both the upper thermal conductive pad 108 and the second control terminal pad 104 are connected to the top of the middle layer 1 .

[0055] As an optional implementation, the lower layer components of the multilayer ceramic substrate include an upper bridge arm bare chip 4 and a DC positive electrode substrate 2;

[0056] The DC positive electrode substrate 2 is a three-layer structure, and the DC positive electrode substrate 2 includes an insulating heat transfer layer located in the middle, a metal layer fixedly connected below the insulating heat transfer layer, and a DC positive electrode layer 201 fixedly connected above the insulating heat transfer layer;

[0057] The upper bridge arm bare chip 4 includes a first control end, a first switch end and a second switch end, the first control end is electrically connected to the first control end pad 103, the first switch end is electrically connected to the first switch end pad 101, and the second switch end is electrically connected to the DC positive electrode layer 201; the first switch end pad 101 and the first control end pad 103 are both located at the bottom of the middle layer 1;

[0058] The upper bridge arm bare chip 4 is arranged between the DC positive electrode layer 201 and the middle layer 1 ; the DC positive electrode layer 201 is electrically connected to the lower thermal conductive pad 109 , and the lower thermal conductive pad 109 is connected to the bottom of the middle layer 1 .

[0059] As an optional implementation, the DC positive electrode layer 201 is electrically connected to one end of a DC positive terminal component 6, the other end of the DC positive terminal component 6 extends to the outside of the DC positive substrate 2, and the DC positive terminal component 6 serves as a DC positive electrode lead-out terminal.

[0060] As an optional embodiment, the DC negative electrode layer 301 is electrically connected to one end of the DC negative electrode terminal 7, and the other end of the DC negative electrode terminal 7 extends to the outside of the DC negative substrate 3, and the DC negative electrode terminal 7 serves as a DC negative electrode lead-out terminal.

[0061] As an optional implementation, the fourth switch terminal pad 102 is electrically connected to the first switch terminal pad 101 via an AC electrode through-hole 110 , and the AC electrode through-hole 110 is disposed through the middle layer 1 .

[0062] As an optional implementation, the first control terminal pad 103 is electrically connected to one end of the first control terminal conductive trace 117, and the other end of the first control terminal conductive trace 117 is electrically connected to the first control terminal pad 106;

[0063] One end of the first control-end conductive trace 117 is electrically connected to the first control-end through hole 111 for connecting to the first control-end pad 103, and the other end of the first control-end conductive trace 117 is electrically connected to the first control-terminal through hole 114 for connecting to the first control-terminal pad 106. The first control-terminal pad 106 is electrically connected to the first control-terminal through hole 114, and the first control-end pad 103 is electrically connected to the first control-end through hole 111;

[0064] The first control terminal pad 106 is electrically connected to the first control terminal piece 9 .

[0065] As an optional implementation, the second control terminal pad 104 is electrically connected to one end of the second control terminal conductive trace 118, and the other end of the second control terminal conductive trace 118 is electrically connected to the second control terminal pad 107;

[0066] One end of the second control-end conductive trace 118 is electrically connected to the second control-end through hole 112 for connecting to the second control-end pad 104, and the other end of the second control-end conductive trace 118 is electrically connected to the second control-terminal through hole 115 for connecting to the second control-terminal pad 107. The second control-terminal pad 107 is electrically connected to the second control-terminal through hole 115, so that the second control-end pad 104 is electrically connected to the second control-end through hole 112;

[0067] The second control terminal pad 107 is electrically connected to the second control terminal member 10 .

[0068] As an optional embodiment, the AC electrode through hole 110 is electrically connected to the AC terminal pad 105 through the AC electrode conductive trace 116, and the AC terminal pad 105 is electrically connected to the AC terminal through hole 113. The AC terminal through hole 113 is used to install the AC terminal component 8, and the AC terminal through hole 113 is electrically connected to the AC terminal component 8.

[0069] A low parasitic inductance power packaging structure suitable for high temperature applications, comprising: an intermediate layer 1, an upper component of a multilayer ceramic substrate, and a lower component of a multilayer ceramic substrate, wherein the intermediate layer 1, the upper component of the multilayer ceramic substrate, and the lower component of the multilayer ceramic substrate are overlapped in a vertical direction to construct a three-dimensional commutation loop;

[0070] The middle layer 1 in the present invention comprises: a first switch end pad 101, a fourth switch end pad 102, a first control end pad 103, a second control end pad 104, an AC terminal pad 105, a first control terminal pad 106, a second control terminal pad 107, an upper thermal conductive pad 108, a lower thermal conductive pad 109, an AC electrode through hole 110, a first control end through hole 111, a second control end through hole 112, an AC terminal through hole 113, a first control terminal through hole 114, a second control terminal through hole 115, an AC electrode conductive trace 116, a first control end conductive trace 117 and a second control end conductive trace 118.

[0071] The first switch terminal pad 101 and the fourth switch terminal pad 102 are electrically connected to each other through the AC electrode through hole 110, the AC terminal pad 105 is electrically connected to the AC terminal through hole 113, and the AC electrode through hole 110 and the AC terminal through hole 113 are electrically connected to each other through the AC electrode conductive trace 116, thereby forming an AC electrode network.

[0072] The first control end pad 103 and the first control terminal pad 106 are electrically connected to each other through the first control end conductive trace 117. One end of the first control end conductive trace 117 is electrically connected to the first control end through hole 111 for connecting to the first control end pad 103, and the other end of the first control end conductive trace 117 is electrically connected to the first control terminal through hole 114 for connecting to the first control terminal pad 106. The first control terminal pad 106 is electrically connected to the first control terminal through hole 114, and the first control terminal pad 103 is electrically connected to the first control end through hole 111, thereby forming a first control end network.

[0073] The second control terminal pad 104 and the second control terminal pad 107 are electrically connected to each other through the second control terminal conductive trace 118. One end of the second control terminal conductive trace 118 is electrically connected to the second control terminal through hole 112 for connecting to the second control terminal pad 104, and the other end of the second control terminal conductive trace 118 is electrically connected to the second control terminal through hole 115 for connecting to the second control terminal pad 107. The second control terminal pad 107 is electrically connected to the second control terminal through hole 115, and the second control terminal pad 104 is electrically connected to the second control terminal through hole 112, thereby forming a second control terminal network.

[0074] The insulating ceramic layer in the middle layer 1 is usually made of ceramic or ceramic-glass composite material; the conductive layer in the middle layer 1 is usually made of metal or alloy material.

[0075] The upper layer components of the multilayer ceramic substrate include: a lower bridge arm bare chip 5 and a DC negative electrode substrate 3. The DC negative electrode substrate 3 includes an insulating heat transfer layer located in the middle, a metal layer fixedly connected above the insulating heat transfer layer, and a DC negative electrode layer 301 fixedly connected below the insulating heat transfer layer. A second control electrode layer 302 is provided in the middle of the DC negative electrode layer 301; its insulating heat transfer layer is an insulating heat transfer material, and its metal layer is an excellent conductive material.

[0076] The lower bridge arm bare chip 5 is provided with a second control terminal, a third switch terminal and a fourth switch terminal, the second control terminal is electrically connected to the second control electrode layer 302, the third switch terminal is electrically connected to the DC negative electrode layer 301, and the fourth switch terminal is electrically connected to the fourth switch terminal pad 102; the lower bridge arm bare chip 5 is arranged between the DC negative electrode layer 301 and the middle layer 1, and is electrically connected to the two; the second control electrode layer 302 and the DC negative electrode layer 301 are arranged on the DC negative substrate 3, the DC negative electrode layer 301 is connected to the upper thermal conductive pad 108, and the second control electrode layer 302 is electrically connected to the second control terminal pad 104.

[0077] The lower layer components of the multilayer ceramic substrate include: an upper bridge arm bare chip 4, a DC positive substrate 2, the DC positive substrate 2 is a three-layer structure, the middle layer is an insulating heat transfer layer, a DC positive electrode layer 201 is fixedly connected above the insulating heat transfer layer, and a metal layer is fixedly connected below the insulating heat transfer layer, and the metal layer is an excellent conductive material; the upper bridge arm bare chip 4 is provided with a first control end, a first switch end and a second switch end, the first control end is electrically connected to the first control end pad 103, the first switch end is electrically connected to the first switch end pad 101, and the second switch end is electrically connected to the DC positive electrode layer 201; the upper bridge arm bare chip 4 is arranged between the DC positive electrode layer 201 and the middle layer 1, and is electrically connected to the two; the DC positive electrode layer 201 is arranged on the DC positive substrate 2, and the DC positive electrode layer 201 is connected to the lower thermal conductive pad 109.

[0078] The present invention also includes: a DC positive terminal member 6, which serves as a DC positive electrode lead-out terminal, one end of the DC positive terminal member 6 is electrically connected to the DC positive electrode layer 201, and the other end extends to the outside of the DC positive substrate 2; a DC negative electrode terminal member 7, which serves as a DC negative electrode lead-out terminal, one end of the DC negative electrode terminal member 7 is electrically connected to the DC negative electrode layer 301, and the other end extends to the outside of the DC negative substrate 3; an AC terminal member 8, which serves as an AC electrode lead-out terminal, one end of the AC terminal member 8 is electrically connected to the AC terminal pad 105, and the other end extends to the outside of the intermediate layer 1; a first control terminal member 9, which serves as a lead-out terminal of the first control end, one end of the first control terminal member 9 is electrically connected to the first control terminal pad 106, and the other end extends to the outside of the intermediate layer 1; a second control terminal member 10, which serves as a lead-out terminal of the second control end, one end of the second control terminal member 10 is electrically connected to the second control terminal pad 107, and the other end extends to the outside of the intermediate layer 1.

[0079] The DC positive terminal 6 and the DC negative electrode terminal 7 overlap in the vertical direction to form a stacked terminal structure; the two terminal components included in the first control terminal 9 overlap in the vertical direction to form a stacked terminal structure; the two terminal components included in the second control terminal 10 overlap in the vertical direction to form a stacked terminal structure.

[0080] In the description of the present invention, it should be understood that the terms "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0081] The embodiments described above are only descriptions of the preferred modes of the present invention, and are not intended to limit the scope of the present invention. Without departing from the design spirit of the present invention, various modifications and improvements made to the technical solutions of the present invention by ordinary technicians in this field should all fall within the protection scope determined by the claims of the present invention.

Claims

1. A low parasitic inductance power packaging structure suitable for high temperature applications, comprising: The intermediate layer (1) and the chip unit electrically connected to the intermediate layer (1) are characterized by: The intermediate layer (1) comprises a plurality of conductive layers and insulating ceramic layers, wherein the conductive layer is arranged between two adjacent insulating ceramic layers; A power supply circuit is arranged in the plurality of conductive layers, one end of the power supply circuit is used to be connected to a power source, and the other end of the power supply circuit is electrically connected to the chip unit; A control circuit is arranged in the plurality of conductive layers, one end of the control circuit is electrically connected to the chip unit, and the other end of the control circuit is electrically connected to the control end.

2. The low parasitic inductance power packaging structure suitable for high temperature applications according to claim 1, characterized in that: The chip unit comprises a multi-layer ceramic substrate upper layer component and a multi-layer ceramic substrate lower layer component, and both the multi-layer ceramic substrate upper layer component and the multi-layer ceramic substrate lower layer component are electrically connected to the intermediate layer (1).

3. The low parasitic inductance power packaging structure suitable for high temperature applications according to claim 2, characterized in that: The upper layer components of the multi-layer ceramic substrate include a lower bridge arm bare chip (5) and a DC negative electrode substrate (3); The DC negative electrode substrate (3) is a three-layer structure, comprising an insulating heat transfer layer located in the middle, a metal layer fixedly connected above the insulating heat transfer layer, and a DC negative electrode layer (301) fixedly connected below the insulating heat transfer layer, wherein a second control electrode layer (302) is provided in the middle of the DC negative electrode layer (301); The lower bridge arm bare chip (5) comprises a second control end, a third switch end and a fourth switch end, the second control end is electrically connected to the second control electrode layer (302), the third switch end is electrically connected to the DC negative electrode layer (301), the fourth switch end is electrically connected to a fourth switch end pad (102), and the fourth switch end pad (102) is arranged on the top of the middle layer (1); The lower bridge arm bare chip (5) is arranged between the DC negative electrode layer (301) and the middle layer (1); The DC negative electrode layer (301) is electrically connected to an upper thermal conductive pad (108), the second control electrode layer (302) is electrically connected to a second control end pad (104), and both the upper thermal conductive pad (108) and the second control end pad (104) are connected to the top of the middle layer (1).

4. The low parasitic inductance power packaging structure suitable for high temperature applications according to claim 3, characterized in that: The lower layer components of the multilayer ceramic substrate include an upper bridge arm bare chip (4) and a DC positive electrode substrate (2); The DC positive electrode substrate (2) is a three-layer structure, comprising an insulating heat transfer layer located in the middle, a metal layer fixedly connected below the insulating heat transfer layer, and a DC positive electrode layer (201) fixedly connected above the insulating heat transfer layer; The upper bridge arm bare chip (4) comprises a first control end, a first switch end and a second switch end, the first control end is electrically connected to a first control end pad (103), the first switch end is electrically connected to a first switch end pad (101), and the second switch end is electrically connected to the DC positive electrode layer (201); the first switch end pad (101) and the first control end pad (103) are both located at the bottom of the middle layer (1); The upper bridge arm bare chip (4) is arranged between the DC positive electrode layer (201) and the middle layer (1); the DC positive electrode layer (201) is electrically connected to a lower thermal conductive pad (109), and the lower thermal conductive pad (109) is connected to the bottom of the middle layer (1).

5. The low parasitic inductance power packaging structure suitable for high temperature applications according to claim 4, characterized in that: The DC positive electrode layer (201) is electrically connected to one end of a DC positive terminal component (6), the other end of the DC positive terminal component (6) extends to the outside of the DC positive substrate (2), and the DC positive terminal component (6) serves as a DC positive electrode lead-out terminal.

6. The low parasitic inductance power packaging structure suitable for high temperature applications according to claim 3, characterized in that: The DC negative electrode layer (301) is electrically connected to one end of a DC negative electrode terminal (7), the other end of the DC negative electrode terminal (7) extends to the outside of the DC negative substrate (3), and the DC negative electrode terminal (7) serves as a DC negative electrode lead-out terminal.

7. The low parasitic inductance power packaging structure suitable for high temperature applications according to claim 4, characterized in that: The fourth switch end pad (102) is electrically connected to the first switch end pad (101) via an AC electrode through hole (110), and the AC electrode through hole (110) is arranged through the middle layer (1).

8. The low parasitic inductance power packaging structure suitable for high temperature applications according to claim 4, characterized in that: The first control terminal pad (103) is electrically connected to one end of a first control terminal conductive trace (117), and the other end of the first control terminal conductive trace (117) is electrically connected to a first control terminal pad (106); One end of the first control-end conductive trace (117) is electrically connected to a first control-end through hole (111) for connecting to the first control-end pad (103), and the other end of the first control-end conductive trace (117) is electrically connected to a first control-terminal through hole (114) for connecting to the first control-terminal pad (106); the first control-terminal pad (106) is electrically connected to the first control-terminal through hole (114), and the first control-end pad (103) is electrically connected to the first control-end through hole (111); The first control terminal pad (106) is electrically connected to a first control terminal piece (9).

9. The low parasitic inductance power packaging structure suitable for high temperature applications according to claim 3, characterized in that: The second control terminal pad (104) is electrically connected to one end of a second control terminal conductive trace (118), and the other end of the second control terminal conductive trace (118) is electrically connected to a second control terminal pad (107); One end of the second control-end conductive trace (118) is electrically connected to a second control-end through hole (112) for connecting to the second control-end soldering pad (104); the other end of the second control-end conductive trace (118) is electrically connected to a second control-terminal through hole (115) for connecting to the second control-terminal soldering pad (107); the second control-terminal soldering pad (107) is electrically connected to the second control-terminal through hole (115), and the second control-end soldering pad (104) is electrically connected to the second control-end through hole (112); The second control terminal pad (107) is electrically connected to a second control terminal member (10).

10. The low parasitic inductance power packaging structure suitable for high temperature applications according to claim 7, characterized in that: The AC electrode through hole (110) is electrically connected to an AC terminal pad (105) via an AC electrode conductive trace (116); the AC terminal pad (105) is electrically connected to an AC terminal through hole (113); the AC terminal through hole (113) is used to install an AC terminal component (8); and the AC terminal through hole (113) is electrically connected to the AC terminal component (8).

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