Semiconductor packaging structure and preparation method thereof

Abstract

The invention provides a semiconductor packaging structure and a preparation method thereof, relates to the technical field of semiconductor chips, and aims to solve the problem of how to improve a large occupied area of a bare chip on a packaging substrate in a bare chip interconnection packaging technology. The embodiment of the invention discloses a semiconductor packaging structure which comprises a packaging substrate and a device assembly layer. The device assembly layer is located on one side of the packaging substrate and connected with the packaging substrate, the device assembly layer comprises a plurality of bare chips arranged at intervals in the first direction, and the first direction is parallel to the packaging substrate; the device assembly layer further comprises a plurality of connecting pieces, and each connecting piece is located between every two adjacent bare chips and connected with the two bare chips respectively. Through the arrangement, the interval between the adjacent bare chips can be reduced, the occupied area of the bare chips on the packaging substrate can be reduced, and the packaging density of the bare chips is improved. Moreover, the connection distance between the two bare chips can be shortened, the resistance between the two adjacent bare chips is reduced, and the signal transmission speed between the bare chips can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor packaging structure and a preparation method thereof. Background Art

[0002] In the multi-die packaging process, the interconnection between the dies is mostly achieved by connecting the micro-bumps on the chip to the interposer, or by connecting the vertically stacked dies two by two through metal wires. However, in the above-mentioned die interconnect packaging technology, there is a problem that the die occupies a large area on the packaging substrate. Summary of the invention

[0003] The embodiments of the present disclosure provide a semiconductor packaging structure and a method for preparing the same, aiming to solve the problem of how to improve the bare die interconnect packaging technology, in which a bare die occupies a large area on a packaging substrate.

[0004] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0005] On the one hand, some embodiments of the present disclosure provide a semiconductor packaging structure, comprising: a packaging substrate and a device component layer. The device component layer is located on one side of the packaging substrate and connected to the packaging substrate, the device component layer comprises a plurality of bare chips spaced apart along a first direction, the first direction being parallel to the packaging substrate; the device component layer further comprises a plurality of connectors, each of which is located between two adjacent bare chips and respectively connected to the two bare chips.

[0006] In the above embodiments of the present disclosure, by arranging the connector between two adjacent bare chips, the signal transmission between the adjacent bare chips can be realized, and the interval between the adjacent bare chips can be reduced, which is conducive to reducing the area occupied by the bare chips on the packaging substrate and improving the density of bare chip packaging. In addition, the connection distance between the two adjacent bare chips can be shortened, and the resistance between the two adjacent bare chips is reduced, which is conducive to improving the signal transmission speed between the bare chips.

[0007] In some embodiments, the die includes a conductive layer; and the connecting element is connected to the conductive layer of adjacent dies.

[0008] In some embodiments, the bare chip includes a central portion, a sealing ring and a peripheral portion, the sealing ring is located between the central portion and the peripheral portion, and the conductive layer is located in the central portion; the bare chip also includes a lead-out member, the lead-out member passes through the sealing ring, one end of the lead-out member extends into the central portion and is connected to the conductive layer, and the other end of the lead-out member extends to the surface of the peripheral portion and is connected to the connecting member.

[0009] In some embodiments, one end of the connector contacts the outer periphery of one of the dies, and the other end of the connector contacts the outer periphery of the other of the dies.

[0010] In some embodiments, the area of ​​the lead-out member exposed to the surface of the peripheral portion is smaller than the orthographic projection area of ​​the connecting member on the peripheral portion.

[0011] In some embodiments, the lead-out member includes a conductive line and an isolation layer, and the isolation layer is located between the conductive line and the sealing ring.

[0012] In some embodiments, an extension direction of the lead-out member is perpendicular to a surface of the peripheral portion.

[0013] In some embodiments, the connector includes a hybrid bonding structure, a bump structure, or a solder ball structure.

[0014] In some embodiments, there are multiple device component layers, and the multiple device component layers are stacked along a second direction, and two adjacent bare chips along the second direction are connected. The second direction is the stacking direction of the device component layers and the packaging substrate.

[0015] In some embodiments, an insulating structure is further included, wherein the insulating structure is located between two of the bare chips adjacent to each other along the first direction, and the connecting member is located in the insulating structure.

[0016] In some embodiments, the plurality of device component layers are staggered in sequence along the first direction, and the plurality of device component layers are overlapped along the second direction.

[0017] In some embodiments, the bare die includes a first surface and a second surface arranged along the second direction; the semiconductor packaging structure also includes a metal lead, the metal lead is electrically connected between the first surfaces of two adjacent bare die along the second direction, or the metal lead is electrically connected between the second surfaces of two adjacent bare die along the second direction.

[0018] In some embodiments, edges of two adjacent device component layers along the second direction are flush.

[0019] In some embodiments, the die further includes a conductive via penetrating the die along the second direction; the semiconductor package structure further includes a bonding component connected between the conductive vias of two adjacent die along the second direction.

[0020] In some embodiments, in two adjacent device component layers, the connectors of one device component layer and the connectors of the other device component layer are alternately arranged in the second direction.

[0021] On the other hand, some embodiments of the present disclosure also provide a method for preparing a semiconductor packaging structure, comprising: providing a packaging substrate; providing a plurality of bare chips and a plurality of connectors; connecting each of the connectors to two of the bare chips in a first direction respectively to form a device component layer; the first direction is parallel to the packaging substrate; wherein the device component layer is located on one side of the packaging substrate and is connected to the packaging substrate.

[0022] In some embodiments, providing a bare chip includes: providing a first structural layer, the first structural layer including a first central portion, a first sealing ring and a first peripheral portion, the first sealing ring being located between the first central portion and the first peripheral portion; forming a second structural layer on the first structural layer, the second structural layer including a second central portion, a second sealing ring, a second peripheral portion and a lead-out member, the second sealing ring being located between the second central portion and the second peripheral portion, the lead-out member being arranged between the second central portion, the second sealing ring and the second peripheral portion; forming a third structural layer on a side of the second structural layer away from the first structural layer, the third structural layer including a third central portion, a third sealing ring and a third peripheral portion, the third sealing ring being located between the third central portion and the third peripheral portion; wherein the first central portion, the second central portion and the third central portion together constitute a central portion; the first sealing ring, the second sealing ring and the third sealing ring together constitute a sealing ring; the first peripheral portion, the second peripheral portion and the third peripheral portion together constitute a peripheral portion.

[0023] In some embodiments, forming a second structural layer on the first structural layer includes: forming a base layer, the base layer including a central area, a sealing area and a peripheral area, the sealing area being located between the central area and the peripheral area; performing a photolithography process on the base layer to form a second sealing ring in a portion of the sealing area, and at the same time, forming a conductive line in a portion of the central area, a portion of the sealing area and a portion of the peripheral area; wherein the portion of the base layer retained in the sealing area constitutes an isolation layer.

[0024] In some embodiments, forming a second structural layer on the first structural layer includes: forming a base layer, the base layer including a central area, a sealing area and a peripheral area, the sealing area being located between the central area and the peripheral area; removing a portion of the base layer located in the sealing area to form a first groove, the first groove being arranged along a partial edge of the central area; forming the second sealing ring in the first groove; removing a remaining portion of the base layer located in the sealing area, a portion of the base layer located in the central area, and a portion of the base layer located in the peripheral area to form a second groove, the second groove being arranged spaced apart from the first groove; and forming a conductive line in the second groove.

[0025] In some embodiments, after forming the device component layer, the method further includes: filling an insulating material between two adjacent bare chips along the first direction to form an insulating structure.

[0026] In some embodiments, the preparation method further includes: stacking a plurality of the device component layers in a second direction, where the second direction is a stacking direction of the device component layers and the packaging substrate; and electrically connecting two adjacent bare chips in the second direction.

[0027] In some embodiments, electrically connecting the two adjacent bare chips in the second direction includes: providing a metal lead, so that two ends of the metal lead are respectively connected to surfaces of the two adjacent bare chips along the second direction.

[0028] In some embodiments, providing multiple bare chips includes: forming conductive vias on the bare chips; electrically connecting two adjacent bare chips in the second direction includes: providing a bonding member so that the bonding member is connected between the conductive vias of two adjacent bare chips along the second direction.

[0029] It can be understood that the beneficial effects that can be achieved by the method for preparing the semiconductor packaging structure provided by the above embodiments of the present disclosure can refer to the beneficial effects of the semiconductor packaging structure described above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0031] Figure 1is a schematic structural diagram of a semiconductor package structure according to some embodiments;

[0032] Figure 2 is a schematic structural diagram of a semiconductor package structure according to some embodiments;

[0033] Figure 3 is a schematic structural diagram of a semiconductor package structure according to some embodiments;

[0034] Figure 4 is a schematic structural diagram of a semiconductor package structure according to some embodiments;

[0035] Figure 5 is a schematic structural diagram of a semiconductor package structure according to some embodiments;

[0036] Figure 6 is a schematic structural diagram of a semiconductor package structure according to some embodiments;

[0037] Figure 7 for Figure 6 Cross-sectional view of AA in the middle;

[0038] Figure 8 is a schematic structural diagram of a semiconductor package structure according to some embodiments;

[0039] Fig. 9 is a schematic structural diagram of a semiconductor package structure according to some embodiments;

[0040] Fig.10 is a schematic structural diagram of a die according to some embodiments;

[0041] Fig.11 is a schematic structural diagram of a semiconductor package structure according to some embodiments;

[0042] Fig.12 is a flow chart of a method for preparing a semiconductor package structure according to some embodiments;

[0043] Fig.13 is a flow chart of a method for preparing a semiconductor package structure according to some embodiments;

[0044] Fig.14 is a schematic diagram of a method for preparing a die according to some embodiments;

[0045] Fig.15 is a schematic diagram of a method for preparing a die according to some embodiments;

[0046] Fig.16 is a schematic diagram of a method for preparing a die according to some embodiments;

[0047] Fig.17is a schematic diagram of a method for preparing a die according to some embodiments;

[0048] Fig.18 is a schematic diagram of a method for preparing a die according to some embodiments;

[0049] Fig.19 is a schematic diagram of a method for preparing a die according to some embodiments. DETAILED DESCRIPTION

[0050] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0051] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0052] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0053] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0054] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0055] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0056] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0057] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0058] In the context of the present disclosure, the meanings of “on,” “over,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “over” or “above” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something without intervening features or layers therebetween (i.e., directly on something).

[0059] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0060] As used herein, the term "substrate" refers to a material on which subsequent material layers may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0061] Figure 1 is a schematic structural diagram of a semiconductor package structure according to some embodiments.

[0062] like Figure 1 As shown, in some embodiments, the semiconductor package structure 1' includes a package substrate 20' and a device component layer 10'. The device component layer 10' is located on one side of the package substrate 20' and is connected to the package substrate 20'. The semiconductor package structure 1' in this embodiment uses the Embedded Multi-Die Interconnect Bridge (EMIB) technology to transmit signals between multiple dies. Figure 1 As shown, the embedded multi-die interconnection bridge A' can be embedded in the packaging substrate 20' and electrically coupled to the packaging substrate 20'. The present disclosure takes the direction parallel to the packaging substrate 20' as the first direction X as an example to explain and illustrate the embodiments below. The device component layer 10' includes a plurality of bare chips arranged at intervals along the first direction X. The device component layer 10' in this embodiment includes a first bare chip 11' and a second bare chip 12', and the first bare chip 11' and the second bare chip 12' are arranged at intervals on the packaging substrate 20'. Among them, the first bare chip 11' is electrically connected to the packaging substrate 20' and the embedded multi-die interconnection bridge A'. The second bare chip 12' is electrically connected to the packaging substrate 20' and the embedded multi-die interconnection bridge A'. The embedded multi-die interconnection bridge A' can realize signal transmission between the first bare chip 11' and the second bare chip 12'.

[0063] Alternatively, the first die 11 ′ and the second die 12 ′ in the semiconductor package structure 1 ′ may be connected to each other by conductive wires, thereby realizing signal transmission between the die.

[0064] However, there is a large gap between the first bare chip 11' and the second bare chip 12' in the semiconductor packaging structure 1' of the above embodiment, so that the device component layer 10' occupies a large area on the packaging substrate 20', and the more bare chips are packaged, the larger the area occupied by the device component layer 10' on the packaging substrate 20', which is not conducive to packaging more bare chips, nor is it conducive to the miniaturization of electronic devices.

[0065] Since the device component layer 10' in some embodiments occupies a large area on the package substrate 20', the area of ​​the semiconductor package structure 1' is large. Figure 2 As shown, some embodiments of the present disclosure provide a semiconductor package structure 1, wherein the device component layer 10 further includes a plurality of connectors 12, each connector 12 being located between two adjacent bare chips 11, and each connector 12 is respectively connected to the two bare chips 11. Exemplarily, the connector 12 may include a solder ball structure or a wire.

[0066] It should be noted that “each connector 12 is located between two adjacent bare chips 11” means that Figure 2 As shown, each connecting member 12 is located between opposite side walls of two adjacent dies 11 along the first direction X.

[0067] In this embodiment, Figure 2 As shown, a conductive contact point can be drawn out on the side wall of the die 11, and the connector 12 is connected to the conductive contact points on the side walls of two adjacent die 11 along the first direction X, so as to realize signal transmission between the two die 11. Through the above arrangement, the interval between the adjacent die 11 along the first direction X can be reduced. Therefore, the semiconductor packaging structure 1 provided by the present disclosure is conducive to reducing the area occupied by the die 11 on the packaging substrate 20 and improving the packaging density of the die 11. In addition, the connection distance between the two adjacent die 11 can be shortened, so the resistance between the two adjacent die 11 is reduced, which is conducive to improving the signal transmission speed between the die 11.

[0068] In some embodiments, Figure 3 and Figure 4 As shown, the die 11 includes a central portion 112, a sealing ring 113 and a peripheral portion 114, wherein the sealing ring 113 is located between the central portion 112 and the peripheral portion 114. The sealing ring 113 can seal the central portion 112.

[0069] The die 11 further includes a plurality of conductive layers 111, which may be located in a central portion 112 of the die 11. The connector 12 is connected to the conductive layers 111 of adjacent die 11. Exemplarily, the die 11 may further include a lead 115, which penetrates the sealing ring 113, one end of which extends into the central portion 112 and is connected to the conductive layer 111, and the other end of which extends to the surface of the peripheral portion 114 and is connected to the connector 12, thereby realizing signal transmission between adjacent die 11. Exemplarily, the lead 115 may include a conductive line 1151.

[0070] It should be noted that “the other end of the lead-out member 115 extends to the surface of the peripheral portion 114” means that the other end of the lead-out member 115 extends to the peripheral surface of the peripheral portion 114, and the peripheral surface of the peripheral portion 114 can expose the other end of the lead-out member 115, and the exposed lead-out member 115 is the conductive contact point in the above embodiment. Alternatively, the other end of the lead-out member 115 can extend beyond the peripheral surface of the peripheral portion 114 to facilitate connection with the connector 12.

[0071] Exemplarily, there may be multiple lead-out members 115 , and there may also be multiple connectors 12 . One lead-out member 115 of one die 11 is connected to one lead-out member 115 of another die 11 via one connector 12 .

[0072] Through the above arrangement, the connector 12 can be connected to the conductive layers 111 of the adjacent bare chips 11 along the first direction X, so that signal transmission between adjacent bare chips 11 is realized. In addition, the interval between adjacent bare chips 11 can be reduced, which is beneficial to reducing the area occupied by the bare chips 11 on the packaging substrate 20 and improving the packaging density of the bare chips 11. At the same time, the connection distance between two adjacent bare chips 11 can be shortened, and the resistance between the two adjacent bare chips 11 is reduced, which is beneficial to improving the signal transmission speed between the bare chips 11.

[0073] In some embodiments, Figure 3 and Figure 4 As shown, one end of the connector 12 contacts the peripheral portion 114 of one die 11, and the other end of the connector 12 contacts the peripheral portion 114 of another die 11. Exemplarily, when the connector 12 is a conductive wire 1151, one end of the conductive wire 1151 contacts the lead-out piece 115 exposed from the peripheral portion 114 of one die 11, and the other end of the conductive wire 1151 contacts the lead-out piece 115 exposed from the peripheral portion 114 of another die 11, so that the conductive wire 1151 is electrically connected to the conductive layer 111 of the adjacent die 11. Exemplarily, when the connector 12 is a solder ball structure, one end of the solder ball structure contacts the lead-out piece 115 exposed from the peripheral portion 114 of one die 11, and the other end of the solder ball structure contacts the lead-out piece 115 exposed from the peripheral portion 114 of another die 11, so that the solder ball structure is electrically connected to the conductive layer 111 of the adjacent die 11.

[0074] In some embodiments, Figure 4 As shown, the surface area of ​​the lead-out member 115 exposed to the peripheral portion 114 is smaller than the positive projection area of ​​the connector 12 on the peripheral portion 114. This arrangement makes it easier for the connector 12 to contact the portion of the surface of the lead-out member 115 exposed to the peripheral portion 114, thereby facilitating the connection of the connector 12 with the lead-out member 115.

[0075] In some embodiments, Figure 4 As shown, the lead-out member 115 includes a conductive line 1151 and an isolation layer 1152, and the isolation layer 1152 is located between the conductive line 1151 and the sealing ring 113. The sealing ring 113 generally includes a conductive material. The isolation layer 1152 can be made of an insulating material, for example, the insulating material can be a combination of one or more of silicon oxide, silicon nitride, and a high dielectric constant insulating material, or other materials with insulating functions. Therefore, the isolation layer 1152 can isolate the conductive line 1151 from the sealing ring 113, which is beneficial to improving the safety of the bare die 11.

[0076] In some embodiments, Figure 4 As shown, the extension direction of the lead-out member 115 is perpendicular to the surface of the peripheral portion 114, so that the extension length of the lead-out member 115 is the shortest, which is beneficial to cost saving. In addition, the distance between the conductive layer 111 and the connecting member 12 is the shortest, the connection distance between two adjacent bare chips 11 is shortened, and the resistance between adjacent bare chips 11 is reduced, which is beneficial to improving the signal transmission speed between the bare chips 11.

[0077] In some embodiments, Figure 4 As shown, the connector 12 may include a hybrid bonding structure, a bump structure or a solder ball structure. The connector 12 is connected to the lead-out member 115 exposed on the peripheral surface of two adjacent bare chips 11 along the first direction X, so as to realize signal transmission between the two bare chips 11. Through the above arrangement, the interval between the adjacent bare chips 11 along the first direction X is reduced. Therefore, the semiconductor packaging structure 1 provided by the present disclosure is conducive to reducing the area occupied by the bare chip 11 on the packaging substrate 20, and improving the density of the bare chip 11 packaging. In addition, the connection distance between the two adjacent bare chips 11 can be shortened, so the resistance between the two adjacent bare chips 11 is reduced, which is conducive to improving the signal transmission speed between the bare chips 11.

[0078] Figure 5 FIG. 1 is a schematic diagram of a semiconductor package structure according to some embodiments. Figure 5 As shown, when packaging multiple bare chips 11, the multiple bare chips 11 can be stacked and arranged, and the following explanation is taken as an example that the stacking direction of the bare chips 11 is the second direction Y. The multiple bare chips 11 stacked along the second direction Y are sequentially staggered along the first direction X by a distance, but not completely staggered, so that the bare chips 11 adjacent to each other along the second direction Y are interconnected through the conductive wires 1151. Figure 5 As shown, there is a certain interval d between the adjacent dies 11 along the first direction X. In this embodiment, compared with the die of a single-layer package, the die 11 occupies a larger space in the first direction X of the package substrate 20 ′.

[0079] Based on this, in some embodiments of the present disclosure, the semiconductor package structure 1 is provided, such as Figure 6and Figure 7 As shown, the conductor packaging structure 1 may include a plurality of device component layers 10, and the plurality of device component layers 10 are stacked along the second direction Y, and two adjacent bare chips 11 along the second direction Y are connected. In this embodiment, two adjacent bare chips 11 along the first direction X are interconnected by a connector 12, and the connector 12 is located between the side walls of the two adjacent bare chips 11. Compared with the above-mentioned interconnection between bare chips that needs to be connected to the intermediate layer through a conductive wire, the technical solution provided by this embodiment can shorten the interval between the adjacent bare chips 11 along the first direction X, which is conducive to reducing the area occupied by the bare chip 11 on the packaging substrate 20, and improving the density of the bare chip 11 packaging. In addition, the connection distance between the two adjacent bare chips 11 can be shortened, and the resistance between the two adjacent bare chips 11 is reduced, which is conducive to improving the signal transmission speed between the bare chips 11.

[0080] In some embodiments, Figure 6 and Figure 7 As shown, the semiconductor package structure 1 further includes an insulating structure 30, and the insulating structure 30 is located between two adjacent bare chips 11 along the first direction X. The insulating structure 30 covers the peripheral surface of the connector 12, and the connector 12 is located in the insulating structure 30. The insulating structure 30 is provided to insulate the connectors 12 from each other, which is beneficial to improving the safety of the semiconductor package structure 1.

[0081] In some embodiments, Figure 8 As shown, multiple device component layers 10 are staggered in sequence along the first direction X, and multiple device component layers 10 overlap along the second direction. The staggered directions of the multiple device component layers 10 are consistent, for example Figure 8 In any two adjacent device component layers 10, the upper device component layer 10 is moved to the right by a certain distance, so that a portion of the upper surface of the device component layer 10 is reserved, so as to facilitate the interconnection of the device component layers 10 stacked along the second direction Y. The staggered distances of the multiple device component layers 10 along the first direction X can be the same or different. In this embodiment, Figure 8 As shown, the distances of the multiple device component layers 10 staggered along the first direction X are the same.

[0082] In some embodiments, Figure 8As shown, the die 11 includes a first surface 1101 and a second surface 1102 arranged along the second direction Y. The first surface 1101 and the second surface 1102 are arranged relatively to each other along the second direction Y. The semiconductor package structure 1 also includes a metal lead 40, and the metal lead 40 is electrically connected between the first surfaces 1101 of two adjacent die 11 along the second direction Y, or the metal lead 40 is electrically connected between the second surfaces 1102 of two adjacent die 11 along the second direction. Through the above arrangement, communication and interconnection between the adjacent die 11 along the second direction Y can be achieved.

[0083] In some embodiments, Fig. 9 As shown, the edges of two adjacent device component layers 10 along the second direction Y are flush. In this way, the area occupied by the device component layer 10 on the packaging substrate 20 is further reduced, the packaging density of the bare die 11 on the packaging substrate 20 is increased, and the size of the semiconductor packaging structure 1 is reduced.

[0084] In some embodiments, Fig. 9 and Fig.10 As shown, the die 11 further includes a conductive via 116 penetrating the die along the second direction Y. The semiconductor package structure 1 further includes a bonding member 117, and the bonding member 117 is connected between the conductive vias 116 of two adjacent die 11 along the second direction Y. Fig.10 In the embodiment, the bonding member 117 is connected between the die B and the die C. For example, the conductive via 116 may include a through silicon via. The conductive vias 116 of two adjacent dies 11 along the second direction Y are connected by the bonding member 117 to achieve communication and interconnection between the adjacent dies 11 along the second direction Y.

[0085] In some embodiments, Figure 7 and Figure 8 As shown, in two adjacent device component layers 10, the connectors 12 of one device component layer 10 are arranged alternately with the connectors 12 of the other device component layer 10 in the second direction Y. Figure 7 and Figure 8As shown, "a connector 12 of a layer of device component layer 10" refers to a connector 12 between two adjacent bare chips 11 along a first direction X. A layer of device component layer 10 may include a plurality of connectors 12, and the connectors 12 in two adjacent layers of device component layers 10 along a second direction Y are staggered in the second direction Y. Exemplarily, the connectors 12 of the first layer of device component layer 10 above the package substrate are arranged at intervals, and the connectors 12 of the second layer of device component layer 10 above the package substrate are arranged at intervals, and the connectors 12 of the first layer of device component layer 10 are staggered with the connectors 12 of the second layer of device component layer 10 in the second direction Y. The connectors 12 in the first layer of device component layer 10 and the connectors 12 in the second layer of device component layer 10 can be alternately stacked. The above arrangement is conducive to preventing short circuits caused by accidental touch between the connectors 12, thereby improving the safety of the semiconductor packaging structure 1.

[0086] In some embodiments, Fig.11 As shown, when multiple bare chips 11 are packaged on one side of the packaging substrate 20, the multiple bare chips 11 can be arranged in multiple rows and columns. Two adjacent bare chips 11 along the row direction are connected by a connector 12, and the connector 12 is located between the side walls of the two adjacent bare chips 11. Fig.11 2 shows two rows and two columns of bare chips 11. In the column direction, a group of two adjacent bare chips 11 are connected by a connector 12, and the connector 12 is located between the side walls of the two adjacent bare chips 11 along the column direction. When packaging multiple rows and multiple columns of bare chips, among any two rows of bare chips 11 adjacent in the column direction, at least one group of two adjacent bare chips 11 along the column direction is connected by a connector 12. Through the above arrangement, the space occupied by the bare chips 11 on the packaging substrate 20 can be reduced, and the packaging density of the bare chips 11 can be improved. In addition, the connection distance between two adjacent bare chips 11 is shortened, and the resistance between the two adjacent bare chips 11 is reduced, which is conducive to improving the signal transmission speed between the bare chips 11.

[0087] Some embodiments of the present disclosure also provide a method for preparing a semiconductor packaging structure 1, such as Fig.12 As shown, it includes: S1~S6.

[0088] S1. Provide a packaging substrate.

[0089] In the above steps, if Fig. 9 and Fig.10 As shown, the package substrate 20 may be a circuit board with a wiring circuit, or may be a substrate formed of silicon (e.g., single crystal silicon), ceramic, glass, or any other appropriate material. In some embodiments, the package substrate 20 may be provided with a plurality of structures for forming electrical connections, such as a pad structure located on the upper surface of the package substrate 20, a contact structure located on the lower surface of the package substrate 20, and a circuit structure located inside the package substrate 20.

[0090] S2. Provide multiple bare chips and multiple connectors.

[0091] In the above steps, illustratively, a plurality of bare chips are provided, such as Fig.13 As shown, it may include S21 to S23.

[0092] S21. Provide a first structural layer, wherein the first structural layer includes a first central portion, a first sealing ring, and a first peripheral portion, wherein the first sealing ring is located between the first central portion and the first peripheral portion.

[0093] In the above steps, if Fig.14 As shown, a deposition process may be used to deposit semiconductor materials to form a first central portion 61 , a first sealing ring 63 , and a first peripheral portion 62 . The first central portion 61 , the first sealing ring 63 , and the first peripheral portion 62 together constitute a first structural layer 60 .

[0094] S22. Form a second structural layer on the first structural layer, the second structural layer including a second central portion, a second sealing ring, a second peripheral portion and a lead-out piece, the second sealing ring being located between the second central portion and the second peripheral portion, and the lead-out piece being arranged between the second central portion, the second sealing ring and the second peripheral portion.

[0095] In the above steps, if Fig.15 As shown, when forming the second structure layer 70 , the conductive layer 111 and the lead-out member 115 are formed simultaneously, so that the conductive layer 111 is electrically connected to one end of the lead-out member 115 , and the other end of the lead-out member 115 is connected to the connector 12 , thereby achieving communication and interconnection between the bare chips 11 .

[0096] In some embodiments, Fig.14 , Fig.15 , Fig.16 and Fig.17 As shown, in step S22, forming a second structure layer on the first structure layer may include:

[0097] A base layer 50 is formed. The base layer 50 includes a central area 51 , a sealing area 53 and a peripheral area 52 . The sealing area 53 is located between the central area 51 and the peripheral area 52 .

[0098] Exemplarily, in the above steps, the base layer 50 can be formed by a deposition process, that is, the central area 51, the sealing area 53 and the peripheral area 52 can be formed simultaneously by a deposition process. The base layer 50 is subjected to a photolithography process to form a second sealing ring 73 in a portion of the sealing area 53, and at the same time, a conductive line 1151 is formed in a portion of the central area 51, a portion of the sealing area 53 and a portion of the peripheral area 52; wherein the portion of the base layer 50 retained in the sealing area 53 constitutes an isolation layer 1152.

[0099] In the above steps, the conductive wire 1151 formed in part of the central area 51, part of the sealing area 53 and part of the peripheral area 52 has one end extending to the peripheral surface of the base layer 50 in the peripheral area 52, and the other end extending to connect with the conductive layer 111 located in the central area 51. The part of the base layer 50 retained in the sealing area 53 constitutes an isolation layer 1152. The isolation layer 1152 can help isolate the conductive wire 1151 from the sealing ring to prevent leakage.

[0100] In other embodiments, Fig.17 and Fig.18 As shown, a second structure layer 70 is formed on the first structure layer 60, including:

[0101] A base layer 50 is formed. The base layer 50 includes a central area 51 , a sealing area 53 and a peripheral area 52 . The sealing area 53 is located between the central area 51 and the peripheral area 52 .

[0102] In the above steps, illustratively, the base layer 50 may be formed by a deposition process, that is, the central region 51 , the sealing region 53 , and the peripheral region 52 may be formed simultaneously by a deposition process.

[0103] A portion of the base layer 50 located in the sealing area 53 is removed to form a first groove 54 . The first groove 54 is disposed along a portion of the edge of the central area 51 .

[0104] In the above steps, if Fig.18 As shown, an etching process can be used to remove part of the base layer 50 located in the sealing area 53, and a first groove 54 can be formed in part of the sealing area 53. The first groove 54 is arranged at a part of the edge of the central area 51, that is, the first groove 54 is located between the base layer 50 in the central area 51 and the base layer 50 in the peripheral area 52. From a top view, the first groove 54 is annular with a gap, and the "gap" is the part of the base layer 50 retained in the sealing area 53. Exemplarily, the first groove 54 can be formed by a photolithography process.

[0105] After the first groove 54 is formed in the partial sealing area 53 , a second sealing ring 73 is formed in the first groove 54 .

[0106] In the above steps, after the first groove 54 is formed, a metal material may be deposited in the first groove 54 by a deposition process to form the second sealing ring 73 .

[0107] After forming the second sealing ring 73 , the remaining base layer 50 in the sealing area 53 , the base layer 50 in the central area 51 , and the base layer 50 in the peripheral area 52 are removed to form a second groove 55 , which is spaced apart from the first groove 54 .

[0108] A conductive line 1151 is formed in the second groove 55 .

[0109] In the above steps, after forming the second sealing ring 73, an etching process may be used to remove the middle portion of the remaining part of the base layer 50 located in the sealing area 53, the part of the base layer 50 located in the central area 51, and the part of the base layer 50 located in the peripheral area 52 to form a second groove 55. "The second groove 55 is spaced apart from the first groove 54" means that there is a remaining part of the base layer 50 located in the sealing area 53 between the second groove 55 and the first groove 54, so the second groove 55 is spaced apart from the first groove 54. The etching process is used to remove the part of the base layer 50 remaining in the middle of the sealing area 53 to form the second groove 55. At the same time, the etching process is performed on the part of the central area 51 and the part of the peripheral area 52 so that the second groove 55 extends to the peripheral surface of the base layer 50 in the peripheral area 52, and the second groove 55 extends to the conductive layer 111 in the central area 51. After forming the second groove 55, a deposition process may be used to deposit a conductive material in the second groove 55 to form a conductive line 1151. The part of the base layer 50 remaining in the sealing area 53 constitutes an isolation layer 1152. The isolation layer 1152 can help isolate the conductive wire 1151 from the sealing ring 113 to prevent leakage.

[0110] S23, forming a third structural layer on a side of the second structural layer away from the first structural layer, the third structural layer comprising a third central portion, a third sealing ring and a third peripheral portion, the third sealing ring being located between the third central portion and the third peripheral portion.

[0111] Among them, Fig.14 , Fig.15 and Fig.19 As shown, in the above steps, the first central portion 61, the second central portion 71 and the third central portion 81 together constitute the central portion 112. The first sealing ring 63, the second sealing ring 73 and the third sealing ring 83 together constitute the sealing ring 113. The first peripheral portion 62, the second peripheral portion 72 and the third peripheral portion 82 together constitute the peripheral portion 114. The conductive wire 1151 and the isolation layer 1152 together constitute the lead-out member 115. Among them, the central portion 112 includes a plurality of conductive layers 111, one end of the conductive wire 1151 is connected to the conductive layer 111 of the central portion 112, and the other end of the conductive wire 1151 extends to the peripheral surface of the peripheral portion 114, which is conducive to the connection between the bare chip 11 and the connector 12.

[0112] S3. Connect each connector to two bare chips in a first direction respectively to form a device component layer; the first direction is parallel to the packaging substrate; wherein the device component layer is located on one side of the packaging substrate and connected to the packaging substrate.

[0113] In the above steps, if Figure 6 , Figure 7 and Figure 8As shown, exemplarily, the connector 12 may include a solder ball structure. Each connector 12 is connected to the lead-out members 115 exposed on the side walls of the two bare chips 11 in the first direction X, respectively, to achieve communication and interconnection between the bare chips 11. The interval between adjacent bare chips 11 is reduced, which is conducive to reducing the area occupied by the bare chips 11 on the packaging substrate 20 and improving the density of the bare chip 11 packaging. In addition, the connection distance between the two adjacent bare chips 11 can be shortened, and the resistance between the two adjacent bare chips 11 is reduced, which is conducive to improving the signal transmission speed between the bare chips 11.

[0114] S4. Filling insulating material between two adjacent bare chips along the first direction to form an insulating structure.

[0115] For example, in the above steps, Figure 6 , Figure 7 and Figure 8 As shown, a deposition process can be used to deposit insulating material between two adjacent bare chips 11 along a first direction to form an insulating structure 30, thereby isolating the connectors 12 to prevent accidental contact between the connectors 12 to cause a short circuit, which is beneficial to improving the safety of the semiconductor packaging structure 1.

[0116] S5. Stack a plurality of device component layers in a second direction, where the second direction is a stacking direction of the device component layers and the packaging substrate.

[0117] In the above steps, if Figure 6 , Figure 7 , Figure 8 and Fig. 9 As shown, exemplarily, when stacking a plurality of device component layers 10 along the second direction Y, the edges of the plurality of device component layers 10 can be flushed to reduce the area occupied by the device component layers 10 on the packaging substrate 20, which is beneficial to improve the packaging density of the bare chip 11. Exemplarily, when stacking a plurality of device component layers 10 along the second direction Y, the plurality of device component layers 10 can be staggered in sequence along the first direction X, and the plurality of device component layers 10 are overlapped in the second direction Y, so as to facilitate electrical connection between the plurality of device component layers 10 along the second direction Y.

[0118] S6. Electrically connect two adjacent bare chips in the second direction.

[0119] In some embodiments, Figure 8 As shown, when multiple device component layers 10 are staggered in sequence along the first direction X, electrically connecting two adjacent bare chips 11 in the second direction Y may include: providing a metal lead 40 so that the two ends of the metal lead 40 are respectively connected to the surfaces of the two adjacent bare chips 11 along the second direction.

[0120] Through the above arrangement, two adjacent bare chips 11 in the second direction Y can be electrically connected to achieve communication and interconnection between the bare chips 11 .

[0121] In other embodiments, Fig. 9 and Fig.10 As shown, when the edges of a plurality of device component layers 10 are flush, conductive vias 116 may be formed on the dies 11 when a plurality of dies 11 are provided.

[0122] Electrically connecting two adjacent bare chips 11 in the second direction Y includes: providing a bonding element 117 so that the bonding element 117 is connected between the conductive through holes 116 of the two adjacent bare chips 11 along the second direction.

[0123] Through the above arrangement, two adjacent bare chips 11 in the second direction Y can be electrically connected to achieve communication and interconnection between the bare chips 11 .

[0124] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A semiconductor packaging structure, It is characterized in that include: Package substrate; A device component layer is located on one side of the packaging substrate and connected to the packaging substrate, wherein the device component layer includes a plurality of bare chips spaced apart along a first direction, wherein the first direction is parallel to the packaging substrate; the device component layer also includes a plurality of connectors, each of which is located between two adjacent bare chips and is respectively connected to the two bare chips.

2. The semiconductor package structure according to claim 1, It is characterized in that The die includes a conductive layer; The connecting members are connected to the conductive layers of the adjacent dies.

3. The semiconductor package structure according to claim 2, It is characterized in that The die comprises a central portion, a sealing ring and a peripheral portion, wherein the sealing ring is located between the central portion and the peripheral portion, and the conductive layer is located in the central portion; The die also includes a lead-out piece that passes through the sealing ring, one end of the lead-out piece extends into the central portion and is connected to the conductive layer, and the other end of the lead-out piece extends to the surface of the peripheral portion and is connected to the connector.

4. The semiconductor package structure according to claim 3, It is characterized in that One end of the connector contacts the outer periphery of one of the die, and the other end of the connector contacts the outer periphery of the other die.

5. The semiconductor package structure according to claim 3, It is characterized in that An area of ​​the surface of the lead-out member exposed to the peripheral portion is smaller than an area of ​​an orthographic projection of the connecting member on the peripheral portion.

6. The semiconductor package structure according to claim 3, It is characterized in that The lead-out member includes a conductive line and an isolation layer, and the isolation layer is located between the conductive line and the sealing ring.

7. The semiconductor package structure according to claim 3, It is characterized in that The leading piece extends in a direction perpendicular to a surface of the peripheral portion.

8. The semiconductor package structure according to any one of claims 1 to 7, It is characterized in that The connecting member includes a hybrid bonding structure, a bump structure or a solder ball structure.

9. The semiconductor package structure according to any one of claims 1 to 7, It is characterized in that There are multiple device component layers, and the multiple device component layers are stacked along a second direction, and two adjacent bare chips along the second direction are connected. The second direction is the stacking direction of the device component layers and the packaging substrate.

10. The semiconductor package structure according to claim 9, It is characterized in that It also includes an insulating structure, where the insulating structure is located between two of the bare chips adjacent to each other along the first direction, and the connecting member is located in the insulating structure.

11. The semiconductor package structure according to claim 10, It is characterized in that The plurality of device component layers are staggered in sequence along the first direction, and the plurality of device component layers are overlapped along the second direction.

12. The semiconductor package structure according to claim 11, It is characterized in that The die includes a first surface and a second surface disposed along the second direction; The semiconductor package structure further includes a metal lead, wherein the metal lead is electrically connected between the first surfaces of two adjacent bare chips along the second direction, or the metal lead is electrically connected between the second surfaces of two adjacent bare chips along the second direction.

13. The semiconductor package structure according to claim 10, It is characterized in that The edges of two device component layers adjacent to each other along the second direction are flush.

14. The semiconductor package structure according to claim 13, It is characterized in that The die also includes a conductive via extending therethrough along the second direction; The semiconductor package structure further includes a bonding component connected between the conductive vias of two adjacent bare chips along the second direction.

15. The semiconductor package structure according to claim 13, It is characterized in that In two adjacent device component layers, the connecting members of one device component layer and the connecting members of the other device component layer are arranged alternately in the second direction.

16. A method for preparing a semiconductor packaging structure, It is characterized in that include: Providing a packaging substrate; Providing a plurality of bare dies and a plurality of connectors; Connecting each of the connecting members to the two bare chips in a first direction to form a device component layer; The first direction is parallel to the packaging substrate; wherein the device component layer is located on one side of the packaging substrate and is connected to the packaging substrate.

17. The method for preparing a semiconductor packaging structure according to claim 16, It is characterized in that Provide bare die, including: Providing a first structural layer, the first structural layer comprising a first central portion, a first sealing ring and a first peripheral portion, the first sealing ring being located between the first central portion and the first peripheral portion; forming a second structural layer on the first structural layer, wherein the second structural layer comprises a second central portion, a second sealing ring, a second peripheral portion, and a lead-out member, wherein the second sealing ring is located between the second central portion and the second peripheral portion, and the lead-out member is disposed between the second central portion, the second sealing ring, and the second peripheral portion; forming a third structural layer on a side of the second structural layer away from the first structural layer, the third structural layer comprising a third central portion, a third sealing ring and a third peripheral portion, the third sealing ring being located between the third central portion and the third peripheral portion; Among them, the first central part, the second central part and the third central part together constitute a central part; the first sealing ring, the second sealing ring and the third sealing ring together constitute a sealing ring; the first peripheral part, the second peripheral part and the third peripheral part together constitute a peripheral part.

18. The method for preparing a semiconductor packaging structure according to claim 17, It is characterized in that The forming of the second structural layer on the first structural layer comprises: forming a base layer, the base layer comprising a central area, a sealing area and a peripheral area, wherein the sealing area is located between the central area and the peripheral area; The base layer is subjected to a photolithography process to form a second sealing ring in part of the sealing area, and at the same time, conductive lines are formed in part of the central area, part of the sealing area and part of the peripheral area; wherein the base layer remains in the sealing area to form an isolation layer.

19. The method for preparing a semiconductor packaging structure according to claim 17, It is characterized in that The forming of the second structural layer on the first structural layer comprises: forming a base layer, the base layer comprising a central area, a sealing area and a peripheral area, wherein the sealing area is located between the central area and the peripheral area; Removing a portion of the base layer located in the sealing area to form a first groove, wherein the first groove is arranged along a portion of the edge of the central area; forming the second sealing ring in the first groove; Removing the remaining portion of the base layer located in the sealing area, the portion of the base layer located in the central area, and the portion of the base layer located in the peripheral area to form a second groove, wherein the second groove is spaced apart from the first groove; A conductive line is formed in the second groove.

20. The method for preparing a semiconductor packaging structure according to claim 16, It is characterized in that After forming the device component layer, the method further includes: An insulating material is filled between two adjacent bare chips along the first direction to form an insulating structure.

21. The method for preparing a semiconductor packaging structure according to any one of claims 16 to 20, It is characterized in that The preparation method further comprises: A plurality of the device component layers are stacked in a second direction, wherein the second direction is a stacking direction of the device component layers and the packaging substrate; Two adjacent bare chips in the second direction are electrically connected.

22. The method for preparing a semiconductor packaging structure according to claim 21, It is characterized in that The step of electrically connecting two adjacent bare chips in the second direction comprises: A metal lead is provided, so that two ends of the metal lead are respectively connected to surfaces of two of the bare chips adjacent to each other along the second direction.

23. The method for preparing a semiconductor packaging structure according to claim 21, It is characterized in that The providing of a plurality of bare chips includes: forming conductive vias on the bare chips; The electrically connecting the two adjacent bare chips in the second direction includes: providing a bonding component, so that the bonding component is connected between the conductive through holes of the two adjacent bare chips in the second direction.

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