Semiconductor device and manufacturing method thereof

Abstract

The present disclosure provides a semiconductor device and a method of manufacturing the same, the semiconductor device comprising: a substrate, and disposed on the substrate: a first transistor comprising a gate region, a source region, and a drain region; a first polysilicon resistor connected between the gate region and the drain region; the second polycrystalline silicon resistor is connected between the drain electrode region and the source electrode region; wherein the second polycrystalline silicon resistor comprises a first divider resistor and a second divider resistor which are connected in series; the voltage of the connecting end of the first divider resistor and the second divider resistor is obtained and used for representing the voltage between the source region and the drain region. According to the semiconductor device, the polycrystalline silicon divider resistor is arranged on the substrate, so that the purpose of detecting the voltage at the source end and the drain end of the transistor is achieved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor devices, and more particularly, to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Accumulation-mode High Voltage Field-Effect Transistor is a special type of field effect transistor (FET) that is usually used in high voltage applications. In ordinary field effect transistors, the electric field controls the conductivity of the channel through the gate. In accumulation-mode high voltage FETs, the electric field forms a low-resistance channel by accumulating a charge layer (referred to as accumulation layer) on the surface of the drift region, which helps to optimize the trade-off between withstand voltage and specific on-resistance. Due to its special structural design, accumulation-mode high voltage FET can provide higher withstand voltage capability and lower on-resistance, thereby providing better performance in high voltage environments.

[0003] However, since the voltage applied between the source and drain of the accumulation-type high-voltage FET is too high, it is inconvenient to detect directly. Therefore, it is necessary to provide a new semiconductor device and a manufacturing method thereof to improve the above-mentioned problem. Summary of the invention

[0004] In view of the above problems, the present disclosure provides a semiconductor device and a method for manufacturing the same, in which a polysilicon voltage divider resistor is arranged on a substrate to detect the voltage across a source and a drain of a transistor.

[0005] According to one aspect of an embodiment of the present disclosure, there is provided a semiconductor device, including:

[0006] A substrate, and disposed on the substrate:

[0007] A first transistor including a gate region, a source region and a drain region;

[0008] a first polysilicon resistor connected between the gate region and the drain region;

[0009] a second polysilicon resistor connected between the drain region and the source region;

[0010] The second polysilicon resistor includes a first voltage-dividing resistor and a second voltage-dividing resistor connected in series; the voltage at the connection end of the first voltage-dividing resistor and the second voltage-dividing resistor is obtained to characterize the voltage between the source region and the drain region.

[0011] Optionally, a second transistor is further included, which has the same gate region, source region and drain region as the first transistor.

[0012] Optionally, it also includes:

[0013] a drift region extending from a surface of the substrate into the substrate;

[0014] a well region extending from a surface of the substrate into the substrate; and

[0015] a dielectric layer, located on the substrate, covering at least a portion of the drift region and the well region between the drift region and the source region,

[0016] The source region is located in the well region, the drain region is located in the drift region, and the first polysilicon resistor, the second polysilicon resistor and the gate region are located on the dielectric layer.

[0017] Optionally, it further includes an interconnection portion located above the first polysilicon resistor and the second polysilicon resistor,

[0018] The first polysilicon resistor discontinuously surrounds the drain region, and the discontinuities of the first polysilicon resistor are connected through the interconnection portion.

[0019] The second polysilicon resistor is located at a discontinuity of the first polysilicon resistor and is separated from the first polysilicon resistor.

[0020] Optionally, an isolation layer is further included, covering the first polysilicon resistor and the second polysilicon resistor.

[0021] The interconnection portion includes a conductive plug and a conductive connection layer, wherein the conductive plug penetrates the isolation layer and is connected to the end of the discontinuity of the first polysilicon resistor, and the conductive connection layer is located on the isolation layer and is connected to the conductive plug.

[0022] Optionally, the dielectric layer includes a gate dielectric layer and a field oxide layer.

[0023] The gate region and at least a portion of the first polysilicon resistor are located on the gate dielectric layer, a discontinuity of the first polysilicon resistor is located on the field oxide layer, and the second polysilicon resistor is located on the field oxide layer.

[0024] The thickness of the field oxide layer is greater than the thickness of the gate dielectric layer.

[0025] Optionally, when the first transistor is turned on, an accumulation layer is formed in the drift region.

[0026] When the first transistor is turned off, the first polysilicon resistor is used to adjust the electric field distribution in the drift region.

[0027] Optionally, the first polysilicon resistor is in a spiral strip shape or a semi-enclosed strip shape surrounding the drain region.

[0028] Optionally, the second polysilicon resistor is in a serpentine shape or a linear shape.

[0029] Optionally, the substrate and the well region are of a first doping type, and the drift region, the source region and the drain region are of a second doping type,

[0030] The first doping type is selected from one of P-type doping and N-type doping, and the second doping type is selected from the other of P-type doping and N-type doping.

[0031] Optionally, the first transistor is an accumulation-type transistor, and the second transistor is a non-accumulation-type transistor.

[0032] Optionally, the resistance values ​​of the first voltage-dividing resistor and the second voltage-dividing resistor are adjustable; and / or the width of the second polysilicon resistor is adjustable.

[0033] According to another aspect of an embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, for forming the semiconductor device as described above.

[0034] Optionally, the method comprises: selectively doping the second polysilicon resistor.

[0035] The second polysilicon resistor includes a first voltage-dividing resistor and a second voltage-dividing resistor connected in series, and the doping concentrations of polysilicon corresponding to the first voltage-dividing resistor and the second voltage-dividing resistor are different to adjust the resistance value and ratio of the first voltage-dividing resistor and the second voltage-dividing resistor.

[0036] Optionally, forming the source region and / or the drain region and selectively doping the second polysilicon resistor are performed in the same step.

[0037] One of the above technical solutions has the following beneficial effects:

[0038] A first transistor, a first polysilicon resistor and a second polysilicon resistor are arranged on a substrate. The first transistor includes a gate region, a source region and a drain region. The first polysilicon resistor is connected between the gate region and the drain region, and the second polysilicon resistor is connected between the drain region and the source region. The first polysilicon resistor can increase the voltage resistance of the device so that the device can be applied to a high-voltage environment. The second polysilicon resistor includes a first voltage-dividing resistor and a second voltage-dividing resistor connected in series. By detecting the voltage at the connection end of the first voltage-dividing resistor and the second voltage-dividing resistor, the purpose of detecting the voltage at both ends of the source and drain of the transistor is achieved.

[0039] In some embodiments, by setting a first polysilicon resistor that discontinuously surrounds the drain region on the dielectric layer, and the discontinuity is reconnected by the interconnection part, when the device is turned off, the first polysilicon resistor can act as a field plate to adjust the electric field in the drift region, thereby increasing the voltage resistance of the device. By setting a second polysilicon resistor at the discontinuity of the first polysilicon resistor, and making the two ends of the second polysilicon resistor electrically connected to the source region and the drain region respectively, the second polysilicon resistor is used to form a series voltage divider resistor, and the voltage applied between the source region and the drain region can be detected by the voltage divider resistor. Since the second polysilicon resistor is set at the discontinuity of the first polysilicon resistor, it is located above the drift region and does not occupy additional area in the device, and the discontinuity of the first polysilicon resistor is reconnected by the interconnection part, the second polysilicon resistor set in the device will not affect the electric field adjustment function of the first polysilicon resistor, and can also realize the voltage division detection function.

[0040] Furthermore, since the first polysilicon resistor and the second polysilicon resistor are separated from each other, the size of the second polysilicon resistor corresponding to the voltage divider resistor can be adjusted as needed without affecting the withstand voltage performance of the device.

[0041] In some embodiments, a first polysilicon resistor is disposed on a gate dielectric layer, and a second polysilicon resistor is disposed on a field oxide layer. Since the gate dielectric layer is relatively thin, when the device is turned on, the first polysilicon resistor can be used to form an accumulation layer in the drift region and then form a low-resistance path, thereby reducing the on-resistance of the device.

[0042] In some embodiments, by selectively doping the second polysilicon resistor, the resistance value and ratio of the corresponding first voltage divider resistor and the second voltage divider resistor can be adjusted, wherein, since there is a thicker field oxide layer underneath the second polysilicon resistor, when the second polysilicon resistor is doped, the field oxide layer can block the doped impurities from entering the drift region, thereby avoiding the doped impurities affecting the voltage resistance performance of the device.

[0043] Furthermore, forming the source region, the drain region and doping the second polysilicon resistor can be performed in the same step, thereby saving the cost of photolithography masks and the time consumption of the process.

[0044] In some embodiments, the first polysilicon resistor is in the shape of a spiral strip surrounding the drain region, and the first polysilicon resistors are arranged in sequence along the direction from the drain region to the source region. When the device is turned on, the potential of the first polysilicon resistor is higher than the potential of the drift region, and charge accumulation is formed on the surface of the drift region to form a low-resistance path, thereby reducing the on-resistance of the device. When the device is turned off, the voltage drops evenly along the spiral resistance, so the potential of the first polysilicon resistors arranged in sequence along the direction from the drain region to the source region also drops evenly, achieving the purpose of evenly reducing the potential and further improving the voltage resistance performance of the device.

[0045] In some embodiments, the second polysilicon resistor is serpentine-shaped, and the length of the second polysilicon resistor is extended as much as possible within a limited space, thereby increasing the resistance of the voltage divider resistor and reducing the current on the resistor, thereby avoiding the device from being turned on by mistake due to excessive leakage between the source region and the drain region when the device is turned off.

[0046] It should be noted that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0048] Figure 1 A circuit schematic diagram of a semiconductor device according to an embodiment of the present disclosure is shown.

[0049] Figure 2 A schematic diagram of the three-dimensional structure of a semiconductor device according to an embodiment of the present disclosure is shown.

[0050] Figure 3 Shown along Figure 2 Schematic diagram of the cross section taken along line AA.

[0051] Figure 4 Shown along Figure 2 Schematic diagram of the cross section taken along line BB.

[0052] Figure 5 Shown along Figure 2 Schematic diagram of the cross section taken along line CC. DETAILED DESCRIPTION

[0053] The present disclosure will be described in more detail below with reference to the accompanying drawings. In each of the drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure.

[0054] It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Furthermore, if the device is turned over, the layer or a region will be "below" or "beneath" another layer or another region.

[0055] If the purpose is to describe the situation of being directly on another layer or another area, this article will use expressions such as "directly on..." or "on... and adjacent to...".

[0056] Many specific details of the present disclosure are described below, such as device structure, materials, dimensions, processing technology and techniques, so as to more clearly understand the present disclosure. However, as those skilled in the art will appreciate, the present disclosure may not be implemented in accordance with these specific details.

[0057] Figure 1 A circuit schematic diagram of a semiconductor device according to an embodiment of the present disclosure is shown.

[0058] like Figure 1 As shown, the semiconductor device of the embodiment of the present disclosure is a high-voltage device, and its circuit includes a first transistor M1, a second transistor M2, a first resistor R1, a first voltage-dividing resistor R2a, and a second voltage-dividing resistor R2b. Among them, the first transistor M1 and the second transistor M2 are connected in parallel, that is, the control ends of the two transistors are short-circuited and connected to the gate potential G, the first current ends of the two transistors are short-circuited and connected to the drain potential D, and the second current ends of the two transistors are short-circuited and connected to the source potential S. The two parallel transistors can be regarded as one transistor, which is turned on or off synchronously. The first resistor R1 is connected in series between the gate region and the drain region of the first transistor M1, the first voltage-dividing resistor R2a and the second voltage-dividing resistor R2b are connected in series between the source region and the drain region of the first transistor M1, and the connection end Q of the first voltage-dividing resistor R2a and the second voltage-dividing resistor R2b is used to provide a sampling voltage V0.

[0059] When the first transistor M1 is turned on, current flows from the drain region of the first transistor M1 to the source region. When the first transistor M1 is turned off, the drain region voltage of the first transistor M1 drops to the gate region through the first resistor R1, thereby protecting the first transistor M1 and improving the voltage resistance performance of the device.

[0060] Since the voltage difference between the drain potential D and the source potential S is too high, it is difficult to directly detect the high voltage in the chip, so the first voltage-dividing resistor R2a and the second voltage-dividing resistor R2b are set to obtain the sampling voltage V0 at the connection terminal Q. For example, when the first transistor M1 is turned off, the drain potential D is 100V, the source potential S is 0V, the ratio of the first voltage-dividing resistor R2a to the second voltage-dividing resistor R2b is 99:1, and the sampling voltage V0 at this time is 1V. By judging whether the sampling voltage V0 is greater than 1V by the comparator, it can be known whether the drain potential D is greater than 100V. In addition, the resistance values ​​of the first voltage-dividing resistor R2a and the second voltage-dividing resistor R2b are very large, and the current flowing through the first voltage-dividing resistor R2a and the second voltage-dividing resistor R2b is very small at this time, which is much smaller than the turn-on current of the first transistor M1.

[0061] In some other embodiments, the first current terminal and the second current terminal may be interchangeable, and the second transistor M2 may not be provided. In some other embodiments, the number of voltage-dividing resistors is not limited to two, and those skilled in the art may set the number as required.

[0062] Figure 2 A schematic diagram of the three-dimensional structure of a semiconductor device according to an embodiment of the present disclosure is shown. Figure 3 Shown along Figure 2 Schematic diagram of the cross section taken along line AA. Figure 4 Shown along Figure 2 Schematic diagram of the cross section taken along line BB. Figure 5 Shown along Figure 2 The cross-sectional view taken along the CC line is shown in FIG. 1 , wherein, in order to more clearly present the positional relationship between the structures of various regions of the semiconductor device, Figure 2 The interconnects and substrate are not shown. Figure 3 It can be regarded as a cross-sectional schematic diagram of the first transistor M1. Figure 4 It can be regarded as a cross-sectional schematic diagram of the second transistor M2.

[0063] See also Figures 2 to 5 The semiconductor device of the embodiment of the present disclosure includes: a substrate 101, a drift region 110, a well region 120, a source region 131, a drain region 132, a third doped region 133, a dielectric layer, a first polysilicon resistor 151, a second polysilicon resistor 152, a gate region 153 and an interconnection portion, wherein the first polysilicon resistor 151 corresponds to a first resistor R1, and the second polysilicon resistor 152 corresponds to a plurality of voltage-dividing resistors, including a first voltage-dividing resistor R2a and a second voltage-dividing resistor R2b.

[0064] The drift region 110 and the well region 120 extend from the surface of the substrate 101 into the substrate 101, the drift region 110 and the well region 120 are adjacent and the depth of the drift region 110 is greater than the depth of the well region 120. The source region 131 and the third doping region 133 are located in the well region 120. The drain region 132 is located in the drift region 110. Among them, the substrate 101, the well region 120 and the third doping region 133 are of the first doping type, and the drift region 110, the source region 131 and the drain region 132 are of the second doping type. In this embodiment, the first doping type is P-type doping, and the second doping type is N-type doping. In some other embodiments, the first doping type is N-type doping, and the second doping type is P-type doping.

[0065] The dielectric layer includes a gate dielectric layer 141 and a field oxide layer 142, both of which are located on the surface of the substrate 101, and the thickness of the field oxide layer 142 is greater than the thickness of the gate dielectric layer 141. The gate dielectric layer 141 covers at least a portion of the well region 120 between the drift region 110 and the source region 131, and the gate dielectric layer 141 and the field oxide layer 142 cover the drift region 110 together.

[0066] The gate region 153 is located on the gate dielectric layer 141 and is at least correspondingly arranged between the drift region 110 and the source region 131. The first polysilicon resistor 151 is located on the surface of the gate dielectric layer 141 above the drift region 110, and surrounds the drain region 132 in a spiral strip shape. One end of the first polysilicon resistor 151 close to the drain region 132 is electrically connected to the drain region 132 through an interconnection structure, and one end close to the source region 131 is directly connected to the gate region 153. In some other embodiments, the gate region 153 is separated from the first polysilicon resistor 151, and one end of the first polysilicon resistor 151 close to the source region 131 can also be electrically connected to the gate region 153 through an interconnection structure. In some optional embodiments, the gate region 153 surrounds the first polysilicon resistor 151. In some optional embodiments, the first polysilicon resistor 151 can also surround the drain region 132 in a semi-enclosed strip shape (e.g., C-shaped).

[0067] The drift region 110, the well region 120, the source region 131, the drain region 132, the third doped region 133, the gate dielectric layer 141 and the gate region 153 are used to form a first transistor M1. The first transistor M1 is an accumulation-type transistor, wherein the third doped region 133 serves as a body potential extraction region of the first transistor M1 and is connected to the source potential S together with the source region 131. In some optional embodiments, the third doped region 133 is not short-circuited with the source region 131, but extracts the body potential separately. Taking the first transistor M1 as an NMOS as an example, along the direction from the drain region 132 to the source region 131 ( Figure 3 The first polysilicon resistors 151 are arranged in sequence. When the first transistor M1 is turned on, the potential of the first polysilicon resistors 151 arranged in sequence is higher than the potential of the drift region 110, and the first polysilicon resistors 151 are below a thin gate dielectric layer 141. Therefore, an accumulation layer can be formed on the surface of the drift region 110 to form a low-resistance path, thereby effectively reducing the on-resistance of the device. When the first transistor M1 is turned off, the potential of the first polysilicon resistors 151 arranged in sequence is uniformly reduced from the drain potential D to the gate potential G, further improving the withstand voltage performance of the device. Specifically, when the first transistor M1 is turned off, see Figure 2 The voltage drops uniformly along the first polysilicon resistor 151 of the spiral line, so see Figure 3 Along the direction of the dotted arrows, the potential of the first polysilicon resistors 151 arranged in sequence also drops evenly. The first polysilicon resistors 151 can play the role of field plates, thereby achieving the purpose of evenly reducing the potential and further improving the voltage resistance performance of the device.

[0068] In this embodiment, the spiral-shaped first polysilicon resistor 151 is discontinuous on one side close to the source region 131. The semiconductor device of the disclosed embodiment further includes an isolation layer 102, which is located on the dielectric layer and covers the first polysilicon resistor 151 and the second polysilicon resistor 152. The interconnection portion includes a conductive plug 160 and a conductive connection layer 170. The conductive plug 160 penetrates the isolation layer 102 and is connected to the first polysilicon resistor 151 at the discontinuity. The conductive connection layer 170 is located on the surface of the isolation layer 102 and is connected to the conductive plug 160, so that the discontinuous first polysilicon resistor 151 is reconnected.

[0069] The field oxide layer 142 is correspondingly arranged at the discontinuity of the first polysilicon resistor 151. Optionally, the end of the first polysilicon resistor 151 at the discontinuity extends to the surface of the field oxide layer 142. The second polysilicon resistor 152 is located on the surface of the field oxide layer 142 and is separated from the first polysilicon resistor 151. One end of the second polysilicon resistor 152 is electrically connected to the source region 131 through an interconnection structure, and the other end is electrically connected to the drain region 132 through an interconnection structure. In the present embodiment, the second polysilicon resistor 152 is distributed in a serpentine shape. In some other embodiments, the second polysilicon resistor 152 extends linearly in the direction from the drain region 132 to the source region 131.

[0070] The drift region 110, the well region 120, the source region 131, the drain region 132, the third doped region 133, the gate dielectric layer 141 and the gate region 153 are also used to form a second transistor M2, which is a non-accumulation-type transistor, wherein the third doped region 133 serves as a body potential extraction region of the second transistor M2 and is connected to the source potential S together with the source region 131. In some optional embodiments, the third doped region 133 is not short-circuited with the source region 131, but extracts the body potential separately.

[0071] Along the direction from the drain region 132 to the source region 131 ( Figure 4 14 ), the second polysilicon resistors 152 are arranged in sequence. When the second transistor M2 is turned on, due to the thick field oxide layer 142, the surface of the drift region 110 below it will not form an accumulation layer low-resistance channel. When the second transistor M2 is turned off, the potential of the second polysilicon resistors 152 arranged in sequence is uniformly reduced from the drain potential D to the source potential S, further improving the withstand voltage performance of the device. Specifically, when the second transistor M2 is turned off, the voltage drops uniformly along the serpentine second polysilicon resistors 152. Therefore, along the direction of the dotted arrow, the potential of the second polysilicon resistors 152 arranged in sequence also drops uniformly. The second polysilicon resistors 152 can play the role of a field plate, achieving the purpose of uniformly reducing the potential and further improving the withstand voltage performance of the device.

[0072] A lead portion is provided at a preset position between the two ends of the second polysilicon resistor 152. The preset position corresponds to the connection end Q between the voltage-dividing resistors R2a and R2b, for example, to obtain the sampling voltage V0. The preset position of the lead portion on the second polysilicon resistor 152 is adjustable, so that the corresponding resistance value and ratio of the voltage-dividing resistors R2a and R2b are adjustable. In addition, see Figure 2 and Figure 4 When the second polysilicon resistor 152 is serpentine, the width d2 of the second polysilicon resistor 152 along the X-axis direction is adjustable, so that the corresponding resistance values ​​and ratios of the voltage divider resistors R2a and R2b are also adjustable. Moreover, the second polysilicon resistor 152 is integrated inside the high-voltage device and does not occupy additional chip area.

[0073] Further, see Figure 2 and Figure 4 When the second polysilicon resistor 152 is serpentine, the length d1 of the second polysilicon resistor 152 along the Y-axis direction is a fixed preset size and does not change with the change of the size of the drift region 110 and the channel width of the first transistor M1. Therefore, even if the doping in the substrate (or inside the wafer) is uneven, it has little effect on the second polysilicon resistor 152, effectively reducing the problem of poor uniformity of the voltage divider resistor caused by uneven doping inside the wafer, thereby improving the voltage accuracy of the voltage divider ratio node (connection terminal Q).

[0074] The second polysilicon resistor 152 is selectively doped so that the doping concentrations corresponding to the voltage-dividing resistors R2a and R2b are different, so as to adjust the voltage-dividing resistors R2a and R2b. For example, during doping, a mask is used to cover the portion of the second polysilicon resistor 152 corresponding to the voltage-dividing resistor R2a, and the portion of the second polysilicon resistor 152 corresponding to the voltage-dividing resistor R2b is doped, so that the resistance value of the voltage-dividing resistor R2b is smaller than that of the voltage-dividing resistor R2a. Since the second polysilicon resistor 152 is provided with a thicker field oxide layer 142 below, when the second polysilicon resistor 152 is doped, the field oxide layer 142 can block the doping impurities from entering the drift region 110, thereby preventing the doping impurities from affecting the withstand voltage performance of the device.

[0075] Furthermore, the formation of the source region 131 , the drain region 132 and the doping of the second polysilicon resistor 152 can be performed in the same step, thereby saving the cost of photolithography masks and the time consumption of the process.

[0076] Since the bottom of the first polysilicon resistor 151 is a relatively thin gate dielectric layer 141, and the bottom of the second polysilicon resistor 152 is a relatively thick field oxide layer 142, when both meet the same withstand voltage, the first polysilicon resistor 151 must be arranged in a smaller width and spacing to suppress the surface electric field peak when the device is off; and there is no special requirement for the width and spacing of the second polysilicon resistor 152. In addition, for Figure 3As shown in the cross section, since the bottom of the first polysilicon resistor 151 is the gate dielectric layer 141, the resistor R1 formed by the first polysilicon resistor 151 cannot be heavily doped to adjust the resistance value, otherwise the drift region 110 at the interval of the first polysilicon resistor 151 will be injected with a high concentration doping region, thereby affecting the device withstand voltage. On the contrary, the spacing, width, and doping type of the second polysilicon resistor 152 used to form the voltage-dividing resistors R2a and R2b are not limited by the structure of the accumulation field effect transistor.

[0077] The disclosed embodiment divides the interior of the high-voltage device into zones, and integrates the drain-to-gate resistor R1 in the accumulation field effect transistor region, that is, above the drift region 110 where the gate dielectric layer 141 is located, to achieve device characteristics of high withstand voltage and low on-resistance. In the non-accumulation field effect transistor region, that is, above the drift region 110 where the field oxide layer 142 is located, the drain region to source region is integrated with adjustable width, spacing, and doping type voltage divider resistors R2a and R2b, which ensure that the device withstand voltage does not drop while achieving high-precision voltage divider ratio high-voltage resistor integration without occupying additional chip area.

[0078] The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, a person skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A semiconductor device, comprising: A substrate, and disposed on the substrate: A first transistor including a gate region, a source region and a drain region; a first polysilicon resistor connected between the gate region and the drain region; a second polysilicon resistor connected between the drain region and the source region; The second polysilicon resistor includes a first voltage-dividing resistor and a second voltage-dividing resistor connected in series; the voltage at the connection end of the first voltage-dividing resistor and the second voltage-dividing resistor is obtained to characterize the voltage between the source region and the drain region. 2 . The semiconductor device according to claim 1 , further comprising a second transistor having the gate region, the source region, and the drain region in common with the first transistor.

3. The semiconductor device according to claim 1, further comprising: a drift region extending from a surface of the substrate into the substrate; A well region extending from a surface of the substrate into the substrate; as well as a dielectric layer, located on the substrate, covering at least a portion of the drift region and the well region between the drift region and the source region, The source region is located in the well region, the drain region is located in the drift region, and the first polysilicon resistor, the second polysilicon resistor and the gate region are located on the dielectric layer.

4. The semiconductor device according to claim 3, further comprising an interconnection portion located above the first polysilicon resistor and the second polysilicon resistor, in, The first polysilicon resistor discontinuously surrounds the drain region, and the discontinuities of the first polysilicon resistor are connected by the interconnection portion. The second polysilicon resistor is located at a discontinuity of the first polysilicon resistor and is separated from the first polysilicon resistor.

5. The semiconductor device according to claim 4, further comprising an isolation layer covering the first polysilicon resistor and the second polysilicon resistor, in, The interconnection portion includes a conductive plug and a conductive connection layer. The conductive plug penetrates the isolation layer and is connected to the end of the discontinuity of the first polysilicon resistor. The conductive connection layer is located on the isolation layer and is connected to the conductive plug.

6. The semiconductor device according to claim 4, wherein: The dielectric layer includes a gate dielectric layer and a field oxide layer. The gate region and at least a portion of the first polysilicon resistor are located on the gate dielectric layer, a discontinuity of the first polysilicon resistor is located on the field oxide layer, and the second polysilicon resistor is located on the field oxide layer. The thickness of the field oxide layer is greater than the thickness of the gate dielectric layer.

7. The semiconductor device according to claim 6, wherein: When the first transistor is turned on, an accumulation layer is formed in the drift region. When the first transistor is turned off, the first polysilicon resistor is used to adjust the electric field distribution in the drift region.

8. The semiconductor device according to any one of claims 1 to 7, wherein: The first polysilicon resistor is in a spiral strip shape or a semi-enclosed strip shape surrounding the drain region.

9. The semiconductor device according to any one of claims 1 to 7, wherein: The second polysilicon resistor is in a serpentine shape or a linear shape.

10. The semiconductor device according to any one of claims 3 to 7, wherein: The substrate and the well region are of a first doping type, and the drift region, the source region, and the drain region are of a second doping type, The first doping type is selected from one of P-type doping and N-type doping, and the second doping type is selected from the other of P-type doping and N-type doping.

11. The semiconductor device according to claim 2, wherein: The first transistor is an accumulation-type transistor, and the second transistor is a non-accumulation-type transistor.

12. The semiconductor device according to any one of claims 1 to 7, wherein: The resistance values ​​of the first voltage-dividing resistor and the second voltage-dividing resistor are adjustable; and / or the width of the second polysilicon resistor is adjustable.

13. A method for manufacturing a semiconductor device, for forming the semiconductor device according to any one of claims 1 to 12.

14. The manufacturing method according to claim 13, comprising: selectively doping the second polysilicon resistor, The second polysilicon resistor includes a first voltage-dividing resistor and a second voltage-dividing resistor connected in series, and the doping concentrations of polysilicon corresponding to the first voltage-dividing resistor and the second voltage-dividing resistor are different to adjust the resistance value and ratio of the first voltage-dividing resistor and the second voltage-dividing resistor.

15. The manufacturing method according to claim 14, wherein: Forming the source region and / or the drain region and selectively doping the second polysilicon resistor are performed in the same step.

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