Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The method comprises the following steps: forming a first capacitor dielectric layer on a first polar plate; forming a second polar plate on the first capacitor dielectric layer; forming a second capacitor dielectric layer on the second polar plate, wherein the second capacitor dielectric layer covers part of the top and the side wall of the second polar plate; forming a side polar plate on part of the top of the first capacitor dielectric layer, wherein the side polar plate is located at the side part of the second capacitor dielectric layer and is isolated from the second polar plate through the second capacitor dielectric layer; and a third polar plate is formed on the second capacitor dielectric layer. Therefore, the first polar plate, the second polar plate and the first capacitor dielectric layer form a first capacitor, the second polar plate, the side polar plate and the second capacitor dielectric layer form a second capacitor, and the third polar plate, the second polar plate and the second capacitor dielectric layer form a third capacitor. The number of capacitors in the formed capacitor structure is increased, that is, the capacitance density of the capacitor structure is increased.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in materials and design in the IC industry have produced successive generations of integrated circuits. Each generation has smaller and more complex circuits than the previous one. However, these advances have increased the complexity of processing and manufacturing integrated circuits, and similar advances in IC processing and manufacturing are required to achieve these advances. Over the course of integrated circuit development, functional density (i.e., the number of interconnected devices per chip area) has increased while geometry size (i.e., the smallest component that can be made using a manufacturing process) has decreased.

[0003] One type of capacitor is a Metal Insulator Metal (MIM) capacitor, which is commonly used in mixed-signal devices and logic devices (such as embedded memory and RF devices). MIM capacitors are commonly used to store charge in various semiconductor devices. In order to meet the performance requirements of the device, the capacitance density of MIM capacitors is also gradually increasing.

[0004] At present, as the demand for improved device performance is met, higher requirements are also placed on the capacitance density of MIM capacitors. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to increase the capacitance density of the capacitor structure.

[0006] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a first electrode plate; a first capacitor dielectric layer, located at a portion of the top of the first electrode plate; a second electrode plate, located at a portion of the top of the first capacitor dielectric layer; a second capacitor dielectric layer, located at a portion of the top and side wall of the second electrode plate; a side electrode plate, located at a portion of the top of the first capacitor dielectric layer, the side electrode plate is located on the side of the second capacitor dielectric layer and is isolated from the second electrode plate by the second capacitor dielectric layer; and a third electrode plate, located at the top of the second capacitor dielectric layer.

[0007] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, including: providing a first electrode plate; forming a first capacitor dielectric layer on the first electrode plate, and the first capacitor dielectric layer covers a portion of the top of the first electrode plate; forming a second electrode plate on the first capacitor dielectric layer, and the second electrode plate covers a portion of the top of the first capacitor dielectric layer; forming a second capacitor dielectric layer on the second electrode plate, and the second capacitor dielectric layer covers a portion of the top and side wall of the second electrode plate; forming a side electrode plate on a portion of the top of the first capacitor dielectric layer, the side electrode plate is located on the side of the second capacitor dielectric layer and is isolated from the second electrode plate by the second capacitor dielectric layer; forming a third electrode plate on the second capacitor dielectric layer.

[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0009] An embodiment of the present invention provides a semiconductor structure, wherein a first capacitor dielectric layer is located at a portion of the top of a first electrode plate, a second electrode plate is located at a portion of the top of the first capacitor dielectric layer, a second capacitor dielectric layer is located at a portion of the top and side wall of the second electrode plate, a side electrode plate is located at a portion of the top of the first capacitor dielectric layer, the side electrode plate is located at a side of the second capacitor dielectric and is isolated from the second electrode plate by the second capacitor dielectric layer, and a third electrode plate is located at the top of the second capacitor dielectric layer. In an embodiment of the present invention, by adding a second electrode plate, a side electrode plate, and a second capacitor dielectric layer structure, the first electrode plate, the second electrode plate, and the first capacitor dielectric layer constitute a first capacitor, the second electrode plate, the side electrode plate, and the second capacitor dielectric layer constitute a second capacitor, and the third electrode plate, the second electrode plate, and the second capacitor dielectric layer constitute a third capacitor, that is, under the same conditions such as the same area, the capacitance density of the capacitor structure is increased.

[0010] The embodiment of the present invention provides a method for forming a semiconductor structure, wherein a first capacitor dielectric layer is formed on a first plate, and the first capacitor dielectric layer covers a portion of the top of the first plate, a second plate is formed on the first capacitor dielectric layer, and the second plate covers a portion of the top of the first capacitor dielectric layer, a second capacitor dielectric layer is formed on the second plate, and the second capacitor dielectric layer covers a portion of the top and sidewall of the second plate, a side plate is formed on a portion of the top of the first capacitor dielectric layer, the side plate is located on the side of the second capacitor dielectric layer and is isolated from the second plate by the second capacitor dielectric layer, and a third plate is formed on the second capacitor dielectric layer. Therefore, the first plate, the second plate, and the first capacitor dielectric layer constitute a first capacitor, the second plate, the side plate, and the second capacitor dielectric layer constitute a second capacitor, and the third plate, the second plate, and the second capacitor dielectric layer constitute a third capacitor. Under the same conditions such as the same area, the number of capacitors in the formed capacitor structure is increased, that is, the capacitance density of the capacitor structure is increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1It is a schematic diagram of the structure of a semiconductor structure;

[0012] Figure 2 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;

[0013] Figures 3 to 12 is a schematic structural diagram corresponding to each step in the first embodiment of the method for forming a semiconductor structure of the present invention;

[0014] Figures 13 to 18 is a schematic structural diagram corresponding to each step in the second embodiment of the method for forming a semiconductor structure of the present invention;

[0015] Figures 19 to 23 It is a schematic structural diagram corresponding to each step in the third embodiment of the method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0016] At present, the capacitance density of the capacitor structure needs to be improved. Now, combined with a capacitor structure, the reasons why the capacitance density of the capacitor structure needs to be improved are analyzed.

[0017] Figure 1 It is a structural diagram of a semiconductor structure.

[0018] refer to Figure 1 The semiconductor structure includes: a lower plate 10; a capacitor dielectric layer 11, located on a portion of the top of the lower plate 10; and an upper plate 12, located on the top of the capacitor dielectric layer 11.

[0019] It should be noted that the semiconductor structure also includes: a first through-hole interconnection structure 10B, located on the lower electrode plate 10 and electrically connected to the lower electrode plate 10; a second through-hole interconnection structure 12B, located on the upper electrode plate 12 and electrically connected to the upper electrode plate 12; a first interconnection line 15, connecting the first through-hole interconnection structure 10B; and a second interconnection line 16, connecting the second through-hole interconnection structure 12B.

[0020] Research has found that in the traditional MIM capacitor structure, the upper plate 12, the lower plate 10, and the capacitor dielectric layer 11 constitute a capacitor, that is, under other conditions such as the same area, the number of capacitors in the capacitor structure is low, that is, the capacitor density is low, which is difficult to meet application requirements.

[0021] There are two common methods for increasing the capacitance density of MIM capacitors. One method is to reduce the thickness of the capacitor dielectric layer 11, but reducing the thickness of the capacitor dielectric layer 11 will correspondingly lead to a decrease in the linearity between the capacitance value and the thickness of the capacitor dielectric layer 11, and it is also easy to cause the electric field strength to be too high and cause leakage current problems. Another method is to increase the area of ​​the upper plate 12 and the lower plate 10, but since both are planar structures, increasing the area will occupy a larger substrate area, which is not conducive to improving the integration.

[0022] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: forming a first capacitor dielectric layer on a first electrode plate, and the first capacitor dielectric layer covers a portion of the top of the first electrode plate, forming a second electrode plate on the first capacitor dielectric layer, and the second electrode plate covers a portion of the top of the first capacitor dielectric layer, forming a second capacitor dielectric layer on the second electrode plate, and the second capacitor dielectric layer covers a portion of the top and side wall of the second electrode plate, forming a side electrode plate on a portion of the top of the first capacitor dielectric layer, the side electrode plate is located on the side of the second capacitor dielectric layer and is isolated from the second electrode plate by the second capacitor dielectric layer, and forming a third electrode plate on the second capacitor dielectric layer.

[0023] In the scheme disclosed in the embodiment of the present invention, by adding the structure of the second electrode plate, the side electrode plate, and the second capacitor dielectric layer, the first electrode plate, the second electrode plate, and the first capacitor dielectric layer constitute the first capacitor, the second electrode plate, the side electrode plate, and the second capacitor dielectric layer constitute the second capacitor, and the third electrode plate, the second electrode plate, and the second capacitor dielectric layer constitute the third capacitor, that is, under the same area and other conditions, the number of capacitors in the formed capacitor structure is increased, that is, the capacitance density of the capacitor structure is increased.

[0024] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0025] Figure 2 It is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention.

[0026] The semiconductor structure includes: a first electrode 100; a first capacitor dielectric layer 101, located at a portion of the top of the first electrode 100; a second electrode 102, located at a portion of the top of the first capacitor dielectric layer 101; a second capacitor dielectric layer 106, located at a portion of the top and side wall of the second electrode 102; a side electrode 107, located at a portion of the top of the first capacitor dielectric layer 101, the side electrode 107 is located on the side of the second capacitor dielectric layer 106 and is isolated from the second electrode 102 by the second capacitor dielectric layer 106; a third electrode 108, located at the top of the second capacitor dielectric layer 106.

[0027] In this embodiment, by adding the second electrode plate 102, the side electrode plate 107, and the second capacitor dielectric layer 106, the first electrode plate 100, the second electrode plate 102, and the first capacitor dielectric layer 101 constitute a first capacitor, the second electrode plate 102, the side electrode plate 107, and the second capacitor dielectric layer 106 constitute a second capacitor, and the third electrode plate 108, the second electrode plate 102, and the second capacitor dielectric layer 106 constitute a third capacitor. That is, under the same conditions such as the same area, the number of capacitors in the formed capacitor structure is increased, that is, the capacitance density of the capacitor structure is increased.

[0028] The first electrode plate 100 is used to provide a process platform for forming a capacitor structure. Specifically, the first electrode plate 100 is used as a bottom plate of the capacitor structure.

[0029] To this end, in this embodiment, the material of the first electrode plate 100 is a conductive material, and the material of the first electrode plate 100 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0030] In this embodiment, the material of the first electrode plate 100 is metal nitride, so that the first electrode plate 100 has higher stability to improve the problem of metal ion diffusion. As an example, the material of the first electrode plate 100 is TiN.

[0031] It should be noted that, in this embodiment, the thickness of the first electrode plate 100 should not be too large or too small. If the thickness of the first electrode plate 100 is too large, it is easy to occupy too much space and affect the integration of the semiconductor structure; if the thickness of the first electrode plate 100 is too small, it is easy to cause the resistance of the first electrode plate 100 to be too large, affecting the performance of the capacitor structure. For this reason, in this embodiment, the thickness of the first electrode plate 100 is to

[0032] The first capacitor dielectric layer 101 is used as an insulating layer in the capacitor structure.

[0033] In this embodiment, the first capacitor dielectric layer 101 is located on a portion of the top of the first electrode plate 100 to expose a portion of the first electrode plate 100 , thereby facilitating electrical connection between the first electrode plate 100 and other interconnection structures.

[0034] In this embodiment, the material of the first capacitor dielectric layer 101 includes HfO 2 、HfSiO、TiO 2 , HfZrO, HfSiON, HfTaO, HfTiO, Ta 2 O 5 、ZrO 2 、ZrSiO 2 、Al 2 O 3 、SrTiO 3 , BaSrTiO and SiN.

[0035] In this embodiment, the material of the first capacitor dielectric layer 101 is a high-k dielectric material; wherein the high-k dielectric material refers to a dielectric material whose relative dielectric constant is greater than the relative dielectric constant of silicon oxide. By selecting a high-k dielectric material, it is beneficial to improve the capacitance density of the MIM capacitor. As an example, the material of the first capacitor dielectric layer 101 is HfO 2 .

[0036] The thickness of the first capacitor dielectric layer 101 should not be too small or too large. If the thickness of the first capacitor dielectric layer 101 is too small, the insulation effect of the first capacitor dielectric layer 101 on the first electrode 100 and the subsequent second electrode 102 is poor; if the thickness of the first capacitor dielectric layer 101 is too large, it is easy to reduce the capacitance value of the semiconductor structure. For this reason, in this embodiment, the thickness of the first capacitor dielectric layer 101 is to

[0037] The second electrode plate 102 is used as a middle plate of the capacitor structure.

[0038] In this embodiment, the second electrode plate 102 is located on a portion of the top of the first capacitor dielectric layer 101 to expose a portion of the first capacitor dielectric layer 101 , so as to facilitate the subsequent formation of a side electrode plate 107 on the top of the first capacitor dielectric layer 101 .

[0039] In this embodiment, the material of the second electrode plate 102 is a conductive material. The material of the second electrode plate 102 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al. As an example, the material of the second electrode plate 102 is TiN.

[0040] At least any two of the side electrode plate 107 , the third electrode plate 108 and the second electrode plate 102 have the same thickness, and a uniform electric field is easily generated between the electrodes with the same thickness.

[0041] In this embodiment, the thickness of the second electrode plate 102 is equal to the thickness of the third electrode plate 108 .

[0042] Specifically, on the one hand, a uniform electric field can be generated between the second electrode plate 102 and the third electrode plate 108 ; on the other hand, it is helpful to reduce the complexity of the process.

[0043] It should be noted that the thickness of the second electrode plate 102 should not be too large or too small. If the thickness of the second electrode plate 102 is too large, it is easy to occupy too much space and affect the integration of the semiconductor structure; if the thickness of the second electrode plate 102 is too small, it is easy to increase the difficulty of forming the second electrode plate 102 and affect the quality of forming the second capacitor dielectric layer 106. Therefore, in this embodiment, the thickness of the second electrode plate 102 is to

[0045] For the description of the second electrode plate 102 , reference may be made to the aforementioned description of the first electrode plate 100 .

[0046] The second capacitor dielectric layer 106 is used as an insulating layer in the capacitor structure.

[0047] In this embodiment, the second capacitor dielectric layer 106 is located on a portion of the top and sidewall of the second electrode plate 102 .

[0048] The second capacitor dielectric layer 106 is located on a portion of the top of the second electrode plate 102 to expose a portion of the second electrode plate 102 , so as to facilitate electrical connection of the second electrode plate 102 with other interconnection structures.

[0049] In this embodiment, the material of the second capacitor dielectric layer 106 includes HfO 2 、HfSiO、TiO 2 , HfZrO, HfSiON, HfTaO, HfTiO, Ta 2 O 5 、ZrO 2 、ZrSiO 2 、Al 2 O 3 、SrTiO 3 As an example, the material of the second capacitor dielectric layer 106 is HfO 2 .

[0050] For the description of the second capacitor dielectric layer 106 , reference may be made to the aforementioned description of the first capacitor dielectric layer 101 .

[0051] In this embodiment, the thickness of the second capacitor dielectric layer 106 is equal to the thickness of the first capacitor dielectric layer 101. Specifically, on the one hand, the consistency of capacitor performance can be improved; on the other hand, it is helpful to reduce process complexity.

[0052] It should be noted that the thickness of the second capacitor dielectric layer 106 should not be too small or too large. If the thickness of the second capacitor dielectric layer 106 is too small, the insulation effect of the second capacitor dielectric layer 106 on the second plate 102 and the subsequent third plate 108, as well as the side plate 107 is poor, and the probability of the second capacitor dielectric layer 106 breaking at the corner is high; if the thickness of the second capacitor dielectric layer 106 is too large, it is easy to reduce the capacitance value of the semiconductor structure. For this reason, in this embodiment, the thickness of the second capacitor dielectric layer 101 is to

[0053] The side plates 107 are used as electrode plates in the capacitor structure.

[0054] In this embodiment, the side plate 107 is located at a portion of the top of the first capacitor dielectric layer 101 , and the side plate 107 is located at a side of the second capacitor dielectric layer 106 and is isolated from the second plate 102 by the second capacitor dielectric layer 106 .

[0055] In this embodiment, the side electrode plate 107 and the third electrode plate 108 expose the corners of the second capacitor dielectric layer 106 .

[0056] On the one hand, by forming the isolated side plates 107 and the third plate 108, the number of electrode plates in the semiconductor structure is increased under the same area, thereby increasing the number of capacitors and further increasing the capacitance density; on the other hand, compared with the second capacitor dielectric layer 106 located on the top of the second plate 102, the second capacitor dielectric layer 106 at the corner is relatively thin, and the probability of the second capacitor dielectric layer 106 at the corner being broken down becomes higher. Therefore, exposing the corners of the second capacitor dielectric layer 106 by the side plates 107 and the third plate 108 can reduce the leakage of the capacitor and improve the reliability of the semiconductor structure.

[0057] In this embodiment, the thickness of the side plate 107 is equal to the thickness of the third plate 108. The thickness of the side plate 107 refers to the longitudinal dimension of the side plate 107 along the normal direction of the surface of the second plate 102 (that is, the thickness direction of the second plate); the thickness of the third plate 108 refers to the longitudinal dimension of the third plate 108 along the normal direction of the surface of the second plate 102.

[0058] The thickness of the side electrode plate 107 is equal to that of the third electrode plate 108 , which means that the side electrode plate 107 and the third electrode plate 108 are formed in the same film deposition process, thereby reducing the number of film deposition times.

[0059] In other embodiments, the thickness of the side electrode plate may also be equal to the thickness of the second electrode plate.

[0060] The thickness of the side electrode plate refers to the longitudinal dimension of the side electrode plate along the normal direction of the surface of the second electrode plate 102 (ie, the thickness direction of the second electrode plate).

[0061] The thickness of the side electrode plate is equal to the thickness of the second electrode plate, which means that the side electrode plate and the second electrode plate 102 are formed in the same film deposition process, thereby reducing the number of film deposition times.

[0062] If the thickness of the side plate is greater than that of the second plate, it is easy to cause uneven electric field distribution, increasing the risk of breakdown of the second capacitor dielectric layer; if the thickness of the side plate is less than that of the second plate, it is easy to reduce the facing area of ​​the side plate and the second plate, resulting in poor effect of improving capacitance density.

[0063] The third electrode plate 108 is used as an upper plate in the capacitor structure.

[0064] To this end, in this embodiment, the material of the third electrode plate 108 is a conductive material. The material of the third electrode plate 108 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al. As an example, the material of the third electrode plate 108 is TiN.

[0065] For the description of the third electrode plate 108 , reference may be made to the aforementioned description of the first electrode plate 100 and the second electrode plate 102 .

[0066] In this embodiment, the third electrode plate 108 is located on the top of the second capacitor dielectric layer 106 .

[0067] In this embodiment, the thickness of the third electrode plate 108 should not be too large or too small. If the thickness of the third electrode plate 108 is too large, it is easy to occupy too much space and affect the integration of the semiconductor structure; if the thickness of the third electrode plate 108 is too small, it is easy to increase the difficulty of forming the third electrode plate 108, resulting in excessive resistance of the third electrode plate 108, affecting the performance of the capacitor structure. For this reason, in this embodiment, the thickness of the third electrode plate 108 is to

[0068] It should be noted that, by adding the second electrode plate 102, the side electrode plate 107, and the second capacitor dielectric layer 106, the first electrode plate 100, the second electrode plate 102, and the first capacitor dielectric layer 101 constitute a first capacitor, the second electrode plate 102, the side electrode plate 107, and the second capacitor dielectric layer 106 constitute a second capacitor, and the third electrode plate 108, the second electrode plate 102, and the second capacitor dielectric layer 106 constitute a third capacitor, that is, under the same conditions such as the same area, the capacitance density of the capacitor structure is increased.

[0069] It should be noted that the semiconductor structure also includes: a first through-hole interconnect structure 100B, located on the first electrode plate 100 and electrically connected to the first electrode plate 100; a second through-hole interconnect structure 102B, located on the second electrode plate 102 and electrically connected to the second electrode plate 102; a third through-hole interconnect structure 108B, located on the third electrode plate 108 and electrically connected to the third electrode plate 108; a fourth through-hole interconnect structure 107B, located on the side electrode plate 107 and electrically connected to the side electrode plate 107; a first interconnect line 104, connecting the first through-hole interconnect structure 100B, the third through-hole interconnect structure 108B and the fourth through-hole interconnect structure 107B; and a second interconnect line 105, connecting the second through-hole interconnect structure 102B.

[0070] In this embodiment, the first through-hole interconnection structure 100B is electrically connected to the first electrode plate 100; the third through-hole interconnection structure 108B is electrically connected to the third electrode plate 108; the fourth through-hole interconnection structure 107B is electrically connected to the side electrode plate 107; the first interconnection line 104 connects the first through-hole interconnection structure 100B, the third through-hole interconnection structure 108B, and the fourth through-hole interconnection structure 107B, that is, the first interconnection line 104 is electrically connected to the first electrode plate 100, the third electrode plate 108, and the side electrode plate 107; the second through-hole interconnection structure 102B is electrically connected to the second electrode plate 102; the second interconnection line 105 is used to electrically connect the second through-hole interconnection structure 102B, that is, the second interconnection line 105 is electrically connected to the second electrode plate 102. When different voltages are applied to the first interconnection line 104 and the second interconnection line 105, that is, the voltages on the first electrode plate 100, the third electrode plate 108, and the side electrode plate 107 are the same, and different from the voltage on the second electrode plate 102. Therefore, an electric field is generated between the first electrode plate 100 and the second electrode plate 102 to form a first capacitor structure; an electric field is generated between the second electrode plate 102 and the side electrode plate 107 to form a second capacitor structure; and an electric field is generated between the second electrode plate 102 and the third electrode plate 108 to form a third capacitor structure.

[0071] Correspondingly, the present invention also provides a method for forming a semiconductor structure. Figures 3 to 12 It is a schematic structural diagram corresponding to each step in the first embodiment of the method for forming a semiconductor structure of the present invention.

[0072] refer to Figure 3 , providing a first electrode plate 20.

[0073] The first electrode plate 20 provides a process platform for subsequent process steps.

[0074] Specifically, the first electrode plate 20 is used to provide a process platform for forming the first capacitor dielectric layer 21 .

[0075] In this embodiment, the first electrode plate 20 is used as the lower electrode plate of the semiconductor structure.

[0076] To this end, in this embodiment, the material of the first electrode plate 20 is a conductive material, and the material of the first electrode plate 20 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0077] In this embodiment, the material of the first electrode plate 20 is metal nitride, so that the first electrode plate 20 has higher stability to improve the problem of metal ion diffusion. As an example, the material of the first electrode plate 20 is TiN.

[0078] It should be noted that, in this embodiment, the thickness of the first electrode plate 20 should not be too large or too small. If the thickness of the first electrode plate 20 is too large, it is easy to occupy too much space, affecting the integration of the semiconductor structure; if the thickness of the first electrode plate 20 is too small, it is easy to cause the resistance of the first electrode plate 20 to be too large, affecting the performance of the capacitor structure. For this reason, in this embodiment, the thickness of the first electrode plate 20 is to

[0079] Combined with reference Figure 4 and Figure 5 , forming a first capacitor dielectric layer on the first electrode plate, and the first capacitor dielectric layer covers a portion of the top of the first electrode plate.

[0080] The first capacitor dielectric layer 21 is used as an insulating layer in the capacitor structure.

[0081] In this embodiment, the first capacitor dielectric layer 21 is located on a portion of the top of the first electrode plate 20 to expose a portion of the first electrode plate 20 to facilitate electrical connection between the first electrode plate 20 and other interconnection structures.

[0082] In this embodiment, the material of the first capacitor dielectric layer 21 includes HfO 2 、HfSiO、TiO 2 , HfZrO, HfSiON, HfTaO, HfTiO, Ta 2 O 5 、ZrO 2 、ZrSiO 2 、Al 2 O 3 、SrTiO 3 , BaSrTiO and SiN.

[0083] In this embodiment, the material of the first capacitor dielectric layer 21 is a high-k dielectric material; wherein the high-k dielectric material refers to a dielectric material whose relative dielectric constant is greater than the relative dielectric constant of silicon oxide. By selecting a high-k dielectric material, it is beneficial to improve the capacitance density of the MIM capacitor. As an example, the material of the first capacitor dielectric layer 21 is HfO 2 .

[0084] The thickness of the first capacitor dielectric layer 21 should not be too small or too large. If the thickness of the first capacitor dielectric layer 21 is too small, the insulation effect of the first capacitor dielectric layer 21 on the first electrode 20 and the subsequent second electrode 22 is poor; if the thickness of the first capacitor dielectric layer 21 is too large, it is easy to reduce the capacitance value of the semiconductor structure. For this reason, in this embodiment, the thickness of the first capacitor dielectric layer 21 is to

[0085] Specifically, the steps of forming the first capacitor dielectric layer 21 include: referring to Figure 4 , depositing a first capacitor dielectric material layer 21A on the first electrode plate 20; Figure 5 , patterning the first capacitor dielectric material layer 21A, forming the first capacitor dielectric layer 21 on the first electrode plate 20 , and the first capacitor dielectric layer 21 covers a portion of the top of the first electrode plate 20 .

[0086] The first capacitor dielectric material layer 21A is used to form a first capacitor dielectric layer 21 after patterning.

[0087] Accordingly, based on the material of the first capacitor dielectric layer 21 , a first capacitor dielectric material layer 21A made of the same material is formed.

[0088] In this embodiment, the first capacitor dielectric material layer 21A is formed by atomic layer deposition process to improve the thickness uniformity of the first capacitor dielectric layer 21. In other embodiments, the first capacitor dielectric material layer may be formed by other deposition processes, such as plasma chemical vapor deposition process.

[0089] In this embodiment, the first capacitor dielectric material layer 21A is patterned by dry etching (eg, anisotropic dry etching process).

[0090] Combined with reference Figure 6 and Figure 7 A second electrode plate 22 is formed on the first capacitor dielectric layer 21 , and the second electrode plate 22 covers a portion of the top of the first capacitor dielectric layer 21 .

[0091] The second electrode plate 22 is used as the middle electrode plate of the capacitor structure.

[0092] In this embodiment, the second electrode plate 22 is located on a portion of the top of the first capacitor dielectric layer 21 to expose a portion of the first capacitor dielectric layer 21 , so as to facilitate the subsequent formation of a side electrode plate on the top of the first capacitor dielectric layer 21 .

[0093] In this embodiment, the material of the second electrode plate 22 is a conductive material. The material of the second electrode plate 22 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al. As an example, the material of the second electrode plate 22 is TiN.

[0094] It should be noted that the thickness of the second electrode plate 22 and at least any two of the third electrode plate and the side electrode plates formed subsequently are equal, and a uniform electric field is easily generated between the electrode plates with equal thickness.

[0095] In this embodiment, the thickness of the second electrode plate 22 is equal to the thickness of the third electrode plate.

[0096] Specifically, on the one hand, a uniform electric field can be generated between the second electrode plate 22 and the third electrode plate 28 ; on the other hand, it is helpful to reduce the complexity of the process.

[0097] It should be noted that the thickness of the second electrode plate 22 should not be too large or too small. If the thickness of the second electrode plate 22 is too large, it is easy to occupy too much space and affect the integration of the semiconductor structure; if the thickness of the second electrode plate 22 is too small, it is easy to increase the difficulty of forming the second electrode plate 22 and affect the formation quality of the second capacitor dielectric layer 26. For this reason, in this embodiment, the thickness of the second electrode plate 22 is to

[0098] The step of forming the second electrode plate 22 on the first capacitor dielectric layer 21 includes: referring to Figure 6 , depositing a second electrode material layer 22A on the first capacitor dielectric layer 21; Figure 7 , patterning the second electrode material layer 22A, forming the second electrode 22 on the first capacitor dielectric layer 21 , and the second electrode 22 covers a portion of the top of the first capacitor dielectric layer 21 .

[0099] The second electrode material layer 22A is used to form the second electrode 22 after patterning.

[0100] Accordingly, based on the material of the second electrode plate 22 , a second electrode plate material layer 22A made of the same material is formed.

[0101] In this embodiment, the second electrode material layer 22A is formed by a physical vapor deposition process. In other embodiments, the second electrode material layer may also be formed by an atomic layer deposition process.

[0102] In this embodiment, the second electrode material layer 22A is patterned by dry etching (eg, an anisotropic dry etching process).

[0103] Combined with reference Figure 8 and Fig. 9 A second capacitor dielectric layer 26 is formed on the second electrode plate 22 , and the second capacitor dielectric layer 26 covers a portion of the top and sidewalls of the second electrode plate 22 .

[0104] The second capacitor dielectric layer 26 is used as an insulating layer in the capacitor structure.

[0105] In this embodiment, the second capacitor dielectric layer 26 is located on a portion of the top of the second electrode plate 22 to expose a portion of the second electrode plate 22 , so as to facilitate electrical connection between the second electrode plate 22 and other interconnection structures.

[0106] In this embodiment, the material of the second capacitor dielectric layer 26 includes HfO 2 、HfSiO、TiO 2, HfZrO, HfSiON, HfTaO, HfTiO, Ta 2 O 5 、ZrO 2 、ZrSiO 2 、Al 2 O 3 、SrTiO 3 As an example, the material of the second capacitor dielectric layer 26 is HfO 2 .

[0107] For the description of the second capacitor dielectric layer 26 , reference may be made to the aforementioned description of the first capacitor dielectric layer 21 .

[0108] In this embodiment, the thickness of the second capacitor dielectric layer 26 is equal to the thickness of the first capacitor dielectric layer 21 .

[0109] Specifically, on the one hand, the consistency of capacitor performance can be improved; on the other hand, it is helpful to reduce process complexity.

[0110] It should be noted that the thickness of the second capacitor dielectric layer 26 should not be too small or too large. If the thickness of the second capacitor dielectric layer 26 is too small, the insulation effect of the second capacitor dielectric layer 26 on the second plate 22 and the subsequent third plate and the side plate is poor, and the probability of the second capacitor dielectric layer 26 breaking at the corner is high; if the thickness of the second capacitor dielectric layer 26 is too large, it is easy to reduce the capacitance value of the semiconductor structure. For this reason, in this embodiment, the thickness of the second capacitor dielectric layer 26 is to

[0111] Specifically, the steps of forming the second capacitor dielectric layer 26 include: referring to Figure 8 , depositing a second capacitor dielectric material layer 26A on the second electrode plate 22; Fig. 9 , patterning the second capacitor dielectric material layer 26A, retaining the portion of the top covering the second electrode plate 22 and the remaining second capacitor dielectric material layer 26A covering the sidewall of the second electrode plate 22 as the second capacitor dielectric layer 26 .

[0112] The second capacitor dielectric material layer 26A is used to form a second capacitor dielectric layer 26 after patterning.

[0113] Accordingly, based on the material of the second capacitor dielectric layer 26 , a second capacitor dielectric material layer 26A made of the same material is formed.

[0114] In this embodiment, the second capacitor dielectric material layer 26A is formed by atomic layer deposition process to improve the thickness uniformity of the second capacitor dielectric layer 26. In other embodiments, the second capacitor dielectric material layer may be formed by other deposition processes, such as plasma chemical vapor deposition process.

[0115] In this embodiment, the second capacitor dielectric material layer 26A is patterned by dry etching (eg, an anisotropic dry etching process).

[0116] Combined with reference Fig.10 and Fig.11 , a third electrode plate 28 is formed on the second capacitor dielectric layer 26 ; a side electrode plate 27 is formed on a portion of the top of the first capacitor dielectric layer 21 , and the side electrode plate 27 is located on the side of the second capacitor dielectric layer 26 and is isolated from the second electrode plate 22 by the second capacitor dielectric layer 26 .

[0117] The third electrode plate 28 is used as the upper electrode plate in the capacitor structure. The side electrode plate 27 is also used as the electrode plate in the capacitor structure. In this embodiment, the side electrode plate 27 is formed on the side wall of the second capacitor dielectric layer 26.

[0118] In this embodiment, by adding the second electrode plate 22, the side electrode plate 27, and the second capacitor dielectric layer 26, the first electrode plate 20, the second electrode plate 22, and the first capacitor dielectric layer 21 constitute the first capacitor, the second electrode plate 22, the side electrode plate 27, and the second capacitor dielectric layer 26 constitute the second capacitor, and the third electrode plate 28, the second electrode plate 22, and the second capacitor dielectric layer 26 constitute the third capacitor, that is, under the same conditions such as the same area, the capacitance density of the capacitor structure is increased.

[0119] In this embodiment, the material of the third electrode plate 28 is a conductive material. The material of the third electrode plate 28 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al. As an example, the material of the third electrode plate 28 is TiN.

[0120] For the description of the third electrode plate 28 , reference may be made to the aforementioned description of the first electrode plate 20 and the second electrode plate 22 .

[0121] In this embodiment, the material of the side plate 28 is a conductive material. The material of the side plate 28 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al. As an example, the material of the side plate 28 is TiN.

[0122] In this embodiment, the side electrode plate 27 and the third electrode plate 28 expose the corners of the second capacitor dielectric layer 26 .

[0123] On the one hand, by forming the isolated side plates 27 and the third plate 28, the number of electrode plates in the semiconductor structure is increased under the same area, thereby increasing the number of capacitors and further increasing the capacitance density; on the other hand, compared with the second capacitor dielectric layer 26 located on the top of the second plate 22, the second capacitor dielectric layer 26 at the corner is relatively thin, and the probability of the second capacitor dielectric layer 26 at the corner being broken down becomes higher. Therefore, exposing the corners of the second capacitor dielectric layer 26 by the side plates 27 and the third plate 28 can reduce the leakage of the capacitor and improve the reliability of the semiconductor structure.

[0124] In this embodiment, the side electrode plate 27 and the third electrode plate 28 are formed in the same step, thereby reducing the number of film deposition times.

[0125] Specifically, the steps of forming the third electrode plate 28 and the side electrode plate 27 include: referring to Fig.10 , forming a third plate material layer 28A on the top and sidewalls of the second capacitor dielectric layer 26; Fig.11 , pattern the third electrode material layer 28A, retain the remaining portion of the third electrode material layer 28A located on the top of the second capacitor dielectric layer 26 as the third electrode 28, and retain the remaining portion of the third electrode material layer 28A on the side wall of the second capacitor dielectric layer 26 as the side electrode 27.

[0126] The third electrode material layer 28A is used to form the third electrode 28 and the side electrode 27 after patterning.

[0127] Accordingly, based on the material of the third electrode plate 28 and the material of the side electrode plate 27 , a third electrode plate material layer 28A made of the same material is formed.

[0128] In this embodiment, the third electrode material layer 28A is formed by a physical vapor deposition process. In other embodiments, the third electrode material layer may also be formed by an atomic layer deposition process.

[0129] In this embodiment, the third electrode material layer 28A is patterned by dry etching (eg, an anisotropic dry etching process).

[0130] Correspondingly, in this embodiment, the thickness of the side electrode plate 27 is equal to the thickness of the third electrode plate 28 .

[0131] Among them, the thickness of the side electrode plate 27 refers to: the longitudinal dimension of the side electrode plate 27 along the normal direction of the surface of the second electrode plate 22 (that is, the thickness direction of the second electrode plate); the thickness of the third electrode plate 28 refers to: the longitudinal dimension of the third electrode plate 28 along the normal direction of the surface of the second electrode plate 22.

[0132] In this embodiment, during the process of patterning the third electrode material layer 28A, the corner of the second capacitor dielectric layer 26 covering the corner of the second electrode 22 is exposed.

[0133] Removing the third plate material layer 28A covering the corner of the second capacitor dielectric layer 26 during the patterning process is helpful to improve the photolithography alignment accuracy, so that the position accuracy of the side plate 27 and the third plate 28 formed after patterning is higher.

[0134] In this embodiment, the thickness of the third electrode plate 28 should not be too large or too small. If the thickness of the third electrode plate 28 is too large, it is easy to occupy too much space and affect the integration of the semiconductor structure; if the thickness of the third electrode plate 28 is too small, it is easy to increase the difficulty of forming the third electrode plate 28, resulting in excessive resistance of the third electrode plate 28, affecting the performance of the capacitor structure. Therefore, in this embodiment, the thickness of the third electrode plate 28 is to

[0135] refer to Fig.12 After forming the third electrode plate 28 and the side electrode plate 27, the forming method further includes: forming a first through-hole interconnection structure 20B on the first electrode plate 20, and the first through-hole interconnection structure 20B is electrically connected to the first electrode plate 20; forming a second through-hole interconnection structure 22B on the second electrode plate 22, and the second through-hole interconnection structure 22B is electrically connected to the second electrode plate 22; forming a third through-hole interconnection structure 28B on the third electrode plate 28, and the third through-hole interconnection structure 28B is electrically connected to the third electrode plate 28; forming a fourth through-hole interconnection structure 27B on the side electrode plate 27, and the fourth through-hole interconnection structure 27B is electrically connected to the side electrode plate 27; forming a first interconnection line 24, connecting the first through-hole interconnection structure 20B, the third through-hole interconnection structure 28B and the fourth through-hole interconnection structure 27B; forming a second interconnection line 25, connecting the second through-hole interconnection structure 22B.

[0136] In this embodiment, the first through-hole interconnection structure 20B is electrically connected to the first electrode plate 20; the third through-hole interconnection structure 28B is electrically connected to the third electrode plate 28; the fourth through-hole interconnection structure 27B is electrically connected to the side electrode plate 27; the first interconnection line 24 connects the first through-hole interconnection structure 20B, the third through-hole interconnection structure 28B, and the fourth through-hole interconnection structure 27B, that is, the first interconnection line 24 is electrically connected to the first electrode plate 20, the third electrode plate 28, and the side electrode plate 27; the second through-hole interconnection structure 22B is electrically connected to the second electrode plate 22; the second interconnection line 25 is used to electrically connect the second through-hole interconnection structure 22B, that is, the second interconnection line 25 is electrically connected to the second electrode plate 22. When different voltages are applied to the first interconnection line 24 and the second interconnection line 25, that is, the voltages on the first electrode plate 20, the third electrode plate 28, and the side electrode plate 27 are the same, and different from the voltage on the second electrode plate 22. Therefore, an electric field is generated between the first electrode plate 20 and the second electrode plate 22 to form a first capacitor structure; an electric field is generated between the second electrode plate 22 and the side electrode plate 27 to form a second capacitor structure; and an electric field is generated between the second electrode plate 22 and the third electrode plate 28 to form a third capacitor structure.

[0137] Figures 13 to 18 It is a schematic structural diagram corresponding to each step in the second embodiment of the method for forming a semiconductor structure of the present invention.

[0138] The similarities between this embodiment and the first embodiment are not repeated here. The difference between this embodiment and the first embodiment is that the process steps for forming the first capacitor dielectric layer 31, the second capacitor dielectric layer 36, the third electrode plate 38, and the side electrode plate 37 are different.

[0139] refer to Fig.13 Before forming the first capacitor dielectric layer 31 on the first electrode plate 30 , a first capacitor dielectric material layer 31A covering the first electrode plate 30 is first formed.

[0140] The first capacitor dielectric material layer 31A is used to form a first capacitor dielectric layer 31 after patterning.

[0141] refer to Fig.14 A second electrode 32 is formed on a portion of the top of the first capacitor dielectric material layer 31A.

[0142] refer to Fig.15 Before forming the second capacitor dielectric layer 36 on the second electrode plate 32, an initial second capacitor dielectric layer 36A is first formed to cover the top and sidewalls of the second electrode plate 32, and the initial second capacitor dielectric layer 36A exposes the first capacitor dielectric material layer 31A.

[0143] Subsequently, the second capacitor dielectric material layer (not shown) on the first capacitor dielectric material layer 31A on the side of the second electrode plate 32 is removed to form a second capacitor dielectric layer 36A.

[0144] Specifically, after forming the second capacitor dielectric material layer covering the second electrode 32 and the first capacitor dielectric material layer 31A, the second capacitor dielectric material layer on the first capacitor dielectric material layer 31A on the side of the second electrode 32 is removed to form an initial second capacitor dielectric layer 36A.

[0145] Accordingly, in the subsequent process of forming the third electrode plate and the side electrode plate, the unnecessary initial second capacitor dielectric layer 36A and the first capacitor dielectric material layer 31A are removed.

[0146] Accordingly, combined with reference Figures 16 to 18 The steps of forming the third electrode plate 38 and the side electrode plate 37 include: forming a third electrode plate material layer 38A (such as Fig.16 ); patterning the third plate material layer 38A, retaining the remaining third plate material layer 38A located on the top of the initial second capacitor dielectric layer 36A as the third plate 38, retaining the remaining third plate material layer 38A located on the side wall of the initial second capacitor dielectric layer 36A as the side plate 37 (as shown in Fig.17 and Fig.18 shown).

[0147] It should be noted that if Fig.17 and Fig.18 As shown, in the same process of patterning the third electrode material layer 38A, after patterning the third electrode material layer 38A, the initial second capacitor dielectric layer 36A and the first capacitor dielectric material layer 31A exposed by the third electrode 38 and the side electrode 37 are also patterned, and the initial second capacitor dielectric layer 36A covering the portion of the top and the side wall of the second electrode 32 is retained as the second capacitor dielectric layer 36, and the remaining first capacitor dielectric material layer 31A covering the portion of the top of the first electrode 30 is retained as the first capacitor dielectric layer 31.

[0148] Specifically, simultaneously patterning the third plate material layer 38A, the initial second capacitor dielectric layer 36A, and the first capacitor dielectric material layer 31A can ensure that the boundaries of the formed third plate 38, the second capacitor dielectric layer 36, the side plate 27, and the first capacitor dielectric layer 31 are flush.

[0149] On the one hand, one-time patterning can save masks and use the same mask to form the third electrode 38, the second capacitor dielectric layer 36, the side electrode 37, and the first capacitor dielectric layer 31; on the other hand, it can reduce alignment errors and improve manufacturing accuracy, for example, reduce the probability of the second capacitor dielectric layer 36 or the first capacitor dielectric layer 31 covering an unnecessary position, or reduce the probability of the third electrode 38 or the side electrode 37 contacting other electrodes.

[0150] In this embodiment, after the third electrode material layer 38A is patterned, the third electrode 38 is connected to the side electrode 37 and covers the corner of the second capacitor dielectric layer 36 (such as Fig.17 As shown), therefore, the forming method further includes: removing the portion where the third electrode plate 38 and the side electrode plate 37 are connected, so that the corner of the second capacitor dielectric layer 36 covering the corner of the second electrode plate 32 is exposed (as shown in FIG. Fig.18 shown).

[0151] On the one hand, the portion where the third electrode plate 38 and the side electrode plate 37 are connected at the corner is removed, so that the third electrode plate material layer 38 is divided into the side electrode plate 37 and the third electrode plate 38, that is, under the same area, the number of electrode plates in the semiconductor structure is increased, thereby increasing the number of capacitors, and further increasing the capacitance density; on the other hand, the second capacitor dielectric layer 36 at the corner is relatively thin, and the portion where the third electrode plate 38 and the side electrode plate 37 are connected at the corner can reduce the leakage of the capacitor, thereby improving the reliability of the semiconductor structure.

[0152] For the detailed description of the forming method of this embodiment, reference can be made to the related description of the first embodiment.

[0153] Figures 19 to 23 It is a schematic structural diagram corresponding to each step in the third embodiment of the method for forming a semiconductor structure of the present invention.

[0154] The similarities between this embodiment and the above embodiment are not described in detail here. The difference between this embodiment and the above embodiment is that the side electrode plate 57 and the second electrode plate 52 are formed in the same process.

[0155] refer to Figure 19 to Figure 20 A second plate material layer 52A (eg, Fig.19 ); patterning the second electrode material layer 52A to form an opening 59 (as shown in FIG. 5A ) in the second electrode material layer 52A; Fig. 20 As shown), the opening 59 exposes the first capacitor dielectric layer 51, the remaining portion of the second electrode material layer 52A on one side of the opening 59 serves as the second electrode 52, and the remaining portion of the second electrode material layer 52A on the other side of the opening 59 serves as the side electrode 57.

[0156] By forming the opening 59 in the second electrode material layer 52A, the opening 59 is used to provide a space for the subsequent formation of the second capacitor dielectric layer, so as to fill the second capacitor dielectric material layer to form the second dielectric layer.

[0157] The side electrode plate 57 and the second electrode plate 52 are formed in the same film deposition process, thereby reducing the number of film depositions.

[0158] Therefore, in this embodiment, the thickness of the side plate 57 may be equal to the thickness of the second plate 52. The thickness of the side plate 57 refers to the longitudinal dimension of the side plate 57 along the normal direction of the surface of the second plate 52 (ie, the thickness direction of the second plate 52).

[0159] It should be noted that the side electrode plate 57 is formed together with the second electrode plate 52 , which can ensure that the thickness of the side electrode plate 57 is equal to the thickness of the second electrode plate 52 , so that a uniform electric field can be generated between the side electrode plate 57 and the second electrode plate 52 .

[0160] It should also be noted that if the thickness of the side plate 57 is greater than the thickness of the second plate 52, it is easy to cause uneven electric field distribution, increasing the risk of breakdown of the second capacitor dielectric layer 56; if the thickness of the side plate 57 is less than the thickness of the second plate 52, it is easy to reduce the facing area of ​​the side plate 57 and the second plate 52, resulting in poor effect of improving the capacitance density.

[0161] Accordingly, reference Figure 21 to Figure 22 In the step of forming the second capacitor dielectric layer 56 on the second electrode plate 52 , the second capacitor dielectric layer 56 is filled into the opening 59 .

[0162] Specifically, the step of forming the second capacitor dielectric layer 56 includes: forming a second capacitor dielectric material layer 56A covering the second electrode plate 52 and the side electrode plate 57, and the second capacitor dielectric material layer 56A is also filled in the opening 59 (such as Fig.21 ); patterning the second dielectric material layer 56A to form a second capacitor dielectric layer 56 (as shown); Fig. 22 shown).

[0163] In this embodiment, the process of filling the second capacitor dielectric material layer 56A in the opening 59 includes an atomic layer deposition process or a plasma chemical vapor deposition process.

[0164] The atomic layer deposition process includes performing multiple atomic layer deposition cycles. The atomic layer deposition process has good gap filling performance and step coverage, which correspondingly improves the filling capacity of the second capacitor dielectric material layer 56A in the opening 59 .

[0165] refer to Fig.23 A third electrode plate 58 is formed on the top of the second capacitor dielectric layer 56 .

[0166] The detailed description of the third electrode plate 58 is omitted here.

[0167] For the detailed description of the forming method of this embodiment, reference can be made to the related description of the first embodiment.

[0168] It should be noted that the semiconductor structure of the embodiment of the present invention may be formed by any of the formation methods of the aforementioned embodiments, or may be formed by other formation methods.

[0169] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, It is characterized in that include: A first plate; A first capacitor dielectric layer, located on a portion of the top of the first electrode plate; A second electrode plate, located on a portion of the top of the first capacitor dielectric layer; A second capacitor dielectric layer is located on a portion of the top and sidewall of the second electrode plate; A side plate, located on a portion of the top of the first capacitor dielectric layer, the side plate is located on a side of the second capacitor dielectric layer and is isolated from the second plate by the second capacitor dielectric layer; The third electrode plate is located on the top of the second capacitor dielectric layer.

2. The semiconductor structure according to claim 1, It is characterized in that The side electrode plate and the third electrode plate expose corners of the second capacitor dielectric layer.

3. The semiconductor structure according to claim 1 or 2, It is characterized in that At least any two of the side electrode plate, the third electrode plate and the second electrode plate have the same thickness.

4. The semiconductor structure according to claim 1, It is characterized in that The thickness of the first electrode plate is to 5. The semiconductor structure according to claim 1, It is characterized in that The thickness of the third electrode plate is to 6. The semiconductor structure according to claim 1, It is characterized in that The thickness of the first capacitor dielectric layer is to 7. The semiconductor structure according to claim 1, It is characterized in that The thickness of the second capacitor dielectric layer is equal to the thickness of the first capacitor dielectric layer.

8. The semiconductor structure according to claim 1, It is characterized in that The material of the first capacitor dielectric layer includes HfO 2 、HfSiO、TiO 2 , HfZrO, HfSiON, HfTaO, HfTiO, Ta 2 O 5 、ZrO 2 、ZrSiO 2 、Al 2 O 3 、SrTiO 3 , BaSrTiO and SiN; The material of the second capacitor dielectric layer includes HfO 2 、HfSiO、TiO 2 , HfZrO, HfSiON, HfTaO, HfTiO, Ta 2 O 5 、ZrO 2 、ZrSiO 2 、Al 2 O 3 、SrTiO 3 , BaSrTiO and SiN; The material of the first electrode plate includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al; The material of the second electrode plate includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al; The material of the third electrode plate includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

9. The semiconductor structure according to claim 1, It is characterized in that The semiconductor structure further includes: a first through-hole interconnect structure, located on the first electrode plate and electrically connected to the first electrode plate; a second through-hole interconnect structure, located on the second electrode plate and electrically connected to the second electrode plate; A third through-hole interconnect structure, located on the third electrode plate and electrically connected to the third electrode plate; A fourth through-hole interconnection structure is located on the side electrode plate and electrically connected to the side electrode plate; a first interconnection line connecting the first through-hole interconnection structure, the third through-hole interconnection structure and the fourth through-hole interconnection structure; The second interconnection line connects the second through-hole interconnection structure.

10. A method for forming a semiconductor structure, It is characterized in that include: providing a first electrode plate; forming a first capacitor dielectric layer on the first electrode plate, wherein the first capacitor dielectric layer covers a portion of the top of the first electrode plate; Forming a second electrode plate on the first capacitor dielectric layer, wherein the second electrode plate covers a portion of the top of the first capacitor dielectric layer; forming a second capacitor dielectric layer on the second electrode plate, wherein the second capacitor dielectric layer covers a portion of the top and sidewall of the second electrode plate; forming a side plate on a portion of the top of the first capacitor dielectric layer, the side plate being located on a side of the second capacitor dielectric layer and isolated from the second plate by the second capacitor dielectric layer; A third electrode plate is formed on the second capacitor dielectric layer.

11. The method for forming a semiconductor structure according to claim 10, It is characterized in that The side electrode plate and the third electrode plate are exposed at corners of the second capacitor dielectric layer covering the corners of the second electrode plate.

12. The method for forming a semiconductor structure according to claim 10 or 11, It is characterized in that The step of forming the third electrode plate and the side electrode plate includes: forming a third electrode plate material layer on the top and side walls of the second capacitor dielectric layer; The third electrode material layer is patterned, and the remaining portion of the third electrode material layer on the top of the second capacitor dielectric layer is retained as the third electrode plate, and the remaining portion of the third electrode material layer on the side wall of the second capacitor dielectric layer is retained as the side electrode plate.

13. The method for forming a semiconductor structure according to claim 12, It is characterized in that In the process of patterning the third electrode material layer, the corner of the second capacitor dielectric layer covering the corner of the second electrode is exposed.

14. The method for forming a semiconductor structure according to claim 12, It is characterized in that The step of forming a second capacitor dielectric layer on the second electrode plate includes: forming a second capacitor dielectric material layer covering the second electrode plate; The second capacitor dielectric material layer is patterned, and the remaining second capacitor dielectric material layer covering a portion of the top of the second electrode plate and the side wall of the second electrode plate is retained as the second capacitor dielectric layer.

15. The method for forming a semiconductor structure according to claim 10 or 11, It is characterized in that Before forming the first capacitor dielectric layer on the first electrode plate, the method further includes: forming a first capacitor dielectric material layer covering the first electrode plate; Before forming the second capacitor dielectric layer on the second electrode plate, the method further includes: forming an initial second capacitor dielectric layer covering the top and sidewalls of the second electrode plate, wherein the initial second capacitor dielectric layer exposes the first capacitor dielectric material; The steps of forming the third electrode plate and the side electrode plate include: forming a third electrode plate material layer on the top and side wall of the initial second capacitor dielectric layer; patterning the third electrode plate material layer, retaining the remaining third electrode plate material layer on the top of the initial second capacitor dielectric layer as the third electrode plate, and retaining the remaining third electrode plate material layer on the side wall of the initial second capacitor dielectric layer as the side electrode plate; Wherein, in the same process of patterning the third electrode material layer, after patterning the third electrode material layer, the initial second capacitor dielectric layer and the first capacitor dielectric material layer are also patterned, and the initial second capacitor dielectric layer covering a portion of the top and side walls of the second electrode is retained as the second capacitor dielectric layer, and the remaining first capacitor dielectric material layer covering a portion of the top of the first electrode is retained as the first capacitor dielectric layer.

16. The method for forming a semiconductor structure according to claim 15, It is characterized in that After patterning the third electrode material layer, the method further includes: removing a portion of the third electrode plate connected to the side electrode plate, so that a corner of the second capacitor dielectric layer covering the corner of the second electrode plate is exposed.

17. The method for forming a semiconductor structure according to claim 10 or 11, It is characterized in that The step of forming the second electrode plate and the side electrode plate includes: forming a second electrode plate material layer on the top of the first capacitor dielectric layer; patterning the second electrode plate material layer to form an opening in the second electrode plate material layer, wherein the opening exposes the first capacitor dielectric layer, and the remaining portion of the second electrode plate material layer on one side of the opening serves as the second electrode plate, and the remaining portion of the second electrode plate material layer on the other side of the opening serves as the side electrode plate; In the step of forming a second capacitor dielectric layer on the second electrode plate, the second capacitor dielectric layer is filled into the opening.

18. The method for forming a semiconductor structure according to claim 10, It is characterized in that The process of forming any one of the first capacitor dielectric layer and the second capacitor dielectric layer includes an atomic layer deposition process or a plasma chemical vapor deposition process.

19. The method for forming a semiconductor structure according to claim 10, It is characterized in that The method of the semiconductor structure further includes: forming a first through-hole interconnect structure on the first plate, and the first through-hole interconnect structure is electrically connected to the first plate; forming a second through-hole interconnection structure on the second electrode plate, and the second through-hole interconnection structure is electrically connected to the second electrode plate; A third through-hole interconnect structure is formed on the third electrode plate, and the third through-hole interconnect structure is electrically connected to the third electrode plate; A fourth through-hole interconnect structure is formed on the side plate, and the fourth through-hole interconnect structure is electrically connected to the side plate; forming a first interconnection line connecting the first through-hole interconnection structure, the third through-hole interconnection structure and the fourth through-hole interconnection structure; A second interconnection line is formed to connect the second through-hole interconnection structure.

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