Switch control circuit capable of completely turning off power supply

Abstract

The invention discloses a switch control circuit capable of completely turning off a power supply, which comprises a power supply button connected with a battery, a fourth resistor and a second resistor, the other end of the fourth resistor is connected with a fifth resistor and a chip, the grid electrode of a second switch tube is connected with the other end of the second resistor, and a third resistor and a second capacitor are connected with the grid electrode of the second switch tube. The source electrode of the second switch tube is grounded, the drain electrode of the second switch tube is connected with the first resistor and the grid electrode of the first switch tube, the source electrode of the first switch tube and the other end of the first resistor are connected with the battery end together, and the drain electrode of the first switch tube outputs a power supply to supply power to the whole circuit. The power button is pressed for a long time during startup, so that the battery supplies power to the chip capable of controlling input / output IO, and after the chip works, the output is pulled up, the power supply is self-locked, the power button is released, and continuous power supply is realized. The power button is pressed for a long time during shutdown, the chip detects a level signal, the chip is pulled down and output, self-locking of the power supply is relieved, the power button is released, and the equipment is completely powered off, so that the phenomenon of electrical loss in a closed state due to the fact that a soft switch cannot physically cut off battery power supply can be avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of switch circuits, and in particular to a switch control circuit capable of completely shutting off a power supply. Background Art

[0002] At present, the power switch control of battery-powered devices mostly uses a dip switch design to perform pure hardware physical power off and power on, commonly known as a hard switch. Another method is to use a key switch to control the power supply. However, the use of a key switch design cannot achieve pure hardware physical power off and power supply control, and the power switch control can only be performed through software judgment, that is, a soft switch. This power button soft switch design cannot completely physically cut off the power supply of the device. It can only be judged by software, using a chip with controllable input / output IO to control the power switch of other modules to cut off the power of most modules. However, the power supply of this power management chip cannot be turned off, resulting in a constant loss of power. Summary of the invention

[0003] The main technical problem solved by the present invention is to provide a switch control circuit that can completely shut down the power supply. The switch control circuit that can completely shut down the power supply can avoid the phenomenon that the soft switch cannot physically shut down the battery power supply, resulting in power loss in the off state.

[0004] In order to solve the above technical problems, the present invention provides a switch control circuit that can completely shut down the power supply, the switch control circuit that can completely shut down the power supply includes a power button SW1, a chip U1, a first capacitor C1, a second capacitor C2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first switch tube Q1 and a second switch tube Q2, wherein one end of the power button SW1 is connected to a battery, and the other end is connected to the fourth resistor R4 and the second resistor R2; the other end of the fourth resistor R4 is connected to the fifth resistor R5 , the chip input pin is connected, and the other end of the fifth resistor R5 is grounded, the gate of the second switch tube Q2 is connected to the other end of the second resistor R2, the third resistor R3 and the second capacitor C2 are connected to the gate of the second switch tube Q2, the other end of the third resistor R3 is connected to the chip U1 output pin 2, the other end of the second capacitor C2 is grounded, the source of the second switch tube Q2 is grounded, the drain is connected to the first resistor R1 and the gate of the first switch tube Q1, the source of the first switch tube Q1 is connected to the other end of the first resistor R1, and connected to the battery end together, and the drain of the first switch tube Q1 outputs the power supply VCC to power the entire circuit.

[0005] Furthermore, the first switch tube is an enhancement type PMOS tube, and the second switch tube is an enhancement type NMOS tube.

[0006] Furthermore, the fourth resistor R4 and the fifth resistor R5 are voltage-dividing resistors.

[0007] Furthermore, the first capacitor C1 and the second capacitor C2 are filter capacitors, wherein the first capacitor C1 allows the battery to pass through the button SW1 more smoothly, so that the chip U1 obtains a relatively smooth high-level signal; the second capacitor C2 filters the output to the gate level burrs of the second switch tube Q2.

[0008] Specifically, the enhanced NMOS transistor conduction condition is that the Vgs voltage is greater than the Vgs(th) voltage; the enhanced PMOS transistor conduction condition is that the Vgs voltage is less than the Vgs(th) voltage.

[0009] The present invention discloses a switch control circuit that can completely shut down the power supply, including a power button SW1, one end of which is connected to a battery, and the other end of which is connected to a fourth resistor R4 and a second resistor R2; the other end of the fourth resistor R4 is connected to a fifth resistor R5 and a chip input pin, and the other end of the fifth resistor R5 is grounded, the gate of the second switch tube Q2 is connected to the other end of the second resistor R2, the third resistor R3 and the second capacitor C2 are connected to the gate of the second switch tube Q2, the other end of the third resistor R3 is connected to the output pin 2 of the chip U1, the other end of the second capacitor C2 is grounded, the source of the second switch tube Q2 is grounded, the drain is connected to the first resistor R1 and the gate of the first switch tube Q1, the source of the first switch tube Q1 is connected to the other end of the first resistor R1, and connected to the battery terminal together, and the drain of the first switch tube Q1 outputs the power supply VCC to power the entire circuit. By combining the power switch button with software judgment, the battery-powered power supply can be completely shut down and the power supply can be controlled. The fast switching capability of enhanced N-channel MOS field effect transistors (NMOS tubes) and enhanced P-channel MOS field effect transistors (PMOS tubes) is used as switching elements, and the key switch is used as control, combined with software judgment, to lock the on and off of the MOS tube, thereby achieving the purpose of completely cutting off and supplying the power supply. Avoid the phenomenon of power loss in the off state caused by the inability of the soft switch to physically cut off the battery power supply. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the description only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0011] Figure 1 The figure is a circuit diagram of an embodiment of a switch control circuit capable of completely shutting off power.

[0012] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0013] The claims of the present invention are further described in detail below in conjunction with specific embodiments and drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments proposed by ordinary technicians in this field before making creative work also fall within the scope of protection of the present invention.

[0014] It should be understood that, in the description of the embodiments of the present invention, all directional indication terms, such as "up", "down", "left", "right", "front", "back", etc., indicate the orientation or position relationship based on the orientation, position relationship shown in the drawings or the orientation or position relationship in which the invented product is usually placed when in use, which is only for the convenience of simplifying the description of the present invention, and does not expressly or imply that the device, element or component referred to must have a specific orientation and a specific orientation structure, and should not be understood as a limitation on the present invention. It is only used to explain the relative position relationship, movement, etc. between the components shown in the drawings. When the specific posture changes, the directional indication may also change accordingly.

[0015] In addition, ordinal numbers such as "first" and "second" in the present invention are only used for the purpose of distinction, and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. The features defined as "first" and "second" can explicitly or implicitly indicate at least one of the technical features. In the description of the present invention, "multiple" means at least two, that is, two or more, unless otherwise clearly defined; "at least one" means one or one and more.

[0016] In the present invention, unless otherwise clearly stipulated and limited, the terms such as "installation", "setting", "connection", "fixation" and "screw-on" should be understood in a broad sense. For example, the positional relationship between components can be relatively fixed, or the components can be physically fixedly connected; they can be detachably connected or integrated; they can be mechanically connected or electrically connected; they can be directly connected or indirectly connected through an intermediate medium or component; they can be internally connected between two elements or interact with each other. Unless otherwise clearly defined in the specification, other interpretations may not achieve the corresponding functions or effects. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0017] The controller and control circuit involved in the present invention are conventional control technologies or units of those skilled in the art. For example, the control circuit of the controller can be realized by ordinary technicians in the field using existing technologies, such as simple programming. If the software or program involved in the control result is not described in detail, it belongs to the use of existing technologies or conventional technologies of ordinary technicians in the field. The power supply also uses the existing technologies in the field, and the main technical point of the present invention is to improve the mechanical device, so the present invention will not describe the specific circuit control relationship and circuit connection in detail.

[0018] The disclosure of the present invention provides many different embodiments or examples to realize different structures of the present invention. In order to simplify the disclosure of the present invention, the components and settings of specific examples are described in the present invention. Of course, they are only examples, and the purpose is not to limit the present invention. In addition, the present invention can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplicity and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the present invention provides various specific examples of processes and materials, but those of ordinary skill in the art can be aware of the application of other processes and / or the use of other materials.

[0019] The preferred embodiments of the present invention are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0020] like Figure 1 As shown, the present invention provides an embodiment of a switch control circuit that can completely shut down a power supply.

[0021] The switch control circuit that can completely shut down the power supply includes a power button SW1, a chip U1, a first capacitor C1, a second capacitor C2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first switch tube Q1 and a second switch tube Q2, wherein one end of the power button SW1 is connected to a battery, and the other end is connected to the fourth resistor R4 and the second resistor R2; the other end of the fourth resistor R4 is connected to the fifth resistor R5 , the chip input pin is connected, and the other end of the fifth resistor R5 is grounded, the gate of the second switch tube Q2 is connected to the other end of the second resistor R2, the third resistor R3 and the second capacitor C2 are connected to the gate of the second switch tube Q2, the other end of the third resistor R3 is connected to the chip U1 output pin 2, the other end of the second capacitor C2 is grounded, the source of the second switch tube Q2 is grounded, the drain is connected to the first resistor R1 and the gate of the first switch tube Q1, the source of the first switch tube Q1 is connected to the other end of the first resistor R1, and connected to the battery end together, and the drain of the first switch tube Q1 outputs the power supply VCC to power the entire circuit.

[0022] Specifically, the first switch tube is an enhanced PMOS tube, and the second switch tube is an enhanced NMOS tube. The conduction condition of the enhanced NMOS tube is that the Vgs voltage is greater than the Vgs(th) voltage; the conduction condition of the enhanced PMOS tube is that the Vgs voltage is less than the Vgs(th) voltage. The fourth resistor R4 and the fifth resistor R5 are voltage divider resistors. The first capacitor C1 and the second capacitor C2 are filter capacitors, wherein the first capacitor C1 allows the battery to pass through the button SW1 more smoothly, so that the chip U1 obtains a relatively smooth high-level signal; the second capacitor C2 filters the output to the second switch tube Q2 gate level burrs, spikes, etc., to avoid the second switch tube Q2 from switching incorrectly.

[0023] Turn on the device and long press the power button to allow the battery to power the chip with controllable input / output IO. When the chip is running, the corresponding output IO is pulled up to make the power supply self-locking. The power supply can be continuously supplied even if the power button is released.

[0024] Shutdown: Long press the power button to send a level signal to the chip. When the chip is running, it detects the level signal output by the power button and pulls down the corresponding output IO to release the self-locking of the power supply. When the power button is released, the device is completely powered off.

[0025] Specifically, when the device is in the off state, long press the power button SW1 to connect its two ends, and the battery provides current flowing to the second resistor R2 and the gate of the second switch tube Q2, and the gate voltage of the second switch tube Q2 is increased to the battery voltage, that is, the Vgs of the second switch tube Q2 is equal to the battery voltage, which is greater than Vgs(th), and the second switch tube Q2 is turned on, so the gate voltage of the first switch tube Q1 drops to close to zero volts, and the source of the first switch tube Q1 is connected to the battery, that is, the source voltage of the first switch tube Q1 is equal to the battery voltage, Vgs is approximately equal to the negative battery voltage, so Vgs is less than Vgs(th), the first switch tube Q1 is turned on, and its drain output power supply VCC supplies power to the entire circuit. When the chip U1 is running, the chip U1 output pin 2 outputs a continuous high level to the second resistor R3, which keeps the gate voltage of the second switch tube Q2 high (locked at a high level), so that the Vgs of the second switch tube Q2 is always greater than Vgs(th), and the second switch tube Q2 is always turned on, and the gate voltage of the first switch tube Q1 is always close to zero volts, that is, the Vgs of the first switch tube Q1 is always less than Vgs(th), and the first switch tube Q1 can be turned on, and its drain can continuously output the power supply VCC to power the entire circuit. At this time, release the power button and the device can also operate normally.

[0026] When the device is in the power-on state: long press the power button SW1 to connect its two ends, and output a high-level signal to the fourth resistor R4. Since the IO port voltage of the chip U1 is not enough to withstand the battery voltage, the high level is divided by the voltage-dividing fourth resistor R4 and the fifth resistor R5, and then output to the chip U1 input pin 1. When the input pin 1 of the chip U1 detects the high-level signal output from the power button SW1, the output pin 2 of the chip U1 outputs a low level to the third resistor R3, and the gate voltage of the second switch tube Q2 is pulled down to release the high-level self-locking, that is, the gate voltage of the second switch tube Q2 is close to zero volts, so that the Vgs of the second switch tube Q2 is less than Vgs(th), that is, the second switch tube Q2 is turned off. At this time, the gate of the first switch tube Q1 is pulled up to the battery voltage through the first resistor R1, that is, the gate voltage of the first switch tube Q1 is approximately equal to the battery voltage, and Vgs of the first switch tube Q1 is greater than Vgs(th). The first switch tube Q1 is turned off, so there is no power output at the drain of the first switch tube Q1. When the power button SW1 is released, the entire circuit is completely powered off, the device stops running, and no electronic devices consume battery power.

[0027] The fast switching capability of enhanced N-channel MOS field effect transistors (NMOS tubes) and enhanced P-channel MOS field effect transistors (PMOS tubes) are used as switching elements. A key switch is used as control, combined with software judgment, to lock the on and off of the MOS tube, thereby achieving the purpose of completely cutting off and supplying power to the power supply.

[0028] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents, and these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A switch control circuit that can completely shut down the power supply, It is characterized in that It includes a power button SW1, a chip U1, a first capacitor C1, a second capacitor C2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first switch tube and a second switch tube, wherein one end of the power button is connected to a battery, and the other end is connected to the fourth resistor R4 and the second resistor R2; the other end of the fourth resistor R4 is connected to the fifth resistor R5 and the chip input pin, and the other end of the fifth resistor R5 is grounded, the gate of the second switch tube is connected to the other end of the second resistor R2, the third resistor R3, the second capacitor C2, and the gate of Q2 are connected together, the other end of R3 is connected to the chip U1 output pin 2, and the other end of C2 is connected to GND, the source of the second switch tube Q2 is grounded, and the drain is connected to the first resistor R1 and the gate of the first switch tube Q1, the source of the first switch tube Q1 is connected to the other end of the first resistor R1, and connected to the battery end together, and the drain of the first switch tube Q1 outputs the power supply VCC to power the entire circuit.

2. The switch control circuit capable of completely shutting off the power supply according to claim 1, It is characterized in that The first switch tube Q1 is an enhanced PMOS tube, and the second switch tube Q2 is an enhanced NMOS tube.

3. The switch control circuit capable of completely shutting off the power supply according to claim 1, It is characterized in that The fourth resistor R4 and the fifth resistor R5 are voltage dividing resistors.

4. A switch control circuit capable of completely shutting off a power supply according to any one of claims 1 to 3, It is characterized in that The first capacitor C1 and the second capacitor C2 are filter capacitors, wherein the first capacitor C1 allows the battery to pass through the button SW1 more smoothly, so that the chip U1 obtains a relatively smooth high-level signal; the second capacitor C2 filters the output to the gate level burrs of the second switch tube Q2.

5. The switch control circuit capable of completely shutting off the power supply according to claim 2, It is characterized in that The conduction condition of the enhancement type NMOS tube is that the Vgs voltage is greater than the Vgs(th) voltage; the conduction condition of the enhancement type PMOS tube is that the Vgs voltage is less than the Vgs(th) voltage.

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