Current sharing circuit and method of multi-phase voltage reduction unit

Abstract

The invention discloses a current sharing circuit and method of a multiphase step-down unit, and belongs to the technical field of electric energy conversion, the current sharing circuit comprises N phases of current sharing units, the first end of each phase of current sharing unit is short-circuited, and each phase of current sharing unit correspondingly collects an inductive current signal of one phase of step-down unit; and the second end of each phase of current sharing unit correspondingly outputs a control signal of the switch in one phase of voltage reduction unit. According to the current sharing circuit and method of the multi-phase step-down unit, current sharing among phases of the multi-phase step-down unit can be achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of electric energy conversion, and in particular to a current balancing circuit and method for a multi-phase buck unit. Background Art

[0002] In a step-down power management system, the buck converter (BUCK) is the core power conversion module, and its load capacity directly affects the output performance of the system. Single-phase buck converters are limited by factors such as the current carrying capacity of power devices, heat dissipation conditions, and parasitic parameters, and the maximum load current is usually about 25A. In order to meet higher power requirements, the industry generally adopts a multi-phase buck unit parallel architecture to increase the total load capacity of the system by superimposing multi-phase currents. Ideally, the current of each phase should be evenly distributed to achieve optimal heat distribution and efficiency. However, in actual applications, due to factors such as process deviations of each phase buck chip, differences in control signal delays, and mismatches in power circuit parasitic parameters, the current distribution of each phase will be uneven, which will lead to problems such as local overheating risks, reduced efficiency, and reliability risks.

[0003] Therefore, there is an urgent need for an efficient and reliable multi-phase buck unit current equalization circuit and method that can achieve fast dynamic current equalization under complex working conditions while taking into account system cost and integration to meet the stringent requirements of high power density power supply systems. Summary of the invention

[0004] The present invention aims to provide a current sharing circuit and method for a multi-phase step-down unit.

[0005] To achieve the above object, the technical solution of the present invention is: A current balancing circuit for a multi-phase buck unit, comprising N-phase current balancing units, wherein the first end of each phase current balancing unit is short-circuited, each phase current balancing unit correspondingly collects an inductor current signal of a phase buck unit, and the second end of each phase current balancing unit correspondingly outputs a control signal of a switch in the phase buck unit; The current balancing unit includes a voltage dividing module, an error amplifying module, a PWM generating module, a conduction time generating module, an RS triggering module, and a logic control module. The first end of the voltage dividing module is connected to the output voltage of the step-down unit, the second end of the voltage dividing module is connected to the negative input end of the error amplifying module, the positive input end of the error amplifying module is connected to the chip reference voltage, the output end of the error amplifying module outputs a first voltage and is connected to the first end of the PWM generating module, the second end of the PWM generating module is connected to the first input end of the RS triggering module, the second input end of the RS triggering module is connected to the conduction time generating module, the first output end of the RS triggering module is connected to the first end of the logic control module, and the second and third ends of the logic control module output control signals of switches in the step-down unit.

[0006] In a specific embodiment, the PWM generation module includes multiple transistors, multiple amplifiers and a first current source, the first ends of the second transistor, the third transistor and the fourth transistor are connected to the second voltage, the second end of the second transistor is connected to the first current source, the second end of the third transistor is connected to the first end of the first trimming resistor, the second end of the first trimming resistor is connected to the first ground, the third end of the second transistor is connected to the third end of the third transistor, the second end of the second transistor and the third end of the fourth transistor, the second end of the fourth transistor is connected to the negative input end of the second amplifier and the first end of the fourth resistor, the second end of the fourth resistor is connected to the second ground, the positive input end of the second amplifier is connected to the first voltage, the output end of the second amplifier is connected to the third end of the eighth transistor, and the The first end of the eighth transistor is connected to the first end of the fourth resistor, the second end of the eighth transistor is connected to the second end of the ninth transistor, the third end of the ninth transistor, and the third end of the tenth transistor, the first ends of the ninth transistor and the tenth transistor are connected to the second voltage, the second end of the tenth transistor is connected to the first end of the second trimming resistor, and the second end of the second trimming resistor is connected to the third voltage; the first end of the first proportional trimmer is connected to the second voltage, the second end of the first proportional trimmer is connected to the second end of the tenth transistor, and the third end of the first proportional trimmer is connected to the third end of the ninth transistor; the second end of the tenth transistor is connected to the positive input end of the third amplifier, the negative input end of the third amplifier is connected to the fourth voltage, and the output end of the third amplifier outputs a PWM signal.

[0007] In a specific embodiment, the PWM generation module includes multiple transistors, multiple amplifiers, and multiple resistors. The positive input terminal of the fourth amplifier is connected to the chip reference voltage, the negative input terminal of the fourth amplifier is connected to the first terminal of the eighteenth transistor, the output terminal of the fourth amplifier is connected to the third terminal of the eighteenth transistor, the first terminal of the eighteenth transistor is connected to the first terminal of the fifth resistor, the second terminal of the fifth resistor is connected to the first terminal of the first resistor trimmer, the second terminal of the first resistor trimmer is connected to the second ground, the second voltage is connected to the first terminal of the nineteenth transistor and the twenty-second transistor, the second terminal of the nineteenth transistor is connected to the third terminal of the nineteenth transistor, the second terminal of the eighteenth transistor, the third terminal of the twenty-second transistor, and the third terminal of the thirty-first transistor, the second terminal of the twenty-second transistor is connected to the first terminal of the third trimming resistor, the second terminal of the third trimming resistor is connected to the first ground, the first terminal of the second ratio trimmer is connected to the second voltage, the third terminal of the second ratio trimmer is connected to the third terminal of the nineteenth transistor, and the second terminal of the second ratio trimmer is connected to the second voltage. the second end of the thirty-first transistor is connected to the negative input end of the fifth amplifier and the first end of the ninth resistor, the first positive input end of the fifth amplifier is connected to the first voltage, the second positive input end of the fifth amplifier is connected to the fifth voltage, the output end of the fifth amplifier is connected to the third end of the thirty-second transistor, the first end of the thirty-second transistor is connected to the first end of the ninth resistor, the second end of the ninth resistor is connected to the first end of the second resistor trimmer, the second end of the second resistor trimmer is connected to the second ground, the second voltage is connected to the first ends of the thirty-third transistor and the thirty-fourth transistor, the second end of the thirty-third transistor is connected to the third end of the thirty-fourth transistor, the third end of the thirty-third transistor and the second end of the thirty-second transistor, the second end of the thirty-fourth transistor is connected to the first end of the fourth trimming resistor, the second end of the fourth trimming resistor is connected to the third voltage, the second end of the thirty-fourth transistor is connected to the positive input end of the sixth amplifier, the negative input end of the sixth amplifier is connected to the fourth voltage, and the output end of the sixth amplifier outputs a PWM signal.

[0008] In a specific embodiment, the first ratio trimmer includes a plurality of transistors, and each two transistors are connected in series between the second voltage and the second end of the tenth transistor; The second ratio trimmer includes a plurality of transistors, and every two transistors are connected in series and connected between the second voltage and the second end of the twenty-second transistor.

[0009] In a specific embodiment, each of the first trimming resistor, the second trimming resistor, the third trimming resistor, and the fourth trimming resistor comprises an equivalent resistor of a plurality of transistors connected in series.

[0010] In a specific embodiment, the first resistance trimmer includes a plurality of resistors and a plurality of transistors, the plurality of resistors are connected in series between the fifth resistor and the second ground, and a transistor is connected in parallel at both ends of each resistor; The second resistance trimmer includes a plurality of resistors and a plurality of transistors. The plurality of resistors are connected in series and connected between the ninth resistor and the second ground. A transistor is connected in parallel at both ends of each resistor.

[0011] In a specific embodiment, the driving circuit of the transistor includes a second current source, a first fuse, a first Schmitt trigger, and a first inverter. The second current source is connected to the first end of the first fuse, the second end of the first fuse is connected to the second ground, and the first end of the first fuse, the first Schmitt trigger, and the first inverter are connected in sequence.

[0012] In a specific embodiment, the driving circuit of the transistor further includes a second inverter, and the first end of the first fuse, the first Schmitt trigger, the first inverter, and the second inverter are connected in sequence.

[0013] In a specific embodiment, the current sharing circuit of the multi-phase buck unit further includes a clamping module, the output end of the error amplification module is connected to the first end of the clamping module, and the second end of the clamping module is connected to the first end of the PWM generation module.

[0014] A current balancing method for a multi-phase buck unit, applied to a current balancing circuit of the multi-phase buck unit, comprising: Connecting the first voltages of the current sharing units of each phase together; The current sampling resistor and the output voltage of the error amplifier module at zero inductance current are adjusted through the proportional coefficient.

[0015] The above-mentioned current balancing method for a multi-phase buck unit further includes adjusting the target current limit.

[0016] Beneficial effect: The present invention provides a current balancing circuit and method for a multi-phase buck unit, which can achieve current balancing between each phase of the multi-phase buck unit; C0 and current sampling resistor R I The proportional coefficient is adjusted to ensure that the voltage V C In the case of a short circuit, the inductor current I L equal to achieve current sharing between phases; in addition, the current sampling resistor R I The output voltage V of the error amplifier module when the inductor current is zero C0 Can be adjusted individually and no additional adjustment is required for the target current limit I MAX Adjusting it separately again saves adjustment steps and testing time.

[0017] In order to make the above features and advantages of the invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 The present invention is a schematic structural diagram of a current sharing circuit of a multi-phase buck unit.

[0019] Figure 2 for Figure 1 Circuit diagram of the current balancing unit.

[0020] Figure 3 for Figure 2 FIG. 1 is a circuit diagram of a first specific embodiment of a PWM generation module.

[0021] Figure 4 for Figure 2 FIG. 1 is a circuit diagram of a second specific embodiment of a PWM generation module.

[0022] Figure 5 FIG. 4 is a circuit diagram of a first specific embodiment of a transistor driving circuit.

[0023] Figure 6 FIG. 4 is a circuit diagram of a second specific embodiment of a transistor driving circuit.

[0024] Figure 7 for Figure 4 Circuit diagram of amplifier A5. DETAILED DESCRIPTION

[0025] In order to make the purpose and technical solution of the embodiment of the present invention clearer, the technical solution of the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all of the embodiments. Based on the described embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0026] Figure 1 FIG. 1 is a schematic diagram of a current sharing circuit of a multi-phase buck unit of the present invention. Figure 1As shown, a current balancing circuit 1 of a multi-phase buck unit of the present invention is connected to a multi-phase buck circuit 2, wherein the multi-phase buck circuit 2 includes N-phase buck units, specifically a first-phase buck unit 21, a second-phase buck unit 22, and up to the N-phase buck unit 2N, the input ends of the N-phase buck units are connected in parallel, and the output ends of the N-phase buck units are connected in parallel. The current balancing circuit 1 of the multi-phase buck unit includes N-phase current balancing units, specifically a first-phase current balancing unit 11, a second-phase current balancing unit 12, and up to the N-phase current balancing unit 1N, the first end of each phase current balancing unit is short-circuited, each phase current balancing unit corresponds to collecting the inductor current signal of a phase buck unit, and the second end of each phase current balancing unit corresponds to outputting the control signal of the switch in the phase buck unit.

[0027] Please refer to Figure 2 , the following takes the first phase buck unit 21 and the first phase current equalizing unit 11 as an example to introduce the specific topology of the current equalizing circuit of a multi-phase buck unit of the present invention. More specifically, the first phase buck unit 21 includes a switch S1, a switch S2, an inductor L1 and a capacitor C1, and the input voltage V in The positive electrode is connected to the first end of the switch S1, the second end of the switch S1 is connected to the first end of the switch S2, and the second end of the switch S2 is connected to the input voltage V in The first end of the switch S2 is connected to the first end of the inductor L1, the second end of the inductor L1 is connected to the first end of the capacitor C1, the second end of the capacitor C1 is connected to the second end of the switch S2, and the output voltage V is across the capacitor C1. o The node voltage between switch S1 and switch S2 is V SW , switch S1 is the upper tube of the buck unit, and switch S2 is the lower tube of the buck unit.

[0028] More specifically, the first current balancing unit 11 includes a voltage dividing module 111, an error amplifying module 112, a clamping module 113, a PWM generating module 114, a conduction time generating module 115, an RS triggering module 116, and a logic control module 117. The first end of the voltage dividing module 111 is connected to the output voltage V o The second end of the voltage divider module 111 is connected to the negative input end of the error amplifier module 112, and the positive input end of the error amplifier module 112 is connected to the chip reference voltage V ref , the output voltage V of the output terminal of the error amplifier module 112 C The first end of the clamp module 113 is connected to the second end of the clamp module 113, the first end of the PWM generation module 114 is connected to the second end of the PWM generation module 114, the second end of the PWM generation module 114 is connected to the S input end of the RS trigger module 116, the R input end of the RS trigger module 116 is connected to the conduction time generation module 115, the Q output end of the RS trigger module 116 is connected to the first end of the logic control module 117, and the second end and the third end of the logic control module 117 output the control signal G of the switch S1. S1The control signal G of switch S2 S2 .

[0029] More specifically, the voltage dividing unit 111 includes a resistor R1 and a resistor R2. The first end of the resistor R1 is connected to the output voltage V o The second end of the resistor R1 is connected to the first end of the resistor R2, the second end of the resistor R2 is connected to the first ground PGND, and the first end of the resistor R2 outputs a voltage V FB To the negative input terminal of the error amplification module 112 .

[0030] More specifically, the error amplification module 112 includes an amplifier, the second end of the voltage divider module 111 is connected to the negative input end of the amplifier, and the positive input end of the amplifier is connected to the chip reference voltage V ref , the output voltage of the amplifier is V C And connected to the first end of the clamping module 113.

[0031] More specifically, the clamping module 113 includes an amplifier A1 and a transistor Q1, wherein a first end of the transistor Q1 is connected to an output end of the error amplifying module 112, a second end of the transistor Q1 is grounded, a third end of the transistor Q1 is connected to an output end of the amplifier A1, a negative input end of the amplifier A1 is connected to an output end of the error amplifying module 112 and a first end of the PWM generating module 114, and a positive input end of the amplifier A1 is connected to a voltage V CMAX When the voltage V at the negative input of amplifier A1 is C Greater than voltage V CMAX When the output of amplifier A1 outputs a low level, transistor Q1 is turned on, pulling down the voltage V C So that it is smaller than the voltage V CMAX , the output terminal of amplifier A1 outputs a high level, turning off transistor Q1, thereby achieving the voltage V C The voltage V C The maximum value is clamped to the voltage V CMAX , which can limit the maximum inductor current of the buck unit, that is, the "current limit" function can be easily realized by using the current loop. Among them, the voltage V CMAX The voltage V of the step-down chip C upper limit.

[0032] Furthermore, the first current balancing unit 11 may further include a filtering module 118. The output end of the error amplification module 112 is grounded through the filtering module 118, and is used to adjust the voltage V output by the error amplification module 112. C Perform filtering.

[0033] More specifically, the filtering module 118 includes a resistor R3 and a capacitor C2 , a first end of the resistor R3 is connected to the output end of the error amplification module 112 , a second end of the resistor R3 is connected to a first end of the capacitor C2 , and a second end of the capacitor C2 is grounded SGND.

[0034] More specifically, the on-time generation module 115 outputs the on-time T of the switch S1. on The level signal.

[0035] Furthermore, the first current balancing unit 11 may further include a first driving module 119 and a second driving module 1110. The second end of the logic control module 117 outputs a control signal G of the switch S1 through the first driving module 119. S1 The third terminal of the logic control module 117 outputs the control signal G of the switch S2 through the second driving module 1110. S2 .

[0036] More specifically, the voltage dividing module 111 collects the output voltage V of the first phase buck unit 21. o , generating a voltage V FB To the error amplification module 112, the error amplification module 112 converts the chip reference voltage V ref With voltage V FB The error is amplified to get the voltage V C , the PWM generation module 114 generates a PWM signal to the S input terminal of the RS trigger module 116, and the on-time generation module 115 outputs the on-time T of the switch S1. on The relevant level signal is sent to the Q input terminal of the RS trigger module 116, and the RS trigger module 116 outputs the level signal to the logic control module 117, and the logic control module 117 outputs the control signal G of the switch S1. S1 The control signal G of switch S2 S2 .

[0037] Among them, the voltage V C In valley current mode, the voltage V C has a fixed proportional relationship with the inductor current valley value; in peak current mode, the voltage V C It is in fixed proportion to the peak value of the inductor current. When the load becomes heavier, the voltage V C When the load becomes lighter, the voltage V C Therefore, in the multi-phase buck circuit, the output end of the error amplifier module of each phase current balancing unit is short-circuited, that is, the voltage V C Short-circuit them together and ensure that the proportional relationship is the same, that is, current sharing of each phase can be achieved. Among them, the proportional relationship is realized by the PWM generation module of each phase.

[0038] Furthermore, the topology and function of the remaining phase step-down units and the remaining phase current balancing units are similar to Figure 2 The same as in, no further description is given here.

[0039] For further information, please refer to Figure 3 , Figure 3 FIG. 1 is a schematic diagram of a first specific embodiment of a PWM generation module. In this specific embodiment, the PWM generation module includes a plurality of transistors, a plurality of amplifiers and a current source I b The first terminals of transistors Q2, Q3 and Q4 are connected to voltage Vcc, and the second terminal of transistor Q2 is connected to current source I b , the second end of transistor Q3 is connected to resistor R DS1 The first end of the resistor R DS1 The second end of transistor Q2 is connected to the first ground PGND, the third end of transistor Q2 is connected to the third end of transistor Q3, the second end of transistor Q2, and the third end of transistor Q4, the second end of transistor Q4 is connected to the negative input end of amplifier A2 and the first end of resistor R4, the second end of resistor R4 is connected to the second ground SGND, and the positive input end of amplifier A2 is connected to voltage V C The output end of the amplifier A2 is connected to the third end of the transistor Q8, the first end of the transistor Q8 is connected to the first end of the resistor R4, the second end of the transistor Q8 is connected to the second end of the transistor Q9, the third end of the transistor Q9, and the third end of the transistor Q10, the first ends of the transistor Q9 and the transistor Q10 are connected to the voltage Vcc, and the second end of the transistor Q10 is connected to the resistor R DS2 The first end of the resistor R DS2 The second end is connected to the voltage V SW The first end of the first ratio trimmer 1141 is connected to the voltage Vcc, the second end of the first ratio trimmer 1141 is connected to the second end of the transistor Q10, and the third end of the first ratio trimmer 1141 is connected to the third end of the transistor Q9; the second end of the transistor Q10 is connected to the positive input end of the amplifier A3, and the negative input end of the amplifier A3 is connected to the voltage V R , the output end of amplifier A3 outputs PWM signal. Among them, the voltage V R is the resistance R DS1 The voltage across the two ends, voltage V X is the resistance R DS2 The voltage at the first terminal.

[0040] Furthermore, the first ratio adjuster 1141 includes a plurality of transistors, and each two transistors are connected in series between the voltage Vcc and the second end of the transistor Q10. Figure 3In the embodiment of the invention, the first ratio adjuster 1141 includes four transistors, the first ends of transistors Q14 and Q15 are connected to the voltage Vcc, the second end of transistor Q14 is connected to the first end of transistor Q16, the second end of transistor Q16 is connected to the second end of transistor Q10, the second end of transistor Q15 is connected to the first end of transistor Q17, the second end of transistor Q17 is connected to the second end of transistor Q10, the third end of transistor Q16 is connected to the control signal TR1, and the third end of transistor Q17 is connected to the control signal TR2. Among them, transistor Q9 and transistor Q10 form a current mirror, and by controlling the switches of transistors Q16 and transistor Q17, the number of transistors connected to the current mirror can be controlled, thereby adjusting the proportional coefficient k.

[0041] Furthermore, the resistor R DS1 Includes the equivalent resistance of multiple transistors connected in series. Figure 3 In the specific embodiment, the resistor R DS1 It includes an equivalent resistance of transistor Q5, transistor Q6 and transistor Q7 connected in series. Transistor Q5, transistor Q6 and transistor Q7 work in a linear region. The third terminals of transistor Q5, transistor Q6 and transistor Q7 are connected to voltage Vcc.

[0042] Furthermore, the resistor R DS2 Includes the equivalent resistance of multiple transistors connected in series. Figure 3 In the specific embodiment, the resistor R DS2 It includes an equivalent resistance of a transistor Q11, a transistor Q12, and a transistor Q13 connected in series. The transistor Q11, the transistor Q12, and the transistor Q13 work in a linear region. The third terminals of the transistor Q11, the transistor Q12, and the transistor Q13 are connected to a voltage Vcc.

[0043] More specifically, the current source I b Through the current mirror composed of transistor Q2, transistor Q3, and transistor Q4, the resistor R DS1 The voltage V R For I b *R DS1 Comparator A2 and transistor Q8 form a voltage holding circuit, which keeps the voltage at the negative input of comparator A2 at the voltage V at the positive input. C , generating a current I flowing through resistor R4 VC , where I VC =V C / R4, and transmits current to the current mirror composed of transistors Q9, Q10, Q14, and Q15 through the second end of transistor Q8. The current flows through resistor R DS2 Generates a voltage and superimposes it on the voltage V SW The voltage V X.

[0044] At voltage V X With voltage V R When they are equal, we can get the following equation: , (1) Where k is the proportionality coefficient.

[0045] For valley current mode, the voltage V SW and the inductor current I L The relationship is V SW =-I L ×R on , where R on is the on-resistance of switch S2, and substituting it into equation (1) yields: . (2) By taking the derivative of formula (2), we can get: (3) Among them, R I is the current sampling resistor, which is one of the key parameters in multi-phase buck design; R I is the voltage V C The amount of change and the inductor current I L Change The ratio of voltage V C How much has the inductor current I changed? L How much has changed accordingly?

[0046] Let the inductor current be equal to 0, equation (2) is: (4) Among them, the voltage V C0 The output voltage of the error amplifier module when the inductor current is zero, that is, the inductor current I L When θ is equal to 0, the output voltage of the error amplifier module 112 is

[0047] Among them, the voltage V C and the inductor current I L The relationship can usually be simplified to the expression: (5) It can be seen that in multi-phase buck applications (i.e., the voltage VC of each phase is short-circuited together and equal), even if the current sampling resistors RI are exactly the same, the output voltage VC0 of the error amplifier module at zero inductor current is quite different, which will still lead to a large difference in the inductor current IL, that is, the current sharing effect is not good. Therefore, the output voltage VC0 of the error amplifier module at zero inductor current is also one of the key parameters in multi-phase buck applications.

[0048] In the actual operation of multi-phase buck, due to the difference between chips, the voltage V C0 and current sampling resistor R I There will also be differences, resulting in the inductor current I L Different, that is, the current sharing effect is not good. Therefore, referring to formula (3) and formula (4), Figure 3 The voltage V C0 and current sampling resistor R I Adjust by proportional coefficient k, that is, change the voltage V C The current generated is the same as the current flowing through the resistor R DS2 The ratio of the current mirror between the currents ensures that the voltage V C In the case of a short circuit, the inductor current I L equal, achieving current sharing among the phases.

[0049] In addition, the current sampling resistor R I Or the output voltage V of the error amplifier module when the inductor current is zero C0 After that, the target current limit I MAX The current is usually limited by adjusting the voltage V C clamping is achieved. Since the voltage V C The maximum is clamped at V CMAX , then the target current limit I MAX As shown in formula (6): (6) Therefore, by adjusting the current sampling resistor R I Or the output voltage V of the error amplifier module when the inductor current is zero C0 After improving the current sharing performance, the target current limit I MAX Continue to adjust, otherwise the difference in current limit between multi-phase buck chips will become more significant.

[0050] Optionally, the current sampling resistor R I Usually take constant temperature coefficient resistor, resistor R DS1 and resistor R DS2 The power tube resistor is of the same type as the lower tube, so that better temperature characteristics can be obtained and the two parameters can be kept small when the process changes.

[0051] When switch S1 is turned off and switch S2 is turned on, the voltage V SW is the inductor current I L Multiply by the on-resistance R of switch S2 on , which is a negative voltage relative to the ground. As the inductor current I L The voltage V SWGradually increases, voltage V X Also gradually increases; when the voltage V X Greater than voltage V R , the PWM signal output by comparator A3 is high level, and the off time is T off At the end, switch S1 is turned on and switch S2 is turned off. At this time, the level signal output by the on-time generating module 115 is low level, and the duration is the on-time T of switch S1. on When the level signal output by the on-time generating module 115 is at a high level, the on-time T on Ends and enters the next cycle. In this stage, the inductor current I L Rising, voltage V SW Gradually decreases, the voltage V X Also gradually decreases. Among them, the conduction time T on At input voltage V in and output voltage V o Once determined, it can be fixed and controlled by the on-time generating module 115; the off-time T off Determined by the PWM generation module 114 .

[0052] For further information, please refer to Figure 4 , Figure 4 FIG. 1 is a schematic diagram of a second specific embodiment of a PWM generation module. In this specific embodiment, the PWM generation module includes multiple transistors, multiple amplifiers, and multiple resistors. The positive input terminal of the amplifier A4 is connected to the chip reference voltage V ref , the negative input terminal of the amplifier A4 is connected to the first terminal of the transistor Q18, the output terminal of the amplifier A4 is connected to the third terminal of the transistor Q18, the first terminal of the transistor Q18 is connected to the first terminal of the resistor R5, the second terminal of the resistor R5 is connected to the first terminal of the first resistor trimmer 1143, the second terminal of the first resistor trimmer 1143 is connected to the second ground SGND, the voltage Vcc is connected to the first terminal of the transistor Q19 and the transistor Q22, the second terminal of the transistor Q19 is connected to the third terminal of the transistor Q19, the second terminal of the transistor Q18, the third terminal of the transistor Q22, and the third terminal of the transistor Q31, and the second terminal of the transistor Q22 is connected to the resistor R DS3 The first end of the resistor R DS3 The second end of the second proportional trimmer 1142 is connected to the first ground PGND, the first end of the second proportional trimmer 1142 is connected to the voltage Vcc, the third end of the second proportional trimmer 1142 is connected to the third end of the transistor Q19, and the second end of the second proportional trimmer 1142 is connected to the second end of the transistor Q22; the second end of the transistor Q31 is connected to the negative input end of the amplifier A5 and the first end of the resistor R9, and the first positive input end of the amplifier A5 is connected to the voltage V C The second positive input terminal of amplifier A5 is connected to the voltage V CMAXThe output end of the amplifier A5 is connected to the third end of the transistor Q32, the first end of the transistor Q32 is connected to the first end of the resistor R9, the second end of the resistor R9 is connected to the first end of the second resistor trimmer 1144, the second end of the second resistor trimmer 1144 is connected to the second ground SGND, the voltage Vcc is connected to the first end of the transistor Q33 and the transistor Q34, the second end of the transistor Q33 is connected to the third end of the transistor Q34, the third end of the transistor Q33 and the second end of the transistor Q32, and the second end of the transistor Q34 is connected to the resistor R DS4 The first end of the resistor R DS4 The second end is connected to the voltage V SW The second end of transistor Q34 is connected to the positive input end of amplifier A6, and the negative input end of amplifier A6 is connected to voltage V R , the output end of amplifier A6 outputs PWM signal. Among them, the voltage V R is the resistance R DS3 The voltage across the two ends, voltage V X is the resistance R DS4 The voltage at the first end. The resistance values ​​of the resistor R5 and the resistor R9 are equal.

[0053] Furthermore, the first resistance trimmer 1143 includes a plurality of resistors and a plurality of transistors, the plurality of resistors are connected in series between the resistor R5 and the second ground SGND, and a transistor is connected in parallel at both ends of each resistor. Figure 4 In the embodiment, the first resistance trimmer 1143 includes three resistors, wherein resistors R6, R7, and R8 are connected in series and connected between resistor R5 and the second ground SGND, two ends of resistor R6 are connected in parallel with the first end and the second end of transistor Q25, two ends of transistor R7 are connected in parallel with the first end and the second end of transistor Q26, two ends of transistor R8 are connected in parallel with the first end and the second end of transistor Q27, the third end of transistor Q25 is connected to the control signal TRN1, the third end of transistor Q26 is connected to the control signal TRN2, and the third end of transistor Q27 is connected to the control signal TRN3.

[0054] Optionally, the resistance values ​​of resistors R6, R7 and R8 are equal to the resistance value of resistor R5, and by controlling the on and off of transistors Q25, Q26 and Q27, the resistance value of resistor R5 connected in series with the first resistance trimmer 1143 is k1*R5.

[0055] Furthermore, the second ratio adjuster 1142 includes a plurality of transistors, and each two transistors are connected in series between the voltage Vcc and the second end of the transistor Q22. Figure 4In the embodiment of the invention, the second ratio adjuster 1142 includes four transistors, the first end of transistor Q20 is connected to the voltage Vcc, the second end of transistor Q20 is connected to the first end of transistor Q23, the second end of transistor Q23 is connected to the second end of transistor Q22, the second end of transistor Q21 is connected to the first end of transistor Q24, the second end of transistor Q24 is connected to the second end of transistor Q22, the third end of transistor Q23 is connected to the control signal TR3, and the third end of transistor Q24 is connected to the control signal TR4. Among them, transistor Q19 and transistor Q22 form a current mirror, and by controlling the switches of transistor Q23 and transistor Q24, the number of transistors connected to the current mirror can be controlled, thereby adjusting the proportional coefficient k2. In addition, transistor Q19 and transistor Q31 form a current mirror.

[0056] Furthermore, the resistor R DS3 Includes the equivalent resistance of multiple transistors connected in series. Figure 4 In the specific embodiment, the resistor R DS3 It includes an equivalent resistance of transistor Q28, transistor Q29 and transistor Q30 connected in series. Transistor Q28, transistor Q29 and transistor Q30 work in a linear region. The third terminals of transistor Q28, transistor Q29 and transistor Q30 are connected to voltage Vcc.

[0057] Furthermore, the resistor R DS4 Includes the equivalent resistance of multiple transistors connected in series. Figure 4 In the specific embodiment, the resistor R DS4 It includes an equivalent resistance of transistor Q38, transistor Q39, and transistor Q40 connected in series. Transistor Q38, transistor Q39, and transistor Q40 work in the linear region. The third terminals of transistor Q38, transistor Q39, and transistor Q40 are connected to voltage Vcc.

[0058] Furthermore, the second resistance trimmer 1144 includes a plurality of resistors and a plurality of transistors, the plurality of resistors are connected in series between the resistor R9 and the second ground SGND, and a transistor is connected in parallel at both ends of each resistor. Figure 4 In the embodiment, the second resistance trimmer 1144 includes three resistors, wherein a resistor R9, a resistor R10, and a resistor R11 are connected in series and connected between the resistor R9 and the second ground SGND, two ends of the resistor R9 are connected in parallel with the first end and the second end of the transistor Q35, two ends of the transistor R10 are connected in parallel with the first end and the second end of the transistor Q36, two ends of the transistor R11 are connected in parallel with the first end and the second end of the transistor Q37, the third end of the transistor Q35 is connected to the control signal TRN4, the third end of the transistor Q26 is connected to the control signal TRN5, and the third end of the transistor Q27 is connected to the control signal TRN6.

[0059] Optionally, the resistance values ​​of resistors R9, R10, and R11 are equal to the resistance value of resistor R9, and the resistance value of resistor R5 is equal to the resistance value of resistor R9. By controlling the on and off of transistors Q35, Q36, and Q37, the resistance value of resistor R9 connected in series with the second resistance trimmer 1144 is k1*R5.

[0060] exist Figure 4 In the specific embodiment, the comparator A4 and the transistor Q18 form a voltage holding circuit to keep the voltage of the negative input terminal of the comparator A4 at the voltage V of the positive input terminal. ref , then the current I flowing through resistor R5 R5 V ref / (k1*R5). The current I flowing through resistor R5 is converted by the current mirror. R5 Passed to resistor R DS3 , then the voltage V R V ref / ( k1*R5)* k2*R DS3 The current I flowing through resistor R5 is reduced by the current mirror. R5 The voltage of the negative input terminal of the comparator A5 is maintained at the voltage V of the first positive input terminal. C , then the current I flowing through transistor Q33 Q33 V C / (k1*R5)- V ref / (k1*R5). Transistor Q33 and transistor Q34 also form a current mirror, so the voltage V X is (V C / (k1*R5)- V ref / (k1*R5))* R DS4 +V SW .

[0061] Thus, the following equation can be obtained: (7) (8) . (9) also, Figure 4 The amplifier A5 of the specific embodiment includes two positive input terminals, which function to C Greater than voltage V CMAX When the amplifier A5 uses the voltage V CMAX Maintain the voltage to achieve the voltage V C clamping and chip current limiting purposes. Figure 4 When using amplifier A5, Figure 2The clamping module 113 in the embodiment may be omitted.

[0062] As shown in equations (8) and (9), compared with Figure 3 In the specific embodiment, it can be seen that Figure 4 In the specific embodiment, the current sampling resistor R I The output voltage V of the error amplifier module when the inductor current is zero C0 More specifically, the proportional coefficient k2 can be adjusted to adjust the output voltage V of the error amplifier module when the inductor current is zero. C0 , and then adjust the proportional coefficient k1 to adjust the current sampling resistor R I , thereby achieving that the voltage V C Under the short-circuit condition, ensure that the current sampling resistor R I The output voltage V of the error amplifier module when the inductor current is zero C0 equal, thus ensuring that the inductor current I of each phase L equal.

[0063] also, Figure 4 The specific embodiment has another advantage: As shown in formula (6), when the inductor current is zero, the output voltage V C0 After the adjustment is completed, the target current limit I can be adjusted directly by adjusting the proportional coefficient k1. MAX , that is, only one step of adjustment is required to complete the current sampling resistor R I and the target valley current limit I MAX Two parameters are adjusted. Among them, the voltage V C Upper limit V CMAX Usually comes from the reference module, and must be adjusted before the chip leaves the factory, so the consistency between chips is high. From formula (6), it can be seen that: when the zero inductor current is completed, the output voltage V C0 After the adjustment, the target current limit I of each chip is adjusted by adjusting the proportional coefficient k1. MAX When the current sampling resistor R I That is, in this way, there is no need to set the target current limit I MAX Adjusting it separately again saves adjustment steps and testing time.

[0064] It should be noted that the transistors in the present application include but are not limited to MOSFET, IGBT and other devices, wherein the MOSFET can be a P-type MOSFET or an N-type MOSFET.

[0065] For example, for Figure 3 The transistor Q16, the transistor Q17, and Figure 4The P-type MOSFETs such as transistor Q23 and transistor Q24 in the embodiment can be used as follows Figure 5 The transistor driving circuit shown specifically includes a current source I1, a fuse F1, a Schmitt trigger Trigger 1, and an inverter Inv 1. The current source I1 is connected to the first end of the fuse F1, the second end of the fuse F1 is connected to the second ground SGND, the first end of the fuse F1, the Schmitt trigger Trigger 1, and the inverter Inv 1 are connected in sequence, and the inverter Inv 1 outputs a control signal TRx of the transistor, where x=1, 2, 3, 4.

[0066] More specifically, the resistance of the fuse is very small (for example, 50 ohms), and the current flowing through it is about 10uA; when the fuse F1 is not blown, the voltage across the fuse F1 is only 0.5mv, and the inverter Inv 1 outputs a low level; when the fuse F1 is blown, the resistance of the fuse will increase greatly, and can reach a few hundred K ohms (for example, 300K ohms). At this time, the voltage across the fuse F1 will be 3V, and the inverter Inv 1 outputs a high level. Therefore, the relevant proportional coefficient can be adjusted by controlling the on and off of the fuse. Among them, the function of the Schmitt trigger Trigger 1 is to resist interference.

[0067] Optionally, Figure 5 The Schmitt trigger Trigger 1 in can also be replaced by an inverter.

[0068] For example, for Figure 4 The N-type MOSFETs such as transistors Q25, Q26, Q27, Q35, Q36, and Q37 in the embodiment may be used as follows: Figure 6 The transistor driving circuit shown specifically includes a current source I2, a fuse F2, a Schmitt trigger Trigger 2, an inverter Inv2, and an inverter Inv3. The current source I2 is connected to the first end of the fuse F2, the second end of the fuse F2 is connected to the second ground SGND, the first end of the fuse F2, the Schmitt trigger Trigger 2, the inverter Inv 2, and the inverter Inv3 are connected in sequence, and the inverter Inv 3 outputs a control signal TRy of the transistor, where y=1,2,3,4,5,6.

[0069] More specifically, the resistance of the fuse is very small (for example, 50 ohms), and the current flowing through it is about 10uA; when the fuse F2 is not blown, the voltage across the fuse F2 is only 0.5mv, and the inverter Inv 3 outputs a high level; when the fuse F2 is blown, the resistance of the fuse will increase greatly, and can reach a few hundred K ohms (for example, 300K ohms). At this time, the voltage across the fuse F2 will be 3V, and the inverter Inv 3 outputs a low level. Therefore, the relevant proportional coefficient can be adjusted by controlling the on and off of the fuse. Among them, the function of the Schmitt trigger Trigger 2 is anti-interference.

[0070] Optionally, Figure 6 The Schmitt trigger Trigger 2 in can also be replaced by an inverter.

[0071] exist Figure 5 and Figure 6 In the specific embodiment of the present invention, the control signal TRx and the control signal Try are in the default state that the driving transistor is turned on, and after the corresponding fuse is blown, the driving transistor is turned off. Figure 5 and Figure 6 In the specific embodiment of each adding an inverter, the default state of the control signal TRx and the control signal Try is that the transistor is turned off, and after the corresponding fuse is burned, the driving transistor is turned on. The present invention is not limited thereto.

[0072] Figure 7 for Figure 41 is a circuit diagram of a specific embodiment of the amplifier A5, wherein the amplifier A5 includes a plurality of transistors, a voltage Vcc is connected to the first ends of transistors Q41, Q42, Q44, and Q47, a second end of transistor Q41 is connected to the third end of transistor Q41 and the current source I3, a third end of transistor Q42 is connected to the third end of transistor Q41, a second end of transistor Q42 is connected to the second end and the third end of transistor Q43, a first end of transistor Q43 is connected to the second ground SGND, a third end of transistor Q44 is connected to the third end of transistor Q41, a second end of transistor Q44 is connected to the second end of transistor Q45 and the third end of transistor Q46, a first end of transistor Q43 is connected to the second ground SGND, a third end of transistor Q44 is connected to the third end of transistor Q41, a second end of transistor Q44 is connected to the second end of transistor Q45 and the third end of transistor Q47, The first terminal of transistor Q45 is connected to the second ground SGND; the second terminal of transistor Q46 is connected to the second terminal of transistor Q48, the third terminal of transistor Q48 is connected to the third terminal of transistor Q43, and the first terminal of transistor Q48 is connected to the second ground SGND; the third terminal of transistor Q47 is connected to the third terminal of transistor Q41, the second terminal of transistor Q47 is connected to the first terminal of transistor Q49, transistor Q50, and transistor Q51, the third terminal of transistor Q49 is connected to the second input terminal IN2, the second terminal of transistor Q49 is connected to the second terminal of transistor Q50, the third terminal of transistor Q50 is connected to the first input terminal IN1, and transistor Q The second end of transistor Q50 is connected to the second end of transistor Q58, the third end of transistor Q51 is connected to the third input terminal IN3, and the second end of transistor Q51 is connected to the second end of transistor Q59; voltage Vcc is connected to the first ends of transistors Q52 and Q53, the second end of transistor Q52 is connected to the first end of transistor Q54, the third end of transistor Q52 is connected to the second end of transistor Q54 and the third end of transistor Q53, the second end of transistor Q54 is connected to the second end of transistor Q56, the first end of transistor Q56 is connected to the second end of transistor Q58, the third end of transistor Q56 is connected to the third end of transistor Q43, and transistor Q44 is connected to the third end of transistor Q43. The third terminal of transistor Q58 is connected to the third terminal of transistor Q43, the first input terminal of transistor Q58 is connected to the second ground SGND, the second terminal of transistor Q53 is connected to the first terminal of transistor Q55, the third terminal of transistor Q55 is connected to the third terminal of transistor Q46, the second terminal of transistor Q55 is connected to the second terminal of transistor Q57, the third terminal of transistor Q57 is connected to the third terminal of transistor Q45, the first terminal of transistor Q57 is connected to the second terminal of transistor Q59, the third terminal of transistor Q59 is connected to the third terminal of transistor Q43, the first terminal of transistor Q59 is connected to the second ground SGND, and the second terminal of transistor Q57 is the output terminal OUT. When the voltage of the first input terminal IN1 is higher than the voltage of the second input terminal IN2, it will be limited by the voltage of the second output terminal IN2 to achieve the voltage V C The purpose of clamping and limiting the current of the chip.

[0073] The first input terminal IN1 corresponds to the first positive input terminal of the amplifier A5, and is connected to the voltage VC The second input terminal IN2 corresponds to the second positive input terminal of the amplifier A5, connected to the voltage V CMAX ; The third input terminal IN3 corresponds to the negative input terminal of the amplifier A5; the output terminal OUT is connected to the output terminal of the amplifier A5.

[0074] The present invention also provides a current balancing method for a multi-phase step-down unit, comprising: Step S1: The voltage V C Connect together; Step S2: The current sampling resistor R is adjusted by the proportionality coefficient. I , the output voltage V of the error amplifier module when the inductor current is zero C0 Make adjustments.

[0075] More specifically, for Figure 3 In the specific embodiment, according to formula (3) and formula (4), the current sampling resistor R I , the output voltage V of the error amplifier module when the inductor current is zero C0 Make adjustments.

[0076] More specifically, for Figure 4 In the specific embodiment, according to formula (8) and formula (9), the current sampling resistor R I , the output voltage V of the error amplifier module when the inductor current is zero C0 Make adjustments.

[0077] Furthermore, the current balancing method of a multi-phase buck unit of the present invention further includes: Step S3, set the target current limit I MAX Make adjustments.

[0078] More specifically, according to equation (6), the target current limit I MAX Make adjustments.

[0079] Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Any person having ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application.

Claims

1. A current sharing circuit for a multi-phase buck unit, characterized in that: It includes N-phase current balancing units, the first end of each phase current balancing unit is short-circuited, each phase current balancing unit correspondingly collects the inductor current signal of one phase buck unit, and the second end of each phase current balancing unit correspondingly outputs the control signal of the switch in one phase buck unit; The current balancing unit includes a voltage dividing module, an error amplifying module, a PWM generating module, a conduction time generating module, an RS triggering module, and a logic control module. The first end of the voltage dividing module is connected to the output voltage of the step-down unit, the second end of the voltage dividing module is connected to the negative input end of the error amplifying module, the positive input end of the error amplifying module is connected to the chip reference voltage, the output end of the error amplifying module outputs a first voltage and is connected to the first end of the PWM generating module, the second end of the PWM generating module is connected to the first input end of the RS triggering module, the second input end of the RS triggering module is connected to the conduction time generating module, the first output end of the RS triggering module is connected to the first end of the logic control module, and the second and third ends of the logic control module output control signals of switches in the step-down unit.

2. A current sharing circuit for a multi-phase buck unit as claimed in claim 1, characterized in that: The PWM generation module includes multiple transistors, multiple amplifiers and a first current source. The first ends of the second transistor, the third transistor and the fourth transistor are connected to the second voltage. The second end of the second transistor is connected to the first current source. The second end of the third transistor is connected to the first end of the first trimming resistor. The second end of the first trimming resistor is connected to the first ground. The third end of the second transistor is connected to the third end of the third transistor, the second end of the second transistor and the third end of the fourth transistor. The second end of the fourth transistor is connected to the negative input end of the second amplifier and the first end of the fourth resistor. The second end of the fourth resistor is connected to the second ground. The positive input end of the second amplifier is connected to the first voltage. The output end of the second amplifier is connected to the third end of the eighth transistor. The first end of the transistor is connected to the first end of the fourth resistor, the second end of the eighth transistor is connected to the second end of the ninth transistor, the third end of the ninth transistor, and the third end of the tenth transistor, the first ends of the ninth transistor and the tenth transistor are connected to the second voltage, the second end of the tenth transistor is connected to the first end of the second trimming resistor, and the second end of the second trimming resistor is connected to the third voltage; the first end of the first proportional trimmer is connected to the second voltage, the second end of the first proportional trimmer is connected to the second end of the tenth transistor, and the third end of the first proportional trimmer is connected to the third end of the ninth transistor; the second end of the tenth transistor is connected to the positive input end of the third amplifier, the negative input end of the third amplifier is connected to the fourth voltage, and the output end of the third amplifier outputs a PWM signal.

3. A current sharing circuit for a multi-phase buck unit as claimed in claim 1, characterized in that: The PWM generation module includes multiple transistors, multiple amplifiers, and multiple resistors. The positive input terminal of the fourth amplifier is connected to the chip reference voltage, the negative input terminal of the fourth amplifier is connected to the first terminal of the eighteenth transistor, the output terminal of the fourth amplifier is connected to the third terminal of the eighteenth transistor, the first terminal of the eighteenth transistor is connected to the first terminal of the fifth resistor, the second terminal of the fifth resistor is connected to the first terminal of the first resistor trimmer, the second terminal of the first resistor trimmer is connected to the second ground, the second voltage is connected to the first terminals of the nineteenth transistor and the twenty-second transistor, the second terminal of the nineteenth transistor is connected to the third terminal of the nineteenth transistor, the second terminal of the eighteenth transistor, the third terminal of the twenty-second transistor, and the third terminal of the thirty-first transistor, the second terminal of the twenty-second transistor is connected to the first terminal of the third trimming resistor, the second terminal of the third trimming resistor is connected to the first ground, the first terminal of the second proportional trimmer is connected to the second voltage, the third terminal of the second proportional trimmer is connected to the third terminal of the nineteenth transistor, and the second terminal of the second proportional trimmer is connected to the second terminal of the twenty-second transistor. end; the second end of the thirty-first transistor is connected to the negative input end of the fifth amplifier and the first end of the ninth resistor, the first positive input end of the fifth amplifier is connected to the first voltage, the second positive input end of the fifth amplifier is connected to the fifth voltage, the output end of the fifth amplifier is connected to the third end of the thirty-second transistor, the first end of the thirty-second transistor is connected to the first end of the ninth resistor, the second end of the ninth resistor is connected to the first end of the second resistor trimmer, the second end of the second resistor trimmer is connected to the second ground, the second voltage is connected to the first ends of the thirty-third transistor and the thirty-fourth transistor, the second end of the thirty-third transistor is connected to the third end of the thirty-fourth transistor, the third end of the thirty-third transistor and the second end of the thirty-second transistor, the second end of the thirty-fourth transistor is connected to the first end of the fourth trimming resistor, the second end of the fourth trimming resistor is connected to the third voltage, the second end of the thirty-fourth transistor is connected to the positive input end of the sixth amplifier, the negative input end of the sixth amplifier is connected to the fourth voltage, and the output end of the sixth amplifier outputs a PWM signal.

4. A current sharing circuit for a multi-phase buck unit as claimed in claim 2 or 3, characterized in that: The first ratio trimmer includes a plurality of transistors, and each two transistors are connected in series between the second voltage and the second end of the tenth transistor; The second ratio trimmer includes a plurality of transistors, and every two transistors are connected in series and connected between the second voltage and the second end of the twenty-second transistor.

5. A current sharing circuit for a multi-phase buck unit as claimed in claim 2 or 3, characterized in that: The first trimming resistor, the second trimming resistor, the third trimming resistor, and the fourth trimming resistor each include an equivalent resistor of a plurality of transistors connected in series.

6. A current sharing circuit for a multi-phase buck unit as claimed in claim 3, characterized in that: The first resistance trimmer includes a plurality of resistors and a plurality of transistors, the plurality of resistors are connected in series between the fifth resistor and the second ground, and a transistor is connected in parallel at both ends of each resistor; The second resistance trimmer includes a plurality of resistors and a plurality of transistors. The plurality of resistors are connected in series and connected between the ninth resistor and the second ground. A transistor is connected in parallel at both ends of each resistor.

7. A current sharing circuit for a multi-phase buck unit as claimed in claim 2 or 3, characterized in that: The driving circuit of the transistor includes a second current source, a first fuse, a first Schmitt trigger, and a first inverter. The second current source is connected to the first end of the first fuse, the second end of the first fuse is connected to the second ground, and the first end of the first fuse, the first Schmitt trigger, and the first inverter are connected in sequence.

8. A current sharing circuit for a multi-phase buck unit as claimed in claim 7, characterized in that: The driving circuit of the transistor also includes a second inverter, and the first end of the first fuse, the first Schmitt trigger, the first inverter, and the second inverter are connected in sequence.

9. A current sharing circuit for a multi-phase buck unit as claimed in claim 2, characterized in that: A clamping module is also included, wherein the output end of the error amplifying module is connected to the first end of the clamping module, and the second end of the clamping module is connected to the first end of the PWM generating module.

10. A current balancing method for a multi-phase buck unit, characterized in that: A current sharing circuit applied to a multi-phase buck unit as claimed in any one of claims 1 to 9, comprising: Connecting the first voltages of the current sharing units of each phase together; The current sampling resistor and the output voltage of the error amplifier module at zero inductance current are adjusted through the proportional coefficient.

11. A current sharing method for a multi-phase buck unit as claimed in claim 10, characterized in that: Also included is adjusting the target current limit.

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