High-gain wide-output ring amplifier and pipelined SAR ADC

Abstract

The invention provides a high-gain wide-output ring amplifier and a pipelined SAR ADC (Synthetic Aperture Radar Analog to Digital Converter). The high-gain wide-output ring amplifier comprises a ring amplification module, a level shifting capacitor, a transmission gate switch module and a cascode module, the annular amplification module is used for acquiring a residual signal output by the adjacent SAR ADC module and performing amplification processing on the residual signal to obtain a residual amplification signal; the level shift capacitor is used for performing wide-swing processing on the residual amplification signal under the control of the transmission gate switch module to form a wide-output residual amplification signal; the cascode module adopts a cascode amplification circuit to improve the voltage gain of the annular amplification module; and a high-gain wide-output ring amplifier is arranged between every two SAR ADC modules in the assembly line SAR ADC. Therefore, the gain and the response speed of the assembly line SAR ADC are improved, and the power consumption and the signal delay accumulation are reduced at the same time.

Description

Technical Field

[0001] The invention relates to the technical field of analog-to-digital converter chips, and in particular to a high-gain wide-output type ring amplifier and a pipeline SAR ADC. Background Art

[0002] With the rapid development of the Internet of Things and telecommunications technology, the performance requirements for analog-to-digital converters (ADCs) are increasing. Traditional single-mode ADCs can no longer meet the comprehensive requirements of modern electronic systems for high speed, low power consumption, and high resolution. Pipeline successive approximation register analog-to-digital converters (SAR ADCs) have gradually become the research focus of academia and industry due to their outstanding performance characteristics. In pipeline SAR ADCs, amplifiers, as key components, play a vital role in the overall performance. However, currently commonly used residual amplifiers, such as open-loop amplifiers and closed-loop operational transconductance amplifiers (OTAs), have obvious defects. Although open-loop amplifiers have fast response speeds, they have significant nonlinear problems that affect signal accuracy; while closed-loop OTAs have high gain stability, but slow response speeds and high design complexity. These technical problems limit the performance of pipeline SAR ADCs in high-speed, high-precision applications, and a new amplifier solution is urgently needed to overcome the shortcomings of existing technologies.

[0003] In order to solve the above problems, researchers have proposed a variety of new amplifier technologies, among which the dynamic bias ring amplifier and the segmented ring amplifier are two representative solutions. The dynamic bias ring amplifier achieves efficient power management by dynamically adjusting the bias current and dynamically adjusting the power consumption and gain according to the input signal. It can provide higher gain at high speed and is suitable for battery-powered devices and low-power systems. The segmented ring amplifier divides the amplification process into multiple stages, each of which works independently to reduce nonlinear errors, effectively improve linearity, reduce the gain requirements of a single loop, and improve stability. It is widely used in medical imaging and industrial measurement.

[0004] Although dynamic bias ring amplifiers and segmented ring amplifiers have solved some of the problems of traditional amplifiers to a certain extent, they still have significant defects. Dynamic bias ring amplifiers introduce additional noise when dynamically adjusting the bias current, especially at low signal amplitudes, which may cause a decrease in the signal-to-noise ratio (SNR). In addition, the implementation of the dynamic bias mechanism requires additional control circuits, which increases the complexity of the design and the chip area. At the same time, the adjustment time of the dynamic bias may also limit its response speed in a high-frequency working environment. Although the segmented ring amplifier improves performance through a segmented design, multiple amplification stages increase the power consumption and heat of the circuit. Multi-stage amplification may cause signal processing delay accumulation, limiting the high-frequency response capability of the system. In addition, the multi-stage design also occupies more chip area and is not suitable for application scenarios with strict size requirements. Therefore, the existing technology still needs to be further improved to better meet the needs of pipelined SAR ADCs for high-performance amplifiers. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a high-gain wide-output ring amplifier and a pipeline SAR ADC.

[0006] The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0007] In a first aspect, the present invention provides a high-gain wide-output type ring amplifier, comprising: a ring amplification module, a level shift capacitor, a transmission gate switch module and a common source and common gate module;

[0008] The ring amplification module is used to obtain the residual signal output by the adjacent SAR ADC module, and amplify the residual signal to obtain a residual amplified signal;

[0009] The level shift capacitor is used to perform wide swing processing on the residual amplified signal under the control of the transmission gate switch module to form a wide output residual amplified signal;

[0010] The common source and common gate module adopts a common source and common gate amplifier circuit to improve the voltage gain of the ring amplifier module;

[0011] The high-gain wide-output type ring amplifier is used in the pipeline SAR ADC, and the pipeline SAR ADC is provided with at least two stages of SAR ADC modules, and a high-gain wide-output type ring amplifier is provided between every two SAR ADC modules.

[0012] Optionally, the ring amplification module includes: a PMOS tube M1, an NMOS tube M2, a PMOS tube M3, an NMOS tube M4, a PMOS tube M5, an NMOS tube M6 and a resistor R B ; The level shift capacitor is capacitor CCLS The transmission gate switch module includes: a PMOS tube M13, an NMOS tube M14, an NMOS tube M15, a PMOS tube M16, an NMOS tube M17, a PMOS tube M18, an NMOS tube M19, a PMOS tube M20, a PMOS tube M21 and an NMOS tube M22; the common source and common gate module includes: a PMOS tube M9, an NMOS tube M10, a PMOS tube M11 and an NMOS tube M12;

[0013] The residual signal vin is connected to the gates of the PMOS tube M1 and the NMOS tube M2, the drains of the PMOS tube M1 and the NMOS tube M2 are connected and connected to the gates of the PMOS tube M5 and the NMOS tube M6, and the source of the PMOS tube M1 is connected to the drain of the PMOS tube M3; the gate of the PMOS tube M3 is connected to the bias voltage Vbp1, the source of the PMOS tube M3 is connected to the high level of the driving power supply, the source of the NMOS tube M2 is connected to the drain of the NMOS tube M4, the gate of the NMOS tube M4 is connected to the bias voltage Vbn1, and the source of the NMOS tube M4 is connected to the low level of the driving power supply; the source of the PMOS tube M5 is connected to the high level of the driving power supply, and the drain of the PMOS tube M5 is connected to the gate of the PMOS tube M11 and the resistor R B The source of the NMOS tube M6 is connected to the low level of the driving power supply, and the drain of the NMOS tube M6 is connected to the gate of the NMOS tube M12 and the resistor R B The source of the PMOS tube M11 is connected to the high level of the driving power supply, and the drain of the PMOS tube M11 is connected to one end of the first transmission gate switch; the source and drain of the PMOS tube M13 and the NMOS tube M14 are connected to each other to form a first transmission gate switch; the gate of the PMOS tube M13 is connected to the control signal The gate of the NMOS tube M14 is connected to the control signal CK2; the other end of the first transmission gate switch is connected to the source of the PMOS tube M9; the gate of the PMOS tube M9 is connected to the bias voltage Vbp2, the drain of the PMOS tube M9 is connected to the drain of the NMOS tube M10, and the gate of the NMOS tube M10 is connected to the bias voltage Vbn2; the source and drain of the NMOS tube M15 and the PMOS tube M16 are connected to each other to form a second transmission gate switch, and the source of the NMOS tube M10 is connected to one end of the second transmission gate switch; the gate of the NMOS tube M15 is connected to the control signal CK2, and the gate of the PMOS tube M16 is connected to the control signal ; The other end of the second transmission gate switch is connected to the drain of the NMOS tube M12, and the source of the NMOS tube M12 is connected to the low level of the driving power supply; the source and drain of the NMOS tube M17 and the PMOS tube M18 are connected to each other to form a third transmission gate switch; one end of the third transmission gate switch is respectively connected to the drain of the PMOS tube M11 and one end of the first transmission gate switch; the other end of the third transmission gate switch is connected to the residual amplification signal vout; the gate of the NMOS tube M17 is connected to the control signal CK1, and the gate of the PMOS tube M18 is connected to the control signal The source and drain of the NMOS tube M19 and the PMOS tube M20 are connected to each other to form a fourth transmission gate switch, one end of the fourth transmission gate switch is connected to the drain of the NMOS tube M12 and the other end of the second transmission gate switch; the other end of the fourth transmission gate switch is connected to the residual amplification signal vout, the gate of the NMOS tube M19 is connected to the control signal CK1, and the gate of the PMOS tube M20 is connected to the control signal The source and drain of the PMOS tube M21 and the NMOS tube M22 are connected to each other to form a fifth transmission gate switch. One end of the fifth transmission gate switch is connected to the common mode voltage signal VCM, and the other end of the fifth transmission gate switch is respectively connected to the drain of the PMOS tube M9, the drain of the NMOS tube M10 and the capacitor C CLS The gate of the PMOS tube M21 is connected to the control signal The gate of the NMOS tube M22 is connected to the control signal CK1, and the capacitor C CLS The other end is connected to the residual amplified signal vout.

[0014] Optionally, the levels of the control signals CK1 and CK2 are adjusted to control the on and off of the transmission gate switch module, so as to form an inverter or a cascade inverter in the common source and common gate module, thereby changing the voltage gain of the ring amplifier module.

[0015] Optionally, when the control signal CK1=1 and CK2=0, the NMOS tube M17, the PMOS tube M18, the NMOS tube M19, the PMOS tube M20, the PMOS tube M21 and the NMOS tube M22 are turned on, and the PMOS tube M13, the NMOS tube M14, the NMOS tube M15 and the PMOS tube M16 are turned off, an inverter is formed in the common source and common gate module, and the level shift capacitor is charged.

[0016] Optionally, when the control signal CK1=0 and CK2=1, the NMOS tube M17, the PMOS tube M18, the NMOS tube M19, the PMOS tube M20, the PMOS tube M21 and the NMOS tube M22 are turned off, the PMOS tube M13, the NMOS tube M14, the NMOS tube M15 and the PMOS tube M16 are turned on, the level shift capacitor is discharged and a cascade inverter is formed in the common source and common gate module to improve the voltage gain of the ring amplifier module.

[0017] In a second aspect, the present invention provides a pipeline SAR ADC, comprising: at least two-stage SAR ADC modules, a digital correction circuit, and the high-gain wide-output type ring amplifier of the first aspect;

[0018] A high-gain wide-output ring amplifier is connected between every two-stage SAR ADC module as a residual amplification module;

[0019] The input end of the digital correction circuit is connected to the output ends of all SAR ADC modules, and a final digital signal is formed at the output end of the digital correction circuit.

[0020] Optionally, when the pipeline SAR ADC is a pipeline SAR ADC with a 12-bit resolution, it includes: a first-stage SAR ADC module and a second-stage SAR ADC module;

[0021] The first-level SAR ADC module is a 6-bit SAR ADC module, and the second-level SAR ADC module is a 7-bit SAR ADC module;

[0022] The first-stage SAR ADC module and the second-stage SAR ADC module are both provided with a CDAC module, a comparator module and a SAR logic module.

[0023] The present invention provides a high-gain wide-output type ring amplifier and a pipeline SAR ADC. The high-gain wide-output type ring amplifier includes: a ring amplifier module, a level shift capacitor, a transmission gate switch module and a common source and common gate module; the ring amplifier module is used to obtain the residual signal output by the adjacent SAR ADC module, and amplify the residual signal to obtain the residual amplified signal; the level shift capacitor is used to perform wide swing processing on the residual amplified signal under the control of the transmission gate switch module to form a wide output residual amplified signal; the common source and common gate module adopts a common source and common gate amplifier circuit to improve the voltage gain of the ring amplifier module; the high-gain wide-output type ring amplifier is used in the pipeline SAR ADC, and the pipeline SAR ADC is provided with at least two stages of SAR ADC modules, and a high-gain wide-output type ring amplifier is provided between every two SAR ADC modules. In the present invention, firstly, a high gain and a wide output voltage range are achieved by adopting a common source and common gate structure, which solves the problem of the traditional dynamic bias ring amplifier introducing additional noise and reducing the signal-to-noise ratio when adjusting the bias current; then, by adding a level shift capacitor, the output voltage is optimized without reducing the output voltage range, further solving the problems of increased design complexity, increased chip area and limited response speed caused by the dynamic bias mechanism. Finally, due to the use of a common source and common gate structure and a level shift capacitor, the problems of increased power consumption, heat management and signal delay accumulation caused by multi-stage amplification brought by the segmented ring amplifier are effectively avoided. In summary, this solution improves the gain and response speed of the pipeline SAR ADC, while reducing power consumption and signal delay accumulation.

[0024] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic diagram of the structure of a high-gain wide-output ring amplifier provided by an embodiment of the present invention;

[0026] Figure 2 The timing waveform diagram of a high-gain wide-output ring amplifier is shown by way of example;

[0027] Figure 3 A schematic diagram of the structure of a pipeline SAR ADC provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0028] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0029] In order to improve the gain and response speed of a pipeline SAR ADC, while reducing power consumption and signal delay accumulation, and improving the response speed, an embodiment of the present invention provides a high-gain wide-output ring amplifier. Figure 1 A schematic diagram of the structure of a high-gain wide-output ring amplifier provided by an embodiment of the present invention is shown in FIG. Figure 1 As shown, it includes: a ring amplification module, a level shift capacitor, a transmission gate switch module and a common source and common gate module;

[0030] The ring amplification module is used to obtain the residual signal output by the adjacent SAR ADC module, and amplify the residual signal to obtain a residual amplified signal;

[0031] The level shift capacitor is used to perform wide swing processing on the residual amplified signal under the control of the transmission gate switch module to form a wide output residual amplified signal;

[0032] The common source and common gate module adopts a common source and common gate amplifier circuit to improve the voltage gain of the ring amplifier module;

[0033] The high-gain wide-output type ring amplifier is used in the pipeline SAR ADC, and the pipeline SAR ADC is provided with at least two stages of SAR ADC modules, and a high-gain wide-output type ring amplifier is provided between every two SAR ADC modules.

[0034] Optionally, the ring amplification module includes: a PMOS tube M1, an NMOS tube M2, a PMOS tube M3, an NMOS tube M4, a PMOS tube M5, an NMOS tube M6 and a resistor R B ; The level shift capacitor is capacitor C CLS The transmission gate switch module includes: a PMOS tube M13, an NMOS tube M14, an NMOS tube M15, a PMOS tube M16, an NMOS tube M17, a PMOS tube M18, an NMOS tube M19, a PMOS tube M20, a PMOS tube M21 and an NMOS tube M22; the common source and common gate module includes: a PMOS tube M9, an NMOS tube M10, a PMOS tube M11 and an NMOS tube M12;

[0035] The residual signal vin is connected to the gates of the PMOS tube M1 and the NMOS tube M2, the drains of the PMOS tube M1 and the NMOS tube M2 are connected and connected to the gates of the PMOS tube M5 and the NMOS tube M6, and the source of the PMOS tube M1 is connected to the drain of the PMOS tube M3; the gate of the PMOS tube M3 is connected to the bias voltage Vbp1, the source of the PMOS tube M3 is connected to the high level of the driving power supply, the source of the NMOS tube M2 is connected to the drain of the NMOS tube M4, the gate of the NMOS tube M4 is connected to the bias voltage Vbn1, and the source of the NMOS tube M4 is connected to the low level of the driving power supply; the source of the PMOS tube M5 is connected to the high level of the driving power supply, and the drain of the PMOS tube M5 is connected to the gate of the PMOS tube M11 and the resistor R B The source of the NMOS tube M6 is connected to the low level of the driving power supply, and the drain of the NMOS tube M6 is connected to the gate of the NMOS tube M12 and the resistor R B The source of the PMOS tube M11 is connected to the high level of the driving power supply, and the drain of the PMOS tube M11 is connected to one end of the first transmission gate switch; the source and drain of the PMOS tube M13 and the NMOS tube M14 are connected to each other to form a first transmission gate switch; the gate of the PMOS tube M13 is connected to the control signal The gate of the NMOS tube M14 is connected to the control signal CK2; the other end of the first transmission gate switch is connected to the source of the PMOS tube M9; the gate of the PMOS tube M9 is connected to the bias voltage Vbp2, the drain of the PMOS tube M9 is connected to the drain of the NMOS tube M10, and the gate of the NMOS tube M10 is connected to the bias voltage Vbn2; the source and drain of the NMOS tube M15 and the PMOS tube M16 are connected to each other to form a second transmission gate switch, and the source of the NMOS tube M10 is connected to one end of the second transmission gate switch; the gate of the NMOS tube M15 is connected to the control signal CK2, and the gate of the PMOS tube M16 is connected to the control signal ; The other end of the second transmission gate switch is connected to the drain of the NMOS tube M12, and the source of the NMOS tube M12 is connected to the low level of the driving power supply; the source and drain of the NMOS tube M17 and the PMOS tube M18 are connected to each other to form a third transmission gate switch; one end of the third transmission gate switch is respectively connected to the drain of the PMOS tube M11 and one end of the first transmission gate switch; the other end of the third transmission gate switch is connected to the residual amplification signal vout; the gate of the NMOS tube M17 is connected to the control signal CK1, and the gate of the PMOS tube M18 is connected to the control signal The source and drain of the NMOS tube M19 and the PMOS tube M20 are connected to each other to form a fourth transmission gate switch, one end of the fourth transmission gate switch is connected to the drain of the NMOS tube M12 and the other end of the second transmission gate switch; the other end of the fourth transmission gate switch is connected to the residual amplification signal vout, the gate of the NMOS tube M19 is connected to the control signal CK1, and the gate of the PMOS tube M20 is connected to the control signal The source and drain of the PMOS tube M21 and the NMOS tube M22 are connected to each other to form a fifth transmission gate switch. One end of the fifth transmission gate switch is connected to the common mode voltage signal VCM, and the other end of the fifth transmission gate switch is respectively connected to the drain of the PMOS tube M9, the drain of the NMOS tube M10 and the capacitor C CLS The gate of the PMOS tube M21 is connected to the control signal The gate of the NMOS tube M22 is connected to the control signal CK1, and the capacitor C CLS The other end is connected to the residual amplified signal vout.

[0036] Optionally, the levels of the control signals CK1 and CK2 are adjusted to control the on and off of the transmission gate switch module, so as to form an inverter or a cascade inverter in the common source and common gate module, thereby changing the voltage gain of the ring amplifier module.

[0037] Optionally, when the control signal CK1=1 and CK2=0, the NMOS tube M17, the PMOS tube M18, the NMOS tube M19, the PMOS tube M20, the PMOS tube M21 and the NMOS tube M22 are turned on, and the PMOS tube M13, the NMOS tube M14, the NMOS tube M15 and the PMOS tube M16 are turned off, an inverter is formed in the common source and common gate module, and the level shift capacitor is charged.

[0038] Optionally, when the control signal CK1=0 and CK2=1, the NMOS tube M17, the PMOS tube M18, the NMOS tube M19, the PMOS tube M20, the PMOS tube M21 and the NMOS tube M22 are turned off, the PMOS tube M13, the NMOS tube M14, the NMOS tube M15 and the PMOS tube M16 are turned on, the level shift capacitor is discharged and a cascade inverter is formed in the common source and common gate module to improve the voltage gain of the ring amplifier module.

[0039] ————————————

[0040] In this embodiment, CK1 and CK1 are a pair of differential clock signals, and CK2 and CK2 are a pair of differential clock signals.

[0041] Specifically, when an inverter is formed in the cascode module, the small signal voltage gain is equal to the gain of the conventional ring amplifier and the capacitance C is CLSCharging. Since slew rate control is more important than small signal voltage gain, the common source and common gate module is not so important for the increase of gain during this period. In addition, the small signal in this embodiment refers to a signal with a small amplitude of millivolts and microvolts, because the residual signal output by the previous stage SAR ADC is a signal with a small amplitude.

[0042] When a cascade inverter is formed in the cascode module, the voltage gain of the small signal can be effectively improved. Since the cascode device is added only by opening M13, M14, M15 and M16, the small signal voltage gain of the cascode device will not be affected by the gain reduction caused by the feedback loop, and the effective gain of the ring amplifier can be effectively improved. Compared with adding the number of cascades to increase the amplifier gain, the structure of this amplifier is simpler, and the control signals CK1 and CK2 both work within the amplifier amplification cycle.

[0043] Correspondingly, Figure 2 The timing waveform diagram of a high-gain wide-output ring amplifier is shown as an example. Figure 2 As shown, CK1 and CK2 are high (signal 1), and When it is low (signal 0), the switch is open.

[0044] Based on the same inventive concept, an embodiment of the present invention further provides a pipeline SAR ADC. Figure 3 A schematic diagram of the structure of a pipeline SAR ADC provided by an embodiment of the present invention. Figure 3 As shown, it includes: at least two-stage SAR ADC modules, a digital correction circuit and the high-gain wide-output type ring amplifier in the above embodiment;

[0045] A high-gain wide-output ring amplifier is connected between every two-stage SAR ADC module as a residual amplification module;

[0046] The input end of the digital correction circuit is connected to the output ends of all SAR ADC modules, and a final digital signal is formed at the output end of the digital correction circuit.

[0047] Optionally, when the pipeline SAR ADC is a pipeline SAR ADC with a 12-bit resolution, it includes: a first-stage SAR ADC module and a second-stage SAR ADC module;

[0048] The first-level SAR ADC module is a 6-bit SAR ADC module, and the second-level SAR ADC module is a 7-bit SAR ADC module;

[0049] Both the first-stage SAR ADC module and the second-stage SAR ADC module are provided with a CDAC module, a comparator module and a SAR logic module.

[0050] like Figure 3 The figure shows the structure diagram of the 12-bit pipeline SAR ADC, which consists of a first-stage 6-bit SAR ADC module, a second-stage 7-bit SAR ADC module, a high-gain wide-output ring amplifier and a digital correction circuit. The first-stage SAR ADC module and the second-stage SAR ADC module are both provided with a CDAC module, a comparator module and a SAR logic module. The input signal VIN is input into the first-stage SAR ADC module (6-bit SAR ADC module), and the residual signal obtained after quantization is input into the high-gain wide-output ring amplifier, and then input into the second-stage SAR ADC (7-bit SAR ADC module) after amplification by the high-gain wide-output ring amplifier. The digital output signals obtained in the two stages are both input into the digital correction circuit. Since there is 1-bit redundancy between the two stages, the final output result is 12 bits. The two-stage SAR ADC circuits are both composed of a CDAC module, a comparator and a SAR logic. The digital correction circuit is mainly composed of an error detection module and a calibration control logic. Specifically, the correction circuit compares the error with the preset target by digitally correcting the output of each stage. Whenever the output result deviates from the expected value, the digital correction circuit will feed back these errors to the corresponding stage and correct them by means of gain, bias, nonlinear compensation, etc. The generated digital codes are added in an offset manner to finally obtain a 12-bit digital signal VOUT.

[0051] The embodiment of the present invention provides a high-gain wide-output type ring amplifier and a pipeline SAR ADC. The high-gain wide-output type ring amplifier includes: a ring amplifier module, a level shift capacitor, a transmission gate switch module and a common source and common gate module; the ring amplifier module is used to obtain the residual signal output by the adjacent SAR ADC module, and amplify the residual signal to obtain the residual amplified signal; the level shift capacitor is used to perform wide swing processing on the residual amplified signal under the control of the transmission gate switch module to form a wide output residual amplified signal; the common source and common gate module adopts a common source and common gate amplifier circuit to improve the voltage gain of the ring amplifier module; the high-gain wide-output type ring amplifier is used in the pipeline SAR ADC, and the pipeline SAR ADC is provided with at least two stages of SAR ADC modules, and a high-gain wide-output type ring amplifier is provided between every two SAR ADC modules. In the present invention, firstly, a high gain and a wide output voltage range are achieved by adopting a common source and common gate structure, which solves the problem of the traditional dynamic bias ring amplifier introducing additional noise and reducing the signal-to-noise ratio when adjusting the bias current; then, by adding a level shift capacitor, the output voltage is optimized without reducing the output voltage range, further solving the problems of increased design complexity, increased chip area and limited response speed caused by the dynamic bias mechanism. Finally, due to the use of a common source and common gate structure and a level shift capacitor, the problems of increased power consumption, heat management and signal delay accumulation caused by multi-stage amplification brought by the segmented ring amplifier are effectively avoided. In summary, this solution improves the gain and response speed of the pipeline SAR ADC, while reducing power consumption and signal delay accumulation.

[0052] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0053] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art can understand and implement other changes of the above disclosed embodiments by viewing the drawings and the disclosed content. In the description of the present invention, the term "comprising" does not exclude other components or steps, "one" or "an" does not exclude multiple situations, and the meaning of "multiple" is two or more, unless otherwise clearly and specifically limited. In addition, certain measures are recorded in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0054] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the scope of protection of the present invention.

Claims

1. A high-gain wide-output ring amplifier, characterized in that: include: Ring amplifier module, level shift capacitor, transmission gate switch module and common source and common gate module; The annular amplification module is used to obtain the residual signal output by the adjacent SAR ADC module, and amplify the residual signal to obtain a residual amplified signal; The level shift capacitor is used to perform wide swing processing on the residual amplified signal under the control of the transmission gate switch module to form a wide output residual amplified signal; The common-source and common-gate module adopts a common-source and common-gate amplifier circuit to improve the voltage gain of the ring amplifier module; The high-gain wide-output ring amplifier is used in a pipeline SAR ADC, and the pipeline SAR ADC is provided with at least two stages of SAR ADC modules, and the high-gain wide-output ring amplifier is provided between every two SAR ADC modules.

2. The high-gain wide-output ring amplifier according to claim 1, characterized in that: The ring amplification module includes: a PMOS tube M1, an NMOS tube M2, a PMOS tube M3, an NMOS tube M4, a PMOS tube M5, an NMOS tube M6 and a resistor R B ; The level shift capacitor is a capacitor C CLS The transmission gate switch module includes: a PMOS tube M13, an NMOS tube M14, an NMOS tube M15, a PMOS tube M16, an NMOS tube M17, a PMOS tube M18, an NMOS tube M19, a PMOS tube M20, a PMOS tube M21 and an NMOS tube M22; the common source and common gate module includes: a PMOS tube M9, an NMOS tube M10, a PMOS tube M11 and an NMOS tube M12; The residual signal vin is connected to the gates of the PMOS tube M1 and the NMOS tube M2, the drains of the PMOS tube M1 and the NMOS tube M2 are connected and connected to the gates of the PMOS tube M5 and the NMOS tube M6, and the source of the PMOS tube M1 is connected to the drain of the PMOS tube M3; the gate of the PMOS tube M3 is connected to the bias voltage Vbp1, the source of the PMOS tube M3 is connected to the high level of the driving power supply, the source of the NMOS tube M2 is connected to the drain of the NMOS tube M4, the gate of the NMOS tube M4 is connected to the bias voltage Vbn1, and the source of the NMOS tube M4 is connected to the low level of the driving power supply; the source of the PMOS tube M5 is connected to the high level of the driving power supply, and the drain of the PMOS tube M5 is connected to the gate of the PMOS tube M11 and the resistor R B The source of the NMOS tube M6 is connected to the low level of the driving power supply, and the drain of the NMOS tube M6 is connected to the gate of the NMOS tube M12 and the resistor R B The source of the PMOS tube M11 is connected to the high level of the driving power supply, and the drain of the PMOS tube M11 is connected to one end of the first transmission gate switch; the source and drain of the PMOS tube M13 and the NMOS tube M14 are connected to each other to form the first transmission gate switch; the gate of the PMOS tube M13 is connected to the control signal The gate of the NMOS tube M14 is connected to the control signal CK2; the other end of the first transmission gate switch is connected to the source of the PMOS tube M9; the gate of the PMOS tube M9 is connected to the bias voltage Vbp2, the drain of the PMOS tube M9 is connected to the drain of the NMOS tube M10, and the gate of the NMOS tube M10 is connected to the bias voltage Vbn2; the source and drain of the NMOS tube M15 and the PMOS tube M16 are connected to each other to form a second transmission gate switch, and the source of the NMOS tube M10 is connected to one end of the second transmission gate switch; the gate of the NMOS tube M15 is connected to the control signal CK2, and the gate of the PMOS tube M16 is connected to the control signal The other end of the second transmission gate switch is connected to the drain of the NMOS tube M12, and the source of the NMOS tube M12 is connected to the low level of the driving power supply; the source and drain of the NMOS tube M17 and the PMOS tube M18 are connected to each other to form a third transmission gate switch; one end of the third transmission gate switch is respectively connected to the drain of the PMOS tube M11 and one end of the first transmission gate switch; the other end of the third transmission gate switch is connected to the residual amplification signal vout; the gate of the NMOS tube M17 is connected to the control signal CK1, and the gate of the PMOS tube M18 is connected to the control signal The source and drain of the NMOS tube M19 and the PMOS tube M20 are connected to each other to form a fourth transmission gate switch, one end of the fourth transmission gate switch is connected to the drain of the NMOS tube M12 and the other end of the second transmission gate switch; the other end of the fourth transmission gate switch is connected to the residual amplification signal vout, the gate of the NMOS tube M19 is connected to the control signal CK1, and the gate of the PMOS tube M20 is connected to the control signal The source and drain of the PMOS tube M21 and the NMOS tube M22 are connected to each other to form a fifth transmission gate switch, one end of which is connected to the common mode voltage signal VCM, and the other end of which is respectively connected to the drain of the PMOS tube M9, the drain of the NMOS tube M10 and the capacitor C CLS The gate of the PMOS tube M21 is connected to the control signal The gate of the NMOS tube M22 is connected to the control signal CK1, and the capacitor C CLS The other end is connected to the residual amplified signal vout.

3. The high-gain wide-output ring amplifier according to claim 2, characterized in that: The on and off of the transmission gate switch module is controlled by adjusting the levels of the control signals CK1 and CK2 to form an inverter or a cascade inverter in the common source and common gate module, thereby changing the voltage gain of the ring amplifier module.

4. The high-gain wide-output ring amplifier according to claim 3, characterized in that: When the control signal CK1=1 and CK2=0, the NMOS tube M17, the PMOS tube M18, the NMOS tube M19, the PMOS tube M20, the PMOS tube M21 and the NMOS tube M22 are turned on, and the PMOS tube M13, the NMOS tube M14, the NMOS tube M15 and the PMOS tube M16 are turned off, an inverter is formed in the common source and common gate module, and the level shift capacitor is charged.

5. The high-gain wide-output ring amplifier according to claim 3, characterized in that: When the control signal CK1=0 and CK2=1, the NMOS tube M17, the PMOS tube M18, the NMOS tube M19, the PMOS tube M20, the PMOS tube M21 and the NMOS tube M22 are turned off, and the PMOS tube M13, the NMOS tube M14, the NMOS tube M15 and the PMOS tube M16 are turned on, and the level shift capacitor is discharged and forms a cascade inverter in the common source and common gate module to improve the voltage gain of the ring amplifier module.

6. A pipeline SAR ADC, characterized in that: include: At least two-stage SAR ADC module, a digital correction circuit and a high-gain wide-output ring amplifier as claimed in any one of claims 1 to 5; The high-gain wide-output ring amplifier is connected between every two-stage SAR ADC modules as a residual amplification module; The input end of the digital correction circuit is connected to the output ends of all the SAR ADC modules, and a final digital signal is formed at the output end of the digital correction circuit.

7. The pipeline SAR ADC according to claim 6, characterized in that: When the pipeline SAR ADC is a pipeline SAR ADC with a 12-bit resolution, it includes: a first-stage SAR ADC module and a second-stage SAR ADC module; The first-level SAR ADC module is a 6-bit SAR ADC module, and the second-level SAR ADC module is a 7-bit SAR ADC module; The first-stage SAR ADC module and the second-stage SAR ADC module are both provided with a CDAC module, a comparator module and a SAR logic module.

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