Compact high-power high-efficiency GaN power amplifier chip

Abstract

The invention discloses a compact high-power and high-efficiency GaN power amplifier chip, and belongs to the technical field of radio frequency and microwave integrated circuits. The amplifier adopts a two-stage cascade amplification structure and comprises an input end, an input matching network, a first-stage amplification network, an inter-stage matching network, a second-stage amplification network, an output matching network, an output end and a biasing and stabilizing circuit. The inter-stage matching network integrates functions of power division, grid bias feed, stability design and inter-stage impedance matching, the output matching network integrates functions of power synthesis, drain bias feed and output impedance matching, and the second-stage amplification network is formed by connecting a plurality of GaN tube cores in parallel. Independent elements and wiring space are reduced through function integration, and the chip size is remarkably reduced; a signal amplification link and an energy transmission path are optimized, and the output power and efficiency in a broadband are improved; and by combining a stabilizing circuit and a symmetrical layout design, the stability and the reliability of the chip in a wide working frequency band are enhanced, and the requirements of a communication system on a high-integration-level and high-performance power amplifier are met.

Description

Technical Field

[0001] The present invention relates to the technical field of radio frequency and microwave integrated circuits, and in particular to a compact high-power and high-efficiency GaN power amplifier chip. Background Art

[0002] The current communication system is developing rapidly, the system integration is getting higher and higher, the signal transmission bandwidth is getting wider and wider, and higher requirements are put forward for the miniaturization and high integration of electronic components in the system. Semiconductor devices with higher frequency, higher voltage and higher output power have also emerged. The third generation of semiconductor materials represented by GaN materials have become the research focus of semiconductor devices in the global communication field. Compared with the previous two generations of semiconductor materials, GaN materials have higher breakdown voltage, higher power density, high thermal conductivity, and higher electron mobility, making them very suitable for the design and production of power amplifiers in the RF and microwave fields. As the core device of the transmitter in the communication system, the power amplifier is a key component that restricts the system performance and technical level.

[0003] The use of GaN materials to design and manufacture RF microwave power amplifiers can more effectively improve output power and efficiency. Wider bandwidth can better meet the needs of miniaturization and high integration of communication systems. There are various topological structures of power amplifiers, and different topological structures determine the final size, area, output power and efficiency of the power amplifier. The two commonly used topological structures of broadband power amplifiers are distributed matching structure and reactance matching structure. The advantages of the distributed matching structure are wide bandwidth and better input and output standing waves; the disadvantages are low gain, low output power and efficiency. The advantage of the reactance matching structure is wide bandwidth, and multi-stage cascading can achieve very high gain, while the output power and efficiency are also high; the disadvantage is that the bandwidth is not as wide as the distributed structure.

[0004] The design of a power amplifier requires comprehensive consideration of various indicators, such as operating bandwidth, output power, efficiency, gain, gain flatness, stability, etc. At the same time, the chip area must also be considered from the perspective of cost and miniaturization integration. How to design a power amplifier chip with higher output power and efficiency and stable operation in a smaller size space is a difficult point in power amplifier design. Summary of the invention

[0005] The purpose of the present invention is to overcome one or more deficiencies of existing GaN power amplifier chips and to provide a compact, high-power and high-efficiency GaN power amplifier chip.

[0006] The objective of the present invention is achieved through the following technical solutions:

[0007] A compact, high-power, high-efficiency GaN power amplifier chip includes a two-stage cascade amplification structure, specifically composed of:

[0008] An input terminal, used for inputting a radio frequency signal;

[0009] An input matching network, connected between the input terminal and the first-stage amplification network, for matching the input impedance of the first-stage GaN die to a 50Ω source impedance;

[0010] The first-stage amplifier network includes a single GaN die for first amplification of the input signal;

[0011] An inter-stage matching network, connected between the first-stage amplification network and the second-stage amplification network, for matching the output impedance of the first-stage tube core to the input impedance of the second-stage tube core;

[0012] The second-stage amplification network includes multiple GaN dies connected in parallel, which is used to amplify the signal for the second time;

[0013] An output matching network, connected between the second-stage amplification network and the output terminal, for matching the output impedance of the second-stage die to a 50Ω load impedance;

[0014] A gate bias circuit is connected to the GaN die gates of the first-stage amplification network and the second-stage amplification network, and is used to provide gate DC feeding;

[0015] A drain bias circuit is connected to the drain of the GaN die of the first-stage amplification network and the second-stage amplification network, and is used to provide a drain DC feed;

[0016] The stabilizing circuit is connected in series between the input matching network and the first-stage amplifying network.

[0017] Furthermore, the inter-stage matching network includes:

[0018] The power division structure divides the output signal of the first-stage tube core into multiple signals corresponding to the number of the second-stage tube cores;

[0019] A multi-channel matching unit, each matching unit includes a first microstrip line and a matching capacitor connected in series, a single-channel matching unit is combined with a gate bias, one end of the matching capacitor is connected to the corresponding second-stage tube core input end, and the other end is connected to the gate bias of the second-stage tube core;

[0020] Multi-stage matching structure, through the multi-stage LC matching structure, the multi-channel composite signal is matched to the required impedance value;

[0021] A stable first resistor and a second resistor are connected in series in the signal path of the multi-channel matching unit, wherein the first resistor is close to the input end of the second-stage tube core, and the second resistor is close to the gate bias of the second-stage tube core.

[0022] Furthermore, the output matching network includes:

[0023] The power synthesis structure synthesizes the output signals of multiple parallel-connected dies in the second-stage amplification network into a single-channel signal;

[0024] The drain bias LC unit comprises an inductor and a capacitor connected in series, one end of the inductor is connected to a DC power supply, and the other end is connected to the output end of the power synthesis structure, and the capacitor is connected in parallel between the output end of the power synthesis structure and the ground.

[0025] Furthermore, the stabilizing circuit is an RC parallel network, comprising:

[0026] A resistor and capacitor parallel structure connected in series to the signal path, one end of the resistor is connected to the output of the input matching network, and the other end is connected to the input of the first-stage tube core; the capacitor is connected in parallel with the resistor to reduce the input capacitance of the first-stage tube core.

[0027] Furthermore, the gate bias circuit includes:

[0028] A quarter-wavelength second microstrip line, one end of which is connected to a matching capacitor and the other end is connected to a bypass capacitor;

[0029] The bypass capacitor C2 is connected in parallel between the output end of the second microstrip line and the ground, and the output end of the second microstrip line is connected to the gate of the second-stage tube core through the matching capacitor of the inter-stage matching network.

[0030] Furthermore, the second-stage amplification network includes four parallel-connected GaN tube cores, and the power division structure of the inter-stage matching network divides the signal into four paths, each of which is connected to the corresponding second-stage tube core gate through an independent matching unit (first microstrip line, first resistor, matching capacitor, second resistor), and the power synthesis structure of the output matching network synthesizes the four output signals into a single signal through a symmetrical LC network.

[0031] The beneficial effects of the present invention are:

[0032] (1) Combining multi-stage matching, bias feeding and stability design through functional integration, reducing the number of independent components and wiring space, significantly reducing the chip area, and meeting the requirements of high integration;

[0033] (2) Optimize the signal amplification link and energy transmission path, reduce signal loss and enhance power synthesis capability, and achieve simultaneous improvement of output power and efficiency within a wide bandwidth;

[0034] (3) Through circuit structure design, abnormal oscillations can be suppressed and frequency response can be improved to ensure stable and reliable operation of the power amplifier chip within a wide operating frequency band, thereby improving system-level performance and safety. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1A schematic diagram of the structure of a compact, high-power, high-efficiency GaN power amplifier chip provided in this embodiment;

[0036] Figure 2 A schematic diagram of the structure of the inter-stage matching and gate bias circuit provided in this embodiment;

[0037] Figure 3 It is a schematic diagram of the structure of a conventional power amplifier inter-stage matching and gate bias circuit;

[0038] Figure 4 A schematic diagram of the output matching network structure provided in this embodiment;

[0039] Figure 5 A schematic diagram of the layout structure of the inter-stage matching and bias circuit provided in this embodiment;

[0040] Figure 6 It is a schematic diagram of the layout structure of the conventional power amplifier inter-stage matching and bias circuit;

[0041] Figure 7 This is a simulation result diagram of the chip saturation output power and power added efficiency provided in this embodiment. DETAILED DESCRIPTION

[0042] The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0043] like Figure 1 The structure diagram of a compact high-power and high-efficiency GaN power amplifier chip provided in an embodiment of this specification is shown, and the power amplifier includes:

[0044] Input terminal: used to input the RF signal from the source terminal to the power amplifier chip, and transmit the input RF signal to the input matching network. In this embodiment, the frequency range of the input RF signal is set to 2.7-3.5GHz.

[0045] Input matching network: used to match the input impedance of the first-stage tube core to the 50Ω source impedance. A multi-stage LC matching structure is used here to match the input impedance of the first-stage tube core to the 50Ω source impedance through multi-stage impedance transformation. At the same time, the matching network is combined with a stabilization circuit, such as Figure 1 As shown, the stabilization circuit participates in input matching, which can reduce matching components, reduce losses, and improve circuit output power, efficiency, and stability;

[0046] First-stage amplifier network: GaN die is used to complete the first amplification of the input signal. The GaN die model selected here is a high electron mobility transistor (HEMT) with a gate width of 2.5mm. Under appropriate bias conditions, the die performs the first amplification of the input signal.

[0047] Interstage matching network: used to match the output impedance of the first stage die to the input impedance of the final stage die, and has the functions of power division, gate bias feeding, stability design, and interstage impedance matching. It also uses a multi-stage LC matching structure to ensure a suitable working bandwidth. Figure 2 As shown, by adopting the design method provided in this specification, the inter-stage matching network integrates multiple circuit functions, thereby reducing the chip area;

[0048] The second-stage amplification network uses four GaN dies in parallel to complete the second amplification of the signal. The model of each die here is the same as the first-stage die, with a gate width of 2.5mm to achieve higher output power and efficiency. The four dies work in parallel to amplify the four signals distributed by the inter-stage matching network.

[0049] The output matching network is used to match the output impedance of the second-stage die to a 50Ω load impedance. Figure 4 As shown, the output matching network combines the functions of power synthesis, drain bias feeding, and impedance matching from the die output to the load end, thereby reducing matching components, lowering losses, improving output power and efficiency, and reducing chip area.

[0050] The output end is used to transmit the RF signal amplified by the power amplifier chip to the load end through the output matching network;

[0051] The gate bias circuit is used to perform gate feeding on the transistor in the power amplifier and also has a stability circuit design to improve the stability of the chip.

[0052] The drain bias circuit is used to feed the drain of the transistor in the power amplifier and also has an output impedance matching function.

[0053] The stabilization circuit is used for the stable and reliable operation of the power amplifier.

[0054] Specifically, when the power amplifier chip is working, the RF signal enters the chip through the input terminal, and the input terminal is connected with a DC blocking capacitor, which allows the RF signal to enter the chip, isolating the inflow of the front-stage DC signal and the outflow of the gate DC signal of the power amplifier chip. The input matching network adopts a multi-stage reactance matching method to ensure sufficient working bandwidth of the chip.

[0055] Before the first-stage tube core input, a stabilization circuit is connected in series. The stabilization circuit is composed of a resistor-capacitor parallel RC parallel network. The parallel capacitor in the stabilization network can reduce the input capacitance of the tube core, increase the cutoff frequency of the entire circuit, and improve the high-frequency response; the parallel resistor can reduce the low-frequency gain, improve the stability of the circuit, and improve the gain flatness of the circuit.

[0056] The function of the gate bias circuit is to provide a suitable gate DC bias voltage for transistors at each level, and at the same time to prevent the RF signal in the circuit from leaking to the DC power supply. In addition, in the present embodiment, the gate bias circuit is also connected in series with two small resistors, which can reduce the instability caused by excessive low-frequency gain on the one hand, and effectively isolate the signal loops between the gates of each level of the circuit on the other hand, to avoid causing circuit oscillation to produce unstable points and improve the stability of the circuit. The gate bias circuit is mainly composed of a quarter-wavelength microstrip line and a bypass capacitor. For RF signals within a specific frequency band, the gate bias circuit is high impedance, and the RF signal cannot pass through, thereby achieving the purpose of suppressing the RF signal from flowing to the power supply; and for DC signals, it can directly flow through the bias circuit, thereby achieving the purpose of passing DC.

[0057] In this embodiment, in order to further reduce the chip size, the inter-stage matching circuit and the gate bias circuit are combined. Figure 2 As shown, the matching capacitor C1 participates in the inter-stage matching, and it is combined with the gate bias circuit, so that the Figure 3 The capacitor C3 in the conventional matching circuit shown in the figure reduces the area of ​​inter-stage matching. At the same time, to ensure symmetry, the input end of each tube core is matched with a matching circuit consisting of a first microstrip line L1, a first resistor R1 and a matching capacitor C1. In order to avoid mutual crosstalk between the four tube cores, a first resistor R1 and a second resistor R2 are also connected in series to enhance circuit stability and eliminate oscillation. In this embodiment, Figure 2In the inter-stage matching circuit shown, the RF matching capacitor C1 is usually small in area, and the length of the first microstrip line L1 is also relatively short; while the bypass capacitor C2 in the gate bias circuit is large in area, and the length of the second microstrip line L2 of the quarter-wavelength bias line is also large. After combining the matching capacitor C1 and the gate bias circuit, only the LRC matching network with matching and stabilizing functions composed of the first microstrip line L1, the first resistor R1 and the matching capacitor C1 can be retained between the four tube cores, while the longer second microstrip line L2 and the larger bypass capacitor C2 are removed. This ensures both the matching bandwidth and the stability of the circuit, and reduces the area of ​​the chip inter-stage matching, thereby reducing the area of ​​the entire chip. At the same time, reducing the matching components can also reduce the insertion loss and improve the output power and efficiency. The four tube cores serve as the overall second-stage amplifier circuit, and the gate bias circuit is distributed at the upper and lower ends, and is composed of a quarter-wavelength second microstrip line L2 and a bypass capacitor C2. The layout schematic diagram of the inter-stage matching scheme described in this embodiment and the layout schematic diagram of the conventional matching circuit are respectively shown as follows. Figure 5 and Figure 6 As shown, it can be clearly seen that the inter-stage matching solution described in this embodiment can effectively reduce the chip area.

[0058] The inter-stage matching network integrates the impedance transformation and power division network. On the one hand, it matches the output impedance of the first-stage tube core to the input impedance of the final tube core. On the other hand, it divides the output power of the first-stage tube core into multiple signals with the same amplitude and phase and sends them to the second-stage amplifier circuit. Because the second-stage amplifier circuit is composed of 4 tube cores in parallel, the matching circuit between the first and second stages divides the output power of the first-stage tube core into 4 signals. These 4 signals must be as equal in amplitude and phase as possible. Therefore, the symmetry of the circuit must be ensured as much as possible after the power is divided into 4 signals. As mentioned above, the inter-stage matching network is combined with the gate bias circuit and the stabilization circuit. While completing the impedance matching, it also has the functions of power distribution, gate power supply, and improved stability. It can effectively reduce the chip size, reduce insertion loss, and improve the output power and efficiency of the chip.

[0059] The output matching network and drain bias circuit are combined to match the output impedance of the second-stage die to a 50Ω load impedance. Figure 4 As shown, the inductor L5 and the capacitor C5, on the one hand, act as a drain bias circuit to provide a suitable drain DC bias for the second-stage amplifier circuit; on the other hand, they also participate in impedance matching as part of the output matching network, which can reduce matching components and reduce chip area. At the same time, the output matching network also has the function of power synthesis, synthesizing the 4 output signals of the second-stage amplifier circuit into 1 signal and outputting it through the output end. By combining the output impedance matching with the drain bias circuit and the power distribution network, the matching components can be reduced, the insertion loss can be reduced, and the output power and efficiency can be improved.

[0060] In addition, it should be noted that the input matching network, inter-stage matching network, gate bias network, stabilization circuit and output matching network in the power amplifier described in this specification are not limited to those in this application. Figure 1 The present application does not impose any specific limitation on the structure specifically shown in the specification.

[0061] The working frequency of this embodiment is 2.7-3.5GHz. By adopting the design method of the present invention, the saturated output power (pod) is ≥47.2dBm in the frequency band, and the power added efficiency (PAE) is ≥70% in the frequency band. Figure 7 As shown, Figure 7 (a) is the simulation diagram of chip saturation output power. Figure 7 (b) is a simulation result diagram of chip power added efficiency. The chip area is 3.2mm*2.3mm. Compared with the power amplifier chip of this frequency band and this power level, the chip designed in this embodiment has a smaller chip area and higher output power and efficiency.

[0062] The present invention provides a compact high-power and high-efficiency GaN power amplifier chip. Compared with the prior art, the inter-stage matching structure of the power amplifier chip in the present invention combines impedance matching with gate feeding and stability circuits, which can greatly reduce the chip size and improve the output power, efficiency and stability of the chip. Specifically, the input end is used to input radio frequency signals; the input matching network is used to match the input impedance of the first-stage tube core to the 50Ω source impedance, and is combined with the gate bias circuit and the stability circuit, completing impedance matching while having both gate feeding and stability design, thereby reducing the chip area; the first-stage amplification network uses a GaN tube core to complete the first amplification of the input signal and provide a suitable input power for the second-stage tube core; the inter-stage matching network is used to match the output impedance of the first-stage tube core to the input impedance of the second-stage tube core, and has the functions of power division, gate bias feeding, stability design, and inter-stage impedance matching, thereby reducing matching components, reducing insertion loss, improving output power and efficiency, and reducing chip area; The second-stage amplification network completes the second amplification of the signal; the output matching network is used to match the output impedance of the second-stage tube core to the 50Ω load impedance, and at the same time has the power synthesis function, drain bias feeding, and impedance matching function of the tube core output to the load end, thereby improving the output power and efficiency and reducing the chip area; the gate bias circuit is used to feed the gate of the transistor in the power amplifier, and combined with the impedance matching function, further reducing the chip area; the drain bias circuit is used to feed the drain of the transistor in the power amplifier, and combined with the impedance matching function, further reducing the chip area; the stabilization circuit is used to put the power amplifier in a stable working state and improve the reliability of the power amplifier.

[0063] The above is only a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the form disclosed herein, and should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications and environments, and can be modified within the scope of the concept described herein through the above teachings or the technology or knowledge of the relevant field. The changes and modifications made by those skilled in the art shall not deviate from the spirit and scope of the present invention, and shall be within the scope of protection of the claims attached to the present invention.

Claims

1. A compact, high-power, high-efficiency GaN power amplifier chip, characterized in that: It includes a two-stage cascade amplification structure, which is specifically composed of: An input terminal, used for inputting a radio frequency signal; An input matching network, connected between the input terminal and the first-stage amplification network, for matching the input impedance of the first-stage GaN die to a 50Ω source impedance; The first-stage amplifier network includes a single GaN die for first amplification of the input signal; An inter-stage matching network, connected between the first-stage amplification network and the second-stage amplification network, for matching the output impedance of the first-stage tube core to the input impedance of the second-stage tube core; The second-stage amplification network includes multiple GaN dies connected in parallel, which is used to amplify the signal for the second time; An output matching network, connected between the second-stage amplification network and the output terminal, for matching the output impedance of the second-stage die to a 50Ω load impedance; A gate bias circuit is connected to the GaN die gates of the first-stage amplification network and the second-stage amplification network, and is used to provide gate DC feeding; A drain bias circuit is connected to the drain of the GaN die of the first-stage amplification network and the second-stage amplification network, and is used to provide a drain DC feed; The stabilizing circuit is connected in series between the input matching network and the first-stage amplifying network.

2. The GaN power amplifier chip according to claim 1, characterized in that: The inter-stage matching network comprises: The power division structure divides the output signal of the first-stage tube core into multiple signals corresponding to the number of the second-stage tube cores; A multi-channel matching unit, each matching unit includes a first microstrip line and a matching capacitor connected in series, a single-channel matching unit is combined with a gate bias, one end of the matching capacitor is connected to the corresponding second-stage tube core input end, and the other end is connected to the gate bias of the second-stage tube core; Multi-stage matching structure, through the multi-stage LC matching structure, the multi-channel composite signal is matched to the required impedance value; A stable first resistor and a second resistor are connected in series in the signal path of the multi-channel matching unit, wherein the first resistor is close to the input end of the second-stage tube core, and the second resistor is close to the gate bias of the second-stage tube core.

3. The GaN power amplifier chip according to claim 1, characterized in that: The output matching network comprises: The power synthesis structure synthesizes the output signals of multiple parallel-connected dies in the second-stage amplification network into a single-channel signal; The drain bias LC unit comprises an inductor and a capacitor connected in series, one end of the inductor is connected to a DC power supply, and the other end is connected to the output end of the power synthesis structure, and the capacitor is connected in parallel between the output end of the power synthesis structure and the ground.

4. The GaN power amplifier chip according to claim 1, characterized in that: The stabilizing circuit is an RC parallel network, comprising: A resistor and capacitor parallel structure connected in series to the signal path, one end of the resistor is connected to the output of the input matching network, and the other end is connected to the input of the first-stage tube core; the capacitor is connected in parallel with the resistor to reduce the input capacitance of the first-stage tube core.

5. The GaN power amplifier chip according to claim 1, characterized in that: The gate bias circuit comprises: A quarter-wavelength second microstrip line, one end of which is connected to a matching capacitor and the other end is connected to a bypass capacitor; The bypass capacitor C2 is connected in parallel between the output end of the second microstrip line and the ground, and the output end of the second microstrip line is connected to the gate of the second-stage tube core through the matching capacitor of the inter-stage matching network.

6. The GaN power amplifier chip according to any one of claims 1 to 5, characterized in that: The second-stage amplification network includes four parallel GaN tube cores. The power division structure of the inter-stage matching network divides the signal into four paths, each of which is connected to the corresponding second-stage tube core gate through an independent matching unit, and the matching structure is combined with the gate bias. The power synthesis structure of the output matching network synthesizes the four output signals into a single signal through a symmetrical LC network.

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