Anti-reverse connection driving circuit and circuit control system

Abstract

The invention provides an anti-reverse connection driving circuit and a circuit control system, and relates to the technical field of circuit control. The anti-reverse connection driving circuit comprises a PWM generation circuit, a bootstrap circuit and an NMOS tube, the PWM generation circuit is used for carrying out signal enhancement processing and amplitude amplification processing on a PWM signal so as to enhance the signal driving capability of the PWM signal and amplify the amplitude of the PWM signal, and the bootstrap circuit is used for raising the grid voltage of the NMOS tube. According to the application, the grid voltage of the NMOS transistor is raised by adopting the discrete circuit of the PWM generation circuit and the bootstrap circuit, and then the NMOS transistor is driven, so that the circuit cost can be reduced, and meanwhile, the circuit reliability is improved.

Description

Technical Field

[0001] The present application relates to the field of circuit control technology, and in particular to an anti-reverse connection driving circuit and a circuit control system. Background Art

[0002] In the design of electronic and electrical products, due to the presence of batteries, there is a situation where the battery polarity is connected in reverse during the installation of the batteries. Therefore, it is necessary to add an anti-reverse connection circuit in the design of the main power supply of the corresponding product circuit. At present, NMOS anti-reverse connection circuits are usually used in products with large currents such as currents greater than 15A. However, due to the driving characteristics of the NMOS tube, it is necessary to add a driving circuit to the NMOS anti-reverse connection circuit, and raise the gate voltage of the NMOS tube through the driving circuit to drive the NMOS tube.

[0003] In the related art, an ideal diode driver chip is used to drive an NMOS tube, that is, the gate of the NMOS tube is connected to a pin of the driver chip, and the gate voltage of the NMOS tube is raised through the internal circuit of the driver chip to drive the NMOS tube.

[0004] However, the inventors have found that using a driver chip to drive the NMOS tube has the problems of high cost and poor reliability. Summary of the invention

[0005] The present application provides an anti-reverse connection driving circuit and a circuit control system, which are used to solve the problem of high cost and poor reliability in the related art of using a driving chip to drive an NMOS tube.

[0006] In the first aspect, the present application provides an anti-reverse connection driving circuit, including: a PWM generating circuit, a bootstrap circuit and an NMOS tube; the PWM generating circuit is used to perform signal enhancement processing and amplitude amplification processing on the PWM signal to enhance the signal driving capability of the PWM signal and amplify the amplitude of the PWM signal; the bootstrap circuit is used to raise the gate voltage of the NMOS tube.

[0007] In a possible implementation, an input end of the PWM generating circuit is connected to a microcontroller unit (MCU for short), and the MCU is used to provide a PWM signal to the PWM generating circuit.

[0008] In a possible implementation, the output end of the PWM generating circuit is connected to the input end of the bootstrap circuit, the first output end of the bootstrap circuit is connected to the gate of the NMOS tube, the second output end of the bootstrap circuit and the drain of the NMOS tube are both connected to the load end; the source of the NMOS tube is connected to the positive terminal of the power supply.

[0009] In one possible implementation, the PWM generating circuit includes a first resistor, a first signal processing loop and a second signal processing loop; the first end of the first resistor, the input end of the first signal processing loop and the input end of the second signal processing loop are connected to form the input end of the PWM generating circuit, and the second end of the first resistor is grounded; the first output end of the first signal processing loop is connected to the first output end of the second signal processing loop to form the output end of the PWM generating circuit; the second output end of the first signal processing loop is connected to the first power supply, and the second output end of the second signal processing loop is grounded.

[0010] In one possible implementation, the first signal processing loop includes a second resistor and a PNP transistor; the first end of the second resistor is the input end of the first signal processing loop, and the second end of the second resistor is connected to the base of the PNP transistor; the collector of the PNP transistor is the first output end of the first signal processing loop, and the emitter of the PNP transistor is the second output end of the first signal processing loop.

[0011] In one possible implementation, the second signal processing loop includes a third resistor and a first NPN transistor; the first end of the third resistor is the input end of the second signal processing loop, and the second end of the third resistor is connected to the base of the first NPN transistor; the collector of the first NPN transistor is the first output end of the second signal processing loop, and the emitter of the first NPN transistor is the second output end of the second signal processing loop.

[0012] In one possible implementation, the bootstrap circuit includes a charge and discharge circuit, an anti-reverse connection circuit, and a bootstrap capacitor; the input end of the charge and discharge circuit is the input end of the bootstrap circuit, the first output end of the charge and discharge circuit is connected to the first input end of the anti-reverse connection circuit, and the second output end of the charge and discharge circuit is connected to the second input end of the anti-reverse connection circuit; the first output end of the anti-reverse connection circuit is the first output end of the bootstrap circuit, the second output end of the anti-reverse connection circuit is connected to the first end of the bootstrap capacitor to form the second output end of the bootstrap circuit, and the second end of the bootstrap capacitor is grounded.

[0013] In one possible implementation, the anti-reverse polarity circuit includes a first diode, a second diode, a third diode and a fourth diode connected in series in sequence; the positive terminal of the first diode is the second output terminal of the anti-reverse polarity circuit, and the negative terminal of the first diode is connected to the positive terminal of the second diode to form the first input terminal of the anti-reverse polarity circuit; the negative terminal of the third diode is connected to the positive terminal of the fourth diode to form the second input terminal of the anti-reverse polarity circuit, and the negative terminal of the fourth diode is the first output terminal of the anti-reverse polarity circuit.

[0014] In one possible implementation, the anti-reverse connection drive circuit also includes: a reverse shutdown circuit, the input end of which is connected to the first output end of the bootstrap circuit, and the output end of the reverse shutdown circuit is connected to the gate of the NMOS tube; and the reverse shutdown circuit is used to discharge the gate voltage of the NMOS tube.

[0015] In one possible implementation, the reverse shutdown circuit includes a fourth resistor, a second NPN transistor and a voltage discharge loop; the first end of the fourth resistor is the input end of the reverse shutdown circuit, and the second end of the fourth resistor is connected to the base of the second NPN transistor and the emitter of the second NPN transistor; the collector of the second NPN transistor is connected to the first output end of the voltage discharge loop to form the output end of the reverse shutdown circuit; the input end of the voltage discharge loop is connected to the second power supply.

[0016] In a second aspect, the present application provides a circuit control system, including the anti-reverse connection driving circuit provided in the first aspect above.

[0017] The present application provides an anti-reverse connection driving circuit and a circuit control system, wherein the anti-reverse connection driving circuit includes: a PWM generating circuit, a bootstrap circuit, and an NMOS tube, wherein the PWM generating circuit is used to perform signal enhancement processing and amplitude amplification processing on the PWM signal to enhance the signal driving capability of the PWM signal and amplify the amplitude of the PWM signal, and the bootstrap circuit is used to raise the gate voltage of the NMOS tube. The present application uses a discrete circuit of a PWM generating circuit and a bootstrap circuit to raise the gate voltage of the NMOS tube, thereby driving the NMOS tube, thereby reducing the circuit cost and improving the circuit reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0019] Figure 1 This is a schematic diagram of the circuit structure of using a diode driver chip to drive NMOS;

[0020] Figure 2 A schematic diagram of the structure of the anti-reverse connection driving circuit provided in the embodiment of the present application Figure 1 ;

[0021] Figure 3 A schematic diagram of the structure of a PWM generating circuit provided in an embodiment of the present application;

[0022] Figure 4 A schematic diagram of the structure of a bootstrap circuit provided in an embodiment of the present application;

[0023] Figure 5A schematic diagram of the structure of a reverse shutdown circuit provided in an embodiment of the present application;

[0024] Figure 6 The structure of the anti-reverse connection driving circuit provided in the embodiment of the present application is shown in FIG. Figure 2 ;

[0025] Figure 7 A schematic diagram of a test waveform based on an anti-reverse connection driving circuit provided in an embodiment of the present application;

[0026] Figure 8 A schematic diagram of the structure of a circuit control system provided in an embodiment of the present application.

[0027] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0028] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0029] In the design of electronic and electrical products such as automobiles, due to the presence of batteries, there is a situation where the battery polarity is connected in reverse during the installation of the batteries. Therefore, it is necessary to add an anti-reverse connection circuit in the design of the main power supply of the corresponding product circuit. At present, diodes or PMOS anti-reverse connection circuits are usually used in small current products such as currents less than 15A. In large current products such as currents greater than 15A, NMOS is used for anti-reverse connection due to the high cost of power diodes and high-current PMOS. The circuit using NMOS anti-reverse connection is also called an ideal diode circuit.

[0030] In the related art, due to the driving characteristics of NMOS, it is necessary to add a bootstrap circuit to raise the gate voltage of NMOS to drive NMOS. At present, an ideal diode driver chip is usually used to drive NMOS. However, the integration of the driver chip makes the circuit cost relatively high, and the driver chip has poor anti-electrostatic discharge (ESD) capability, and the cost of the entire circuit is high.

[0031] Figure 1 The following is a schematic diagram of the circuit structure of using a diode driver chip to drive NMOS. Figure 1As shown, the circuit includes a transient suppression diode 101, a capacitor 102, a capacitor 103, an NMOS tube 104, a driver chip 105, a capacitor 106 and a load 107. The driver chip includes pin A, pin B, pin C, pin D, pin EN and pin E.

[0032] Specifically, in the circuit, one end of the capacitor 103 is connected to the positive terminal of the power supply and the pin A of the driver chip, and the other end is connected to the pin D in the driver chip. The capacitor 103 is charged by the power supply, so that the charging of the capacitor can raise the internal voltage of the driver chip through the internal hardware circuit of the driver chip. The pin B of the driver chip is connected to the gate of the NMOS tube, and then the gate voltage of the NMOS tube is raised through the driver chip to turn on the NMOS tube. The pin A of the driver chip is connected to the positive terminal of the power supply and the source of the NMOS tube, and the pin C of the driver chip is connected to the drain of the NMOS tube, and is connected to the internal circuit of the driver chip through pins A and C respectively, for detecting the internal voltage of the driver chip. The pin EN of the driver chip is used to control the enable ON or disable OFF of the driver chip, and the pin E of the driver chip is grounded (GND).

[0033] Based on the problems existing in the related art, the embodiment of the present application uses a discrete circuit of a PWM generating circuit and a bootstrap circuit to raise the gate voltage of the NMOS tube, thereby driving the NMOS tube, which can reduce circuit cost and improve circuit reliability.

[0034] The following first describes the application scenarios of the anti-reverse connection drive circuit and circuit control system provided in the embodiments of the present application.

[0035] The anti-reverse connection drive circuit and circuit control system provided in the embodiments of the present application can be applied to circuit topologies such as high-side drive and load switch, and can also be applied to products such as automotive electronics, consumer electronics and industrial electronics.

[0036] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below in conjunction with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0037] Figure 2 A schematic diagram of the structure of the anti-reverse connection driving circuit provided in the embodiment of the present application Figure 1 .like Figure 2 As shown, the anti-reverse connection driving circuit includes a PWM generating circuit, a bootstrap circuit and an NMOS tube.

[0038] The PWM generating circuit is used to perform signal enhancement processing and amplitude amplification processing on the PWM signal to enhance the signal driving capability of the PWM signal and amplify the amplitude of the PWM signal;

[0039] The bootstrap circuit is used to raise the gate voltage of the NMOS tube.

[0040] Exemplarily, by performing signal enhancement processing on the PWM signal, the driving capability of the PWM signal can be enhanced; by performing amplitude amplification processing on the PWM signal, the amplitude of the PWM signal can be amplified.

[0041] Exemplarily, the PWM generating circuit can also be described as a push-pull circuit. The PWM generating circuit provided in the embodiment of the present application uses a BJT (Bipolar Junction Transistor Push-Pull Pair) push-pull circuit structure to achieve signal enhancement and amplitude amplification of the PWM signal.

[0042] It can be understood that by performing signal enhancement processing and amplitude amplification processing on the PWM signal input through the input end of the PWM generating circuit through the PWM generating circuit, the driving capability of the anti-reverse driving circuit can be improved to ensure that the PWM signal can be effectively transmitted to the load. At the same time, by amplifying the amplitude of the PWM signal, the voltage level of the PWM signal can be increased so that the voltage level of the PWM signal can meet the driving of the NMOS tube, and then by inputting the PWM signal output after the signal enhancement processing and amplitude amplification processing of the PWM generating circuit into the bootstrap circuit, the gate voltage of the NMOS tube can be raised.

[0043] In the embodiment of the present application, the anti-reverse connection driving circuit includes a PWM generating circuit, a bootstrap circuit and an NMOS tube, wherein the PWM generating circuit is used to perform signal enhancement processing and amplitude amplification processing on the PWM signal to enhance the signal driving capability of the PWM signal and amplify the amplitude of the PWM signal, and the bootstrap circuit is used to raise the gate voltage of the NMOS tube. In the embodiment of the present application, by using a discrete circuit of the PWM generating circuit and the bootstrap circuit to raise the gate voltage of the NMOS tube and then drive the NMOS tube, the circuit cost can be reduced and the circuit reliability can be improved.

[0044] Optionally, an input end of the PWM generating circuit is connected to an MCU, and the MCU is used to provide a PWM signal to the PWM generating circuit.

[0045] Exemplarily, the input end of the PWM generating circuit is connected to a pin in the MCU.

[0046] Exemplarily, a timer or counter module is integrated in the MCU, and a PWM signal is generated by the timer or counter module, and the PWM signal is further output to the PWM generating circuit through a pin connected to the input end of the PWM generating circuit.

[0047] In the embodiment of the present application, there is no limitation on the duty ratio of the PWM signal, and it can be determined according to actual application requirements.

[0048] Optionally, the output end of the PWM generating circuit is connected to the input end of the bootstrap circuit, the first output end of the bootstrap circuit is connected to the gate of the NMOS tube, the second output end of the bootstrap circuit and the drain of the NMOS tube are both connected to the load end; the source of the NMOS tube is connected to the positive terminal of the power supply.

[0049] It can be understood that the bootstrap circuit raises the circuit voltage based on the PWM signal output by the PWM generating circuit, and then raises the gate voltage of the NMOS tube through the first output terminal, so that the gate voltage of the NMOS tube is higher than the source voltage of the NMOS tube, thereby driving the NMOS tube.

[0050] Combine the following Figure 3 The PWM generating circuit provided in the embodiment of the present application is described in detail.

[0051] Figure 3 This is a schematic diagram of the structure of the PWM generating circuit provided in the embodiment of the present application. Figure 3 As shown, the PWM generating circuit includes a first resistor 31, a first signal processing loop 32 and a second signal processing loop 33;

[0052] Among them, the first end of the first resistor, the input end of the first signal processing loop and the input end of the second signal processing loop are connected to form the input end 34 of the PWM generating circuit, and the second end of the first resistor is grounded; the first output end of the first signal processing loop is connected to the first output end of the second signal processing loop to form the output end 35 of the PWM generating circuit; the second output end of the first signal processing loop is connected to the first power supply 36, and the second output end of the second signal processing loop is grounded.

[0053] Exemplarily, the first resistor is used for voltage division, and when no PWM signal is input into the PWM generating circuit, the PWM generating circuit is not turned on.

[0054] Exemplarily, the first signal processing loop is used to perform signal enhancement processing and amplitude amplification processing on the input PWM signal, and the second signal processing loop is used to perform signal enhancement processing and amplitude amplification processing on the input PWM signal.

[0055] For example, the voltage output by the first power supply may be 5 V. The present application does not limit the voltage output by the first power supply, which may be determined according to actual application requirements.

[0056] like Figure 3 As shown, optionally, the first signal processing loop 32 includes a second resistor 321 and a PNP transistor 322. The first end of the second resistor is the input end of the first signal processing loop, and the second end of the second resistor is connected to the base of the PNP transistor; the collector of the PNP transistor is the first output end of the first signal processing loop, and the emitter of the PNP transistor is the second output end of the first signal processing loop.

[0057] Exemplarily, the second resistor may be used for current limiting.

[0058] Exemplarily, the emitter of the PNP transistor is connected to the first power supply.

[0059] like Figure 3 As shown, optionally, the second signal processing loop includes a third resistor 331 and a first NPN transistor 332. The first end of the third resistor is the input end of the second signal processing loop, and the second end of the third resistor is connected to the base of the first NPN transistor; the collector of the first NPN transistor is the first output end of the second signal processing loop, and the emitter of the first NPN transistor is the second output end of the second signal processing loop.

[0060] Exemplarily, the third resistor is used for current limiting.

[0061] Exemplarily, the emitter of the first NPN transistor is grounded.

[0062] In an embodiment of the present application, a PWM generating circuit includes a first resistor, a first signal processing loop, and a second signal processing loop. The first end of the first resistor, the input end of the first signal processing loop, and the input end of the second signal processing loop are connected to form the input end of the PWM generating circuit, and the second end of the first resistor is grounded; the first output end of the first signal processing loop is connected to the first output end of the second signal processing loop to form the output end of the PWM generating circuit; the second output end of the first signal processing loop is connected to the first power supply, and the second output end of the second signal processing loop is grounded. In an embodiment of the present application, the PWM generating circuit performs signal enhancement processing and amplitude amplification processing on the PWM signal input through the PWM generating circuit by using the first signal processing loop and the second signal processing loop, thereby enhancing the signal driving capability of the anti-reverse connection driving circuit and amplifying the amplitude, thereby realizing the raising of the gate voltage of the NMOS tube to drive the NMOS tube.

[0063] Combine the following Figure 4 The bootstrap circuit provided in the embodiment of the present application is described in detail.

[0064] Figure 4 This is a schematic diagram of the structure of the bootstrap circuit provided in the embodiment of the present application. Figure 4 As shown, the bootstrap circuit includes a charge and discharge circuit 41 , an anti-reverse connection circuit 42 and a bootstrap capacitor 43 .

[0065] Among them, the input end of the charge and discharge loop 41 is the input end 44 of the bootstrap circuit, the first output end 45 of the charge and discharge loop is connected to the first input end 47 of the anti-reverse polarity loop, and the second output end 46 of the charge and discharge loop is connected to the second input end 48 of the anti-reverse polarity loop; the first output end of the anti-reverse polarity loop 42 is the first output end 49 of the bootstrap circuit, the second output end of the anti-reverse polarity loop is connected to the first end of the bootstrap capacitor 43 to form the second output end of the bootstrap circuit, and the second end of the bootstrap capacitor 43 is grounded.

[0066] Exemplarily, the charge-discharge loop includes a resistor 410, a resistor 412, a capacitor 411, and a capacitor 413. The resistor 410 and the capacitor 411 connected in series are connected in parallel with the resistor 412 and the capacitor 413 connected in series.

[0067] like Figure 4 As shown, optionally, the anti-reverse connection circuit includes a first diode 421, a second diode 422, a third diode 423 and a fourth diode 424 connected in series in sequence;

[0068] The positive terminal of the first diode 421 is the second output terminal of the anti-reverse polarity circuit, and the negative terminal of the first diode 421 is connected to the positive terminal of the second diode 422 to form the first input terminal 47 of the anti-reverse polarity circuit; the negative terminal of the third diode 423 is connected to the positive terminal of the fourth diode 424 to form the second input terminal 48 of the anti-reverse polarity circuit, and the negative terminal of the fourth diode 424 is the first output terminal of the anti-reverse polarity circuit.

[0069] Exemplarily, the reverse connection protection circuit further includes a capacitor 425 and a capacitor 426 .

[0070] The embodiment of the present application does not limit the number of diodes in the bootstrap circuit, which can be determined based on actual application requirements.

[0071] It can be understood that the bootstrap circuit provided in the embodiment of the present application, through a charging and discharging loop including a resistor and a capacitor, utilizes the characteristic that the voltage across the capacitor cannot change suddenly, and the unidirectional conductivity of the diode to achieve circuit voltage raising, thereby achieving the raising of the gate voltage of the NMOS tube.

[0072] Optionally, the anti-reverse polarity driving circuit provided in the embodiment of the present application may further include a reverse shutdown circuit, the input end of the reverse shutdown circuit is connected to the first output end of the bootstrap circuit, the output end of the reverse shutdown circuit is connected to the gate of the NMOS tube, and the reverse shutdown circuit is used to discharge the gate voltage of the NMOS tube.

[0073] In the embodiment of the present application, the gate voltage of the NMOS tube can be quickly discharged through the reverse shutdown circuit, thereby causing the NMOS to be quickly shut down, thereby achieving rapid shutdown of the circuit when the power supply is reversed, thereby preventing damage to components and loads in the circuit.

[0074] Combine the following Figure 5 The reverse shutdown circuit provided in the embodiment of the present application is described in detail.

[0075] Figure 5 This is a schematic diagram of the structure of the reverse shutdown circuit provided in the embodiment of the present application. Figure 5 As shown, the reverse shutdown circuit includes a fourth resistor 51 , a second NPN transistor 52 and a voltage discharge loop 53 .

[0076] Among them, the first end of the fourth resistor is the input end of the reverse shutdown circuit, the second end of the fourth resistor is connected to the base of the second NPN transistor and the emitter of the second NPN transistor; the collector of the second NPN transistor is connected to the first output end of the voltage discharge circuit to form the output end of the reverse shutdown circuit; the input end of the voltage discharge circuit is connected to the second power supply 55.

[0077] For example, the voltage output by the second power supply may be 5 V. The voltage output by the second power supply is not limited in the present embodiment, and may be determined according to actual application requirements.

[0078] like Figure 5 As shown, optionally, the voltage discharge loop may include a resistor 531, an NPN transistor 532, an NPN transistor 533, and an NPN transistor 534. The first end of the resistor 531 is connected to the collector of the NPN transistor 532, the second end of the resistor 531, the collector of the NPN transistor 533, and the base of the NPN transistor 534 are connected, the base of the NPN transistor 532 is connected to the emitter of the NPN transistor 532, forming an input end of the voltage discharge loop, the emitter of the NPN transistor 533, the base of the NPN transistor 533, and the emitter of the NPN transistor 534 are connected, and the base of the NPN transistor 534 is the first output end of the voltage discharge loop.

[0079] It can be understood that the reverse shutdown circuit provided in the embodiment of the present application utilizes the characteristic of the BJT to quickly turn on the tube when the reverse voltage is applied, quickly discharges the gate voltage of the NMOS tube, and quickly turns off the NMOS tube, thereby achieving rapid shutdown of the circuit when the reverse voltage is applied.

[0080] Based on the above embodiments, Figure 6 The anti-reverse connection driving circuit provided in the embodiment of the present application is described in detail.

[0081] Figure 6 The structure of the anti-reverse connection driving circuit provided in the embodiment of the present application is shown in FIG. Figure 2 .like Figure 6 As shown, the anti-reverse connection driving circuit includes a PWM generating circuit 61 , a bootstrap circuit 62 , a reverse shutdown circuit 63 , an NMOS tube 64 , a first power supply 65 and a second power supply 66 .

[0082] The specific implementations of the PWM generating circuit 61 , the bootstrap circuit 62 and the reverse shutdown circuit 63 are similar to those described above and will not be described in detail herein.

[0083] The following first describes in detail the specific implementation method of the PWM generating circuit and the bootstrap circuit to raise the gate voltage of the NMOS tube in conjunction with a specific example.

[0084] Assume that the output voltage of the first power supply is 5V, the output voltage between the positive terminal and the negative terminal of the power supply is 12V, the voltage drop of each diode in the bootstrap circuit is 0.3V, and the duty ratio of the PWM signal is 1:1. In a possible implementation, the PWM generating circuit performs signal enhancement processing and amplitude amplification processing on the PWM signal input through the MCU to obtain a PWM signal with signal enhancement and amplitude amplification output by the PWM generating circuit, that is, the voltage value of the PWM signal is 5V, and the PWM signal is input into the charge and discharge circuit of the bootstrap circuit. The bootstrap capacitor 621 in the bootstrap circuit is connected to the drain of the NMOS tube, that is, the circuit voltage through the bootstrap capacitor is 12V, and the 12V voltage output by the bootstrap capacitor is reduced by 0.3V after passing through the first diode. When passing through the first output terminal 622 of the charge and discharge circuit, the circuit voltage is raised. The circuit voltage is 2.5V higher, and when passing through the second diode and the third diode, the circuit voltage is reduced by 0.3V respectively. When passing through the first output terminal 623 of the charge and discharge loop, the circuit voltage is raised by 2.5V. When passing through the fourth diode, the circuit voltage is reduced by 0.3V. The circuit voltage output by the bootstrap circuit is 15.8V. The output end of the bootstrap circuit is connected to the gate of the NMOS tube, so that the gate voltage of the NMOS tube is 15.8V, that is, the gate voltage of the NMOS tube is higher than the source voltage of the NMOS tube. The gate voltage of the NMOS tube is raised by the PWM generating circuit and the bootstrap circuit to drive the NMOS tube.

[0085] It should be noted that the above is only an example. The embodiment of the present application does not limit the size and type of the diode in the bootstrap circuit and the duty ratio of the PWM type, which can be determined according to actual application requirements.

[0086] It can be understood that in the anti-reverse polarity drive circuit provided in the embodiment of the present application, when a reverse polarity situation exists, that is, when there is a negative pulse at the power input end, the NPN transistor in the reverse shutdown circuit reaches the conduction condition, thereby turning on the anti-reverse polarity drive circuit, and the gate voltage of the NMOS tube is quickly discharged through the NPN transistor in the reverse shutdown circuit, thereby realizing the rapid shutdown of the NMOS tube.

[0087] Figure 7 This is a schematic diagram of a test waveform based on an anti-reverse connection driving circuit provided in an embodiment of the present application. Figure 7 As shown in a, letter A represents the PWM signal input by the PWM generating circuit, letter B represents the PWM signal output by the PWM generating circuit, letter D represents the PWM signal output by the charging and discharging circuit in the bootstrap circuit, letter C represents the circuit voltage output by the bootstrap circuit, letter E represents the circuit voltage output by the bootstrap circuit through the bootstrap capacitor, letter F represents the circuit voltage input by the source of the NMOS tube, that is, the source voltage of the NMOS tube, and letter G represents the gate voltage of the NMOS tube.

[0088] like Figure 7 As shown in Figure b, the amplitude of the PWM signal output by the PWM generating circuit is significantly greater than the amplitude of the PWM signal input to the PWM generating circuit, the PWM signal output by the charge-discharge circuit is the same as the PWM signal output by the PWM generating circuit, and the circuit voltage output by the bootstrap capacitor is significantly higher than the circuit voltage output by the bootstrap capacitor. Among them, the circuit voltage output by the bootstrap circuit is the same as the gate voltage of the NMOS tube, and the circuit voltage input by the bootstrap capacitor is the same as the drain voltage of the NMOS tube.

[0089] Through testing and verification, it can be obtained that the PWM generating circuit and the bootstrap circuit provided by the embodiment of the present application can increase the gate voltage of the NMOS tube, thereby driving the NMOS tube.

[0090] Optionally, an embodiment of the present application further provides a circuit control system, which includes the anti-reverse connection driving circuit as described in the above embodiment.

[0091] Figure 8 This is a schematic diagram of the structure of the circuit control system provided in the embodiment of the present application. Figure 8 As shown, the circuit control system includes a PWM generating circuit, a bootstrap circuit, a reverse shutdown circuit and an NMOS tube.

[0092] Among them, the PWM generation circuit, bootstrap circuit, and reverse shutdown circuit are similar to the above and will not be repeated here.

[0093] In summary, the anti-reverse polarity drive circuit and circuit control system provided in the embodiments of the present application can reduce circuit costs and improve circuit reliability and robustness by adopting discrete circuit solutions such as PWM generation circuit, bootstrap circuit, reverse shutdown circuit, etc. At the same time, the switching frequency of the anti-reverse polarity drive circuit provided in the embodiments of the present application is adjustable, so that the electromagnetic compatibility (EMC) of the circuit is better.

[0094] Finally, it should be noted that those skilled in the art will readily conceive of other embodiments of the present application after considering the specification and practicing the application disclosed herein. The present application is intended to cover any variations, uses or adaptations of the present application, which follow the general principles of the present application and include common knowledge or customary technical means in the art that are not disclosed in the present application, are not limited to the precise structures described above and shown in the drawings, and may be modified and changed in various ways without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A reverse connection protection driving circuit, characterized in that: include: PWM generation circuit, bootstrap circuit and NMOS tube; The PWM generating circuit is used to perform signal enhancement processing and amplitude amplification processing on the PWM signal to enhance the signal driving capability of the PWM signal and amplify the amplitude of the PWM signal; The bootstrap circuit is used to raise the gate voltage of the NMOS tube.

2. The anti-reverse connection driving circuit according to claim 1, characterized in that: The input end of the PWM generating circuit is connected to a microcontroller MCU, and the MCU is used to provide a PWM signal to the PWM generating circuit.

3. The anti-reverse connection driving circuit according to claim 1, characterized in that: The output end of the PWM generating circuit is connected to the input end of the bootstrap circuit, the first output end of the bootstrap circuit is connected to the gate of the NMOS tube, the second output end of the bootstrap circuit and the drain of the NMOS tube are both connected to the load end; the source of the NMOS tube is connected to the positive terminal of the power supply.

4. The anti-reverse connection driving circuit according to any one of claims 1 to 3, characterized in that: The PWM generating circuit includes a first resistor, a first signal processing circuit and a second signal processing circuit; The first end of the first resistor, the input end of the first signal processing loop and the input end of the second signal processing loop are connected to form the input end of the PWM generating circuit, and the second end of the first resistor is grounded; The first output end of the first signal processing circuit is connected to the first output end of the second signal processing circuit to form the output end of the PWM generating circuit; The second output end of the first signal processing loop is connected to the first power supply, and the second output end of the second signal processing loop is grounded.

5. The anti-reverse connection driving circuit according to claim 4, characterized in that: The first signal processing loop includes a second resistor and a PNP transistor; The first end of the second resistor is the input end of the first signal processing loop, and the second end of the second resistor is connected to the base of the PNP transistor; The collector of the PNP transistor is the first output end of the first signal processing loop, and the emitter of the PNP transistor is the second output end of the first signal processing loop.

6. The anti-reverse connection driving circuit according to claim 5, characterized in that: The second signal processing loop includes a third resistor and a first NPN transistor; A first end of the third resistor is an input end of the second signal processing loop, and a second end of the third resistor is connected to a base of the first NPN transistor; The collector of the first NPN transistor is the first output end of the second signal processing loop, and the emitter of the first NPN transistor is the second output end of the second signal processing loop.

7. The anti-reverse connection driving circuit according to any one of claims 1 to 3, characterized in that: The bootstrap circuit includes a charge and discharge circuit, an anti-reverse connection circuit and a bootstrap capacitor; The input end of the charge-discharge loop is the input end of the bootstrap circuit, the first output end of the charge-discharge loop is connected to the first input end of the anti-reverse connection loop, and the second output end of the charge-discharge loop is connected to the second input end of the anti-reverse connection loop; The first output end of the anti-reverse connection loop is the first output end of the bootstrap circuit, the second output end of the anti-reverse connection loop is connected to the first end of the bootstrap capacitor to form the second output end of the bootstrap circuit, and the second end of the bootstrap capacitor is grounded.

8. The anti-reverse connection driving circuit according to claim 7, characterized in that: The anti-reverse connection circuit comprises a first diode, a second diode, a third diode and a fourth diode connected in series in sequence; The positive terminal of the first diode is the second output terminal of the anti-reverse connection loop, and the negative terminal of the first diode is connected to the positive terminal of the second diode to form the first input terminal of the anti-reverse connection loop; The cathode terminal of the third diode is connected to the anode terminal of the fourth diode to form the second input terminal of the anti-reverse connection loop, and the cathode terminal of the fourth diode is the first output terminal of the anti-reverse connection loop.

9. The anti-reverse connection driving circuit according to any one of claims 1 to 3, characterized in that: Also includes: A reverse shutdown circuit, wherein the input end of the reverse shutdown circuit is connected to the first output end of the bootstrap circuit, and the output end of the reverse shutdown circuit is connected to the gate of the NMOS tube; The reverse shutdown circuit is used to discharge the gate voltage of the NMOS tube.

10. The anti-reverse connection driving circuit according to claim 9, characterized in that: The reverse shutdown circuit includes a fourth resistor, a second NPN transistor and a voltage discharge loop; The first end of the fourth resistor is the input end of the reverse shutdown circuit, and the second end of the fourth resistor is connected to the base of the second NPN transistor and the emitter of the second NPN transistor; The collector of the second NPN transistor is connected to the first output end of the voltage discharge circuit to form the output end of the reverse shutdown circuit; The input end of the voltage discharge circuit is connected to the second power supply.

11. A circuit control system, characterized in that: The invention comprises the anti-reverse connection driving circuit as claimed in any one of claims 1 to 10.

Images