Interface anti-creeping protection circuit, chip and electronic equipment

Abstract

The invention discloses an interface anti-creeping protection circuit, a chip and electronic equipment, the interface anti-creeping protection circuit comprises a driving unit, the driving unit comprises a plurality of first driving tubes, the first end of each first driving tube is suitable for being connected with a power supply, and the second end of each first driving tube is suitable for being connected with a signal interface; and the potential control unit is respectively connected with the substrate and the grid electrode of each first driving tube, and the potential control unit is configured to gate the well potential and the grid electrode potential of each first driving tube as a larger value in the potential of the signal interface and the potential of the power supply when the chip is in a power-down mode. According to the circuit, the gate potential and the well potential of each first driving tube are pulled to the high potential through the potential control unit, a parasitic path between a signal interface and a power supply is cut off, leakage current is reduced, then the static power consumption of a chip is reduced, and the reliability of the chip is improved.

Description

Technical Field

[0001] The present application relates to the technical field of interface circuits, and in particular to an interface leakage protection circuit, a chip and an electronic device. Background Art

[0002] In the I / O (Input / Output) interface circuit, since there is a driver tube or electrostatic protection unit circuit between the signal interface and the power supply, when the voltage of the power supply is lower than the voltage of the signal interface, there is a parasitic forward-conducting diode path between the signal interface and the power supply, forming a leakage channel, which increases the static power consumption of the chip. In the related art, in order to cut off this parasitic path, the substrate of the driver tube connected to the power supply will be floated. This method will bring some problems, such as uncontrollable well potential, affecting the threshold voltage of the driver tube, introducing latch effect, and sacrificing reliability and anti-static capabilities such as discharge path, so the chip reliability is poor and it is difficult to pass various reliability capability tests. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems in the related art to a certain extent. To this end, the first purpose of the present invention is to propose an interface leakage protection circuit, in which, when the chip is in power-off mode, the gate potential and well potential of each first driving tube are pulled to a high potential through a potential control unit, thereby cutting off the parasitic path between the signal interface and the power supply, avoiding the current of the signal interface from being input into the power supply, thereby reducing the leakage current, and further reducing the static power consumption of the chip, and the well potential is controllable, thereby improving the reliability of the chip.

[0004] The second objective of the present invention is to provide a chip.

[0005] A third objective of the present invention is to provide an electronic device.

[0006] To achieve the above-mentioned purpose, an interface leakage protection circuit is proposed according to an embodiment of the first aspect of the present invention, comprising: a driving unit, the driving unit comprising a plurality of first driving tubes, the first end of each first driving tube being suitable for connecting to a power supply, and the second end of each first driving tube being suitable for connecting to a signal interface; a potential control unit, the potential control unit being respectively connected to a substrate and a gate of each first driving tube, and the potential control unit being configured to select a well potential and a gate potential of each first driving tube as a larger value between a potential of the signal interface and a potential of the power supply when the chip is in a power-off mode.

[0007] According to an embodiment of the present invention, the interface leakage protection circuit includes a driving unit and a potential control unit. When the chip is in a power-off mode, the potential control unit selects the well potential and gate potential of each first driving tube as the larger value of the potential of the signal interface and the potential of the power supply, so that the gate potential and well potential of each first driving tube are always at a high potential, so that the first driving tube will not enter a subthreshold conduction state, and the parasitic path between the signal interface and the power supply is cut off to avoid the current of the signal interface from being input into the power supply, thereby reducing the leakage current and further reducing the static power consumption of the chip; and the well potential is controllable and is always at a higher potential, so that the carriers can be effectively prevented from entering the base region, increasing the difficulty of triggering the latch effect, and obtaining an avalanche negative resistance hysteresis maintenance channel between the signal interface and the power supply, thereby improving the anti-static ability of the chip and thus improving the reliability of the chip.

[0008] According to one embodiment of the present invention, the potential control unit includes: a well potential control module, the well potential control module is connected to the substrate of each first driving tube, so that when the chip is in a power-down mode, the well potential of each first driving tube is selected as the larger value between the potential of the signal interface and the potential of the power supply; a gate potential control module, the gate potential control module is connected to the gate of each first driving tube, so that when the chip is in a power-down mode, the gate potential of each first driving tube is selected as the larger value between the potential of the signal interface and the potential of the power supply.

[0009] According to one embodiment of the present invention, the well potential control module includes: a first gating submodule, the first end of the first gating submodule is suitable for connecting to a signal interface, the second end of the first gating submodule is connected to the substrate of each first driving tube, the control end of the first gating submodule is suitable for connecting to a power supply, and the first gating submodule is turned on when the potential of the signal interface is greater than the potential of the power supply, so as to gating the well potential of each first driving tube to the potential of the signal interface; a second gating submodule, the first end of the second gating submodule is suitable for connecting to the power supply, the second end of the second gating submodule is connected to the substrate of each first driving tube, and the control end of the second gating submodule is suitable for inputting a power-off signal, and the second gating submodule is turned on when the power-off signal is received and the potential of the signal interface is less than or equal to the potential of the power supply, so as to gating the well potential of each first driving tube to the potential of the power supply.

[0010] According to one embodiment of the present invention, the well potential control module also includes: a first inverter, the input end of the first inverter is suitable for accessing the mode selection signal, the output end of the first inverter is connected to the control end of the second selection submodule, and the first inverter is configured to generate a power-off signal according to the mode selection signal.

[0011] According to one embodiment of the present invention, the first gating submodule includes: a first switching device and a second switching device, wherein the first end of the first switching device is connected to the first end of the second switching device and has a first node, the first node is suitable for connecting to a signal interface, the second end of the first switching device is connected to the second end of the second switching device and has a second node, the second node is connected to the substrate of each first driving tube, and the control end of the first switching device is suitable for connecting to a power supply.

[0012] According to one embodiment of the present invention, the first switching device is a first PMOS tube, the second switching device is a first NMOS tube, the source of the first NMOS tube is the first end of the second switching device, the drain of the first NMOS tube is the second end of the second switching device, and the gate and source of the first NMOS tube are connected.

[0013] According to one embodiment of the present invention, the first switch device is a first PMOS tube, the second switch device is a first diode, the anode of the first diode is the first end of the second switch device, and the cathode of the first diode is the second end of the second switch device.

[0014] According to one embodiment of the present invention, the second gating submodule includes: a third switching device and a fourth switching device, wherein the first end of the third switching device is connected to the first end of the fourth switching device and has a third node, the third node is suitable for connecting to a power supply, the second end of the third switching device is connected to the second end of the fourth switching device and has a fourth node, the fourth node is connected to the substrate of each first driving tube, and the control end of the third switching device is suitable for inputting a power-off signal.

[0015] According to one embodiment of the present invention, the third switching device is a second PMOS tube, the fourth switching device is a second NMOS tube, the source of the second NMOS tube is the first end of the fourth switching device, the drain of the second NMOS tube is the second end of the fourth switching device, and the gate and source of the second NMOS tube are connected.

[0016] According to one embodiment of the present invention, the third switch device is a second PMOS tube, the fourth switch device is a second diode, the anode of the second diode is the first end of the fourth switch device, and the cathode of the second diode is the second end of the fourth switch device.

[0017] According to an embodiment of the present invention, the second gating submodule is also turned on when the chip is in the digital transmission mode, so as to gating the well potential of each first driving tube to the potential of the power supply.

[0018] According to one embodiment of the present invention, there are two first drive tubes, namely, a first target drive tube and a second target drive tube, and the gate potential control module includes: a third gating submodule, the input end of the third gating submodule is suitable for inputting the first control signal, the control end of the third gating submodule is suitable for inputting the power-off signal, the output end of the third gating submodule is connected to the gate of the first target drive tube, and the third gating submodule is opened when the power-off signal is received and the potential of the signal interface is less than or equal to the potential of the power supply, so as to select the gate potential of the first target drive tube to the potential of the power supply; a fourth gating submodule, the input end of the fourth gating submodule is suitable for connecting the signal interface, the control end of the fourth gating submodule is suitable for connecting the power supply, the output end of the fourth gating submodule is connected to the gate of the first target drive tube, and the fourth gating submodule is opened when the potential of the signal interface is greater than the potential of the power supply. , so as to select the gate potential of the first target driving tube as the potential of the signal interface; a fifth selection submodule, the input end of the fifth selection submodule is suitable for inputting the second control signal, the control end of the fifth selection submodule is suitable for inputting the power-off signal, the output end of the fifth selection submodule is connected to the gate of the second target driving tube, and the fifth selection submodule is opened when the power-off signal is received and the potential of the signal interface is less than or equal to the potential of the power supply, so as to select the gate potential of the second target driving tube as the potential of the power supply; a sixth selection submodule, the input end of the sixth selection submodule is suitable for connecting the signal interface, the control end of the sixth selection submodule is suitable for connecting the power supply, the output end of the sixth selection submodule is connected to the gate of the second target driving tube, and the sixth selection submodule is opened when the potential of the signal interface is greater than the potential of the power supply, so as to select the gate potential of the second target driving tube as the potential of the signal interface.

[0019] According to an embodiment of the present invention, the fourth gating submodule and the sixth gating submodule are respectively a third PMOS transistor and a fourth PMOS transistor.

[0020] According to one embodiment of the present invention, the third gating submodule includes: a fifth switching device and a sixth switching device, wherein the first end of the fifth switching device is connected to the first end of the sixth switching device and has a fifth node, the fifth node is suitable for inputting a first control signal, the second end of the fifth switching device is connected to the second end of the sixth switching device and has a sixth node, the sixth node is connected to the gate of the first target driving tube, and the control end of the fifth switching device is suitable for inputting a power-off signal.

[0021] According to one embodiment of the present invention, the fifth switching device is a fifth PMOS tube, the sixth switching device is a third NMOS tube, the source of the third NMOS tube is the first end of the sixth switching device, the drain of the third NMOS tube is the second end of the sixth switching device, and the gate of the third NMOS tube is suitable for connecting to a power supply.

[0022] According to one embodiment of the present invention, the fifth switch device is a fifth PMOS tube, the sixth switch device is a third diode, the anode of the third diode is the first end of the sixth switch device, and the cathode of the third diode is the second end of the sixth switch device.

[0023] According to one embodiment of the present invention, the fifth gating submodule includes: a seventh switching device and an eighth switching device, wherein the first end of the seventh switching device is connected to the first end of the eighth switching device and has a seventh node, the seventh node is suitable for inputting a second control signal, the second end of the seventh switching device is connected to the second end of the eighth switching device and has an eighth node, the eighth node is connected to the gate of the second target driving tube, and the control end of the eighth switching device is suitable for inputting a power-off signal.

[0024] According to one embodiment of the present invention, the seventh switching device is the sixth PMOS tube, the eighth switching device is the fourth NMOS tube, the source of the fourth NMOS tube is the first end of the eighth switching device, the drain of the fourth NMOS tube is the second end of the eighth switching device, and the gate of the fourth NMOS tube is suitable for connecting to a power supply.

[0025] According to one embodiment of the present invention, the seventh switch device is a sixth PMOS tube, the eighth switch device is a fourth diode, the anode of the fourth diode is the first end of the eighth switch device, and the cathode of the fourth diode is the second end of the eighth switch device.

[0026] According to an embodiment of the present invention, the third gating submodule and the fifth gating submodule are also turned on when the chip is in the digital transmission mode.

[0027] According to an embodiment of the present invention, the first driving transistor is a PMOS.

[0028] According to one embodiment of the present invention, the driving unit further comprises a plurality of second driving tubes, which are arranged corresponding to the first driving tubes, wherein the first end of each second driving tube is suitable for connecting to a signal interface, and the second end of each second driving tube is grounded.

[0029] According to an embodiment of the present invention, the second driving transistor is an NMOS.

[0030] To achieve the above object, a chip is provided according to a second aspect of the present invention, comprising the interface leakage protection circuit of any of the above embodiments.

[0031] According to the chip of the embodiment of the present invention, by adopting the above-mentioned interface leakage protection circuit, when the chip is in the power-off mode, the gate potential and the well potential of each first driving tube are pulled to a high potential through the potential control unit, thereby cutting off the parasitic path between the signal interface and the power supply, avoiding the current of the signal interface from being input into the power supply, thereby reducing the leakage current, and further reducing the static power consumption of the chip, and the well potential is controllable, thereby improving the reliability of the chip.

[0032] To achieve the above objective, an electronic device is provided according to a third aspect of the present invention, comprising the aforementioned chip.

[0033] According to the electronic device of the embodiment of the present invention, by adopting the above-mentioned chip, when the chip is in the power-off mode, the gate potential and the well potential of each first driving tube are pulled to a high potential through the potential control unit, thereby cutting off the parasitic path between the signal interface and the power supply, avoiding the current of the signal interface from being input into the power supply, thereby reducing the leakage current, and further reducing the static power consumption of the chip, and the well potential is controllable, thereby improving the reliability of the chip.

[0034] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 is a schematic structural diagram of an interface anti-leakage protection circuit according to an embodiment of the present invention;

[0036] Figure 2 is a schematic structural diagram of a potential control unit according to an embodiment of the present invention;

[0037] Figure 3 is a circuit diagram of a well potential control module according to an embodiment of the present invention;

[0038] Figure 4 is a circuit diagram when the second switch device and the fourth switch device are PMOS according to an embodiment of the present invention;

[0039] Figure 5 is a circuit diagram when the second switching device and the fourth switching device are diodes according to an embodiment of the present invention;

[0040] Figure 6 is a circuit diagram of a gate potential control module according to an embodiment of the present invention;

[0041] Figure 7 is a circuit diagram when the sixth switch device and the eighth switch device are PMOS according to an embodiment of the present invention;

[0042] Figure 8is a circuit diagram when the sixth switching device and the eighth switching device are diodes according to an embodiment of the present invention;

[0043] Fig. 9 is a circuit diagram of an interface anti-leakage protection circuit including a resistor according to an embodiment of the present invention;

[0044] Fig.10 is a voltage curve of each interface of a chip under a digital transmission function according to an embodiment of the present invention;

[0045] Fig.11 is a pull-up and pull-down voltage curve of a chip under a digital transmission function according to an embodiment of the present invention;

[0046] Fig.12 is a DC scanning voltage and current curve of a power supply in a power-off mode according to an embodiment of the present invention;

[0047] Fig.13 is a DC scanning voltage and current curve of a signal interface in a power-off mode according to an embodiment of the present invention;

[0048] Fig.14 is a DC scan voltage and current curve of a signal interface in a fail-safe mode according to an embodiment of the present invention;

[0049] Fig.15 is a DC scanning voltage and current curve of a signal interface in an analog signal transmission mode according to an embodiment of the present invention;

[0050] Fig.16 is a schematic diagram of the structure of a chip according to an embodiment of the present invention;

[0051] Fig.17 is a schematic structural diagram of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0052] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0053] The interface leakage protection circuit, chip and electronic device according to the embodiments of the present invention are described below with reference to the accompanying drawings.

[0054] Figure 1 FIG. 1 is a schematic diagram of the structure of an interface leakage protection circuit according to an embodiment of the present invention. Figure 1 As shown, the interface leakage protection circuit includes: a driving unit 10 and a potential control unit 20.

[0055] The driving unit 10 includes a plurality of first driving tubes Qp, wherein the first end of each first driving tube Qp is suitable for connecting to the power supply VDD, and the second end of each first driving tube Qp is suitable for connecting to the signal interface PAD; the potential control unit 20 is respectively connected to the substrate and the gate of each first driving tube Qp, and the potential control unit 20 is configured to select the well potential and the gate potential of each first driving tube Qp as the larger value of the potential of the signal interface PAD and the potential of the power supply VDD when the chip is in the power-off mode.

[0056] Specifically, when the chip is in the power-down mode, the potential of the signal interface PAD may be greater than the potential of the power supply VDD. If the potential of the substrate and the control end of the first driving tube Qp is lower than the potential of the second end of the first driving tube Qp, the parasitic diode between the substrate of the first driving tube Qp and the second end of the first driving tube Qp will be turned on, and a channel inversion layer will be formed, and the current of the signal interface PAD will flow into the power supply VDD, causing the chip to leak. Therefore, when the chip is in the power-down mode, the potential control unit 20 selects the well potential and the gate potential of each first driving tube Qp as the larger value of the potential of the signal interface PAD and the potential of the power supply VDD, the well potential of the first driving tube Qp is always high, the parasitic diode between the substrate of the first driving tube Qp and the second end of the first driving tube Qp will not be turned on, and the parasitic path between the signal interface PAD and the power supply VDD is cut off. In addition, because the gate potential of the first driving tube Qp is also high, the first driving tube Qp will not be in a subthreshold conduction state, and the current of the signal interface PAD will not flow into the power supply VDD. In addition, since the well potential of the first driving tube Qp is controllable and always at a high potential, it can not only effectively prevent carriers from entering the base region, increasing the difficulty of triggering the latch effect, but also obtain an avalanche negative resistance hysteresis maintenance channel between the power supply VDD and the signal interface PAD.

[0057] Furthermore, in some embodiments, the first driving transistor Qp is a PMOS (Positive Channel Meta-Oxide-Semiconductor).

[0058] It can be understood that the first driving tube Qp is an upper tube, and in order to ensure that the power supply VDD can be fully transmitted to the signal interface PAD, the first driving tube Qp is a PMOS.

[0059] In some embodiments, Figure 2As shown, the driving unit 10 further includes a plurality of second driving tubes Qn, which are arranged corresponding to the first driving tubes Qp, and the first end of each second driving tube Qn is suitable for connecting to the signal interface PAD, and the second end of each second driving tube Qn is grounded GND.

[0060] Specifically, because the signal interface PAD is an I / O interface, the signal transmission direction is not fixed. The driving unit 10 also includes a second driving tube Qn. The second driving tube Qn and the first driving tube Qp are arranged in a one-to-one correspondence. The second driving tube Qn is arranged between the signal interface PAD and the ground to protect the signal interface PAD when the signal interface PAD works in the input mode.

[0061] Furthermore, in some embodiments, the second driving transistor Qn is a NMOS (Negative Channel Meta-Oxide-Semiconductor, negative channel MOS transistor).

[0062] It can be understood that, because the first driving tube Qp is a PMOS, the second driving tube Qn and the first driving tube Qp cannot be turned on at the same time, so the second driving tube Qn is an NMOS.

[0063] It should be noted that the number of the first driving tubes Qp and the second driving tubes Qn in this embodiment is not limited to Figure 2 The 2 shown can also be other quantities. Figure 2 The two first driving tubes Qp and the two second driving tubes Qn shown are exemplary and are not intended to limit the present application.

[0064] In the above embodiment, when the chip is in the power-off mode, the gate potential and the well potential of the first driving tube are pulled to a high potential through the potential control unit, the parasitic diode between the substrate of the first driving tube and the second end of the first driving tube will not be turned on, and the first driving tube will not be in a subthreshold conduction state, so the current of the signal interface will not flow into the power supply, thereby reducing the static power consumption of the chip; and because the well potential of the first driving tube is controllable and is always at a high potential, it can not only effectively prevent carriers from entering the base region, thereby increasing the difficulty of triggering the latch effect, but also obtain an avalanche negative resistance hysteresis maintenance channel between the power supply and the signal interface, thereby improving the anti-static ability and reliability of the chip.

[0065] In some embodiments, Figure 2As shown, the potential control unit 20 includes: a well potential control module 21 and a gate potential control module 22, wherein the well potential control module 21 is connected to the substrate of each first driving tube Qp, so that when the chip is in the power-down mode, the well potential of each first driving tube Qp is selected as the larger value between the potential of the signal interface PAD and the potential of the power supply VDD; the gate potential control module 22 is connected to the gate of each first driving tube Qp, so that when the chip is in the power-down mode, the gate potential of each first driving tube Qp is selected as the larger value between the potential of the signal interface PAD and the potential of the power supply VDD.

[0066] Specifically, the potential control unit 20 includes a well potential control module 21 and a gate potential control module 22. The well potential control module 21 controls the well potential of each first driving tube Qp by connecting the substrate of each first driving tube Qp with the signal interface PAD or the power supply VDD. The gate potential control module 22 controls the gate potential of each first driving tube Qp by connecting the gate of each first driving tube Qp with the signal interface PAD or the power supply VDD.

[0067] In some embodiments, Figure 3 As shown, the well potential control module 21 includes: a first gating submodule 211 and a second gating submodule 212, wherein the first end of the first gating submodule 211 is suitable for connecting to the signal interface PAD, the second end of the first gating submodule 211 is connected to the substrate of each first driving tube Qp, the control end of the first gating submodule 211 is suitable for connecting to the power supply VDD, and the first gating submodule 211 is turned on when the potential of the signal interface PAD is greater than the potential of the power supply VDD, so as to gating the well potential of each first driving tube Qp to the potential of the signal interface PAD; the first end of the second gating submodule 212 is suitable for connecting to the power supply VDD, the second end of the second gating submodule 212 is connected to the substrate of each first driving tube Qp, and the control end of the second gating submodule 212 is suitable for inputting a power-off signal, and the second gating submodule 212 is turned on when the power-off signal is received and the potential of the signal interface PAD is less than or equal to the potential of the power supply VDD, so as to gating the well potential of each first driving tube Qp to the potential of the power supply VDD.

[0068] Specifically, the first end of the first gating submodule 211 is suitable for connecting to the signal interface PAD, and the second end of the first gating submodule 211 is connected to the substrate of each first driving tube Qp, so that when the first gating submodule 211 is turned on, the substrate of each first driving tube Qp is connected to the signal interface PAD, so that the well potential is the potential of the signal interface PAD. The first end of the second gating submodule 212 is suitable for connecting to the power supply VDD, and the second end of the second gating submodule 212 is connected to the substrate of each first driving tube Qp, so that when the second gating submodule 212 is turned on, the substrate of each first driving tube Qp is connected to the power supply VDD, so that the well potential is the potential of the power supply VDD.

[0069] It should be noted that, when the chip is in the digital transmission mode, the first driving tube Qp is turned on, the power supply VDD flows through the first driving tube Qp and is output from the signal interface PAD, and the potential of the signal interface PAD is the same as the potential of the power supply VDD. Therefore, the potential of the signal interface PAD will not be greater than the potential of the power supply VDD. Therefore, the first selection submodule 211 will not be turned on in the digital transmission mode, and the well potential of the first driving tube Qp will not be the potential of the signal interface PAD in the digital transmission mode.

[0070] In some embodiments, the second gating submodule 212 is also turned on when the chip is in the digital transmission mode, so as to gating the well potential of each first driving transistor Qp to the potential of the power supply VDD.

[0071] It can be understood that from the above analysis, when the chip is in digital transmission mode, the potential of the signal interface PAD is less than or equal to the potential of the power supply VDD, so the potential of the power supply VDD is a high potential, and the second selection submodule 212 directly selects the well potential of each first driving tube Qp to the potential of the power supply VDD.

[0072] In the above embodiment, the first gating submodule and the second gating submodule are turned on in time-sharing manner according to the potential of the power supply and the potential of the signal interface, so that the substrate of the first driving tube is connected to the signal interface or the power supply to realize the control of the well potential.

[0073] In some embodiments, Figure 3 As shown, the well potential control module 21 also includes: a first inverter INV1, the input end of the first inverter INV1 is suitable for accessing the mode selection signal FSE, the output end of the first inverter INV1 is connected to the control end of the second selection submodule 212, and the first inverter INV1 is configured to generate a power-off signal according to the mode selection signal FSE.

[0074] Specifically, the chip includes a power-down mode and a digital transmission mode. When the mode selection signal FSE is at a high level, the chip is in the digital transmission mode, the first inverter INV1 outputs a low level, and the power-down signal is a low level. When the mode selection signal FSE is at a low level, the chip is in the power-down mode, the first inverter INV1 outputs a high level, and the power-down signal is a high level. At this time, if the potential of the signal interface PAD is less than or equal to the potential of the power supply VDD, the second enabling submodule 212 is turned on.

[0075] In an optional implementation, the input end of the first inverter INV1 is suitable for connecting to a function selection pin of the chip, and the chip outputs the mode selection signal FSE through the function selection pin.

[0076] It should be noted that the function selection pin is an independent pin of the chip. In actual applications, the input end of the first inverter INV1 is not limited to being connected to the function selection pin of the chip, but can also be connected to the input and output enable pin, pull-up enable pin or pull-down enable pin of the chip. This can reduce the pin occupancy of the chip and reduce the complexity of the circuit, thereby solving the circuit cost.

[0077] In some embodiments, Figure 3 As shown, the first gating submodule 211 includes: a first switching device Q1 and a second switching device Q2, wherein the first end of the first switching device Q1 is connected to the first end of the second switching device Q2 and has a first node J1, and the first node J1 is suitable for connecting to the signal interface PAD, the second end of the first switching device Q1 is connected to the second end of the second switching device Q2 and has a second node J2, and the second node J2 is connected to the substrate of each first driving tube Qp, and the control end of the first switching device Q1 is suitable for connecting to the power supply VDD.

[0078] Specifically, the first switch device Q1 and the second switch device Q2 are turned on when the potential of the signal interface PAD is greater than the potential of the power supply VDD, so the first selection submodule 211 is turned on when the potential of the signal interface PAD is greater than the potential of the power supply VDD, and the well potential of the first driving tube Qp is selected as the potential of the signal interface PAD; the first switch device Q1 and the second switch device Q2 are turned off when the potential of the signal interface PAD is less than or equal to the potential of the power supply VDD, so the first selection submodule 211 is turned off when the potential of the signal interface PAD is less than or equal to the potential of the power supply VDD, and the well potential of the first driving tube Qp is not the potential of the signal interface PAD.

[0079] In some embodiments, Figure 4As shown, the first switch device Q1 is a first PMOS tube PM1, the second switch device Q2 is a first NMOS tube NM1, the source of the first NMOS tube NM1 is the first end of the second switch device Q2, the drain of the first NMOS tube NM1 is the second end of the second switch device Q2, and the gate and source of the first NMOS tube NM1 are connected.

[0080] Specifically, when the first switch device Q1 is the first PMOS tube PM1, and the second switch device Q2 is the first NMOS tube NM1, the source of the first PMOS tube PM1 is the first end of the first switch device Q1, the drain of the first PMOS tube PM1 is the second end of the first switch device Q1, the gate of the first PMOS tube PM1 is the control end of the first switch device Q1, the source of the first NMOS tube NM1 is the first end of the second switch device Q2, the drain of the first NMOS tube NM1 is the second end of the second switch device Q2, and the gate and source of the first NMOS tube NM1 are connected, so the first NMOS tube NM1 can be equivalent to a diode.

[0081] When the potential of the signal interface PAD is less than or equal to the potential of the power supply VDD, the source potential of the first PMOS tube PM1 is less than the gate potential of the first PMOS tube PM1, so the first PMOS tube PM1 remains in the off state, because the well potential of the first driving tube Qp is the potential of the power supply VDD when the potential of the signal interface PAD is less than or equal to the potential of the power supply VDD, so the drain potential of the first NMOS tube NM1 is less than the source potential of the first NMOS tube NM1, and the first NMOS tube NM1 is also in the off state. Therefore, the first selection submodule 211 is in the off state when the potential of the signal interface PAD is less than or equal to the potential of the power supply VDD.

[0082] When the potential of the signal interface PAD is greater than the potential of the power supply VDD, the source potential of the first PMOS tube PM1 is greater than the gate potential of the first PMOS tube PM1, so the first PMOS tube PM1 and the first NMOS tube NM1 are both turned on, and the substrate of the first driving tube Qp is connected to the signal interface PAD, so that the well potential of the first driving tube Qp is the potential of the signal interface PAD.

[0083] In some embodiments, Figure 5 As shown, the first switch device Q1 is a first PMOS transistor PM1, the second switch device Q2 is a first diode D1, the anode of the first diode D1 is the first end of the second switch device Q2, and the cathode of the first diode D1 is the second end of the second switch device Q2.

[0084] It can be understood that when the second switching device Q2 is the first NMOS tube NM1, the gate and source of the first NMOS tube NM1 are connected, and the first NMOS tube NM1 can be equivalent to a diode. Therefore, the first diode D1 can be used to replace the first NMOS tube NM1, thereby further reducing the cost of the interface leakage protection circuit.

[0085] In some embodiments, Figure 3 As shown, the second gating submodule 212 includes: a third switching device Q3 and a fourth switching device Q4, wherein the first end of the third switching device Q3 is connected to the first end of the fourth switching device Q4 and has a third node J3, and the third node J3 is suitable for connecting to the power supply VDD, the second end of the third switching device Q3 is connected to the second end of the fourth switching device Q4 and has a fourth node J4, and the fourth node J4 is connected to the substrate of each first driving tube Qp, and the control end of the third switching device Q3 is suitable for inputting a power-off signal.

[0086] Specifically, the third switch device Q3 and the fourth switch device Q4 are turned on when the power-off signal is at a low level, that is, the third switch device Q3 and the fourth switch device Q4 are turned on when the chip is in the digital transmission mode, so the second selection submodule 212 is turned on when the chip is in the digital transmission mode, and the well potential of the first driving tube Qp is selected as the potential of the power supply VDD. The third switch device Q3 is turned off when the power-off signal is at a high level, and when the potential of the signal interface PAD is less than or equal to the potential of the power supply VDD, the fourth switch device Q4 is turned on, so the second selection submodule 212 is turned on when the power-off signal is received and the potential of the signal interface PAD is less than or equal to the potential of the power supply VDD, and the well potential of the first driving tube Qp is selected as the potential of the power supply VDD.

[0087] In some embodiments, Figure 4 As shown, the third switch device Q3 is the second PMOS tube PM2, the fourth switch device Q4 is the second NMOS tube NM2, the source of the second NMOS tube NM2 is the first end of the fourth switch device Q4, the drain of the second NMOS tube NM2 is the second end of the fourth switch device Q4, and the gate and source of the second NMOS tube NM2 are connected.

[0088] Specifically, when the third switching device Q3 is the second PMOS tube PM2, and the fourth switching device Q4 is the second NMOS tube NM2, the source of the second PMOS tube PM2 is the first end of the third switching device Q3, the drain of the second PMOS tube PM2 is the second end of the third switching device Q3, the gate of the second PMOS tube PM2 is the control end of the third switching device Q3, the source of the second NMOS tube NM2 is the first end of the fourth switching device Q4, the drain of the second NMOS tube NM2 is the second end of the fourth switching device Q4, and the gate and source of the second NMOS tube NM2 are connected, so the second NMOS tube NM2 can be equivalent to a diode.

[0089] When the chip is in digital transmission mode, the mode selection signal FSE is at a high level and the power-off signal is at a low level, so the second PMOS transistor PM2 and the second NMOS transistor NM2 are both turned on, and the substrate of the first driving transistor Qp is connected to the power supply VDD, so that the well potential of the first driving transistor Qp is the potential of the power supply VDD.

[0090] When the chip is in power-down mode, the mode selection signal FSE is at a low level, and the power-down signal is at a high level, so the second PMOS tube PM2 is turned off. When the potential of the signal interface PAD is greater than the potential of the power supply VDD, the first PMOS tube PM1 and the first NMOS tube NM1 are turned on, and the well potential of the first driving tube Qp is the potential of the signal interface PAD, so the drain potential of the second NMOS is greater than the source potential, and the voltage between the source and the drain of the second NMOS tube NM2 is less than the device voltage, and the second NMOS tube NM2 is in the off state, which will block the current of the signal interface PAD from flowing into the power supply VDD, thereby cutting off the leakage channel of the signal interface PAD.

[0091] When the chip is in the power-down mode and the potential of the signal interface PAD is equal to the potential of the power supply VDD, the gate potential and the source potential of the first PMOS tube PM1 are the same, so the first PMOS tube PM1, the first NMOS tube NM1 and the second NMOS tube NM2 are all in the subthreshold conduction state, and the second PMOS tube PM2 remains in the off state. The source of the first NMOS tube NM1 is equivalent to the anode of the diode, the drain of the first NMOS tube NM1 is equivalent to the cathode of the diode, the drain of the second NMOS tube NM2 is equivalent to the cathode of the diode, and the source of the second NMOS tube NM2 is equivalent to the anode of the diode, so the first NMOS tube NM1 and the second NMOS tube NM2 can be equivalent to PNP transistors, the well potential of the first driving tube Qp is the potential of the signal interface PAD or the potential of the power supply VDD, and the substrate of the first driving tube Qp is the base of the PNP transistor, because the emitter, collector and base of the PNP transistor are all the potential of the power supply VDD, the voltage Vbe between the base and the emitter of the PNP transistor and the voltage Vbc between the base and the collector of the PNP transistor are both 0, the PNP transistor is in a cut-off state, so the current of each pole of the PNP transistor is almost 0.

[0092] When the chip is in power-down mode and the signal interface PAD is a transmission port for analog signals, the potential of the signal interface PAD is less than the potential of the power supply VDD, and the gate potential of the first PMOS tube PM1 is greater than the source potential, so the first PMOS tube PM1 is turned off, and the second PMOS tube PM2 remains in the off state. Because the second NMOS tube NM2 can be equivalent to a diode, the second NMOS tube NM2 is in a subthreshold conduction state, the well potential of the first driving tube Qp is the potential of the power supply VDD, so the drain potential of the first NMOS tube NM1 is the potential of the power supply VDD, and because the source potential of the first NMOS tube NM1 is the potential of the signal interface PAD, the first NMOS tube NM1 is in the off state, blocking the channel for the discharge current.

[0093] It should be noted that when the chip is in power-down mode and the potential of the signal interface PAD is less than the potential of the power supply VDD, the well potential will be slightly lower than the potential of the power supply VDD by 0.2V. This is because the barrier voltage in the depletion layer of the second NMOS causes the minority carrier drift to form a non-ideal state, thereby achieving a dynamic balance close to the potential of the power supply VDD, and no current flows through the PN junction.

[0094] In some embodiments, Figure 5 As shown, the third switch device Q3 is the second PMOS tube PM2, the fourth switch device Q4 is the second diode D2, the anode of the second diode D2 is the first end of the fourth switch device Q4, and the cathode of the second diode D2 is the second end of the fourth switch device Q4.

[0095] It can be understood that when the fourth switching device Q4 is the second NMOS tube NM2, the gate and source of the second NMOS tube NM2 are connected, and the second NMOS tube NM2 can be equivalent to a diode. Therefore, the second diode D2 can be used to replace the second NMOS tube NM2, thereby further reducing the cost of the interface leakage protection circuit.

[0096] In some embodiments, Figure 6 As shown, there are two first driving tubes Qp, namely, a first target driving tube Qp1 and a second target driving tube Qp2, and the gate potential control module 22 includes: a third gating submodule 221, a fourth gating submodule 222, a fifth gating submodule 223 and a sixth gating submodule 224, wherein the input end of the third gating submodule 221 is suitable for inputting a first control signal, the control end of the third gating submodule 221 is suitable for inputting a power-off signal, the output end of the third gating submodule 221 is connected to the gate of the first target driving tube Qp1, and the third gating submodule 222 is suitable for inputting a power-off signal. The submodule 221 is turned on when receiving a power-off signal and the potential of the signal interface PAD is less than or equal to the potential of the power supply VDD, so as to select the gate potential of the first target driving tube Qp1 to be the potential of the power supply VDD; the input end of the fourth selection submodule 222 is suitable for connecting to the signal interface PAD, the control end of the fourth selection submodule 222 is suitable for connecting to the power supply VDD, the output end of the fourth selection submodule 222 is connected to the gate of the first target driving tube Qp1, and the fourth selection submodule 222 is connected to the potential of the signal interface PAD. The fifth gating submodule 223 is turned on when the potential of the signal interface PAD is less than or equal to the potential of the power supply VDD, so as to select the gate potential of the first target driving tube Qp1 as the potential of the signal interface PAD; the input end of the fifth gating submodule 223 is suitable for inputting the second control signal, the control end of the fifth gating submodule 223 is suitable for inputting the power-off signal, and the output end of the fifth gating submodule 223 is connected to the gate of the second target driving tube Qp2. The fifth gating submodule 223 is turned on when the power-off signal is received and the potential of the signal interface PAD is less than or equal to the potential of the power supply VDD, so as to select the gate potential of the first target driving tube Qp1 as the potential of the signal interface PAD; the input end of the fifth gating submodule 223 is suitable for inputting the second control signal, the control end of the fifth gating submodule 223 is suitable for inputting the power-off signal, and the output end of the fifth gating submodule 223 is connected to the gate of the second target driving tube Qp2. The gate potential of the second target driving tube Qp2 is selected as the potential of the power supply VDD; the input end of the sixth selection submodule 224 is suitable for connecting to the signal interface PAD, the control end of the sixth selection submodule 224 is suitable for connecting to the power supply VDD, the output end of the sixth selection submodule 224 is connected to the gate of the second target driving tube Qp2, and the sixth selection submodule 224 is turned on when the potential of the signal interface PAD is greater than the potential of the power supply VDD, so as to select the gate potential of the second target driving tube Qp2 as the potential of the signal interface PAD.

[0097] Specifically, if only the well potential of the first driving tube Qp is selected as a high potential, and the gate potential of the first driving tube Qp is maintained at the potential of the power supply VDD, then the gate potential and the source potential of the first driving tube Qp are the same, and the first driving tube Qp can be equivalent to a diode, the cathode of the diode is connected to the power supply VDD, and the anode of the diode is connected to the signal interface PAD. Therefore, when the potential of the signal interface PAD is greater than the potential of the power supply VDD, the diode will be turned on, so the current of the signal interface PAD will flow into the power supply VDD, resulting in leakage problems. Therefore, the gate potential of the first driving tube Qp also needs to be selected as a high potential. Figure 6 As shown, there are two first drive tubes Qp, namely the first target drive tube Qp1 and the second target drive tube Qp2. When the chip is in the digital transmission mode, the first control signal is a digital pulse signal, and the first target drive tube Qp1 switches according to the first control signal to make the signal interface PAD output a pulse signal. The second control signal is a voltage pull-up signal PU, and the second target drive tube Qp2 switches according to the second control signal to pull the potential of the signal interface PAD to the potential of the power supply VDD. Therefore, the gate potentials of the first target drive tube Qp1 and the second target drive tube Qp2 need to be controlled by different gating submodules.

[0098] When the chip is in power-down mode, the first control signal is a first high-level signal, and the amplitude of the first high-level signal is the amplitude of the power supply VDD. When the third selection submodule 221 is turned on, the gate of the first target drive tube Qp1 is suitable for inputting the first control signal, so the gate potential of the first target drive tube Qp1 is the potential of the power supply VDD. The input end of the fourth selection submodule 222 is suitable for connecting the signal interface PAD, so when the fourth selection submodule 222 is turned on, the gate of the first target drive tube Qp1 is connected to the signal interface PAD, and the gate potential of the first target drive tube Qp1 is the potential of the signal interface PAD.

[0099] When the chip is in power-down mode, the second control signal is a second high-level signal, and the amplitude of the second high-level signal is the amplitude of the power supply VDD. When the fifth selection submodule 223 is turned on, the gate of the second target drive tube Qp2 is suitable for inputting the second control signal, so the gate potential of the second target drive tube Qp2 is the potential of the power supply VDD. The input end of the sixth selection submodule 224 is suitable for connecting the signal interface PAD, so when the sixth selection submodule 224 is turned on, the gate of the second target drive tube Qp2 is connected to the signal interface PAD, and the gate potential of the second target drive tube Qp2 is the potential of the signal interface PAD.

[0100] In some embodiments, the third gating submodule 221 and the fifth gating submodule 223 are also turned on when the chip is in the digital transmission mode.

[0101] It can be understood that when the chip is in the digital transmission mode, the potential of the signal interface PAD will not be greater than the potential of the power supply VDD, so the fourth gating submodule 222 and the sixth gating submodule 224 are not turned on, and the third gating submodule 221 and the fifth gating submodule 223 are turned on. At this time, the first control signal is a digital pulse signal, the first target drive tube Qp1 is switched according to the first control signal, the second control signal is a voltage pull-up signal PU, and the second target drive tube Qp2 is switched according to the second control signal.

[0102] In an optional embodiment, if Figure 6 As shown, there are two second drive tubes Qn, namely the third target drive tube Qn1 and the fourth target drive tube Qn2. The control end of the fourth target drive tube Qn2 is suitable for receiving the pull-down signal PD. When the pull-down signal PD is at a high level, the fourth target drive tube Qn2 is turned on, and the signal interface PAD is grounded to GND, so that the potential of the signal interface PAD is 0. The signal interface circuit includes a first NAND gate NAND1, a second NAND gate NAND2, a second inverter INV2 and a NOR gate NOR, wherein the first input end of the first NAND gate NAND1 is suitable for receiving the digital input pulse A, the second input end of the first NAND gate NAND1 is suitable for receiving the enable signal EN, the output end of the first NAND gate NAND1 is connected to the input end of the third selection submodule 221, and the first NAND gate NAND1 is configured to generate a first control signal according to the digital input pulse A and the enable signal EN; the first input end of the second NAND gate NAND2 is suitable for receiving the pull-up signal PU, the second inverter INV2 ... The second input end of the NAND gate NAND2 is suitable for accessing the mode selection signal FSE, the output end of the second NAND gate NAND2 is connected to the input end of the fifth selection submodule 223, and the second NAND gate NAND2 is configured to generate a second control signal according to the pull-up signal PU and the mode selection signal FSE; the input end of the second inverter INV2 is suitable for accessing the enable signal EN, the output end of the second inverter INV2 is connected to the first input end of the NOR gate NOR, the second input end of the NOR gate NOR is suitable for accessing the enable signal EN, and the output end of the NOR gate NOR is connected to the control end of the third target driver tube Qn1.

[0103] Specifically, when the chip is in the digital transmission mode, the enable signal EN and the mode selection signal FSE are both high level, therefore, the first control signal output by the first NAND gate NAND1 is a digital pulse signal obtained by inverting the digital input pulse A, and the second control signal at the output end of the second NAND gate NAND2 is a signal obtained by inverting the pull-up signal PU. When the chip is in the power-off mode, the enable signal EN and the mode selection signal FSE are both low level, therefore, the first control signal output by the first NAND gate NAND1 is a first high level signal, and the second control signal output by the second NAND gate NAND2 is a second high level signal.

[0104] It should be noted that the signal interface circuit is not limited to the above structure, and the structure of the signal interface circuit can be adjusted according to actual functional requirements, such as adding a level conversion circuit and a hysteresis circuit, which is not specifically limited here.

[0105] In the above embodiment, the third gating submodule, the fourth gating submodule, the fifth gating submodule and the sixth submodule are turned on in time according to the potential of the power supply and the potential of the signal interface, so that the gates of the first target driving tube and the second target driving tube are connected to the signal interface or are suitable for receiving high-level signals, thereby realizing control of the gate potential.

[0106] In some embodiments, Figure 6 As shown, the fourth gating submodule 222 and the sixth gating submodule 224 are respectively the third PMOS transistor PM3 and the fourth PMOS transistor PM4.

[0107] Specifically, the source of the third PMOS transistor PM3 is the input terminal of the fourth gating submodule 222, the drain of the third PMOS transistor PM3 is the output terminal of the fourth gating submodule 222, and the gate of the third PMOS transistor PM3 is the control terminal of the fourth gating submodule 222. In the case where the potential of the signal interface PAD is greater than the potential of the power supply VDD, the source potential of the third PMOS transistor PM3 is greater than the gate potential of the third PMOS transistor PM3, the third PMOS transistor PM3 is turned on, and therefore, the fourth gating submodule 222 is turned on, and the gate potential of the first target driving transistor Qp1 is the potential of the signal interface PAD. In the case where the potential of the signal interface PAD is less than or equal to the potential of the power supply VDD, the source potential of the third PMOS transistor PM3 is less than or equal to the gate potential of the third PMOS transistor PM3, the third PMOS transistor PM3 is turned off, and therefore, the fourth gating submodule 222 is in the off state.

[0108] The source of the fourth PMOS transistor PM4 is the input terminal of the sixth gating submodule 224, the drain of the fourth PMOS transistor PM4 is the output terminal of the sixth gating submodule 224, and the gate of the fourth PMOS transistor PM4 is the control terminal of the sixth gating submodule 224. In the case where the potential of the signal interface PAD is greater than the potential of the power supply VDD, the source potential of the fourth PMOS transistor PM4 is greater than the gate potential of the fourth PMOS transistor PM4, the fourth PMOS transistor PM4 is turned on, therefore, the sixth gating submodule 224 is turned on, and the gate potential of the second target driving transistor Qp2 is the potential of the power supply VDD. In the case where the potential of the signal interface PAD is less than or equal to the potential of the power supply VDD, the source potential of the fourth PMOS transistor PM4 is less than or equal to the gate potential of the fourth PMOS transistor PM4, the fourth PMOS transistor PM4 is turned off, therefore, the sixth gating submodule 224 is in the off state.

[0109] In some embodiments, Figure 6 As shown, the third gating submodule 221 includes: a fifth switching device Q5 and a sixth switching device Q6, wherein the first end of the fifth switching device Q5 is connected to the first end of the sixth switching device Q6 and has a fifth node J5, and the fifth node J5 is suitable for inputting a first control signal, the second end of the fifth switching device Q5 is connected to the second end of the sixth switching device Q6 and has a sixth node J6, and the sixth node J6 is connected to the gate of the first target driving tube Qp1, and the control end of the fifth switching device Q5 is suitable for inputting a power-off signal.

[0110] Specifically, the fifth switch device Q5 is turned on when the power-off signal is at a low level, that is, the fifth switch device Q5 is turned on when the chip is in the digital transmission mode, so the third selection submodule 221 is turned on when the chip is in the digital transmission mode, and the gate potential of the first target drive tube Qp1 is selected as the potential of the first control signal. The fifth switch device Q5 is turned off when the power-off signal is at a high level, and when the potential of the signal interface PAD is less than or equal to the potential of the power supply VDD, the sixth switch device Q6 is turned on, so the third selection submodule 221 is turned on when the power-off signal is received and the potential of the signal interface PAD is less than or equal to the potential of the power supply VDD, and the gate potential of the first target drive tube Qp1 is selected as the potential of the power supply VDD.

[0111] In some embodiments, Figure 7 As shown, the fifth switch device Q5 is a fifth PMOS tube PM5, the sixth switch device Q6 is a third NMOS tube NM3, the source of the third NMOS tube NM3 is the first end of the sixth switch device Q6, the drain of the third NMOS tube NM3 is the second end of the sixth switch device Q6, and the gate of the third NMOS tube NM3 is suitable for connecting to the power supply VDD.

[0112] Specifically, the source of the fifth PMOS transistor PM5 is the first end of the fifth switch device Q5, the drain of the fifth PMOS transistor PM5 is the second end of the fifth switch device Q5, and the gate of the fifth PMOS transistor PM5 is the control end of the fifth switch device Q5.

[0113] When the chip is in digital transmission mode, the enable signal EN is at a high level, the first control signal is a digital pulse signal, and the power-off signal is at a low level, so the fifth PMOS tube PM5 is turned on, and the gate of the first target driving tube Qp1 is connected to the output end of the first NAND gate NAND1, so that the gate potential of the first target driving tube Qp1 is the potential of the first control signal.

[0114] When the chip is in power-down mode, the enable signal EN is at a low level, the first control signal is a first high level signal, the mode selection signal FSE is at a low level, and the power-down signal is at a high level, so the fifth PMOS tube PM5 is turned off. When the potential of the signal interface PAD is greater than the potential of the power supply VDD, the third PMOS tube PM3 is turned on, and the gate potential of the first target driving tube Qp1 is the potential of the signal interface PAD, so the drain potential of the third NMOS tube NM3 is greater than the gate potential of the third NMOS tube NM3, and the third NMOS tube NM3 is in a turned-off state. When the potential of the signal interface PAD is less than or equal to the potential of the power supply VDD, since the power-off signal is still a high-level signal, the fifth PMOS tube PM5 remains in the off state, the third PMOS tube PM3 is turned off, the source of the third NMOS tube NM3 is suitable for accessing the first control signal, so the source of the third NMOS tube NM3 is the potential of the power supply VDD, and because the gate of the third NMOS tube NM3 is suitable for connecting to the power supply VDD, the source and gate potentials of the third NMOS tube NM3 are the same, the third NMOS tube NM3 is in a subthreshold conduction state, the gate of the first target driving tube Qp1 is suitable for accessing the first control signal, and the gate potential of the first target driving tube Qp1 is the potential of the power supply VDD.

[0115] In some embodiments, Figure 8 As shown, the fifth switch device Q5 is a fifth PMOS tube PM5, the sixth switch device Q6 is a third diode D3, the anode of the third diode D3 is the first end of the sixth switch device Q6, and the cathode of the third diode D3 is the second end of the sixth switch device Q6.

[0116] It can be understood that, when the chip is in power-down mode and the potential of the signal interface PAD is less than or equal to the potential of the power supply VDD, the source and gate potentials of the third NMOS tube NM3 are the same, and the third NMOS tube NM3 is in a subthreshold conduction state, which can be equivalent to a diode. Therefore, the third diode D3 can be used to replace the third NMOS tube NM3, thereby further reducing the cost of the interface leakage protection circuit.

[0117] In some embodiments, Figure 6 As shown, the fifth gating submodule 223 includes: a seventh switching device Q7 and an eighth switching device Q8, wherein the first end of the seventh switching device Q7 is connected to the first end of the eighth switching device Q8 and has a seventh node J7, and the seventh node J7 is suitable for inputting the second control signal, the second end of the seventh switching device Q7 is connected to the second end of the eighth switching device Q8, and has an eighth node J8, the eighth node J8 is connected to the gate of the second target driving tube Qp2, and the control end of the eighth switching device Q8 is suitable for inputting the power-off signal.

[0118] Specifically, the seventh switch device Q7 is turned on when the power-off signal is at a low level, that is, the seventh switch device Q7 is turned on when the chip is in the digital transmission mode, so the fifth selection submodule 223 is turned on when the chip is in the digital transmission mode, and the gate potential of the first target drive tube Qp1 is selected as the potential of the second control signal. The seventh switch device Q7 is turned off when the power-off signal is at a high level, and when the potential of the signal interface PAD is less than or equal to the potential of the power supply VDD, the eighth switch device Q8 is turned on, so the fifth selection submodule 223 is turned on when the power-off signal is received and the potential of the signal interface PAD is less than or equal to the potential of the power supply VDD, and the gate potential of the first target drive tube Qp1 is selected as the potential of the power supply VDD.

[0119] In some embodiments, Figure 7 As shown, the seventh switch device Q7 is the sixth PMOS tube PM6, the eighth switch device Q8 is the fourth NMOS tube NM4, the source of the fourth NMOS tube NM4 is the first end of the eighth switch device Q8, the drain of the fourth NMOS tube NM4 is the second end of the eighth switch device Q8, and the gate of the fourth NMOS tube NM4 is suitable for connecting to the power supply VDD.

[0120] Specifically, the source of the sixth PMOS transistor PM6 is the first end of the seventh switch device Q7, the drain of the sixth PMOS transistor PM6 is the second end of the seventh switch device Q7, and the gate of the sixth PMOS transistor PM6 is the control end of the seventh switch device Q7.

[0121] When the chip is in digital transmission mode, the enable signal EN is at a high level, the first control signal is a digital pulse signal, and the power-off signal is at a low level, so the sixth PMOS tube PM6 is turned on, and the gate of the second target driving tube Qp2 is connected to the output end of the second NAND gate NAND2, so that the gate potential of the second target driving tube Qp2 is the potential of the second control signal.

[0122] When the chip is in power-down mode, the enable signal EN is at a low level, the second control signal is a second high level signal, the mode selection signal FSE is at a low level, and the power-down signal is at a high level, so the sixth PMOS tube PM6 is turned off. When the potential of the signal interface PAD is greater than the potential of the power supply VDD, the fourth PMOS tube PM4 is turned on, and the gate potential of the second target driving tube Qp2 is the potential of the signal interface PAD, so the drain potential of the fourth NMOS tube NM4 is greater than the gate potential of the third NMOS tube NM3, and the fourth NMOS tube NM4 is in a turned-off state. When the potential of the signal interface PAD is less than or equal to the potential of the power supply VDD, since the power-off signal is still a high-level signal, the sixth PMOS tube PM6 remains in the off state, the fourth PMOS tube PM4 is turned off, the source of the fourth NMOS tube NM4 is suitable for accessing the first control signal, so the source of the fourth NMOS tube NM4 is the potential of the power supply VDD, and because the gate of the fourth NMOS tube NM4 is suitable for connecting to the power supply VDD, the source and gate potentials of the fourth NMOS tube NM4 are the same, the fourth NMOS tube NM4 is in a subthreshold conduction state, the gate of the second target driving tube Qp2 is suitable for accessing the second control signal, and the gate potential of the second target driving tube Qp2 is the potential of the power supply VDD.

[0123] In some embodiments, Figure 8 As shown, the seventh switch device Q7 is the sixth PMOS tube PM6, the eighth switch device Q8 is the fourth diode D4, the anode of the fourth diode D4 is the first end of the eighth switch device Q8, and the cathode of the fourth diode D4 is the second end of the eighth switch device Q8.

[0124] It can be understood that, when the chip is in power-down mode and the potential of the signal interface PAD is less than or equal to the potential of the power supply VDD, the source and gate potentials of the fourth NMOS tube NM4 are the same, and the fourth NMOS tube NM4 is in a subthreshold conduction state, which can be equivalent to a diode. Therefore, the fourth diode D4 can be used to replace the fourth NMOS tube NM4, thereby further reducing the cost of the interface leakage protection circuit.

[0125] It should be noted that, in the present application, the substrates of all PMOS tubes are connected to the well potential control unit 20 , and the substrates of all NMOS tubes are floated.

[0126] In an optional embodiment, if Fig. 9As shown, the interface leakage protection circuit also includes: a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5 and a seventh PMOS tube PM7, wherein one end of the first resistor R1 is suitable for connecting to the power supply VDD, the other end of the first resistor R1 is connected to the control end of the fourth gating submodule 222, one end of the second resistor R2 is connected to the input end of the fourth gating submodule 222, the other end of the second resistor R2 is connected to the first end of the first gating submodule 211, one end of the third resistor R3 is connected to the control end of the first gating submodule 211, the other end of the third resistor R3 is suitable for connecting to the power supply VDD, the fourth resistor One end of R4 is suitable for connecting to the power supply VDD, the other end of the fourth resistor R4 is connected to the control end of the sixth selection submodule 224, one end of the fifth resistor R5 is suitable for connecting to the signal interface PAD, the other end of the fifth resistor R5 is respectively connected to the second target drive tube Qp2 and the fourth target drive tube Qn2, the gate of the seventh PMOS tube PM7 is suitable for connecting to the power supply VDD, the source of the seventh PMOS tube PM7 is connected to the substrate of the second target drive tube Qp2, the drain of the seventh PMOS tube PM7 is connected to the substrate of the first target drive tube Qp1, and the substrate of the seventh PMOS tube PM7 is respectively connected to the source and drain of the seventh PMOS tube PM7. The first resistor R1 to the fifth resistor R5 are used to filter the electrical signal in the interface anti-leakage protection circuit. The seventh PMOS transistor PM7 can be equivalent to a capacitor. When the circuit is running stably, the seventh PMOS transistor PM7 is in an open circuit state and will not affect the well potential of the first driving tube Qp. When the power supply VDD is unstable, the seventh PMOS transistor PM7 filters the power supply VDD and provides the filtered power supply VDD to the substrate of the first driving tube Qp.

[0127] It should be noted that, in actual applications, filtering is not limited to the first resistor R1 to the fifth resistor R5, and filtering can also be performed using a filtering circuit composed of resistors and capacitors. Since the seventh PMOS tube PM7 can be equivalent to a capacitor, a capacitor can also be used to replace the seventh PMOS tube PM7. One end of the capacitor is suitable for connecting to the power supply VDD, and the other end of the capacitor is connected to the substrate of the first driving tube Qp. No specific limitation is made here.

[0128] The technical solution of the present application is further described in detail below in conjunction with specific implementation methods:

[0129] like Figure 7 As shown, the working principle of the interface leakage protection circuit includes the following steps:

[0130] When the chip is in the digital transmission mode, the enable signal EN and the mode selection signal FSE are both at high level, so the power-off signal is at low level, and the second PMOS tube PM2, the fifth PMOS tube PM5 and the sixth PMOS tube PM6 are turned on. The second PMOS tube PM2 is turned on to select the well potential of the first target drive tube Qp1 and the second target drive tube Qp2 as the potential of the power supply VDD. The fifth PMOS tube PM5 is turned on to select the gate potential of the first target drive tube Qp1 as the potential of the first control signal, that is, the gate potential of the first target drive tube Qp1 is selected as the potential opposite to the digital signal. The sixth PMOS tube PM6 is turned on to select the gate potential of the second target drive tube Qp2 as the potential of the second control signal, that is, the gate potential of the second target drive tube Qp2 is selected as the potential opposite to the pull-up signal PU.

[0131] Further, such as Fig.10 and 11 As shown, when the chip is in digital transmission mode, the well potentials of the first target driver tube Qp1 and the second target driver tube Qp2 change with the potential of the power supply VDD, and the gate potential of the first target driver tube Qp1 is a digital pulse signal opposite to the digital input pulse A. When the gate potential of the first target driver tube Qp1 is at a low level, the first target driver tube Qp1 is turned on, and the signal interface PAD outputs a high level signal. When the gate potential of the first target driver tube Qp1 is at a high level, the first target driver tube Qp1 is turned off, and the signal interface PAD outputs a low level. Fig.11 As shown, when the pull-down signal PD is at a low level, the fourth target driving tube Qn2 is in an off state and will not affect the output voltage of the signal interface PAD. When the pull-down signal PD is at a high level, the fourth target driving tube Qn2 is turned on and the output voltage of the signal interface PAD is pulled to 0. The gate potential of the second target driving tube Qp2 is a signal opposite to the pull-up signal PU. When the pull-up signal PU is at a high level, the second target driving tube Qp2 is turned on and the output voltage of the signal interface PAD is pulled to the potential of the power supply VDD. When the pull-up signal PU is at a low level, the second target driving tube Qp2 is turned off and the output voltage of the signal interface PAD is not changed.

[0132] Therefore, when the chip is in the digital transmission mode, the interface leakage protection circuit of this embodiment can realize various functions of the chip without affecting the normal operation of the chip.

[0133] When the chip is in the power-down mode, the enable signal EN and the mode selection signal FSE are both at low levels, so the first control signal, the second control signal and the power-down signal are at high levels, and the second PMOS tube PM2, the fifth PMOS tube PM5 and the sixth PMOS tube PM6 are turned off. When the chip is in the power-down mode and the potential of the signal interface PAD is greater than the potential of the power supply VDD, the first PMOS tube PM1, the third PMOS tube PM3 and the fourth PMOS tube PM4 are turned on, and the well potential and the gate potential of the first target drive tube Qp1 and the second target drive tube Qp2 are pulled to the potential of the signal interface PAD, the first target drive tube Qp1 and the second target drive tube Qp2 will not enter the subthreshold conduction state, and the parasitic path between the signal interface PAD and the power supply VDD is cut off to avoid the current of the signal interface PAD from being input into the power supply VDD, thereby reducing the leakage current. When the chip is in power-down mode and the potential of the signal interface PAD is equal to the potential of the power supply VDD, the third NMOS tube NM3 and the fourth NMOS tube NM4 are turned on, the gate potential of the first target drive tube Qp1 and the second target drive tube Qp2 is the potential of the power supply VDD, the first NMOS tube NM1 and the second NMOS tube NM2 constitute a PNP triode, and the well potential of the first target drive tube Qp1 and the second target drive tube Qp2 is the potential of the power supply VDD. When the chip is in power-down mode and the potential of the signal interface PAD is less than the potential of the power supply VDD, the second NMOS tube NM2 is turned on, the well potential of the first target drive tube Qp1 and the second target drive tube Qp2 is the potential of the power supply VDD, the third NMOS tube NM3 and the fourth NMOS tube NM4 are turned on, and the gate potential of the first target drive tube Qp1 and the second target drive tube Qp2 is the potential of the power supply VDD.

[0134] Further, such as Fig.12 As shown, in the power-off mode, when the potential of the signal interface PAD is maintained at 3V and the potential of the power supply VDD decreases from 5.5V to 3V, since the potential of the signal interface PAD is less than the potential of the power supply VDD, the well potential and the gate potential of the first target driving tube Qp1 and the second target driving tube Qp2 follow the potential of the power supply VDD, and there is a voltage difference of less than 0.2V with the potential of the power supply VDD; when the potential of the power supply VDD decreases from 3V to 0V, since the potential of the signal interface PAD is greater than the potential of the power supply VDD, the well potential and the gate potential of the first target driving tube Qp1 and the second target driving tube Qp2 follow the potential of the signal interface PAD to 3V, and the leakage current of the power supply VDD and the leakage current of the signal interface PAD fluctuate within the range of plus or minus 2.4nA.

[0135] like Fig.13As shown, in the power-off mode, when the potential of the power supply VDD is maintained at 3V and the potential of the signal interface PAD decreases from 5.5V to 3V, the chip is in fault-tolerant mode. Since the potential of the signal interface PAD is greater than the potential of the power supply VDD, the well potential and the gate potential of the first target driver tube Qp1 and the second target driver tube Qp2 follow the potential of the signal interface PAD; when the potential of the signal interface PAD decreases from 3V to 0V, since the potential of the signal interface PAD is less than or equal to the potential of the power supply VDD, the well potential and the gate potential of the first target driver tube Qp1 and the second target driver tube Qp2 follow the potential of the power supply VDD, and there is a voltage difference of less than 0.2V with the potential of the power supply VDD, and the leakage current of the power supply VDD and the leakage current of the signal interface PAD fluctuate within the range of plus or minus 2.6nA.

[0136] like Fig.14 As shown, in the fail-safe mode of the chip, the potential of the power supply VDD drops to 0V, and the potential of the signal interface PAD drops from 5.5V to 0V. Since the potential of the signal interface PAD is greater than the potential of the power supply VDD, the well potential and the gate potential of the first target driving tube Qp1 and the second target driving tube Qp2 follow the potential of the signal interface PAD, and the leakage current of the power supply VDD and the leakage current of the signal interface PAD fluctuate within the range of 43nA.

[0137] like Fig.15 As shown, when the signal interface PAD is a transmission port for analog signals, in the process that the working potential of the power supply VDD is 5V and the potential of the signal interface PAD drops from 5.5V to 0V, when the potential of the signal interface PAD drops from 5.5V to 5V, since the potential of the signal interface PAD is greater than the potential of the power supply VDD, the well potential and the gate potential of the first target driving tube Qp1 and the second target driving tube Qp2 follow the potential of the signal interface PAD; when the potential of the signal interface PAD drops from 5V to 0V, since the potential of the signal interface PAD is less than or equal to the potential of the power supply VDD, the well potential and the gate potential of the first target driving tube Qp1 and the second target driving tube Qp2 follow the potential of the power supply VDD, and there is a voltage difference of less than 0.2V with the potential of the power supply VDD, and the leakage current of the power supply VDD and the leakage current of the signal interface PAD fluctuate within the range of 19nA.

[0138] In the above embodiment, by selecting the gate potential and the well potential to be high level, the parasitic path between the signal interface and the power supply is cut off, which can effectively reduce the leakage current of the power supply and the signal interface, thereby further reducing the static power consumption of the chip.

[0139] In summary, according to an embodiment of the present invention, the interface leakage protection circuit includes a driving unit and a potential control unit. When the chip is in a power-off mode, the potential control unit selects the well potential and gate potential of each first driving tube as the larger value of the potential of the signal interface and the potential of the power supply, so that the gate potential and well potential of each first driving tube are always at a high potential, so that the first driving tube will not enter a subthreshold conduction state, and the parasitic path between the signal interface and the power supply is cut off to avoid the current of the signal interface from being input into the power supply, thereby reducing the leakage current and further reducing the static power consumption of the chip; and the well potential is controllable and is always at a higher potential, which can effectively prevent carriers from entering the base region, increase the difficulty of triggering the latch effect, and obtain an avalanche negative resistance hysteresis maintenance channel between the signal interface and the power supply, thereby improving the anti-static ability of the chip and thus improving the reliability of the chip.

[0140] Corresponding to the above embodiment, the embodiment of the present invention further provides a chip. Fig.16 As shown, the chip 200 includes the interface leakage protection circuit 100 of any of the aforementioned embodiments.

[0141] It should be noted that the chip of this embodiment may be a chip in an air conditioner remote controller or a chip in a home appliance, and no specific limitation is made here.

[0142] According to the chip of the embodiment of the present invention, by adopting the above-mentioned interface leakage protection circuit, when the chip is in the power-off mode, the gate potential and the well potential of each first driving tube are pulled to a high potential through the potential control unit, thereby cutting off the parasitic path between the signal interface and the power supply, avoiding the current of the signal interface from being input into the power supply, thereby reducing the leakage current, and further reducing the static power consumption of the chip, and the well potential is controllable, thereby improving the reliability of the chip.

[0143] Corresponding to the above embodiment, an embodiment of the present invention further provides an electronic device. Fig.17 As shown, the electronic device 300 includes the aforementioned chip 200 .

[0144] It should be noted that when the chip in this embodiment is a chip in an air conditioner remote controller, the electronic device is an air conditioner remote controller; when the chip in this embodiment is a chip in a home appliance, the electronic device in this embodiment is a home appliance.

[0145] According to the electronic device of the embodiment of the present invention, by adopting the above-mentioned chip, when the chip is in the power-off mode, the gate potential and the well potential of each first driving tube are pulled to a high potential through the potential control unit, thereby cutting off the parasitic path between the signal interface and the power supply, avoiding the current of the signal interface from being input into the power supply, thereby reducing the leakage current, and further reducing the static power consumption of the chip, and the well potential is controllable, thereby improving the reliability of the chip.

[0146] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0147] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0148] In addition, the terms "first", "second", etc. used in the embodiments of the present invention are only used for descriptive purposes and should not be understood as indicating or implying relative importance, or implicitly indicating the number of technical features indicated in the present embodiment. Therefore, the features defined by the terms "first", "second", etc. in the embodiments of the present invention can explicitly or implicitly indicate that the embodiment includes at least one of the features. In the description of the present invention, the word "multiple" means at least two or two or more, such as two, three, four, etc., unless otherwise clearly and specifically defined in the embodiments.

[0149] In the present invention, unless otherwise clearly specified or limited in the embodiments, the terms "installed", "connected", "connected" and "fixed" etc. in the embodiments should be understood in a broad sense. For example, the connection can be a fixed connection, a detachable connection, or an integrated connection. It can be understood that it can also be a mechanical connection, an electrical connection, etc.; of course, it can also be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal connection of two elements, or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to the specific implementation situation.

[0150] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. An interface anti-leakage protection circuit, It is characterized in that include: A driving unit, the driving unit comprising a plurality of first driving tubes, a first end of each of the first driving tubes being suitable for connecting to a power supply, and a second end of each of the first driving tubes being suitable for connecting to a signal interface; A potential control unit, the potential control unit is respectively connected to the substrate and the gate of each of the first driving tubes, and the potential control unit is configured to select the well potential and the gate potential of each of the first driving tubes to the larger value of the potential of the signal interface and the potential of the power supply when the chip is in a power-off mode.

2. The interface anti-leakage protection circuit according to claim 1, It is characterized in that The potential control unit comprises: A well potential control module, the well potential control module is connected to the substrate of each of the first driving tubes, so as to select the well potential of each of the first driving tubes to be the larger value between the potential of the signal interface and the potential of the power supply when the chip is in a power-off mode; A gate potential control module, wherein the gate potential control module is connected to the gate of each of the first driving tubes so as to select the gate potential of each of the first driving tubes to be the larger value between the potential of the signal interface and the potential of the power supply when the chip is in a power-off mode.

3. The interface anti-leakage protection circuit according to claim 2, It is characterized in that The well potential control module comprises: a first gating submodule, wherein a first end of the first gating submodule is suitable for connecting to the signal interface, a second end of the first gating submodule is connected to a substrate of each of the first driving tubes, a control end of the first gating submodule is suitable for connecting to the power supply, and the first gating submodule is turned on when the potential of the signal interface is greater than the potential of the power supply, so as to gating the well potential of each of the first driving tubes to the potential of the signal interface; A second gating submodule, wherein the first end of the second gating submodule is suitable for connecting to the power supply, the second end of the second gating submodule is connected to the substrate of each of the first driving tubes, the control end of the second gating submodule is suitable for inputting a power-off signal, and the second gating submodule is turned on when receiving the power-off signal and the potential of the signal interface is less than or equal to the potential of the power supply, so as to select the well potential of each of the first driving tubes to be the potential of the power supply.

4. The interface anti-leakage protection circuit according to claim 3, It is characterized in that The well potential control module also includes: A first inverter, wherein an input end of the first inverter is adapted to access a mode selection signal, an output end of the first inverter is connected to a control end of the second gating submodule, and the first inverter is configured to generate the power-off signal according to the mode selection signal.

5. The interface anti-leakage protection circuit according to claim 3, It is characterized in that The first gating submodule includes: a first switching device and a second switching device, wherein the first end of the first switching device is connected to the first end of the second switching device and has a first node, the first node is suitable for connecting to the signal interface, the second end of the first switching device is connected to the second end of the second switching device and has a second node, the second node is connected to the substrate of each of the first driving tubes, and the control end of the first switching device is suitable for connecting to the power supply.

6. The interface anti-leakage protection circuit according to claim 5, It is characterized in that The first switch device is a first PMOS tube, the second switch device is a first NMOS tube, the source of the first NMOS tube is the first end of the second switch device, the drain of the first NMOS tube is the second end of the second switch device, and the gate and source of the first NMOS tube are connected.

7. The interface anti-leakage protection circuit according to claim 5, It is characterized in that The first switch device is a first PMOS tube, the second switch device is a first diode, the anode of the first diode is the first end of the second switch device, and the cathode of the first diode is the second end of the second switch device.

8. The interface anti-leakage protection circuit according to claim 3, It is characterized in that The second gating submodule includes: a third switch device and a fourth switch device, wherein the first end of the third switch device is connected to the first end of the fourth switch device and has a third node, and the third node is suitable for connecting the power supply, the second end of the third switch device is connected to the second end of the fourth switch device and has a fourth node, and the fourth node is connected to the substrate of each of the first driving tubes, and the control end of the third switch device is suitable for inputting the power-off signal.

9. The interface anti-leakage protection circuit according to claim 8, It is characterized in that The third switch device is a second PMOS tube, the fourth switch device is a second NMOS tube, the source of the second NMOS tube is the first end of the fourth switch device, the drain of the second NMOS tube is the second end of the fourth switch device, and the gate and source of the second NMOS tube are connected.

10. The interface anti-leakage protection circuit according to claim 8, It is characterized in that The third switch device is a second PMOS tube, the fourth switch device is a second diode, the anode of the second diode is the first end of the fourth switch device, and the cathode of the second diode is the second end of the fourth switch device.

11. The interface leakage protection circuit according to any one of claims 3 to 10, It is characterized in that The second gating submodule is also turned on when the chip is in a digital transmission mode, so as to gating the well potential of each of the first driving tubes to the potential of the power supply.

12. The interface anti-leakage protection circuit according to any one of claims 3 to 10, It is characterized in that There are two first drive tubes, namely a first target drive tube and a second target drive tube, and the gate potential control module includes: a third gating submodule, wherein the input end of the third gating submodule is suitable for inputting the first control signal, the control end of the third gating submodule is suitable for inputting the power-off signal, the output end of the third gating submodule is connected to the gate of the first target driving tube, and the third gating submodule is turned on when receiving the power-off signal and the potential of the signal interface is less than or equal to the potential of the power supply, so as to gating the gate potential of the first target driving tube to the potential of the power supply; a fourth gating submodule, wherein the input end of the fourth gating submodule is suitable for connecting to the signal interface, the control end of the fourth gating submodule is suitable for connecting to the power supply, the output end of the fourth gating submodule is connected to the gate of the first target driving tube, and the fourth gating submodule is turned on when the potential of the signal interface is greater than the potential of the power supply, so as to gating the gate potential of the first target driving tube to the potential of the signal interface; a fifth gating submodule, wherein the input end of the fifth gating submodule is suitable for inputting a second control signal, the control end of the fifth gating submodule is suitable for inputting the power-off signal, the output end of the fifth gating submodule is connected to the gate of the second target driving tube, and the fifth gating submodule is turned on when receiving the power-off signal and the potential of the signal interface is less than or equal to the potential of the power supply, so as to gating the gate potential of the second target driving tube to the potential of the power supply; A sixth gating submodule, wherein the input end of the sixth gating submodule is suitable for connecting to the signal interface, the control end of the sixth gating submodule is suitable for connecting to the power supply, the output end of the sixth gating submodule is connected to the gate of the second target driving tube, and the sixth gating submodule is turned on when the potential of the signal interface is greater than the potential of the power supply, so as to select the gate potential of the second target driving tube to the potential of the signal interface.

13. The interface anti-leakage protection circuit according to claim 12, It is characterized in that The fourth gating submodule and the sixth gating submodule are respectively a third PMOS transistor and a fourth PMOS transistor.

14. The interface anti-leakage protection circuit according to claim 12, It is characterized in that The third gating submodule includes: a fifth switching device and a sixth switching device, wherein the first end of the fifth switching device is connected to the first end of the sixth switching device and has a fifth node, and the fifth node is suitable for inputting the first control signal, the second end of the fifth switching device is connected to the second end of the sixth switching device and has a sixth node, and the sixth node is connected to the gate of the first target driving tube, and the control end of the fifth switching device is suitable for inputting the power-off signal.

15. The interface anti-leakage protection circuit according to claim 14, It is characterized in that The fifth switching device is a fifth PMOS tube, the sixth switching device is a third NMOS tube, the source of the third NMOS tube is the first end of the sixth switching device, the drain of the third NMOS tube is the second end of the sixth switching device, and the gate of the third NMOS tube is suitable for connecting to the power supply.

16. The interface anti-leakage protection circuit according to claim 14, It is characterized in that The fifth switch device is a fifth PMOS tube, the sixth switch device is a third diode, the anode of the third diode is the first end of the sixth switch device, and the cathode of the third diode is the second end of the sixth switch device.

17. The interface anti-leakage protection circuit according to claim 12, It is characterized in that The fifth gating submodule includes: a seventh switching device and an eighth switching device, wherein the first end of the seventh switching device is connected to the first end of the eighth switching device and has a seventh node, and the seventh node is suitable for inputting the second control signal, the second end of the seventh switching device is connected to the second end of the eighth switching device and has an eighth node, and the eighth node is connected to the gate of the second target driving tube, and the control end of the eighth switching device is suitable for inputting the power-off signal.

18. The interface anti-leakage protection circuit according to claim 17, It is characterized in that The seventh switching device is a sixth PMOS tube, the eighth switching device is a fourth NMOS tube, the source of the fourth NMOS tube is the first end of the eighth switching device, the drain of the fourth NMOS tube is the second end of the eighth switching device, and the gate of the fourth NMOS tube is suitable for connecting to the power supply.

19. The interface anti-leakage protection circuit according to claim 17, It is characterized in that The seventh switch device is a sixth PMOS tube, the eighth switch device is a fourth diode, the anode of the fourth diode is the first end of the eighth switch device, and the cathode of the fourth diode is the second end of the eighth switch device.

20. The interface anti-leakage protection circuit according to claim 12, It is characterized in that The third gating submodule and the fifth gating submodule are also turned on when the chip is in the digital transmission mode.

21. The interface anti-leakage protection circuit according to claim 1, It is characterized in that The first driving tube is a PMOS.

22. The interface anti-leakage protection circuit according to claim 1, It is characterized in that The driving unit further includes a plurality of second driving tubes, which are arranged corresponding to the first driving tubes, wherein a first end of each of the second driving tubes is suitable for connecting to the signal interface, and a second end of each of the second driving tubes is grounded.

23. The interface anti-leakage protection circuit according to claim 22, It is characterized in that The second driving transistor is an NMOS.

24. A chip, It is characterized in that It comprises an interface leakage protection circuit according to any one of claims 1-23.

25. An electronic device, It is characterized in that Comprising a chip according to claim 24.

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