Pin multiplexing circuit and network equipment

Abstract

The invention discloses a pin multiplexing circuit and network equipment, and relates to the technical field of network equipment, and the pin multiplexing circuit comprises a logic device, a processor, a first function module and a second function module; wherein the logic device comprises a target function pin, the first function module comprises a first function pin corresponding to the target function pin, the second function module comprises a second function pin corresponding to the target function pin, the first function pin of the first function module is connected with the first end of the processor, and the second function pin of the second function module is connected with the second end of the processor. The second function pin of the second function module is connected with the second end of the processor, the third end of the processor is connected with the control signal, and the fourth end of the processor is connected with the target function pin. According to the technical scheme, the target function pin of the logic device can be subjected to multiplexing design, so that the demand for the number of the pins of the logic device is met, the use cost of the logic device can be reduced, and the wiring pressure of the logic device is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of network equipment, and in particular to a pin multiplexing circuit and a network equipment. Background Art

[0002] As a semi-customized integrated circuit, logic devices have the advantages of flexible programming, fast response and high integration. They can be used as an important hub for information exchange between upper-level systems and lower-level devices, so they are increasingly widely used in many fields. However, with the promotion of logic devices and the increasing functional integration, the number of pins required by logic devices has also increased.

[0003] In order to meet the demand for the number of logic device pins, related technologies generally package multiple logic devices or use larger logic devices regardless of cost, which not only causes waste of resources but also increases the wiring pressure of the circuit. Summary of the invention

[0004] The present application provides a pin multiplexing circuit and a network device to at least solve the problem of waste of resources and increased wiring pressure caused by packaging multiple logic devices or selecting larger logic devices regardless of cost in the related art.

[0005] In a first aspect, the present application provides a pin multiplexing circuit, comprising: a logic device, a processor, a first functional module and a second functional module; wherein: the logic device comprises a target functional pin, the first functional module comprises a first functional pin corresponding to the target functional pin, and the second functional module comprises a second functional pin corresponding to the target functional pin;

[0006] The first function pin of the first function module is connected to the first end of the processor, and is used to transmit the first function signal to the processor and receive the first result data returned by the processor;

[0007] The second function pin of the second function module is connected to the second end of the processor, and is used to transmit the second function signal to the processor and receive the second result data returned by the processor;

[0008] The third terminal of the processor is connected to the control signal;

[0009] The fourth end of the processor is connected to the target function pin, and is used to send the received first function signal to the logic device when the control signal is in the first state, and accept the first result data returned by the logic device, so as to return the first result to the first function module; and is also used to send the received second function signal to the logic device when the control signal is in the second state, and accept the second result data returned by the logic device, so as to return the second result to the second function module.

[0010] In a second aspect, the present application provides a network device comprising any one of the above-mentioned pin multiplexing circuits.

[0011] Through the pin multiplexing circuit and network equipment provided by the present application, the target function pin is multiplexed so that the target function pin can be used as the first function pin to transmit the first function signal, or as the second function pin to transmit the second function signal. The processor switches the actual function signal transmitted by the target function pin according to the received control signal, and finally realizes the multiplexing of the target function pin. Therefore, the demand for the number of logic device pins can be met to solve the problem of waste of resources and increased wiring pressure caused by packaging multiple logic devices or selecting larger logic devices regardless of cost in the related technology, thereby reducing the cost of logic devices and reducing the pressure on wiring logic devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0013] Figure 1 A schematic diagram of the hardware architecture of this application example;

[0014] Figure 2 The structure of the pin multiplexing circuit provided in this application is shown as follows Figure 1 ;

[0015] Figure 3 The structure of the pin multiplexing circuit provided in this application is shown as follows Figure 2 ;

[0016] Figure 4 The structure of the pin multiplexing circuit provided in this application is shown as follows Figure 3 ;

[0017] Figure 5 The structure of the pin multiplexing circuit provided in this application is shown as follows Figure 4 ;

[0018] Figure 6 The structure of the pin multiplexing circuit provided in this application is shown as follows Figure 5 ;

[0019] Figure 7 The structure of the pin multiplexing circuit provided in this application is shown as follows Figure 6 ;

[0020] Figure 8 The structure of the pin multiplexing circuit provided in this application is shown as follows Figure 7 ;

[0021] Fig. 9 The structure of the pin multiplexing circuit provided in this application is shown as follows Figure 8 ;

[0022] Fig.10 The structure of the pin multiplexing circuit provided in this application is shown as follows Figure 9 .

[0023] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0024] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0025] It should be noted that, in the description of this application, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in this application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0026] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0027] Logic devices can serve as an important hub for information exchange between upper-level systems and lower-level devices, and can be used more and more widely in multiple fields. However, with the promotion of logic devices and the increasing functional integration, the number of pins required by logic devices has also increased. In order to meet the demand for the number of logic device pins, related technologies generally package multiple logic devices or use larger logic devices regardless of cost, which not only wastes resources but also increases the wiring pressure of the circuit.

[0028] Figure 1 A schematic diagram of the hardware architecture of this application example, such as Figure 1As shown, the pin multiplexing circuit provided in the embodiment of the present application mainly includes four parts, namely a logic device, a processing device, a first functional module and a second functional module. Among them, the logic device can be installed on a circuit board as chip 1, the processing device can be installed on a circuit board as chip 2, the first functional module can be integrated on chip 3, and chip 3 is installed on a circuit board, and the second functional module can be integrated on chip 4, and chip 4 is installed on a circuit board. Among them, chip 1 and chip 2 are connected through the target function pin, chip 2 and chip 3 are connected through the first function pin, and chip 2 and chip 4 are connected through the second function pin.

[0029] Depend on Figure 1 It can be seen that the processor can receive the first function signal sent by the first function module, and can also receive the second function signal sent by the second function module. The processor switches the first function signal and the second function signal so that the processor transmits the first function signal or the second function signal to the logic device, and finally realizes the multiplexing of the target function pin.

[0030] Figure 2 The structure of the pin multiplexing circuit provided in this application is shown as follows Figure 1 ,like Figure 2 As shown, it includes: a logic device, a processor, a first functional module and a second functional module; wherein: the logic device includes a target functional pin, the first functional module includes a first functional pin corresponding to the target functional pin, and the second functional module includes a second functional pin corresponding to the target functional pin;

[0031] The first function pin of the first function module is connected to the first end of the processor, and is used to transmit the first function signal to the processor and receive the first result data returned by the processor;

[0032] The second function pin of the second function module is connected to the second end of the processor, and is used to transmit the second function signal to the processor and receive the second result data returned by the processor;

[0033] The third terminal of the processor is connected to the control signal;

[0034] The fourth end of the processor is connected to the target function pin, and is used to send the received first function signal to the logic device when the control signal is in the first state, and accept the first result data returned by the logic device, so as to return the first result to the first function module; and is also used to send the received second function signal to the logic device when the control signal is in the second state, and accept the second result data returned by the logic device, so as to return the second result to the second function module.

[0035] Combined with the scenario example, the logic function of the logic device can be edited according to the preset requirements. The logic device may include multiple function pins, and a target function pin can be determined from the preset function pins, and the determined target function pin can be multiplexed. Specifically, the function signal that can be transmitted by the target function pin, such as the first function signal and the second function signal, can be determined. Accordingly, the target function pin can be multiplexed as the first function pin and the second function pin, respectively. Among them, the first function pin is used to transmit the first function signal, and the second function pin is used to transmit the second function signal. Among them, the first function signal can be a function signal that can be originally transmitted by the target function pin, and the second function signal can be a preset function signal. The first function signal can be output by the corresponding first function module, and the second function signal can be output by the corresponding second function module.

[0036] The processor can be selected as a microcontroller unit (MCU for short), and the control signal received by the processor can be a selection signal select, and the selection signal includes two states, namely a first state and a second state. When the processor receives the selection signal of the first state, the target function pin is used as the first function pin, the first function signal output by the first function module is received, and the first function signal is transmitted to the logic device, and the logic device can output the first result data based on the first function signal, and then the processor receives the first result data output by the logic device, and transmits the first result data to the first function module. When the processor receives the selection signal of the second state, the target function pin is used as the second function pin, the second function signal output by the second function module is received, and the second function signal is transmitted to the logic device, and the logic device can output the second result data based on the second function signal, and then the processor receives the second result data output by the logic device, and transmits the second result data to the second function module.

[0037] Based on the circuit provided in this example, the target functional pins of the logic device can be reused to meet the demand for the number of logic device pins, which can reduce the cost of using the logic device and reduce the pressure on the wiring of the logic device.

[0038] Optionally, the logic device is a complex programmable logic device;

[0039] Accordingly, the target function pins include joint test workgroup pins and serial peripheral interface pins.

[0040] In combination with the scenario example, the logic device is a complex programmable logic device (CPLD), which includes multiple functional pins, such as the Joint Test Action Group (JTAG) and the Serial Peripheral Interface (SPI). Among them, JTAG is mainly used for internal chip testing, and SPI is a synchronous peripheral interface that allows the microcontroller to communicate with various peripheral devices in serial mode to exchange information.

[0041] Based on the circuit provided in this example, the logic device is determined to be CPLD, which can improve the flexibility and programmability of the circuit.

[0042] Optional, Figure 3 The structure of the pin multiplexing circuit provided in this application is shown as follows Figure 2 ,like Figure 3 As shown, the target functional pins are the joint test working group pins;

[0043] Correspondingly, the first functional module is an upper system module, the first functional signal is general information or online upgrade information, the second functional module is an offline update module, and the second functional signal is offline update information.

[0044] Combined with the scenario example, when the target functional pin is a JTAG pin, the multiplexing design of the JTAG pin includes connecting the JTAG signal of the CPLD to the upper system module, connecting the JTAG signal of the CPLD to the offline update module, and information interaction between the CPLD and the upper system. The upper system module includes but is not limited to the baseboard management controller (Baseboard Management Controller, referred to as BMC) and the central processing unit (Central Processing Unit, referred to as CPU). There are two types of first functional signals sent by the upper system module, namely general information and online upgrade information. General information includes basic status information, verification information or control information, etc. When general information is transmitted between the upper system module and the CPLD, the JTAG pin between the processor MCU and the upper system module can be defined as: Load signal, clock signal (clock, referred to as CLK), data input Data-In and data output Data-Out. Among them, the Load signal is used to control the storage and reading operations of data in the digital circuit. It is a control signal used to indicate when to write data to a storage element (such as a trigger) or read data from a storage element; a clock signal is a periodically changing signal used to synchronize the operation of various parts in a digital circuit to ensure that data is processed and transmitted at the right time; data input Data-In refers to the signal used to input data in a system; data output Data-Out refers to the signal used to output data in digital circuit design.

[0045] When the upper system module needs to upgrade the CPLD, the JTAG pins between the processor MCU and the upper system module can be defined as: Test Mode Select (TMS), Test Clock Input (TCK), Test Data In (TDI) and Test Data Out (TDO). The offline update information output by the offline update module is used to update the CPLD offline. The JTAG pins between the processor MCU and the offline update module can be defined as: TMS, TCK, TDI and TDO. Among them, TCK is used to synchronize the operation on the JTAG interface. By sampling and updating the data on the rising or falling edge of TCK, the synchronous transmission of data on the JTAG interface is realized; TMS is used to control the state machine transition of JTAG. By inputting different values ​​for TMS on each TCK clock cycle, the state of the JTAG state machine can be changed, thereby selecting different test or operation modes; TDI is the channel for sending data to the device under test. By inputting data to TDI on each clock cycle of TCK, test data, instructions or configuration information can be sent to the device under test; TDO is the channel for receiving data from the device under test. By reading data from TDO on each clock cycle of TCK, the test response, status information or output data of the device under test can be obtained. The JTAG pin includes multiple signal transmission paths, including a first signal transmission path defined as TMS or Load, a second signal transmission path defined as TCK or CLK, a third signal transmission path defined as TDI or Data-In, and a fourth signal transmission path defined as TDO or Data-Out.

[0046] Based on the circuit provided in this example, the multiplexing design of the JTAG pin of the CPLD can be completed.

[0047] Optional, Figure 4 The structure of the pin multiplexing circuit provided in this application is shown as follows Figure 3 ,like Figure 4 As shown, the complex programmable logic device also includes a first control interface;

[0048] The control end of the upper system module is connected to the first control interface of the complex programmable logic device, and is used to send a first function signal to the controller as general information when the first control interface is in a low level state, and to send a first function signal to the controller as online upgrade information when the first control interface is in a high level state.

[0049] Combined with the scenario example, since the upper-layer system module can output two first function signals, it can be determined whether the CPLD needs to be upgraded, thereby determining whether to transmit general information or online upgrade information to the CPLD. Specifically, when JTAG-En at the first control interface is at a low level, it can be determined that the CPLD does not need to be upgraded at this time, so the upper-layer system module outputs general information at this time. Specifically, the upper-layer system module transmits the output general information to the processor through the first signal transmission path, the second signal transmission path, and the third signal transmission path, and the processor transmits the general information to the CPLD through the first signal transmission path, the second signal transmission path, and the third signal transmission path. The CPLD returns the first processing result to the processor through the fourth signal transmission path, and the processor returns the first processing result to the upper-layer system module through the fourth signal transmission path.

[0050] When JTAG-En at the first control interface is at a high level, it can be determined that the CPLD needs to be upgraded at this time, so the upper system module outputs online upgrade information at this time, and the online upgrade information can be the upgrade mirror information output by the upper system module. Specifically, the upper system module transmits the output upgrade mirror information to the processor through the first signal transmission path, the second signal transmission path, and the third signal transmission path, and the processor transmits the upgrade mirror information to the CPLD through the first signal transmission path, the second signal transmission path, and the third signal transmission path, and the CPLD returns the first processing result to the processor through the fourth signal transmission path, and the processor returns the first processing result to the upper system module through the fourth signal transmission path.

[0051] Similarly, the offline update module transmits the output offline update information to the processor through the first signal transmission path, the second signal transmission path and the third signal transmission path, the processor transmits the offline update information to the CPLD through the first signal transmission path, the second signal transmission path and the third signal transmission path, the CPLD returns the second processing result to the processor through the fourth signal transmission path, and the processor then returns the second processing result to the upper system module through the fourth signal transmission path.

[0052] Based on the circuit provided in this example, the output information can be determined by judging the status information of JTAG-En.

[0053] Optional, Figure 5 The structure of the pin multiplexing circuit provided in this application is shown as follows Figure 4 ,like Figure 5 As shown, the circuit further includes: a first switch module K1 and a second switch module K2;

[0054] A first end of the first switch module K1 is connected to a high level, and a second end of the first switch module K1 is grounded;

[0055] A first end of the second switch module K2 is connected to a high level, and a second end of the second switch module K2 is grounded;

[0056] The first control interface of the complex programmable logic device is connected to the second end of the first switch module K1, and is in a low level state when the path between the first end and the second end of the first switch module K1 is disconnected; and is in a high level state when the path between the first end and the second end of the first switch module K1 is connected;

[0057] The third end of the controller is connected to the second end of the second switch module K2. When the path between the first end and the second end of the second switch module K2 is disconnected, the received control signal is a control signal of the first state; when the path between the first end and the second end of the second switch module K2 is connected, the received control signal is a control signal of the second state.

[0058] Combined with the scenario example, the default state of the first switch module K1 and the second switch module K2 is disconnected, that is, the path between the first end and the second end is not conductive. Figure 5 It can be seen that when the path between the first end and the second end of the first switch module K1 is not conductive, the JTAG-En at the first control interface of the CPLD is at a low level, and when the path between the first end and the second end of the first switch module K1 is conductive, the JTAG-En at the first control interface of the CPLD is at a high level.

[0059] When the path between the first end and the second end of the second switch module K2 is not conductive, the control signal received by the MCU is a low level, that is, a control signal of the first state, and when the path between the first end and the second end of the second switch module K2 is conductive, the control signal received by the MCU is a high level, that is, a control signal of the second state. Specifically, a jumper cap can be selected to short-circuit the first end and the second end of the first switch module K1, and the first end and the second end of the second switch module K1, so as to connect the path between the first end and the second end of the first switch module K1, and to connect the path between the first end and the second end of the second switch module K1.

[0060] Based on the circuit provided in this example, the level state at the first control interface and the level state of the control signal received by the MCU can be controlled by the first switch module and the second switch module.

[0061] Optional, Figure 6 The structure of the pin multiplexing circuit provided in this application is shown as follows Figure 5 ,like Figure 6 As shown, the circuit further includes: a first resistor R1 and a second resistor R2;

[0062] A first end of the first resistor R1 is connected to a second end of the first switch module K1, and a second end of the first resistor R1 is grounded, so as to reduce the current in the path;

[0063] A first end of the second resistor R2 is connected to a second end of the second switch module K2 , and a second end of the second resistor R2 is grounded, so as to reduce the current in the path.

[0064] Combined with the scenario example, the resistance value of the second resistor R2 can be determined according to the actual situation. At present, the second resistor R2 plays a current limiting role in the circuit to prevent the circuit board from burning due to excessive current.

[0065] Figure 7 The structure of the pin multiplexing circuit provided in this application is shown as follows Figure 6 ,like Figure 7 As shown, the complex programmable logic device integrates an interactive information parsing module, and the upper system module integrates an interactive information parsing module, a bit stream control module and an upgrade module; wherein the interactive information parsing module is used to parse the received data, the bit stream control module is used to control the transmission rate of information interaction, and the upgrade module is used to provide online upgrade information.

[0066] Combined with the scenario example, the CPLD and the upper system module can integrate preset functional modules, such as the interactive information parsing module, the code stream control module and the upgrade module, wherein the data for information exchange between the CPLD and the upper system module can be parsed based on the interactive information parsing module, so that the CPLD and the upper system module can recognize the data. The code stream control module can control the transmission rate of the upper system module, and the upgrade module can provide online upgrade information for online upgrading of the CPLD.

[0067] Optional, Figure 8 The structure of the pin multiplexing circuit provided in this application is shown as follows Figure 7 ,like Figure 8 As shown, the target function pin is a serial peripheral interface pin;

[0068] Correspondingly, the first functional module is a Flash module, the first functional signal is Flash information, the second functional module is a hardware status module, and the second functional signal is hardware status information.

[0069] Combined with the scenario example, when the target functional pin is an SPI pin, for example, the Flash•SPI multiplexing design of the SPI pin includes connecting the Flash•SPI pin of the CPLD to the external Flash pin and the general-purpose input / output (GPIO) pin through the MCU, the CPLD logic design and the CPLD pin function switching, so as to achieve the access to the Flash module and the hardware status module through the SPI pin time-sharing. Among them, accessing the Flash module is Flash access, and Flash access refers to the interactive process with the server-side database through Flash technology. Specifically, the Flash program is responsible for sending a request to the server. After receiving the request, the server accesses the database to obtain data and returns the data in a specific format. The Flash program then presents the data to the user in different forms. Specifically, when the processor accesses the Flash module, the Flash information output by the Flash module can be obtained through the SPI pin, and the Flash information is transmitted to the CPLD. The CPLD returns the first result data to the processor based on the Flash information, and the processor returns the first result data to the Flash module through the SPI pin. When the processor accesses the hardware status module, it can obtain the hardware status information output by the hardware status module through the SPI pin and transmit the hardware status information to the CPLD. The CPLD returns the second result data to the processor based on the hardware status information, and the processor then returns the second result data to the hardware status module through the SPI pin.

[0070] The SPI pins between the MCU and the Flash module can be defined as the Main Clock (MCLK), CSPIN, Master Input Slave Output (MISO), and Master Output Slave Input (MOSI). Among them, MCLK is a clock signal widely used in electronic systems. It is the main time base of the system and is used to synchronize and drive the operation of various internal and external devices. The MCLK signal is usually generated by a crystal oscillator to provide a stable and accurate frequency output to ensure the timing consistency of various parts of the system. MISO refers to the process in which the host is responsible for receiving external input data in a system, while the slave is responsible for processing this data and outputting the results to the external device. MOSI refers to the process in which the host (usually the control device) sends data or instructions to the slave (usually the controlled device) in a communication system, and the slave receives this data or instructions and performs the corresponding operations.

[0071] The hardware status module may be a general-purpose input / output (GPIO) control module, and the hardware status information may be GPIO information representing the status of a specific hardware device, so the SPI pins between the MCU and the general GPIO control module may be defined as GPIO1, GPIO2, GPIO3, and GPIO4.

[0072] Based on the circuit provided in this example, the multiplexing design of the CPLD's SPI pins can be completed.

[0073] Optionally, the complex programmable logic device further includes a second control interface;

[0074] The second control interface is connected to a high level;

[0075] The third end of the controller is connected to the second control interface, and is used to receive the control signal sent by the complex programmable logic device, and when receiving the control signal of the first state, receives the Flash information sent by the Flash module to send the Flash information to the complex programmable logic device, and when receiving the control signal of the second state, receives the hardware status information sent by the hardware status module to send the hardware status information to the complex programmable logic device.

[0076] Combined with scenario examples, such as Figure 8 As shown, the SPI pin includes multiple signal transmission paths, including a first signal transmission path defined as MCLK or GPIO1, a second signal transmission path defined as CSPIN or GPIO2, a third signal transmission path defined as MISO or GPIO3, and a fourth signal transmission path defined as MOSI or GPIO4. After the second control port, the first signal transmission path, and the second signal transmission path are connected to a high level, the second control port, the first signal transmission path, and the second signal transmission path can work normally. The CPLD sends a control signal to the processor through the second control port to control the processor to switch the received information. Specifically, when the control signal sent by the CPLD to the controller is in the first state, the processor switches to receiving the Flash information output by the Flash module, specifically, receives the Flash information through the first signal transmission path, the second signal transmission path, and the third signal transmission path, and transmits the received Flash information to the CPLD through the first signal transmission path, the second signal transmission path, and the third signal transmission path, the CPLD returns the first result data to the processor through the fourth signal transmission path, and the processor returns the first result data to the Flash module through the fourth signal transmission path.

[0077] Similarly, when the control signal sent by the CPLD to the controller is in the second state, the processor switches to receiving the GPIO information output by the hardware status module. Specifically, the processor receives the GPIO information through the first signal transmission path, the second signal transmission path, and the third signal transmission path, and transmits the received GPIO information to the CPLD through the first signal transmission path, the second signal transmission path, and the third signal transmission path. The CPLD returns the second result data to the processor through the fourth signal transmission path, and the processor returns the second result data to the hardware status module through the fourth signal transmission path.

[0078] Based on the circuit provided in this example, the access to the Flash module and the hardware status module can be switched by controlling the status information of the signal, so as to realize time-sharing access to the Flash module and the hardware status module.

[0079] Optional, Fig. 9 The structure of the pin multiplexing circuit provided in this application is shown as follows Figure 8 ,like Fig. 9 As shown, the circuit further includes: a third resistor R3, a fourth resistor R4 and a fifth resistor R5;

[0080] A first end of the third resistor R3 is connected to the high level, and a second end of the third resistor R3 is connected to the second control interface of the complex programmable logic device, for reducing the current in the path;

[0081] A first end of the fourth resistor R4 is connected to the high level, and a second end of the fourth resistor R4 is connected to the first signal transmission path, so as to reduce the current in the path;

[0082] A first end of the fifth resistor R5 is connected to the high level, and a second end of the fifth resistor R5 is connected to the second signal transmission path, so as to reduce the current in the path.

[0083] Combined with the scenario example, the resistance values ​​of the third resistor R3, the fourth resistor R4 and the fifth resistor R5 can be determined according to actual conditions. Currently, the third resistor R3, the fourth resistor R4 and the fifth resistor R5 play a current limiting role in the circuit to prevent the circuit board from burning due to excessive current.

[0084] Fig.10 The structure of the pin multiplexing circuit provided in this application is shown as follows Figure 9 ,like Fig.10 As shown, the complex programmable logic device integrates a time-sharing multiplexing logic module, a pin function switching module and a hardware status information logic control module; wherein the time-sharing multiplexing logic module is used to control the state of the output control signal, the pin function switching module is used to switch the receiving state of the serial peripheral interface pin, and the hardware status information logic control module is used to analyze and process the received hardware status information.

[0085] Combined with the scenario example, the pin function switching module can determine the module that needs to be accessed, and when the Flash module needs to be accessed, the CPLD outputs the control signal of the first state, and when the hardware status module needs to be accessed, the CPLD outputs the control signal of the second state. The time-division multiplexing logic module can define the function switching of the control signal and the SPI pin. For example, it is stipulated that when the CPLD outputs the control signal of the first state, the control processor switches the SPI pin to receive the Flash information, and when the CPLD outputs the control signal of the first state, the control processor switches the SPI pin to receive the hardware status information.

[0086] Optionally, the pin multiplexing circuit obtained above may be verified, and the verification process may be performed by obtaining multiple preset test data, inputting the test data into the pin multiplexing circuit in sequence, and determining whether the pin multiplexing circuit can give a preset response.

[0087] Through the pin multiplexing circuit provided in the present application, the target functional pins are multiplexed to meet the demand for the number of logic device pins, thereby solving the problems of waste of resources and increased wiring pressure caused by packaging multiple logic devices or selecting larger logic devices regardless of cost in related technologies, reducing the cost of logic devices and reducing the pressure on wiring logic devices.

[0088] The present application also provides a network device, which includes the pin multiplexing circuit of each of the above embodiments.

[0089] Wherein, the network device can be any form of network switching device, network card device and other electronic devices. Wherein the network switching device can be a switch or a router. Wherein, the electronic device includes at least one processor and a memory. Optionally, the electronic device also includes a communication component. Wherein, the processor, the memory and the communication component are connected via a bus. In the above embodiment, it should be understood that the processor can be a central processing unit (Cental Processing Unit, referred to as CPU), or other general-purpose processors, digital signal processors (Digital Signal Processor referred to as DSP), application-specific integrated circuits (Application Specific Integrated Circuit, referred to as ASIC), etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in the application can be directly embodied as being executed by a hardware processor, or executed by a combination of hardware and software modules in the processor. The memory may include a high-speed memory (Random Access Memory, referred to as RAM), and may also include a non-volatile memory (NVM), such as at least one disk memory. The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, the bus in the drawings of the present application is not limited to only one bus or one type of bus.

[0090] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method.

[0091] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0092] The above is a detailed introduction to a pin multiplexing circuit provided by the present application. This article uses specific examples to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core ideas of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A pin multiplexing circuit, characterized in that: include: A logic device, a processor, a first functional module and a second functional module; wherein: the logic device includes a target functional pin, the first functional module includes a first functional pin corresponding to the target functional pin, and the second functional module includes a second functional pin corresponding to the target functional pin; The first function pin of the first function module is connected to the first end of the processor, and is used to transmit a first function signal to the processor and receive first result data returned by the processor; The second function pin of the second function module is connected to the second end of the processor, and is used to transmit the second function signal to the processor and receive the second result data returned by the processor; The third terminal of the processor is connected to the control signal; The fourth terminal of the processor is connected to the target function pin, and is used for sending the received first function signal to the logic device and receiving the first result data returned by the logic device when the control signal is in the first state, so as to return the first result to the first function module; It is also used to send the received second function signal to the logic device when the control signal is in the second state, and receive the second result data returned by the logic device, so as to return the second result to the second function module.

2. The circuit according to claim 1, characterized in that The logic device is a complex programmable logic device; Correspondingly, the target function pins include joint test workgroup pins and serial peripheral interface pins.

3. The circuit according to claim 2, characterized in that The target function pin is a joint test working group pin; Correspondingly, the first functional module is an upper-layer system module, the first functional signal is general information or online upgrade information, the second functional module is an offline update module, and the second functional signal is offline update information.

4. The circuit according to claim 3, characterized in that The complex programmable logic device also includes a first control interface; The control end of the upper system module is connected to the first control interface of the complex programmable logic device, and is used to send a first function signal to the controller as general information when the first control interface is in a low level state, and send an online upgrade information to the controller when the first control interface is in a high level state.

5. The circuit according to claim 4, characterized in that The circuit further includes: a first switch module and a second switch module; The first end of the first switch module is connected to a high level, and the second end of the first switch module is grounded; A first end of the second switch module is connected to a high level, and a second end of the second switch module is grounded; The first control interface of the complex programmable logic device is connected to the second end of the first switch module, and is in a low level state when the path between the first end and the second end of the first switch module is disconnected; and is in a high level state when the path between the first end and the second end of the first switch module is connected; The third end of the controller is connected to the second end of the second switch module. When the path between the first end and the second end of the second switch module is disconnected, the received control signal is a control signal of the first state; when the path between the first end and the second end of the second switch module is connected, the received control signal is a control signal of the second state.

6. The circuit according to claim 5, characterized in that The circuit further includes: a first resistor and a second resistor; The first end of the first resistor is connected to the second end of the first switch module, and the second end of the first resistor is grounded, so as to reduce the current in the path; The first end of the second resistor is connected to the second end of the second switch module, and the second end of the second resistor is grounded, so as to reduce the current in the path.

7. The circuit according to claim 2, characterized in that The target function pin is a serial peripheral interface pin; Correspondingly, the first functional module is a Flash module, the first functional signal is Flash information, the second functional module is a hardware status module, and the second functional signal is hardware status information.

8. The circuit according to claim 7, characterized in that The complex programmable logic device also includes a second control interface; The second control interface is connected to a high level; The third end of the controller is connected to the second control interface, and is used to receive the control signal sent by the complex programmable logic device, and when receiving the control signal of the first state, receives the Flash information sent by the Flash module, so as to send the Flash information to the complex programmable logic device, and when receiving the control signal of the second state, receives the hardware status information sent by the hardware status module, so as to send the hardware status information to the complex programmable logic device.

9. The circuit according to claim 8, characterized in that The circuit further comprises: a third resistor, a fourth resistor and a fifth resistor; The first end of the third resistor is connected to the high level, and the second end of the third resistor is connected to the second control interface of the complex programmable logic device, so as to reduce the current in the path; The first end of the fourth resistor is connected to the high level, and the second end of the fourth resistor is connected to the first signal transmission path, so as to reduce the current in the path; A first end of the fifth resistor is connected to a high level, and a second end of the fifth resistor is connected to a second signal transmission path, so as to reduce a current in the path.

10. A network device, comprising the pin multiplexing circuit according to any one of claims 1 to 9.

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