Circuit for level conversion

Abstract

The invention discloses a circuit for level conversion. The circuit comprises a bootstrap circuit used for converting an input voltage into a control voltage; the level conversion circuit is used for providing output voltage according to the control voltage, the level of the output voltage is higher than that of the input voltage, and the voltage amplitude of the control voltage is larger than the threshold voltage of a switching tube of the level conversion circuit. According to the circuit, the level conversion circuit is controlled to perform level conversion by using the control voltage with a relatively high voltage amplitude, relatively high current can be generated, and the level conversion speed is remarkably improved.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and more particularly, to a circuit for level conversion. Background Art

[0002] With the continuous improvement of the design complexity of integrated circuits, integrated circuits have put forward higher requirements for characteristics such as integration, stability, and compatibility. Due to advantages such as high integration, intelligence and automation, high reliability and high stability, multi-core and parallel processing, and the development trend of customization and personalization, mixed-signal chips are widely used in various fields such as communication, medical treatment, and industrial control.

[0003] However, with the development of integrated circuit manufacturing processes, the voltage in the digital voltage domain has become lower and lower, while the voltage in the analog voltage domain remains almost unchanged or even becomes higher in special processes. When a low-voltage digital circuit signal is output to a high-voltage analog circuit, a level conversion circuit is required for level conversion. As the digital frequency becomes higher and higher, the speed requirement for the level conversion circuit is also increasing. The greater the voltage amplitude of the conversion from a digital low level to an analog high level, the slower the conversion speed of the level conversion circuit. Therefore, traditional level conversion circuits cannot meet the requirements of integrated circuits for level conversion speed.

[0004] Therefore, it is desirable to provide an improved level conversion circuit to solve the above problems. Summary of the Invention

[0005] In view of the above problems, an object of the present invention is to provide a circuit for level conversion to improve the level conversion speed.

[0006] According to one aspect of the present invention, there is provided a circuit for level conversion, comprising:

[0007] A bootstrap circuit for converting an input voltage into a control voltage; and

[0008] A level conversion circuit including a plurality of switching transistors for providing an output voltage according to the control voltage, the level of the output voltage being higher than the level of the input voltage,

[0009] wherein the voltage amplitude of the control voltage is greater than the threshold voltage of the switching transistors of the level conversion circuit.

[0010] Optionally, the voltage amplitude of the control voltage is greater than or equal to twice the voltage amplitude of the input voltage.

[0011] Optionally, the control voltage includes complementary first and second voltages, and the bootstrap circuit includes first and second branches having the same circuit structure,

[0012] The first branch performs charge and discharge using a first capacitor to obtain the first voltage;

[0013] The second branch performs charge and discharge using a second capacitor to obtain the second voltage,

[0014] wherein, the charge and discharge paths of the first branch and the second branch are controlled by the input voltage.

[0015] Optionally, when the input voltage is at a high level, a first power supply charges the first capacitor, the first voltage is pulled down to the reference ground, the second capacitor starts to discharge to provide the second voltage, and the path from the second voltage to the reference ground is turned off;

[0016] When the input voltage is at a low level, the first capacitor starts to discharge to provide the first voltage, the path from the first voltage to the reference ground is turned off, the first power supply charges the second capacitor, and the second voltage is pulled down to the reference ground.

[0017] Optionally, the first branch includes:

[0018] A first inverter for converting the input voltage into a first intermediate voltage;

[0019] The first capacitor, whose second end is connected to the output end of the first inverter;

[0020] A first switching transistor connected between the first power supply and the first end of the first capacitor, and the control end of the first switching transistor is connected to the first end of the second capacitor;

[0021] A second switching transistor connected between the first end of the first capacitor and the first output end;

[0022] A third switching transistor connected between the first output end and the reference ground;

[0023] The second branch includes:

[0024] A second inverter connected to the output end of the first inverter for converting the first intermediate voltage into a second intermediate voltage;

[0025] The second capacitor, whose second end is connected to the output end of the second inverter;

[0026] A fourth switching transistor connected between the first power supply and the first end of the second capacitor, and the control end of the fourth switching transistor is connected to the second end of the first capacitor;

[0027] A fifth switching transistor connected between the first end of the second capacitor and the second output end;

[0028] The sixth switching transistor is connected between the second output terminal and the reference ground.

[0029] Optionally, the second switching transistor and the third switching transistor are controlled by the second intermediate voltage, and the fifth switching transistor and the sixth switching transistor are controlled by the first intermediate voltage; the first switching transistor, the third switching transistor, the fourth switching transistor, and the sixth switching transistor have the same conduction type, and are opposite to the conduction types of the second switching transistor and the fifth switching transistor.

[0030] Optionally, the control voltage includes complementary first and second voltages, and the level conversion circuit includes:

[0031] A seventh switching transistor, an eighth switching transistor, and a ninth switching transistor connected in sequence between the second power supply and the reference ground,

[0032] A tenth switching transistor, an eleventh switching transistor, and a twelfth switching transistor connected in sequence between the second power supply and the reference ground,

[0033] wherein, the control terminals of the eighth switching transistor and the ninth switching transistor are connected and receive the second voltage, the control terminals of the eleventh switching transistor and the twelfth switching transistor are connected and receive the first voltage, the control terminal of the seventh switching transistor is connected to the second node between the eleventh switching transistor and the twelfth switching transistor, the control terminal of the tenth switching transistor is connected to the first node between the eighth switching transistor and the ninth switching transistor, and the second node provides the output voltage,

[0034] The voltage amplitude of the control voltage is greater than the threshold voltages of the eighth switching transistor, the ninth switching transistor, the eleventh switching transistor, and the twelfth switching transistor.

[0035] Optionally, the control voltage includes complementary first and second voltages, and the level conversion circuit includes:

[0036] A seventh switching transistor, an eighth switching transistor, and a ninth switching transistor connected in sequence between the second power supply and the reference ground,

[0037] A tenth switching transistor, an eleventh switching transistor, and a twelfth switching transistor connected in sequence between the second power supply and the reference ground,

[0038] wherein, the control terminal of the ninth switching transistor receives the second voltage, the control terminal of the twelfth switching transistor receives the first voltage, the control terminals of the seventh switching transistor and the eleventh switching transistor are respectively connected to the first node between the eighth switching transistor and the ninth switching transistor, the control terminals of the eighth switching transistor and the tenth switching transistor are respectively connected to the second node between the eleventh switching transistor and the twelfth switching transistor, and the second node provides the output voltage,

[0039] The voltage amplitude of the control voltage is greater than the threshold voltages of the ninth switching transistor and the twelfth switching transistor.

[0040] Optionally, the control voltage includes complementary first and second voltages, and the level conversion circuit includes:

[0041] A current mirror circuit including a third branch and a fourth branch;

[0042] A seventh switching transistor connected to the third branch, the seventh switching transistor being controlled by the second voltage; and

[0043] An eighth switching transistor connected to the fourth branch, the eighth switching transistor being controlled by the first voltage,

[0044] The voltage amplitude of the control voltage is greater than the threshold voltages of the seventh switching transistor and the eighth switching transistor.

[0045] Optionally, the control voltage includes complementary first and second voltages, and the level conversion circuit includes:

[0046] A current mirror circuit including a third branch and a fourth branch;

[0047] A seventh switching transistor connected to the third branch, the seventh switching transistor being controlled by the second voltage;

[0048] An eighth switching transistor connected to the fourth branch, the eighth switching transistor being controlled by the first voltage; and

[0049] A ninth switching transistor connected between a second power supply and the third branch, or connected between the third branch and the seventh switching transistor, and controlled by the output voltage,

[0050] wherein when the output voltage is high, the ninth switching transistor is turned off,

[0051] The voltage amplitude of the control voltage is greater than the threshold voltages of the seventh switching transistor and the eighth switching transistor.

[0052] The circuit for level conversion provided by the present invention controls the level conversion circuit to perform level conversion by using a control voltage with a relatively high voltage amplitude, can generate a relatively large current, and significantly improves the level conversion speed.

[0053] In some alternative embodiments, the circuit improves the level conversion circuit, and an inverter structure is formed in the level conversion circuit, which can pull down the voltage of the first node / second node faster, further improving the level conversion speed.

[0054] In some alternative embodiments, the circuit improves the level conversion circuit, eliminates the static current, and has the advantages of low power consumption and anti-leakage. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Through the following description of the embodiments of the present invention with reference to the accompanying drawings, the above and other objects, features, and advantages of the present invention will become more apparent. In the drawings:

[0056] Figure 1 A schematic diagram of a circuit for level conversion according to a first embodiment of the present invention is shown;

[0057] Figure 2 A schematic diagram of a bootstrap circuit according to an embodiment of the present invention is shown;

[0058] Figure 3 A signal waveform diagram of voltages at various parts of a circuit for level conversion according to an embodiment of the present invention is shown;

[0059] Figure 4 A schematic diagram of a circuit for level conversion according to a second embodiment of the present invention is shown;

[0060] Figure 5 A schematic diagram of a circuit for level conversion according to a third embodiment of the present invention is shown;

[0061] Figure 6 A schematic diagram of a circuit for level conversion according to a fourth embodiment of the present invention is shown. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0062] The present invention will be described in more detail below with reference to the accompanying drawings. In the respective drawings, the same elements are denoted by like reference numerals. For clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown in the figures.

[0063] Many specific details of the present invention are described below, such as the structure, materials, dimensions, processing techniques, and technologies of the devices, in order to understand the present invention more clearly. However, as those skilled in the art can understand, the present invention can be implemented without these specific details.

[0064] It should be understood that the connection / coupling between A and B in the embodiments of the present application means that A and B can be connected in series or in parallel, or A and B are connected through other devices, and the embodiments of the present application do not limit this.

[0065] Embodiments of a circuit for level conversion provided by the present application will be described below with reference to the accompanying drawings.

[0066] Figure 1 A schematic diagram of a circuit for level conversion according to a first embodiment of the present invention is shown;Figure 2 The figure shows a schematic diagram of a bootstrap circuit according to an embodiment of the present invention; Figure 3 The figure shows a signal waveform diagram of voltages at various parts of a circuit for level conversion according to an embodiment of the present invention.

[0067] As Figure 1 As shown, the circuit 100 for level conversion provided by an embodiment of the present invention includes a bootstrap circuit 110 and a level conversion circuit 120, and this circuit 100 can convert an input voltage VIN into an output voltage VOUT.

[0068] In some embodiments, this circuit 100 is applied to a display driver chip, a power chip, etc., or is applied to a System On Chip (SoC) or a digital - analog hybrid circuit. The input voltage VIN is applied to the digital circuit part in these chips or circuits, and its voltage amplitude is relatively low. The output voltage VOUT is applied to the analog circuit part in these chips or circuits, and its voltage amplitude is relatively high.

[0069] The bootstrap circuit 110 is used to convert the input voltage VIN into a control voltage. Specifically, the control voltage at least includes a first voltage VN and a second voltage VP, and the first voltage VN and the second voltage VP are complementary. For example, when the first voltage VN is at a high level, the second voltage VP is at a low level; when the first voltage VN is at a low level, the second voltage VP is at a high level. In an embodiment of the present invention, the voltage amplitude of the control voltage is configured to be greater than the threshold voltage of the switching transistor in the level conversion circuit 120, and the voltage amplitude of the control voltage is greater than or equal to twice the voltage amplitude of the input voltage VIN. For example, if the high level of the input voltage VIN is VDDL, then the high levels of both the first voltage VN and the second voltage VP are 2*VDDL, and if the low level of the input voltage VIN is 0, then the low levels of both the first voltage VN and the second voltage VP are also 0.

[0070] The level conversion circuit 120 is used to provide the output voltage VOUT according to the control voltage, and the level of the output voltage VOUT is higher than the level of the input voltage VIN. In some embodiments, this level conversion circuit 120 implements level conversion based on a current mirror.

[0071] In an embodiment of the present invention, the bootstrap circuit 110 is used to convert the input voltage VIN into a control voltage with a relatively high voltage amplitude, so that a larger current can be generated in the level conversion circuit 120, thereby improving the speed of level conversion.

[0072] Please refer to Figure 2, the bootstrap circuit 110 includes a first branch 111 and a second branch 112 with the same circuit structure. The first branch 111 charges and discharges using a first capacitor C1 to obtain a first voltage VN, and the charge and discharge path of the first branch 111 is controlled by the input voltage VIN; the second branch 112 charges and discharges using a second capacitor C2 to obtain a second voltage VP, and the charge and discharge path of the second branch 112 is controlled by the inverted voltage of the input voltage VIN. Since the first branch 111 and the second branch 112 are controlled by opposite voltages, the bootstrap circuit 110 can generate complementary first voltage VN and second voltage VP according to the input voltage VIN.

[0073] In this embodiment, when the input voltage VIN is at a high level, the first power supply VDDL charges the first capacitor C1, the first voltage VN is pulled down to the reference ground GND (usually 0), the second capacitor C2 starts to discharge to provide the second voltage VP, and the path from the second voltage VP to the reference ground GND is turned off; when the input voltage VIN is at a low level, the first capacitor C1 starts to discharge to provide the first voltage VN, the path from the first voltage VN to the reference ground GND is turned off, the first power supply VDDL charges the second capacitor C2, and the second voltage VP is pulled down to the reference ground GND.

[0074] Specifically, the first branch 111 includes a first inverter INV1, a first switching transistor M1, a second switching transistor M2, a third switching transistor M3, and a first capacitor C1. The input terminal of the first inverter INV1 receives the input voltage VIN and is used to convert the input voltage VIN into a first intermediate voltage VG1; the second terminal of the first capacitor C1 is connected to the output terminal of the first inverter INV1; the first switching transistor M1 is connected between the first power supply VDDL and the first terminal of the first capacitor C1; the second switching transistor M2 is connected between the first terminal of the first capacitor C1 and the first output terminal; the third switching transistor M3 is connected between the first output terminal and the reference ground GND; wherein, the control terminal of the first switching transistor M1 is connected to the first terminal of the second capacitor C2 and is controlled by a fourth intermediate voltage VG4, and the second switching transistor M2 and the third switching transistor M3 are controlled by a second intermediate voltage VG2. The second intermediate voltage VG2 is also equivalent to the voltage obtained by delaying the input voltage VIN, and the fourth intermediate voltage VG4 is the voltage at the first terminal of the second capacitor C2.

[0075] The second branch 112 includes a second inverter INV2, a fourth switching transistor M4, a fifth switching transistor M5, a sixth switching transistor M6, and a second capacitor C2. The input terminal of the second inverter INV2 is connected to the output terminal of the first inverter INV1 and is configured to convert the first intermediate voltage VG1 into a second intermediate voltage VG2; the second terminal of the second capacitor C2 is connected to the output terminal of the second inverter INV2; the fourth switching transistor M4 is connected between the first power supply VDDL and the first terminal of the second capacitor C2; the fifth switching transistor M5 is connected between the first terminal of the second capacitor C2 and the second output terminal; the sixth switching transistor M6 is connected between the second output terminal and the reference ground GND; wherein, the control terminal of the fourth switching transistor M4 is connected to the first terminal of the first capacitor C1 and is controlled by the third intermediate voltage VG3, and the fifth switching transistor M5 and the sixth switching transistor M6 are controlled by the first intermediate voltage VG1. The first intermediate voltage VG1 is also equivalent to the inverted voltage of the input voltage VIN, and the third intermediate voltage VG3 is the voltage at the first terminal of the first capacitor C1.

[0076] In this embodiment, the first switching transistor M1, the third switching transistor M3, the fourth switching transistor M4, and the sixth switching transistor M6 have the same conduction type, and are opposite to the conduction types of the second switching transistor M2 and the fifth switching transistor M5. For example, the first switching transistor M1, the third switching transistor M3, the fourth switching transistor M4, and the sixth switching transistor M6 are all N-type metal oxide semiconductor field effect transistors (Negative Channel Metal Oxide Semiconductor, NMOS), and the second switching transistor M2 and the fifth switching transistor M5 are both P-type metal oxide semiconductor field effect transistors (Positive Channel Metal Oxide Semiconductor, PMOS).

[0077] After the circuit enters the steady state, the first power supply VDDL charges the upper plates (the first terminals) of the first capacitor C1 and the second capacitor C2 to VDDL respectively. The low level of the input voltage VIN is, for example, 0, and the high level is, for example, VDDL.

[0078] When the input voltage VIN switches from high level to low level, the first intermediate voltage VG1 provided by the first inverter INV1 is at high level, and the second intermediate voltage VG2 provided by the second inverter INV2 is at low level. At this time, the second terminal of the first capacitor C1 is charged to VDDL. Based on the principle that the capacitor voltage cannot change suddenly, the voltage at the first terminal of the first capacitor C1 becomes VDDL + VDDL = 2*VDDL at this time, and the fourth switching transistor M4 is turned on. The charging path from the first power supply VDDL to the second capacitor C2 is turned on, and the first terminal of the second capacitor C2 is charged to VDDL. At this time, the second switching transistor M2 is turned on, the third switching transistor M3 is turned off, the fifth switching transistor M5 is turned off, and the sixth switching transistor M6 is turned on. Therefore, the discharging path from the first capacitor C1 to the first output terminal is turned on, and the current path between the first output terminal and the reference ground GND is turned off, and the first voltage VN provided by the first output terminal is at high level; the discharging path from the second capacitor C2 to the second output terminal is turned off, and the current path between the second output terminal and the reference ground GND is turned on, and the second voltage VP provided by the second output terminal is at low level. Therefore, when the input voltage VIN changes from high level to low level, the first voltage VN changes from low level to high level, the second voltage VP changes from high level to low level, and the high level of the first voltage VN is twice the high level of the input voltage VIN.

[0079] When the input voltage VIN switches from low level to high level, the first intermediate voltage VG1 provided by the first inverter INV1 is at low level, and the second intermediate voltage VG2 provided by the second inverter INV2 is at high level. At this time, the second terminal of the second capacitor C2 is charged to VDDL. Based on the principle that the capacitor voltage cannot change suddenly, the voltage at the first terminal of the second capacitor C2 becomes VDDL + VDDL = 2*VDDL at this time, and the first switching transistor M1 is turned on. The charging path from the first power supply VDDL to the first capacitor C1 is turned on, and the first terminal of the first capacitor C1 is charged to VDDL. At this time, the second switching transistor M2 is turned off, the third switching transistor M3 is turned on, the fifth switching transistor M5 is turned on, and the sixth switching transistor M6 is turned off. Therefore, the discharging path from the first capacitor C1 to the first output terminal is turned off, and the current path between the first output terminal and the reference ground GND is turned on, and the first voltage VN provided by the first output terminal is at low level; the discharging path from the second capacitor C2 to the second output terminal is turned on, and the current path between the second output terminal and the reference ground GND is turned off, and the second voltage VP provided by the second output terminal is at high level. Therefore, when the input voltage VIN changes from low level to high level, the first voltage VN changes from high level to low level, the second voltage VP changes from low level to high level, and the high level of the second voltage VP is twice the high level of the input voltage VIN.

[0080] It should be understood that the circuit structures of the foregoing first branch 111 and second branch 112 are only illustrative examples. Those skilled in the art can achieve the same or similar technical effects by changing parameters such as the type of switching transistors and the corresponding circuit connection relationships. In addition, the voltage value of the first power supply VDDL can be the same as the input voltage VIN, so that the voltage amplitudes of the first voltage VN and the second voltage VP are approximately twice the voltage amplitude of the input voltage VIN; the voltage value of the first power supply VDDL can be greater than the input voltage VIN, so that the voltage amplitudes of the first voltage VN and the second voltage VP are greater than twice the voltage amplitude of the input voltage VIN. By adjusting the voltage value of the first power supply VDDL, the voltage amplitudes of the first voltage VN and the second voltage VP can be controlled so that the voltage amplitudes of the first voltage VN and the second voltage VP are greater than the threshold voltages of the switching transistors in the level conversion circuit 120.

[0081] In this embodiment, the level conversion circuit 120 includes a seventh switching transistor M7, an eighth switching transistor M8, a ninth switching transistor M9, a tenth switching transistor M10, an eleventh switching transistor M11, and a twelfth switching transistor M12.

[0082] The seventh switching transistor M7, the eighth switching transistor M8, and the ninth switching transistor M9 are sequentially connected between the second power supply VDDH and the reference ground GND. The tenth switching transistor M10, the eleventh switching transistor M11, and the twelfth switching transistor M12 are also sequentially connected between the second power supply VDDH and the reference ground GND. The control terminal of the eighth switching transistor M8 and the control terminal of the ninth switching transistor M9 are connected and receive the second voltage VP. The control terminal of the eleventh switching transistor M11 and the control terminal of the twelfth switching transistor M12 are connected and receive the first voltage VN. The control terminal of the seventh switching transistor M7 is connected to the second node Q2 between the eleventh switching transistor M11 and the twelfth switching transistor M12. The control terminal of the tenth switching transistor M10 is connected to the first node Q1 between the eighth switching transistor M8 and the ninth switching transistor M9. The second node Q2 provides the output voltage VOUT. Therefore, the eighth switching transistor M8 and the ninth switching transistor M9 form an inverter structure, and the eleventh switching transistor M11 and the twelfth switching transistor M12 form an inverter structure. In this embodiment, the voltage amplitudes of the control voltages (including the first voltage VN and the second voltage VP) are greater than the threshold voltages of the eighth switching transistor M8, the ninth switching transistor M9, the eleventh switching transistor M11, and the twelfth switching transistor M12.

[0083] In this embodiment, the seventh switching transistor M7, the eighth switching transistor M8, the tenth switching transistor M10, and the eleventh switching transistor M11 are all PMOS transistors, and the ninth switching transistor M9 and the twelfth switching transistor M12 are all NMOS transistors.

[0084] In this embodiment, for example, the high level of the input voltage VIN is set to VDDL, the high levels of the first voltage VN and the second voltage VP are both 2*VDDL, and the low levels of the input voltage VIN, the first voltage VN, and the second voltage VP are all 0.

[0085] When the input voltage VIN is at a high level, the first voltage VN provided by the bootstrap circuit 110 is at a low level and the second voltage VP is at a high level. The eighth switching transistor M8 is turned off and the ninth switching transistor M9 is turned on. Therefore, the first node Q1 can be quickly pulled down to a low level. The eleventh switching transistor M11 is turned on and the twelfth switching transistor M12 is turned off. The second node Q2 can be charged to a high level more quickly.

[0086] When the input voltage VIN is at a low level, the first voltage VN provided by the bootstrap circuit 110 is at a high level and the second voltage VP is at a low level. The eighth switching transistor M8 is turned on and the ninth switching transistor M9 is turned off. Therefore, the first node Q1 can be quickly charged to a high level. The eleventh switching transistor M11 is turned off and the twelfth switching transistor M12 is turned on. The second node Q2 can be discharged to a low level more quickly.

[0087] In this embodiment, the eighth switching transistor M8 and the ninth switching transistor M9 form an inverter structure, and the eleventh switching transistor M11 and the twelfth switching transistor M12 form an inverter structure. Therefore, the level conversion is further accelerated.

[0088] It should be understood that the circuit structure of the above level conversion circuit 120 is only a schematic example. Those skilled in the art can achieve the same or similar technical effects by changing parameters such as the type of switching transistors and the corresponding circuit connection relationships. In addition, the magnitude of the output voltage VOUT can be adjusted by adjusting the voltage value of the second power supply VDDH.

[0089] After the above signal processing process, the circuit 100 for level conversion according to the embodiment of the present invention converts the input voltage VIN with a lower level into an output voltage VOUT with a higher level. Please refer to Figure 3 that the first power supply VDDL charges the third intermediate voltage VG3 on the first capacitor C1 and the fourth intermediate voltage VG4 on the second capacitor C2 to VDDL, and the third intermediate voltage VG3 on the first capacitor C1 and the fourth intermediate voltage VG4 on the second capacitor C2 are alternately pulled up to 2*VDD under the action of the input voltage VIN. Therefore, the bootstrap circuit 110 converts the input voltage VIN with a voltage amplitude of VDDL into the first voltage VN and the second voltage VP with a voltage amplitude of 2*VDDL, and the level conversion circuit 120 generates an output voltage VOUT with a voltage amplitude of VDDH based on the first voltage VN and the second voltage VP. The phases of the input voltage VIN and the output voltage VOUT are basically synchronized.

[0090] Some examples of the circuit for level conversion according to the embodiments of the present invention are described above. However, the embodiments of the present invention are not limited thereto, and there may be other ways of extension and variation.

[0091] For example, it should be understood that the reference ground potential in the foregoing embodiments may be replaced with other non-zero reference potentials (having a positive voltage amplitude or a negative voltage amplitude) or a reference signal with a controlled change in alternative embodiments.

[0092] Again, for example, the capacitor provided in the embodiments of the present application may be a lumped parameter capacitor element, or may also be other equivalent elements with functions similar to those of a capacitor. The equivalent structures described herein are, for example but not limited to, microstrip lines, varactor diodes, conductor structures with a certain pattern, etc., which can provide capacitive impedance.

[0093] At the same time, those of ordinary skill in the art can realize that, for the structures and methods of each example described in combination with the embodiments disclosed herein, different configuration methods or adjustment methods can be used to implement the described functions for each structure or a reasonable deformation of the structure, but such implementation should not be considered to exceed the scope of the present application. And it should be understood that the connection relationships between the various components of the amplifier in the foregoing figures in the embodiments of the present application are illustrative examples and do not impose any limitation on the embodiments of the present application.

[0094] Figure 4 A schematic diagram of a circuit for level conversion according to the second embodiment of the present invention is shown. The circuit structure of the bootstrap circuit 110 in the second embodiment of the present invention is exactly the same as that of the bootstrap circuit 110 in the first embodiment, and will not be described herein again.

[0095] In this embodiment, the level conversion circuit 120 includes a seventh switching transistor M7, an eighth switching transistor M8, a ninth switching transistor M9, a tenth switching transistor M10, an eleventh switching transistor M11, a twelfth switching transistor M12, and a third inverter INV3.

[0096] The seventh switching transistor M7, the eighth switching transistor M8, and the ninth switching transistor M9 are sequentially connected between the second power supply VDDH and the reference ground GND, and the tenth switching transistor M10, the eleventh switching transistor M11, and the twelfth switching transistor M12 are also sequentially connected between the second power supply VDDH and the reference ground GND.

[0097] The control terminal of the ninth switching transistor M9 receives the second voltage VP, the control terminal of the twelfth switching transistor M12 receives the first voltage VN, the control terminals of the seventh switching transistor M7 and the eleventh switching transistor M11 are respectively connected to the first node Q1. The first node Q1 is the connection node between the eighth switching transistor M8 and the ninth switching transistor M9. The control terminals of the eighth switching transistor M8 and the tenth switching transistor M10 are respectively connected to the second node Q2. The second node Q2 is the connection node between the eleventh switching transistor M11 and the twelfth switching transistor M12. The second node Q2 is connected to the input terminal of the third inverter INV3, and the output terminal of the third inverter INV3 provides the output voltage VOUT. In this embodiment, the voltage amplitudes of the control voltages (including the first voltage VN and the second voltage VP) are greater than the threshold voltages of the ninth switching transistor M9 and the twelfth switching transistor M12.

[0098] In this embodiment, the seventh switching transistor M7, the eighth switching transistor M8, the tenth switching transistor M10, and the eleventh switching transistor M11 are all PMOS transistors, and the ninth switching transistor M9 and the twelfth switching transistor M12 are both NMOS transistors.

[0099] In this embodiment, for example, the high level of the input voltage VIN is set to VDDL, the high levels of the first voltage VN and the second voltage VP are both 2*VDDL, and the low levels of the input voltage VIN, the first voltage VN, and the second voltage VP are all 0.

[0100] When the input voltage VIN is at a high level, the first voltage VN provided by the bootstrap circuit 110 is at a low level and the second voltage VP is at a high level. The eighth switching transistor, the ninth switching transistor M9, and the tenth switching transistor M10 are turned on, so the first node Q1 can be quickly pulled down to a low level. The seventh switching transistor M7, the eleventh switching transistor M11, and the twelfth switching transistor M12 are turned off, and the second node Q2 can be charged to a high level faster.

[0101] When the input voltage VIN is at a low level, the first voltage VN provided by the bootstrap circuit 110 is at a high level and the second voltage VP is at a low level. The eighth switching transistor, the ninth switching transistor M9, and the tenth switching transistor M10 are turned off, so the first node Q1 can be quickly charged to a high level. The seventh switching transistor M7, the eleventh switching transistor M11, and the twelfth switching transistor M12 are turned on, and the second node Q2 can be discharged to a low level faster.

[0102] It should be understood that the circuit structure of the above-mentioned level conversion circuit 120 is only a schematic example. Those skilled in the art can achieve the same or similar technical effects by changing parameters such as the type of switching transistors and the corresponding circuit connection relationships. In addition, the magnitude of the output voltage VOUT can be adjusted by adjusting the voltage value of the second power supply VDDH.

[0103] Figure 5Shows a schematic diagram of a circuit for level conversion according to a third embodiment of the present invention.

[0104] In this embodiment, the level conversion circuit 120 includes a current mirror circuit, a seventh switching transistor M7, and an eighth switching transistor M8. The current mirror circuit includes a third branch 121 and a fourth branch 122. The third branch 121 is a current input branch, and the fourth branch 122 is a current output branch. The seventh switching transistor M7 is connected to the third branch 121 and is controlled by the second voltage VP; the eighth switching transistor M8 is connected to the fourth branch 122 and is controlled by the first voltage VN. The connection node of the fourth branch 122 and the eighth switching transistor M8 serves as the output terminal of the level conversion circuit 120 and provides an output voltage VOUT.

[0105] As an example, the third branch 121 includes an eleventh switching transistor M11, and the fourth branch 122 includes a twelfth switching transistor M12. The first current terminal of the eleventh switching transistor M11 is directly connected to the second power supply VDDH. The second current terminal of the eleventh switching transistor M11 is connected to the reference ground GND through the seventh switching transistor M7. The control terminal of the eleventh switching transistor M11 is connected to the control terminal of the twelfth switching transistor M12 and is connected to the second current terminal of the eleventh switching transistor M11. The first current terminal of the twelfth switching transistor M12 is directly connected to the second power supply VDDH. The second current terminal of the twelfth switching transistor M12 is connected to the reference ground GND through the eighth switching transistor M8.

[0106] In this example, the seventh switching transistor M7 and the eighth switching transistor M8 are NMOS transistors, and the eleventh switching transistor M11 and the twelfth switching transistor M12 are PMOS transistors.

[0107] In this example, for instance, the high level of the input voltage VIN is set to VDDL, the high levels of both the first voltage VN and the second voltage VP are 2*VDDL, and the low levels of the input voltage VIN, the first voltage VN, and the second voltage VP are all 0.

[0108] When the input voltage VIN is at a high level, the first voltage VN provided by the bootstrap circuit 110 is at a low level and the second voltage VP is at a high level. The seventh switching transistor M7 is turned on, and the eighth switching transistor M8 is turned off. The gate voltage of the eleventh switching transistor M11 is pulled down to the reference ground GND (usually 0 level). Therefore, the eleventh switching transistor M11 and the twelfth switching transistor M12 are turned on, and the output voltage VOUT provided by the output terminal of the level conversion circuit 120 is pulled up to VDDH.

[0109] When the input voltage VIN is at a low level, the first voltage VN provided by the bootstrap circuit 110 is at a high level, and the second voltage VP is at a low level. The seventh switching transistor M7 is turned off, the eighth switching transistor M8 is turned on, and the output voltage VOUT provided at the output terminal of the level conversion circuit 120 is pulled down to the reference ground GND voltage.

[0110] It should be understood that the circuit structure of the above-mentioned level conversion circuit 120 is only a schematic example, and those skilled in the art can achieve the same or similar technical effects by changing parameters such as the type of switching transistors and the corresponding circuit connection relationships. In addition, the magnitude of the output voltage VOUT can be adjusted by adjusting the voltage value of the second power supply VDDH.

[0111] Figure 6 FIG. shows a schematic diagram of a circuit for level conversion according to the fourth embodiment of the present invention.

[0112] In this embodiment, the level conversion circuit 120 includes a current mirror circuit, a seventh switching transistor M7, an eighth switching transistor M8, and a ninth switching transistor M9. The current mirror circuit includes a third branch 121 and a fourth branch 122. The third branch 121 is a current input branch, and the fourth branch 122 is a current output branch. The seventh switching transistor M7 is connected to the third branch 121 and is controlled by the second voltage VP; the eighth switching transistor M8 is connected to the fourth branch 122 and is controlled by the first voltage VN. The ninth switching transistor M9 is connected between the third branch 121 and the seventh switching transistor M7 and is controlled by the output voltage VOUT; the connection node between the fourth branch 122 and the eighth switching transistor M8 serves as the output terminal of the level conversion circuit 120 and provides the output voltage VOUT. In some other embodiments, the ninth switching transistor M9 is connected between the third branch 121 and the second power supply VDDH.

[0113] As an example, the third branch 121 includes an eleventh switching transistor M11, and the fourth branch 122 includes a twelfth switching transistor M12. The first current terminal of the eleventh switching transistor M11 is directly connected to the second power supply VDDH, the second current terminal of the eleventh switching transistor M11 is sequentially connected to the reference ground GND through the ninth switching transistor M9 and the seventh switching transistor M7, and the control terminal of the eleventh switching transistor M11 is connected to the control terminal of the twelfth switching transistor M12 and is connected to the second current terminal of the eleventh switching transistor M11. The first current terminal of the twelfth switching transistor M12 is directly connected to the second power supply VDDH, and the second current terminal of the twelfth switching transistor M12 is connected to the reference ground GND through the eighth switching transistor M8.

[0114] In this example, the seventh switching transistor M7 and the eighth switching transistor M8 are NMOS transistors, and the ninth switching transistor M9, the eleventh switching transistor M11, and the twelfth switching transistor M12 are all PMOS transistors.

[0115] In this example, for instance, the high level of the input voltage VIN is set to VDDL, the high levels of the first voltage VN and the second voltage VP are both set to 2*VDDL, and the low levels of the input voltage VIN, the first voltage VN, and the second voltage VP are all 0.

[0116] When the input voltage VIN is at a high level, the first voltage VN provided by the bootstrap circuit 110 is at a low level and the second voltage VP is at a high level. The seventh switching transistor M7 is turned on and the eighth switching transistor M8 is turned off. The gate voltage of the eleventh switching transistor M11 is pulled down to the reference ground GND (usually at 0 level). Therefore, the eleventh switching transistor M11 and the twelfth switching transistor M12 are turned on, and the output voltage VOUT provided by the output terminal of the level conversion circuit 120 is pulled up to VDDH. At this time, the ninth switching transistor M9 is turned off and the leakage path is closed. Therefore, the generation of leakage current is avoided, the static current is eliminated, and the circuit power consumption is reduced.

[0117] When the input voltage VIN is at a low level, the first voltage VN provided by the bootstrap circuit 110 is at a high level and the second voltage VP is at a low level. The seventh switching transistor M7 is turned off and the eighth switching transistor M8 is turned on, and the output voltage VOUT provided by the output terminal of the level conversion circuit 120 is pulled down to the reference ground GND voltage.

[0118] In this embodiment, the ninth switching transistor M9 for eliminating the static current is provided, so it has the advantages of low power consumption and anti-leakage.

[0119] It should be understood that the circuit structure of the above level conversion circuit 120 is only a schematic example. Those skilled in the art can achieve the same or similar technical effects by changing parameters such as the type of switching transistors and the corresponding circuit connection relationships. In addition, the magnitude of the output voltage VOUT can be adjusted by adjusting the voltage value of the second power supply VDDH.

[0120] In summary, the embodiment of the present invention provides a circuit for level conversion. By using a control voltage with a relatively high voltage amplitude to control the level conversion circuit 120 for level conversion, a relatively large current can be generated, significantly improving the level conversion speed.

[0121] In some optional embodiments, the circuit improves the current mirror circuit, eliminates the static current, and has the advantages of low power consumption and anti-leakage.

[0122] It should be noted that, in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the said element.

[0123] As described above in accordance with the embodiments of the present invention, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made according to the above description. These embodiments are selected and specifically described in this specification in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and its modifications based on the present invention. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. A circuit for level conversion, comprising: A bootstrap circuit for converting an input voltage into a control voltage; as well as The level conversion circuit includes a plurality of switch tubes, and is used to provide an output voltage according to the control voltage, wherein the level of the output voltage is higher than the level of the input voltage. Wherein, the voltage amplitude of the control voltage is greater than the threshold voltage of the switch tube of the level conversion circuit.

2. The circuit according to claim 1, wherein The voltage amplitude of the control voltage is greater than or equal to twice the voltage amplitude of the input voltage.

3. The circuit according to claim 1, wherein: The control voltage includes a complementary first voltage and a second voltage, the bootstrap circuit includes a first branch and a second branch having the same circuit structure, The first branch uses a first capacitor to charge and discharge to obtain the first voltage; The second branch uses the second capacitor to charge and discharge to obtain the second voltage, The charging and discharging paths of the first branch and the second branch are controlled by the input voltage.

4. The circuit according to claim 3, wherein: When the input voltage is at a high level, the first power supply charges the first capacitor, the first voltage is pulled down to the reference ground, the second capacitor starts to discharge to provide the second voltage, and the path from the second voltage to the reference ground is cut off; When the input voltage is at a low level, the first capacitor starts to discharge to provide the first voltage, the path from the first voltage to the reference ground is cut off, the first power supply charges the second capacitor, and the second voltage is pulled down to the reference ground.

5. The circuit according to claim 3 or 4, wherein: The first branch comprises: A first inverter, used for converting the input voltage into a first intermediate voltage; The first capacitor has a second end connected to the output end of the first inverter; A first switch tube is connected between the first power supply and the first end of the first capacitor, and a control end of the first switch tube is connected to the first end of the second capacitor; A second switch tube is connected between the first end of the first capacitor and the first output end; A third switch tube is connected between the first output terminal and the reference ground; The second branch comprises: a second inverter, connected to an output terminal of the first inverter, and configured to convert the first intermediate voltage into a second intermediate voltage; The second capacitor, a second end of which is connected to the output end of the second inverter; a fourth switch tube, connected between the first power supply and the first end of the second capacitor, wherein a control end of the fourth switch tube is connected to the second end of the first capacitor; a fifth switch tube, connected between the first end and the second output end of the second capacitor; A sixth switch tube is connected between the second output terminal and the reference ground.

6. The circuit according to claim 5, wherein: The second switch tube and the third switch tube are controlled by the second intermediate voltage, and the fifth switch tube and the sixth switch tube are controlled by the first intermediate voltage; the conduction type of the first switch tube, the third switch tube, the fourth switch tube and the sixth switch tube is the same, and opposite to the conduction type of the second switch tube and the fifth switch tube.

7. The circuit according to claim 1, wherein: The control voltage includes a complementary first voltage and a second voltage, and the level conversion circuit includes: a seventh switch tube, an eighth switch tube and a ninth switch tube connected in sequence between the second power supply and the reference ground, a tenth switch tube, an eleventh switch tube and a twelfth switch tube connected in sequence between the second power supply and the reference ground, The control end of the eighth switch tube is connected to the control end of the ninth switch tube and receives the second voltage, the control end of the eleventh switch tube is connected to the control end of the twelfth switch tube and receives the first voltage, the control end of the seventh switch tube is connected to the second node between the eleventh switch tube and the twelfth switch tube, the control end of the tenth switch tube is connected to the first node between the eighth switch tube and the ninth switch tube, and the second node provides the output voltage. The voltage amplitude of the control voltage is greater than the threshold voltages of the eighth switch tube, the ninth switch tube, the eleventh switch tube and the twelfth switch tube.

8. The circuit according to claim 1, wherein: The control voltage includes a complementary first voltage and a second voltage, and the level conversion circuit includes: a seventh switch tube, an eighth switch tube and a ninth switch tube connected in sequence between the second power supply and the reference ground, a tenth switch tube, an eleventh switch tube and a twelfth switch tube connected in sequence between the second power supply and the reference ground, The control end of the ninth switch tube receives the second voltage, the control end of the twelfth switch tube receives the first voltage, the control end of the seventh switch tube and the control end of the eleventh switch tube are respectively connected to a first node between the eighth switch tube and the ninth switch tube, the control end of the eighth switch tube and the control end of the tenth switch tube are respectively connected to a second node between the eleventh switch tube and the twelfth switch tube, and the second node provides the output voltage. The voltage amplitude of the control voltage is greater than the threshold voltages of the ninth switch tube and the twelfth switch tube.

9. The circuit according to claim 1, wherein: The control voltage includes a complementary first voltage and a second voltage, and the level conversion circuit includes: A current mirror circuit includes a third branch and a fourth branch; a seventh switch tube, connected to the third branch, the seventh switch tube being controlled by the second voltage; and an eighth switch tube, connected to the fourth branch, the eighth switch tube being controlled by the first voltage, The voltage amplitude of the control voltage is greater than the threshold voltages of the seventh switch tube and the eighth switch tube.

10. The circuit of claim 1, wherein: The control voltage includes a complementary first voltage and a second voltage, and the level conversion circuit includes: A current mirror circuit includes a third branch and a fourth branch; a seventh switch tube, connected to the third branch, and the seventh switch tube is controlled by the second voltage; an eighth switch tube, connected to the fourth branch, the eighth switch tube being controlled by the first voltage; and a ninth switch tube, connected between the second power supply and the third branch, or connected between the third branch and the seventh switch tube, and controlled by the output voltage, Wherein, when the output voltage is at a high level, the ninth switch tube is turned off. The voltage amplitude of the control voltage is greater than the threshold voltages of the seventh switch tube and the eighth switch tube.

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