Analog-to-digital conversion circuits, analog-to-digital conversion methods, chips and electronic devices

Abstract

This application discloses an analog-to-digital (ADC) conversion circuit, an ADC conversion method, a chip, and an electronic device. The ADC circuit, used as a cyclic approximation ADC, includes a capacitor degradation amplifier, a digital-to-analog (D / A) converter, a comparator, a first switched-capacitor circuit, and a second switched-capacitor circuit. The D / A converter is connected to the comparator, the first switched-capacitor circuit, and the second switched-capacitor circuit, respectively. The comparator is connected to both the first and second switched-capacitor circuits. The capacitor degradation amplifier is connected to both the first and second switched-capacitor circuits. The cyclic approximation ADC is implemented based on an open-loop capacitor degradation amplifier, and low-power technologies such as charge sharing are applied to significantly reduce the power consumption of the cyclic approximation ADC while ensuring high linearity.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, specifically to an analog-to-digital conversion circuit, an analog-to-digital conversion method, a chip, and an electronic device. Background Technology

[0002] Cyclic ADCs are among the fastest types of ADCs, suitable for applications requiring rapid measurements. They can also be combined with Sigma delta ADCs to form hybrid structures, reducing the number of conversion cycles for high-precision measurements. Cyclic ADCs offer high circuit reusability and low hardware requirements, making them widely used in image sensors, biomedical sensors, and other fields. Considering heat generation and power consumption, on-chip circuit design must minimize power consumption, necessitating optimization of the cyclic ADCs integrated within the on-chip circuitry. Summary of the Invention

[0003] The main technical problem addressed in this application is how to reduce power consumption while maintaining high linearity in a cyclic approximation analog-to-digital converter.

[0004] According to a first aspect, in one embodiment of this application, an analog-to-digital conversion circuit is provided for use as a cyclic approximation analog-to-digital converter, including a capacitor degradation amplifier, a digital-to-analog converter, a comparator, a first switched capacitor circuit, and a second switched capacitor circuit.

[0005] The digital-to-analog converter includes a first conversion connection terminal, a second conversion connection terminal, a first comparison connection terminal, a first switch control connection terminal, and a second switch control connection terminal; the first conversion connection terminal and the second conversion connection terminal of the digital-to-analog converter are used as input and output connection terminals of the analog-to-digital conversion circuit, respectively for a preset first reference voltage V. refp Second reference voltage V refn The input; the first comparison connection terminal of the digital-to-analog converter is connected to the comparator; the first switch control connection terminal and the second switch control connection terminal of the digital-to-analog converter are respectively connected to the first switched capacitor circuit and the second switched capacitor circuit;

[0006] The comparator includes a first connection terminal, a second connection terminal, and a third connection terminal; the first connection terminal and the second connection terminal of the comparator are respectively connected to the first switched capacitor circuit and the second switched capacitor circuit; the third connection terminal of the comparator is connected to the first comparison connection terminal of the digital-to-analog converter.

[0007] The capacitor degradation amplifier includes a positive input connection terminal, a negative input connection terminal, a positive output connection terminal, and a negative output connection terminal; the positive input connection terminal and the negative output connection terminal of the capacitor degradation amplifier are connected to the first switched capacitor circuit, and the negative input connection terminal and the positive output connection terminal of the capacitor degradation amplifier are connected to the second switched capacitor circuit.

[0008] In one embodiment, the capacitor degradation amplifier includes a first switch Φ CS11 Second switch Φ CS21 Third switch Φ A11 Fourth switch Φ A21 Fifth switch Φ A12 Sixth switch Φ A21 Seventh switch Φ CS12 Eighth switch Φ CS22 First capacitor C DEG1 Second capacitor C DEG2 First transistor M A11 Second transistor M A21 Third transistor M A12 Fourth transistor M A22 First node V SP11 Second node V SP21 Third node V SP12 Fourth node V SP22 and degradation switch S R ;

[0009] The first transistor M A11 and the third transistor M A12 The control electrode serves as the positive input connection terminal of the capacitor degradation amplifier; the second transistor M A21 and the fourth transistor M A22 The control electrode serves as the negative input connection terminal of the capacitor degradation amplifier, and the degradation switch S R The two ends are respectively used as the positive output connection terminal and the negative output connection terminal of the capacitor degradation amplifier;

[0010] The first transistor M A11 The second electrode and the third transistor M A12 The second terminal connection, the second transistor M A21 The second electrode and the fourth transistor M A22 The second pole connection;

[0011] The first switch Φ CS11 One end is used for the working power supply V DD The input is connected to the first node V at the other end. SP11 Connection; the second switch Φ CS21 One end is used for the operating voltage VDD The input is connected to the second node V at the other end. SP21 Connection; the third switch Φ A11 One end is connected to the first node V SP11 The other end is connected to the first transistor M. A11 The first pole connection; the fourth switch Φ A21 One end is connected to the second node V SP21 The other end is connected to the second transistor M. A21 The first pole connection;

[0012] The fifth switch Φ A12 One end is connected to the third transistor M A12 The first pole is connected, and the other end is connected to the third node V. SP12 Connection; the sixth switch Φ A21 One end is connected to the fourth transistor M A22 The first pole is connected, and the other end is connected to the fourth node V. SP22 Connection; the seventh switch Φ CS12 One end is connected to the third node V SP12 Connect one end to the ground; the eighth switch Φ CS22 One end is connected to the fourth node V SP22 Connect one end to the ground;

[0013] The first capacitor C DEG1 One end is connected to the second node V SP21 The other end is connected to the third node V. SP12 Connection; the second capacitor C DEG2 One end is connected to the first node V SP11 The other end is connected to the fourth node V. SP22 connect;

[0014] The degradation switch S R One end is connected to the first transistor M A11 The second terminal is connected, and the other end is connected to the second transistor M. A21 The second pole connection.

[0015] In one embodiment, the first switched capacitor circuit and the second switched capacitor circuit each include an analog input first connection terminal, a converter connection terminal, a comparator connection terminal, an amplification first connection terminal, an amplification second connection terminal, and a third capacitor C. ref Fourth capacitor C s Fifth capacitor C L First capacitor switch Φ A0 Second capacitor switch Φ re Third capacitor switch Φ S_BAR Fourth capacitor switch ΦCS1 Fifth capacitor switch Φ COM The sixth capacitor switch Φ A1 The seventh capacitor switch Φ CS2 Eighth capacitor switch Φ A2 Ninth capacitor switch Φ CS3 10th Capacitor Switch Φ CS4 Eleventh Capacitor Switch Φ A3 12th Capacitor Switch Φ CS5 First capacitor node V CK0 Second capacitor node V CK1 Third capacitor node V CK2 Fourth capacitor node V CK3 Fifth capacitor node V CK4 The sixth capacitor node V CK5 and voltage conversion node V CM ;

[0016] The voltage conversion node V CM Used as a connection node for a reference common-mode voltage signal;

[0017] The first analog input connection terminal is used as an analog signal V. BN / P Input;

[0018] The converter connection terminal is connected to the digital-to-analog converter;

[0019] The comparator connection terminal is connected to the comparator;

[0020] The first amplification connection terminal and the second amplification connection terminal are respectively connected to the positive input connection terminal and the negative output connection terminal of the capacitor degradation amplifier, or to the negative input connection terminal and the positive output connection terminal of the capacitor degradation amplifier;

[0021] The first capacitor switch Φ A0 One end is connected to the amplified second connection end, and the other end is connected to the fifth capacitor node V. CK4 Connection; the second capacitor switch Φ re One end is connected to the fifth capacitor node V CK4 The other end is connected to the voltage conversion node V. CM Connection; the third capacitor switch Φ S_BAR One end is connected to the fifth capacitor node V CK4 One end is connected to the comparator connection terminal; the fourth capacitor switch Φ CS1 One end is connected to the comparator connection terminal, and the other end is connected to the fourth capacitor node V. CK3 Connection; the fifth capacitor switch Φ COM One end is connected to the fourth capacitor node V CK3The other end is connected to the third capacitor node V. CK2 Connection; the sixth capacitor switch Φ A1 One end is connected to the fourth capacitor node V CK3 The first end of the connector is connected to the second end, and the second end is connected to the amplified first connection end; the seventh capacitor switch Φ CS2 One end is connected to the third capacitor node V CK2 The other end is connected to the voltage conversion node V. CM Connection; the eighth capacitor switch Φ A2 One end is connected to the third capacitor node V CK2 The other end is connected to the second capacitor node V. CK1 Connection; the ninth capacitor switch Φ CS3 One end is connected to the converter connection terminal, and the other end is connected to the second capacitor node V. CK1 Connection; the tenth capacitor switch Φ CS4 One end is connected to the voltage conversion node V CM The other end is connected to the first capacitor node V. CK0 Connection; the eleventh capacitor switch Φ A3 One end is connected to the first capacitor node V CK0 One end is connected to the first connection terminal of the analog input; the twelfth capacitor switch Φ CS5 One end is connected to the first analog input connection terminal, and the other end is connected to the first amplification connection terminal;

[0022] The third capacitor C ref One end is connected to the first capacitor node V CK0 The other end is connected to the second capacitor node V. CK1 Connection; the fourth capacitor C s One end is connected to the third capacitor node V CK2 The other end is connected to the fourth capacitor node V. CK3 Connection; the fifth capacitor C L One end is connected to the voltage conversion node V CM The other end is connected to the fifth capacitor node V. CK4 connect.

[0023] In one embodiment, the first switched capacitor circuit and the second switched capacitor circuit further include an analog input second connection terminal and a sixth capacitor C, respectively. S_pre Thirteenth Capacitor Switch Φ S Fourteenth capacitor switch Φ S_pre The fifteenth capacitor switch Φ S_pre_BAR and the sixth capacitor node V CK5 ;

[0024] The second analog input terminal is used as the analog first input signal V. inp Or simulate the second input signal V inn Input;

[0025] The sixth capacitor C S_pre One end is connected to the voltage conversion node V CM The other end is connected to the sixth capacitor node V. CK5 connect;

[0026] The thirteenth capacitor switch Φ S One end is connected to the comparator connection terminal, and the other end is connected to the sixth capacitor node V. CK5 connect;

[0027] The fourteenth capacitor switch Φ S_pre One end is connected to the sixth capacitor node V CK5 One end is connected to the analog input second connection terminal;

[0028] The fifteenth capacitor switch Φ S_pre_BAR One end is connected to the sixth capacitor node V CK5 The other end is connected to the voltage conversion node V. CM connect.

[0029] In one embodiment, the first capacitor C DEG1 The second capacitor C DEG2 The third capacitor C ref The fourth capacitor C s The fifth capacitor C L and the sixth capacitor C S_pre The ratio of capacitance values ​​is a preset fixed value.

[0030] In one embodiment, the digital-to-analog converter further includes a second comparison connection terminal, which is connected to the comparator;

[0031] The comparator further includes a fourth connection terminal, which is connected to the second comparison connection terminal of the digital-to-analog converter;

[0032] The digital-to-analog converter is used to convert the 1.5-bit digital signal output by the comparator into an analog signal.

[0033] In one embodiment, the comparator includes a first comparator circuit and a second comparator circuit;

[0034] The first comparison circuit and the second comparison circuit each include a first input connection terminal, a second input connection terminal, and a comparison output terminal;

[0035] The first input connection terminal and the second input connection terminal of the first comparator circuit are respectively connected to the first switched capacitor circuit and the second switched capacitor circuit, and the comparator output terminal of the first comparator circuit is connected to the first comparator connection terminal of the digital-to-analog converter.

[0036] The first input connection terminal and the second input connection terminal of the second comparison circuit are respectively connected to the first switched capacitor circuit and the second switched capacitor circuit, and the comparison output terminal of the second comparison circuit is connected to the second comparison connection terminal of the digital-to-analog converter.

[0037] According to a second aspect, in one embodiment of this application, an analog-to-digital conversion method is provided, applied to the analog-to-digital conversion circuit as described in the first aspect, the analog-to-digital conversion method comprising:

[0038] When the capacitor degradation amplifier is operating in the amplification phase, the degradation switch S R Disconnected, while the degradation switch S is in the off phase when the capacitor degradation amplifier is operating. R Closed conduction.

[0039] According to a third aspect, in one embodiment of this application, a chip is provided, including the analog-to-digital conversion circuit as described in the first aspect.

[0040] According to a fourth aspect, an electronic device is provided in one embodiment of this application, including the chip as described in the third aspect.

[0041] Based on the analog-to-digital converter circuit in the above embodiments, a cyclic approximation analog-to-digital converter is realized using an open-loop capacitor degradation amplifier. Low-power technologies such as charge sharing are applied to greatly reduce the power consumption of the cyclic approximation analog-to-digital converter while ensuring high linearity. Attached Figure Description

[0042] Figure 1 This is a schematic diagram of the structural connection of an analog-to-digital converter circuit in one embodiment;

[0043] Figure 2 This is a schematic diagram of the circuit connection of a capacitor degradation amplifier in one embodiment;

[0044] Figure 3 This is a schematic diagram of the circuit connection of the first switched capacitor circuit and the second switched capacitor circuit in one embodiment.

[0045] Figure 4 This is a circuit diagram of a capacitor degradation amplifier;

[0046] Figure 5 This is a schematic diagram of the linear amplification characteristics of a capacitor-degraded amplifier.

[0047] Figure 6This is a schematic diagram illustrating the effect of the drain parasitic capacitance of a capacitor-degraded amplifier on the output signal.

[0048] Figure 7 Schematic diagram of the input voltage compression circuit;

[0049] Figure 8 This is a diagram illustrating the compression of the input voltage value.

[0050] Figure 9 This is a timing diagram of a cyclic approximation analog-to-digital converter in one embodiment. Detailed Implementation

[0051] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings. Similar elements in different embodiments are referred to by associated similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of this application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to this application are not shown or described in the specification. This is to avoid obscuring the core parts of this application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0052] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0053] The serial numbers assigned to components herein, such as "first," "second," etc., are solely for distinguishing the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages). The terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0054] In the description of the embodiments of this application, the words "example" or "for example" are used to indicate exemplification, illustration, or description. Any embodiment or design described as "example" or "for example" in the embodiments of this application is not to be construed as being better or having more advantages than another embodiment or design. The use of the words "example" or "for example" is intended to present relative concepts in a clear manner. "Multiple" in the embodiments of this application refers to two or more, and thus, "multiple" can also be understood as "at least two" in the embodiments of this application. "At least one" can be understood as one or more, for example, one, two, or more. For example, including at least one means including one, two, or more, and is not limited to which ones are included. For example, including at least one of A, B, and C, then it can include A, B, C, A and B, A and C, B and C, or A and B and C.

[0055] It is important to note that in this application's embodiments, "and / or" describes the association relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. The character " / ", unless otherwise specified, generally indicates that the preceding and following related objects have an "or" relationship. In this application's embodiments, "connection" can be understood as an electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.

[0056] In the embodiments of this application, the first terminal / first end of each transistor is one of the source and the drain, and the second terminal / second end of each transistor is the other of the source and the drain. Since the source and drain of a transistor can be structurally symmetrical, they can be structurally indistinguishable. That is, the first terminal / first end and the second terminal / second end of the transistor in the embodiments of this application can be structurally indistinguishable. For example, when the transistor is a P-type transistor, the first terminal / first end is the source, and the second terminal / second end is the drain; for example, when the transistor is an N-type transistor, the first terminal / first end is the drain, and the second terminal / second end is the source.

[0057] A typical cyclic approximation analog-to-digital converter (ADC) includes a sample-and-hold circuit, an operational amplifier, a comparator, and a digital-to-analog converter (DAC). The operational amplifier is the key module for implementing cyclic operational logic and accounts for a significant portion of the power consumption. Therefore, optimizing a cyclic approximation ADC requires prioritizing the optimization of the amplifier circuit. Open-loop amplifiers offer a significant advantage in low power consumption compared to traditional op-amps, but their linearity is greatly limited by variations in transconductance. Capacitor degradation amplifiers, on the other hand, do not depend on the transconductance stability of transistors and exhibit high linearity.

[0058] In this embodiment, a multi-bit Cyclic ADC is implemented based on an open-loop capacitor degradation amplifier. At the same time, low-power techniques such as charge sharing are used in the loop, which greatly reduces the power consumption of the Cyclic ADC while ensuring high linearity.

[0059] Example 1:

[0060] Please refer to Figure 1 This is a schematic diagram of the structural connection of an analog-to-digital conversion circuit in one embodiment. The circuit serves as a cyclic approximation analog-to-digital converter and includes a capacitor degradation amplifier 10, a digital-to-analog converter 30, a comparator 20, a first switched-capacitor circuit 40, and a second switched-capacitor circuit 50. The digital-to-analog converter 30 includes a first conversion connection terminal, a second conversion connection terminal, a first comparator connection terminal, a first switch control connection terminal, and a second switch control connection terminal. The first and second conversion connection terminals of the digital-to-analog converter 30 serve as the input and output connection terminals of the analog-to-digital conversion circuit, respectively used for a preset first reference voltage V. refp Second reference voltage V refn The input is provided. The first comparison connection terminal of the digital-to-analog converter 30 is connected to the comparator 20, and the first and second switch control connection terminals of the digital-to-analog converter 30 are respectively connected to the first switched capacitor circuit 40 and the second switched capacitor circuit 50. The digital-to-analog converter 30 is used to convert the digital signal output by the comparator 20 into an analog signal, and output the converted analog signal to the first switched capacitor circuit 40 and the second switched capacitor circuit 50. The comparator 20 includes a first connection terminal, a second connection terminal, and a third connection terminal. The first and second connection terminals of the comparator 20 are respectively connected to the first switched capacitor circuit 40 and the second switched capacitor circuit 50, and the third connection terminal of the comparator 20 is connected to the first comparison connection terminal of the digital-to-analog converter 30. The capacitor degradation amplifier 10 includes a positive input connection terminal, a negative input connection terminal, a positive output connection terminal, and a negative output connection terminal. The positive input connection terminal and the negative output connection terminal of the capacitor degradation amplifier 10 are connected to the first switched capacitor circuit 40, and the negative input connection terminal and the positive output connection terminal of the capacitor degradation amplifier 10 are connected to the second switched capacitor circuit 50.

[0061] Please refer to Figure 2 This is a circuit connection diagram of a capacitor degradation amplifier in one embodiment. The capacitor degradation amplifier includes a first switch Φ. CS11 Second switch Φ CS21 Third switch Φ A11 Fourth switch Φ A21 Fifth switch Φ A12 Sixth switch Φ A21 Seventh switch Φ CS12 Eighth switch Φ CS22 First capacitor C DEG1 Second capacitor C DEG2 First transistor M A11 Second transistor M A21 Third transistor M A12 Fourth transistor M A22 First node V SP11 Second node V SP21 Third node V SP12 Fourth node V SP22 and degradation switch S R .

[0062] First transistor M A11 and the third transistor M A12 The control terminal is connected as the positive input terminal of the capacitor degradation amplifier 10, and the second transistor M A21 and the fourth transistor M A22 The control electrode is connected as the negative input terminal of the capacitor degradation amplifier 10, and the degradation switch S R The two ends are respectively used as the positive output connection terminal and the negative output connection terminal of the capacitor degradation amplifier 10.

[0063] First transistor M A11 The second and third transistors M A12 The second terminal connection, the second transistor M A21 The second electrode and the fourth transistor M A22 The second pole connection. First switch Φ CS11 One end is used for the working power supply V DD The input is connected to the first node V at the other end. SP11 Connection. Second switch Φ CS21 One end is used for the working voltage V DD The input is connected to the second node V at the other end. SP21 Connection. Third switch Φ A11 One end is connected to the first node V SP11 The other end is connected to the first transistor M. A11 The first pole connection. The fourth switch Φ A21 One end and the second node V SP21 The other end is connected to the second transistor M.A21 The first pole connection. The fifth switch Φ A12 One end is connected to the third transistor M A12 The first pole is connected, and the other end is connected to the third node V. SP12 Connection. Sixth switch Φ A21 One end is connected to the fourth transistor M A22 The first pole is connected, and the other end is connected to the fourth node V. SP22 Connection. Seventh switch Φ CS12 One end and the third node V SP12 Connect one end to the ground. The eighth switch Φ CS22 One end and the fourth node V SP22 Connect one end to the ground, and ground the other end. First capacitor C DEG1 One end and the second node V SP21 Connect the other end to the third node V. SP12 Connection. Second capacitor C DEG2 One end is connected to the first node V SP11 Connect the other end to the fourth node V. SP22 Connection. Degradation switch S R One end is connected to the first transistor M A11 The second terminal is connected, and the other end is connected to the second transistor M. A21 The second pole connection. When the capacitor degenerate amplifier 10 is operating in the amplification stage, the degenerate switch S R Disconnected, while the degradation switch S is in the off phase when the capacitor degradation amplifier 10 is operating. R Closed conduction.

[0064] Please refer to Figure 3 This is a schematic diagram of the circuit connection of the first switched capacitor circuit and the second switched capacitor circuit in one embodiment. In one embodiment, the first switched capacitor circuit 40 and the second switched capacitor circuit 50 respectively include an analog input first connection terminal, a converter connection terminal, a comparator connection terminal, an amplification first connection terminal, an amplification second connection terminal, and a third capacitor C. ref Fourth capacitor C s Fifth capacitor C L First capacitor switch Φ A0 Second capacitor switch Φ re Third capacitor switch Φ S_BAR Fourth capacitor switch Φ CS1 Fifth capacitor switch Φ COM The sixth capacitor switch Φ A1 The seventh capacitor switch Φ CS2 Eighth capacitor switch Φ A2 Ninth capacitor switch Φ CS3 10th Capacitor Switch Φ CS4 Eleventh Capacitor Switch Φ A3 12th Capacitor Switch ΦCS5 First capacitor node V CK0 Second capacitor node V CK1 Third capacitor node V CK2 Fourth capacitor node V CK3 Fifth capacitor node V CK4 The sixth capacitor node V CK5 and voltage conversion node V CM Voltage conversion node V CM This is used as a connection node for a reference common-mode voltage signal. BN / P The input of the converter is connected to the digital-to-analog converter 30, the comparator is connected to the comparator 20, and the first and second amplification terminals are connected to the positive input and negative output terminals of the capacitor degradation amplifier 10, respectively, or to the negative input and positive output terminals of the capacitor degradation amplifier 10. The first capacitor switch Φ A0 One end is connected to the second amplification terminal, and the other end is connected to the fifth capacitor node V. CK4 Connection. Second capacitor switch Φ re One end is connected to the fifth capacitor node V CK4 Connect the other end to the voltage conversion node V. CM Connection. Third capacitor switch Φ S_BAR One end is connected to the fifth capacitor node V CK4 Connect one end to the comparator terminal, and the other end to the comparator terminal. Fourth capacitor switch Φ CS1 One end is connected to the comparator connection terminal, and the other end is connected to the fourth capacitor node V. CK3 Connection. Fifth capacitor switch Φ COM One end is connected to the fourth capacitor node V CK3 Connect the other end to the third capacitor node V. CK2 Connection. Sixth capacitor switch Φ A1 One end is connected to the fourth capacitor node V CK3 Connect one end to the first amplification terminal, and the other end to the first connection terminal. Seventh capacitor switch Φ CS2 One end is connected to the third capacitor node V CK2 Connect the other end to the voltage conversion node V. CM Connection. Eighth capacitor switch Φ A2 One end is connected to the third capacitor node V CK2 Connect the other end to the second capacitor node V. CK1 Connection. Ninth capacitor switch Φ CS3 One end is connected to the converter connection terminal, and the other end is connected to the second capacitor node V. CK1 Connection. Tenth capacitor switch Φ CS4 One end is connected to the voltage conversion node V CM Connect the other end to the first capacitor node V. CK0Connection. Eleventh capacitor switch Φ A3 One end is connected to the first capacitor node V CK0 Connect one end to the analog input first connection terminal. Twelfth capacitor switch Φ CS5 One end of the capacitor is connected to the first analog input terminal, and the other end is connected to the first amplification terminal. The third capacitor C... ref One end is connected to the first capacitor node V CK0 Connect the other end to the second capacitor node V. CK1 Connection. Fourth capacitor C. s One end is connected to the third capacitor node V CK2 Connect the other end to the fourth capacitor node V. CK3 Connection. Fifth capacitor C L One end is connected to the voltage conversion node V CM Connect the other end to the fifth capacitor node V. CK4 Connection. In one embodiment, the first switched capacitor circuit 40 and the second switched capacitor circuit 50 respectively further include an analog input second connection terminal and a sixth capacitor C. S_pre Thirteenth Capacitor Switch Φ S Fourteenth capacitor switch Φ S_pre The fifteenth capacitor switch Φ S_pre_BAR and the sixth capacitor node V CK5 The second analog input terminal is used as the analog first input signal V. inp (like Figure 3 As shown, the analog input signal of the first switched capacitor circuit 40 or the analog second input signal V inn Input (such as) Figure 3 As shown, the analog input signal of the second switched capacitor circuit 50). The sixth capacitor C S_pre One end is connected to the voltage conversion node V CM Connect the other end to the sixth capacitor node V. CK5 Connection. Thirteenth capacitor switch Φ S One end is connected to the comparator connection terminal, and the other end is connected to the sixth capacitor node V. CK5 Connection. Fourteenth capacitor switch Φ S_pre One end is connected to the sixth capacitor node V CK5 Connect one end to the analog input second connection terminal. The fifteenth capacitor switch Φ S_pre_BAR One end is connected to the sixth capacitor node V CK5 Connect the other end to the voltage conversion node V. CM connect.

[0065] In one embodiment, the first capacitor C DEG1 Second capacitor C DEG2 Third capacitor C ref Fourth capacitor C sFifth capacitor C L and the sixth capacitor C S_pre The ratio of capacitance values ​​is a preset fixed value.

[0066] In one embodiment, such as Figure 1 As shown, the digital-to-analog converter 30 further includes a second comparison connection terminal, which is connected to the comparator 20. The comparator 20 also includes a fourth connection terminal, which is connected to the second comparison connection terminal of the digital-to-analog converter 30. The digital-to-analog converter 30 is used to convert the digital signal output by the comparator 20 into an analog signal, and the comparator 20 is used to convert a continuous analog signal into a 1.5-bit digital signal in each cycle. In one embodiment, the comparator 20 includes a first comparison circuit and a second comparison circuit. The first comparison circuit and the second comparison circuit each include a first input connection terminal, a second input connection terminal, and a comparison output terminal. The first input connection terminal and the second input connection terminal of the first comparison circuit are respectively connected to the first switched capacitor circuit 40 and the second switched capacitor circuit 50, and the comparison output terminal of the first comparison circuit is connected to the first comparison connection terminal of the digital-to-analog converter 30. The first input connection terminal and the second input connection terminal of the second comparison circuit are respectively connected to the first switched capacitor circuit 40 and the second switched capacitor circuit 50, and the comparison output terminal of the second comparison circuit is connected to the second comparison connection terminal of the digital-to-analog converter 30.

[0067] To facilitate understanding of the application of a degraded capacitor amplifier in a Cyclic ADC in this embodiment, replacing the traditional closed-loop operational amplifier to implement cyclic operation functions, the degraded capacitor amplifier has been improved to enhance the ADC's performance. The following provides a detailed description of both the implementation of the degraded capacitor amplifier and the implementation of the Cyclic ADC, specifically including:

[0068] Please refer to Figure 4 This is a circuit diagram of a capacitor degradation amplifier, and... Figure 2 Compared to the circuit of the capacitor degradation amplifier in the middle, excluding the degradation switch S R However, it is also connected to external circuits (first switched capacitor circuit 40 and second switched capacitor circuit 50), wherein capacitor C L1 Capacitor switch Φ RE1 and voltage conversion node V cm13 The fifth capacitor C in the first switched capacitor circuit 40 L Second capacitor switch Φ re and voltage conversion node V CM Capacitor C L2 Capacitor switch Φ RE2 and voltage conversion node V cm23 The fifth capacitor C of the second switched capacitor circuit 50 L Second capacitor switch Φre and voltage conversion node V CM .

[0069] Please refer to Figure 5 , is a schematic diagram of the linear amplification characteristics of a capacitor-degraded amplifier, where A opt For linear amplification factor, t opt For the first capacitor switch Φ A0 The duration of linear amplification during conduction, according to the MOSFET subthreshold current formula and charge conservation, t opt The formula for obtaining it is:

[0070] ;

[0071] The linear amplification factor A varies with the input signal size. opt =2C DEG / nC L Among them, capacitor C DEG The first capacitor C DEG1 Or the second capacitor C DEG2 The capacitance value, C L The fifth capacitor C L The value of .

[0072] like Figure 5 The linear amplification characteristics shown can meet the multiplication operation requirements in a Cyclic ADC. Simulations of the ADC's duty cycle revealed a brief and rapid charging process in the initial stage of the capacitor-degraded amplifier's output curve.

[0073] Please refer to Figure 6 This diagram illustrates the effect of the drain parasitic capacitance of a capacitor-degraded amplifier on the output signal, where capacitor C... D1 Parasitic capacitance can cause a decrease in the linearity of an amplifier. This phenomenon is caused by the parasitic capacitance C of the drain of the MOSFET. D1 The charge stored on it causes the first capacitor switch Φ to switch during the amplification stage. A0 When conduction ends, the switch between the transistor, power supply, and load is opened, and the drain voltage remains at the value at the end of the previous amplification cycle. When the switch closes in the next cycle, the parasitic capacitance C... D1 The stored charge is first released to the fifth capacitor C, which acts as the load capacitor. L This violates the charge conservation principle during the amplification stage.

[0074] Please refer to Figure 7 and Figure 8 This is a schematic diagram of the input voltage compression circuit and a schematic diagram of input voltage value compression. Figure 3The analog-to-digital converter circuit shown performs comparison, multiplication by 2, and addition or subtraction of a reference voltage on the signal to determine one bit of output per cycle. The proposed ADC employs two comparators and implements a 1.5-bit-per-cycle algorithm, which significantly reduces the accuracy requirements of the comparators. The differential push-pull capacitor degenerate amplifier has four inputs; for simplicity, only one representative input from each differential side is shown. The capacitor degenerate amplifier connects to a fifth capacitor C before the output signal is fully stabilized. L Disconnecting the capacitor results in a linearly amplified output signal, which is then stored in the fifth capacitor C. L The charge on the capacitor is represented by a charge on the capacitor and is not driven by a stable voltage. Therefore, in order to perform subsequent signal processing and feed the signal back to the input of the next cycle, charge transfer and sharing are required between different capacitors. In one embodiment, the amplifier first amplifies the signal by 4 times, and then switches the fifth capacitor C... L The fourth capacitor C of the same size s Parallel connection is used to achieve charge sharing, ultimately generating a signal twice the size of the original signal, which serves as the input for the next cycle. For example... Figure 2 As shown, V is input to the positive input terminal, negative input terminal, positive output terminal, and negative output terminal of the capacitor degradation amplifier 10, respectively. BP +V in_duff / 2 V BN +V in_duff / 2 V BP +V in_duff / 2 and V BN +V in_duff / 2 Add or subtract V ref Traditional adders rely on stable voltage drives for operation, which is unsuitable for charge-mode signals. Considering the additional switching count and timing complexity resulting from adding charge sharing again, this invention employs a series capacitor structure to implement voltage signal addition. During the comparison phase, V is added or subtracted... ref Stored in the form of charge in capacitor C ref Up, and through capacitor C ref and capacitor C s Voltage addition is achieved by connecting them in series.

[0075] The input range of a capacitor-degraded amplifier is limited by subthreshold operating conditions, therefore the input voltage needs to be scaled to match the amplifier's input range. In one embodiment of this application, charge-sharing technology is used to achieve this. Figure 7 As shown, in the pre-sampling stage, the input voltage is first sampled from the capacitor C. S_pre Then, through the parallel capacitor C s By implementing charge sharing, the input voltage is reduced to one-fifth of its original value, thus achieving an input voltage range of ±3V. Within one ADC cycle, except for the first capacitor C...DEG1 Or the second capacitor C DEG2 Outside of the charging phase, all circuit operations are completed through charge transfer and sharing, thus achieving zero static power consumption.

[0076] Please refer to Figure 9 This is a timing diagram of a cyclic approximation analog-to-digital converter in one embodiment, showing the timing of the capacitor switch Φ. S_pre During the (presampling) phase, the input signal is sampled and stored in the presampling capacitor C. S_pre Above. Capacitor switch Φ S This is the sampling phase. During this phase, the capacitance C... S_pre Through the switch and capacitor C S The connection enables charge sharing. This operation reduces the input voltage to one-fifth of its original value. Capacitor switch Φ A Stage (including capacitor switch Φ) A0 Capacitor switch Φ A1 Capacitor switch Φ A2 and capacitor switch Φ A3 This is the amplification stage, and the capacitor C... ref and capacitor C s The series connection, capacitor C ref The lower plate is connected to the bias voltage, shifting the input signal to the bias voltage baseline. The capacitor degrades, and the amplifier's internal transistor turns on, putting the circuit into amplification mode. At the capacitor switch Φ... com During the comparison phase, the amplifier's output is fed into the comparator to generate a 1.5-bit result. Simultaneously, this phase also clears capacitor C. s The charge on the capacitor switch Φ. CS (including capacitor switch Φ) CS1 Capacitor switch Φ CS2 Capacitor switch Φ CS3 Capacitor switch Φ CS4 and capacitor switch Φ CS5 During the charge sharing phase, the capacitance C L The charge on the capacitor is transferred to the capacitor C through the switch. S And capacitor C ref Connected to the output of the DAC, storing ±V ref Or a 0V voltage signal. Capacitor switch Φ re It occurred at the capacitor switch Φ CS and capacitor switch Φ A The reset phase between [the two points]. At the capacitor switch Φ re Stage, stored in floating capacitor C LThe charge on the circuit is cleared, preparing it for the next amplification cycle. In this embodiment, the timing stage ensures that the Cyclic ADC can accurately convert analog signals into digital signals, maintaining low power consumption and high linearity by utilizing a charge-sharing mechanism and accurate timing control.

[0077] In one embodiment of this application, an analog-to-digital conversion method is also disclosed, applied to the analog-to-digital conversion circuit described above. The method includes: when the capacitor degradation amplifier is operating in the amplification phase, the degradation switch S... R Disconnected, while the degradation switch S is in the off phase when the capacitor degradation amplifier is operating. R Closed conduction.

[0078] In one embodiment of this application, a chip is also disclosed, including the analog-to-digital conversion circuit described above.

[0079] An electronic device is also disclosed in one embodiment of this application, including the chip described above.

[0080] The analog-to-digital converter (ADC) circuit disclosed in this application is used as a cyclic approximation ADC, including a capacitor degradation amplifier, a digital-to-analog converter (DAC), a comparator, a first switched-capacitor circuit, and a second switched-capacitor circuit. The DAC is connected to the comparator, the first switched-capacitor circuit, and the second switched-capacitor circuit, respectively. The comparator is connected to both the first and second switched-capacitor circuits. The capacitor degradation amplifier is connected to both the first and second switched-capacitor circuits. The cyclic approximation ADC is implemented based on an open-loop capacitor degradation amplifier, and low-power technologies such as charge sharing are applied to significantly reduce the power consumption of the cyclic approximation ADC while ensuring high linearity.

[0081] The above examples illustrate the present invention only to aid in understanding it and are not intended to limit the scope of the invention. Those skilled in the art can make various simple deductions, modifications, or substitutions based on the principles of this invention.

Claims

1. An analog-to-digital converter circuit, characterized in that, Used as a cyclic approximation analog-to-digital converter, including a capacitor degradation amplifier, a digital-to-analog converter, a comparator, a first switched capacitor circuit, and a second switched capacitor circuit; The digital-to-analog converter includes a first conversion connection terminal, a second conversion connection terminal, a first comparison connection terminal, a first switch control connection terminal, and a second switch control connection terminal; the first conversion connection terminal and the second conversion connection terminal of the digital-to-analog converter are used as input and output connection terminals of the analog-to-digital conversion circuit, respectively for a preset first reference voltage V. refp Second reference voltage V refn The input; the first comparison connection terminal of the digital-to-analog converter is connected to the comparator; the first switch control connection terminal and the second switch control connection terminal of the digital-to-analog converter are respectively connected to the first switched capacitor circuit and the second switched capacitor circuit; The comparator includes a first connection terminal, a second connection terminal, and a third connection terminal; the first connection terminal and the second connection terminal of the comparator are respectively connected to the first switched capacitor circuit and the second switched capacitor circuit; the third connection terminal of the comparator is connected to the first comparison connection terminal of the digital-to-analog converter. The capacitor degradation amplifier includes a positive input connection terminal, a negative input connection terminal, a positive output connection terminal, and a negative output connection terminal; the positive input connection terminal and the negative output connection terminal of the capacitor degradation amplifier are connected to the first switched capacitor circuit, and the negative input connection terminal and the positive output connection terminal of the capacitor degradation amplifier are connected to the second switched capacitor circuit. The capacitor degradation amplifier includes a first switch Φ CS11 Second switch Φ CS21 Third switch Φ A11 Fourth switch Φ A21 Fifth switch Φ A12 Sixth switch Φ A21 Seventh switch Φ CS12 Eighth switch Φ CS22 First capacitor C DEG1 Second capacitor C DEG2 First transistor M A11 Second transistor M A21 Third transistor M A12 Fourth transistor M A22 First node V SP11 Second node V SP21 Third node V SP12 Fourth node V SP22 and degradation switch S R ; The first transistor M A11 and the third transistor M A12 The control electrode serves as the positive input connection terminal of the capacitor degradation amplifier; the second transistor M A21 and the fourth transistor M A22 The control electrode serves as the negative input connection terminal of the capacitor degradation amplifier, and the degradation switch S R The two ends are respectively used as the positive output connection terminal and the negative output connection terminal of the capacitor degradation amplifier; The first transistor M A11 The second electrode and the third transistor M A12 The second terminal connection, the second transistor M A21 The second electrode and the fourth transistor M A22 The second pole connection; The first switch Φ CS11 One end is used for the working power supply V DD The input is connected to the first node V at the other end. SP11 Connection; the second switch Φ CS21 One end is used for the working power supply V DD The input is connected to the second node V at the other end. SP21 Connection; the third switch Φ A11 One end is connected to the first node V SP11 The other end is connected to the first transistor M. A11 The first pole connection; the fourth switch Φ A21 One end is connected to the second node V SP21 The other end is connected to the second transistor M. A21 The first pole connection; The fifth switch Φ A12 One end is connected to the third transistor M A12 The first pole is connected, and the other end is connected to the third node V. SP12 Connection; the sixth switch Φ A21 One end is connected to the fourth transistor M A22 The first pole is connected, and the other end is connected to the fourth node V. SP22 Connection; the seventh switch Φ CS12 One end is connected to the third node V SP12 Connect one end to the ground; the eighth switch Φ CS22 One end is connected to the fourth node V SP22 Connect one end to the ground; The first capacitor C DEG1 One end is connected to the second node V SP21 The other end is connected to the third node V. SP12 Connection; the second capacitor C DEG2 One end is connected to the first node V SP11 The other end is connected to the fourth node V. SP22 connect; The degradation switch S R One end is connected to the first transistor M A11 The second terminal is connected, and the other end is connected to the second transistor M. A21 The second pole connection.

2. The analog-to-digital converter circuit as described in claim 1, characterized in that, The first switched-capacitor circuit and the second switched-capacitor circuit each include an analog input first connection terminal, a converter connection terminal, a comparator connection terminal, an amplification first connection terminal, an amplification second connection terminal, and a third capacitor C. ref Fourth capacitor C s Fifth capacitor C L First capacitor switch Φ A0 Second capacitor switch Φ re Third capacitor switch Φ S_BAR Fourth capacitor switch Φ CS1 Fifth capacitor switch Φ COM The sixth capacitor switch Φ A1 The seventh capacitor switch Φ CS2 Eighth capacitor switch Φ A2 Ninth capacitor switch Φ CS3 10th Capacitor Switch Φ CS4 Eleventh Capacitor Switch Φ A3 12th Capacitor Switch Φ CS5 First capacitor node V CK0 Second capacitor node V CK1 Third capacitor node V CK2 Fourth capacitor node V CK3 Fifth capacitor node V CK4 The sixth capacitor node V CK5 and voltage conversion node V CM ; The voltage conversion node V CM Used as a connection node for a reference common-mode voltage signal; The first analog input connection terminal is used as an analog signal V. BN / P Input; The converter connection terminal is connected to the digital-to-analog converter; The comparator connection terminal is connected to the comparator; The amplification first connection terminal and the amplification second connection terminal are respectively connected to the positive input connection terminal and the negative output connection terminal of the capacitor degradation amplifier, or to the negative input connection terminal and the positive output connection terminal of the capacitor degradation amplifier; The first capacitor switch Φ A0 One end is connected to the amplified second connection end, and the other end is connected to the fifth capacitor node V. CK4 Connection; the second capacitor switch Φ re One end is connected to the fifth capacitor node V CK4 The other end is connected to the voltage conversion node V. CM Connection; the third capacitor switch Φ S_BAR One end is connected to the fifth capacitor node V CK4 One end is connected to the comparator connection terminal; the fourth capacitor switch Φ CS1 One end is connected to the comparator connection terminal, and the other end is connected to the fourth capacitor node V. CK3 Connection; the fifth capacitor switch Φ COM One end is connected to the fourth capacitor node V CK3 The other end is connected to the third capacitor node V. CK2 Connection; the sixth capacitor switch Φ A1 One end is connected to the fourth capacitor node V CK3 The first end of the connector is connected to the second end, and the second end is connected to the amplified first connection end; the seventh capacitor switch Φ CS2 One end is connected to the third capacitor node V CK2 The other end is connected to the voltage conversion node V. CM Connection; the eighth capacitor switch Φ A2 One end is connected to the third capacitor node V CK2 The other end is connected to the second capacitor node V. CK1 Connection; the ninth capacitor switch Φ CS3 One end is connected to the converter connection terminal, and the other end is connected to the second capacitor node V. CK1 Connection; the tenth capacitor switch Φ CS4 One end is connected to the voltage conversion node V CM The other end is connected to the first capacitor node V. CK0 Connection; the eleventh capacitor switch Φ A3 One end is connected to the first capacitor node V CK0 One end is connected to the first connection terminal of the analog input; the twelfth capacitor switch Φ CS5 One end is connected to the first analog input connection terminal, and the other end is connected to the first amplification connection terminal; The third capacitor C ref One end is connected to the first capacitor node V CK0 The other end is connected to the second capacitor node V. CK1 Connection; the fourth capacitor C s One end is connected to the third capacitor node V CK2 The other end is connected to the fourth capacitor node V. CK3 Connection; the fifth capacitor C L One end is connected to the voltage conversion node V CM The other end is connected to the fifth capacitor node V. CK4 connect.

3. The analog-to-digital converter circuit as described in claim 2, characterized in that, The first switched capacitor circuit and the second switched capacitor circuit each further include a second analog input connection terminal and a sixth capacitor C. S_pre Thirteenth Capacitor Switch Φ S Fourteenth capacitor switch Φ S_pre The fifteenth capacitor switch Φ S_pre_BAR and the sixth capacitor node V CK5 ; The second analog input terminal is used as the analog first input signal V. inp Or simulate the second input signal V inn Input; The sixth capacitor C S_pre One end is connected to the voltage conversion node V CM The other end is connected to the sixth capacitor node V. CK5 connect; The thirteenth capacitor switch Φ S One end is connected to the comparator connection terminal, and the other end is connected to the sixth capacitor node V. CK5 connect; The fourteenth capacitor switch Φ S_pre One end is connected to the sixth capacitor node V CK5 One end is connected to the analog input second connection terminal; The fifteenth capacitor switch Φ S_pre_BAR One end is connected to the sixth capacitor node V CK5 The other end is connected to the voltage conversion node V. CM connect.

4. The analog-to-digital converter circuit as described in claim 3, characterized in that, The first capacitor C DEG1 The second capacitor C DEG2 The third capacitor C ref The fourth capacitor C s The fifth capacitor C L and the sixth capacitor C S_pre The ratio of capacitance values ​​is a preset fixed value.

5. The analog-to-digital converter circuit as described in claim 1, characterized in that, The digital-to-analog converter further includes a second comparison connection terminal, which is connected to the comparator. The comparator further includes a fourth connection terminal, which is connected to the second comparison connection terminal of the digital-to-analog converter.

6. The analog-to-digital converter circuit as described in claim 5, characterized in that, The comparator includes a first comparator circuit and a second comparator circuit; The first comparison circuit and the second comparison circuit each include a first input connection terminal, a second input connection terminal, and a comparison output terminal; The first input connection terminal and the second input connection terminal of the first comparator circuit are respectively connected to the first switched capacitor circuit and the second switched capacitor circuit, and the comparator output terminal of the first comparator circuit is connected to the first comparator connection terminal of the digital-to-analog converter. The first input connection terminal and the second input connection terminal of the second comparison circuit are respectively connected to the first switched capacitor circuit and the second switched capacitor circuit, and the comparison output terminal of the second comparison circuit is connected to the second comparison connection terminal of the digital-to-analog converter.

7. An analog-to-digital conversion method, characterized in that, The method, applied to the analog-to-digital converter circuit as described in any one of claims 1 to 6, comprises: When the capacitor degradation amplifier is operating in the amplification phase, the degradation switch S R Disconnected, while the degradation switch S is in the off phase when the capacitor degradation amplifier is operating. R Closed conduction.

8. A chip, characterized in that, Includes the analog-to-digital conversion circuit as described in any one of claims 1 to 6.

9. An electronic device, characterized in that, Includes the chip as described in claim 8.

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