Semiconductor device

Abstract

A semiconductor device may include: a first lower active contact; a first source / drain pattern on the first lower active contact; a second lower active contact; a second source / drain pattern on the second lower active contact; a lower conductive layer electrically connected to the first lower active contact and the second lower active contact; a third source / drain pattern and a fourth source / drain pattern between the first source / drain pattern and the second source / drain pattern; a first upper active contact on the third source / drain pattern; a second upper active contact on the fourth source / drain pattern; and an upper lead electrically connected to the first upper active contact and the second upper active contact. First to fourth source / drain patterns, first and second lower active contacts, and first and second upper active contacts may be disposed between the lower conductive layer and the upper conductive line.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims the priority of Korean Patent Application No. 10-2023-0162686 filed in the Korean Intellectual Property Office on November 21, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a semiconductor device, and in particular, to a semiconductor device including a static random access memory (SRAM) cell. Background Art

[0004] Semiconductor devices are regarded as important components in the electronics industry due to their small size, multifunctionality and / or low cost. Semiconductor devices are classified into semiconductor memory devices for storing data, semiconductor logic devices for processing data, and hybrid semiconductor devices including memory and logic elements. With the high development of the electronics industry, the demand for semiconductor devices with improved characteristics is increasing. For example, the demand for semiconductor devices with high reliability, high performance and / or multifunctionality is increasing. In order to meet these technical requirements, the complexity and / or integration density of semiconductor devices are increasing. Summary of the invention

[0005] The present disclosure provides a semiconductor device having improved electrical and reliability characteristics and a method of manufacturing the same.

[0006] A semiconductor device may include: a first lower active contact; a first source / drain pattern on the first lower active contact; a second lower active contact; a second source / drain pattern on the second lower active contact; a lower conductive layer electrically connected to the first lower active contact and the second lower active contact; a third source / drain pattern and a fourth source / drain pattern between the first source / drain pattern and the second source / drain pattern; a first upper active contact on the third source / drain pattern; a second upper active contact on the fourth source / drain pattern; and an upper conductive line electrically connected to the first upper active contact and the second upper active contact. The first to fourth source / drain patterns, the first and second lower active contacts, and the first and second upper active contacts may be disposed between the lower conductive layer and the upper conductive line.

[0007] A semiconductor device may include: a first source / drain pattern; a first lower active contact in contact with a lower portion of the first source / drain pattern; a second source / drain pattern; a second lower active contact in contact with a lower portion of the second source / drain pattern; a lower conductive layer electrically connected to the first lower active contact and the second lower active contact; a third source / drain pattern; a first upper active contact in contact with an upper portion of the third source / drain pattern; an upper conductive line electrically connected to the upper active contact; a fourth source / drain pattern; a second upper active contact in contact with an upper portion of the fourth source / drain pattern; and a first bit line electrically connected to the second upper active contact. The lower conductive layer may include: a first lower conductive part in contact with the first lower active contact; a second lower conductive part in contact with the second lower active contact; and a third lower conductive part connecting the first lower conductive part and the second lower conductive part to each other. The first lower conductive part may overlap with the first bit line, and the third lower conductive part may overlap with the upper conductive line.

[0008] A semiconductor device may include: a first lower insulating layer; a first word line and a second word line, which are arranged in the first lower insulating layer and extend in a first direction; a second lower insulating layer, which is on the first lower insulating layer; a first word line connection contact and a second word line connection contact, which are in the second lower insulating layer; a first lower conductive pattern, which is on the first word line connection contact; a second lower conductive pattern, which is on the second word line connection contact; a first insulating pattern, which surrounds the first lower conductive pattern; a second insulating pattern, which surrounds the second lower conductive pattern; a lower conductive layer, which is on the second lower insulating layer; a first lower active contact, which is on the lower conductive layer; a first source / drain pattern, which is on the first lower active contact; a second lower active contact, which is on the lower conductive layer; a second source / drain pattern, which is on the second lower active contact; a first lower gate contact, which is on the first lower conductive pattern; a first gate electrode, on the first lower gate contact; the second lower gate contact, on the second lower conductive pattern; the second gate electrode, on the second lower gate contact; the third source / drain pattern, adjacent to the first gate electrode; the first upper active contact, on the third source / drain pattern; the first bit line, electrically connected to the first upper active contact; the fourth source / drain pattern, adjacent to the second gate electrode; the second upper active contact, on the fourth source / drain pattern; the second bit line, electrically connected to the second upper active contact; the fifth source / drain pattern, adjacent to the first source / drain pattern in the first direction; the third upper active contact, on the fifth source / drain pattern; the sixth source / drain pattern, adjacent to the second source / drain pattern in the first direction; the fourth upper active contact, on the sixth source / drain pattern; and the upper conductive line, electrically connected to the third upper active contact and the fourth upper active contact. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is an equivalent circuit diagram illustrating an example static random access memory (SRAM) cell.

[0010] Figure 2A is a plan view showing word lines of an example semiconductor device.

[0011] Figure 2B is a plan view illustrating a lower conductive layer, a lower conductive pattern, and a word line connection pattern of an example semiconductor device.

[0012] Figure 2C is a plan view showing a source / drain pattern, a lower active contact, an upper active contact, a lower gate contact, an upper gate contact, and a gate electrode of an example semiconductor device.

[0013] Figure 2D is a plan view showing upper conductive lines and bit lines of an example semiconductor device.

[0014] Figure 2E is along FIG. 2A to FIG. 2D A cross-sectional view taken along line AA'.

[0015] Figure 2F is along FIG. 2A to FIG. 2D A cross-sectional view taken along line BB'.

[0016] Figure 2G is along FIG. 2A to FIG. 2D A cross-sectional view taken along line CC'.

[0017] Figure 3A , Figure 3B , Figure 3C , Figure 4A , Figure 4B , Figure 4C , Figure 5A , Figure 5B , Figure 5C , Fig. 6A , Figure 6B , Fig. 7A , Figure 7B and Figure 7C It shows the manufacturing Figures 2A to 2G A cross-sectional view of a method for a semiconductor device.

[0018] Fig. 8A and Figure 8B is a cross-sectional view showing an example semiconductor device.

[0019] Fig.9A and Fig. 9B is a cross-sectional view showing an example semiconductor device.

[0020] Fig. 10A is a plan view showing word lines of an example semiconductor device.

[0021] Fig. 10B is a plan view illustrating a lower conductive layer, a lower conductive pattern, and a word line connection pattern of an example semiconductor device.

[0022] Fig. 10C is a plan view showing a source / drain pattern, a lower active contact, an upper active contact, a lower gate contact, an upper gate contact, and a gate electrode of an example semiconductor device.

[0023] Fig. 10D is a plan view showing an upper conductive line, a bit line, a read word line, and a read bit line of a semiconductor device.

[0024] Fig.11A is a plan view showing a word line, a dummy line, and a read word line of a semiconductor device.

[0025] Fig. 11B is a plan view illustrating a lower conductive layer, a lower conductive pattern, and a word line connection pattern of an example semiconductor device.

[0026] Fig. 11C is a plan view showing a source / drain pattern, a lower active contact, an upper active contact, a lower gate contact, an upper gate contact, and a gate electrode of an example semiconductor device.

[0027] Fig.11D is a plan view showing an upper conductive line, a bit line, a read word line, a read bit line, and a dummy pattern of an example semiconductor device. DETAILED DESCRIPTION

[0028] Figure 1 is an equivalent circuit diagram showing a static random access memory (SRAM) cell.

[0029] Reference Figure 1 , the SRAM cell may include a first pull-up transistor PU1, a first pull-down transistor PD1, a second pull-up transistor PU2, a second pull-down transistor PD2, a first pass-gate transistor PG1, and a second pass-gate transistor PG2. In an embodiment, the first pull-up transistor PU1 and the second pull-up transistor PU2 may be PMOS transistors, and the first pull-down transistor PD1 and the second pull-down transistor PD2 and the first pass-gate transistor PG1 and the second pass-gate transistor PG2 may be NMOS transistors. In an embodiment, the first pull-up transistor PU1 and the second pull-up transistor PU2 and the first pass-gate transistor PG1 and the second pass-gate transistor PG2 may be PMOS transistors, and the first pull-down transistor PD1 and the second pull-down transistor PD2 may be NMOS transistors.

[0030] A first source / drain electrode of the first pull-up transistor PU1 and a first source / drain electrode of the first pull-down transistor PD1 may be connected to a first node N1. The source / drain electrode may include a source electrode of a transistor or a drain electrode of a transistor. In some embodiments, the same source / drain electrode may be a source electrode of one transistor and a drain electrode of another transistor. A second source / drain electrode of the first pull-up transistor PU1 may be connected to a power line VDD, and a second source / drain electrode of the first pull-down transistor PD1 may be connected to a ground line VSS. A gate electrode of the first pull-up transistor PU1 and a gate electrode of the first pull-down transistor PD1 may be electrically connected to each other. The first pull-up transistor PU1 and the first pull-down transistor PD1 may constitute a first inverter. The gate electrodes of the first pull-up transistor PU1 and the first pull-down transistor PD1 connected to each other may correspond to an input node of the first inverter, and the first node N1 may correspond to an output node of the first inverter.

[0031] A first source / drain electrode of the second pull-up transistor PU2 and a first source / drain electrode of the second pull-down transistor PD2 may be connected to a second node N2. A second source / drain electrode of the second pull-up transistor PU2 may be connected to a power supply line VDD, and a second source / drain electrode of the second pull-down transistor PD2 may be connected to a ground line VSS. A gate electrode of the second pull-up transistor PU2 and a gate electrode of the second pull-down transistor PD2 may be electrically connected to each other. The second pull-up transistor PU2 and the second pull-down transistor PD2 may constitute a second inverter. The gate electrodes of the second pull-up transistor PU2 and the second pull-down transistor PD2 connected to each other may correspond to an input node of the second inverter, and the second node N2 may correspond to an output node of the second inverter.

[0032] The first inverter and the second inverter may be combined to form a latch structure. For example, the gate electrodes of the first pull-up transistor PU1 and the first pull-down transistor PD1 may be electrically connected to the second node N2, and the gate electrodes of the second pull-up transistor PU2 and the second pull-down transistor PD2 may be electrically connected to the first node N1. The first source / drain electrode of the first pass-gate transistor PG1 may be connected to the first node N1, and the second source / drain electrode of the first pass-gate transistor PG1 may be connected to the first bit line BL1. The first source / drain electrode of the second pass-gate transistor PG2 may be connected to the second node N2, and the second source / drain electrode of the second pass-gate transistor PG2 may be connected to the second bit line BL2. The gate electrodes of the first pass-gate transistor PG1 and the second pass-gate transistor PG2 may be electrically coupled to the word line WL.

[0033] Figure 2A is a plan view showing a word line of a semiconductor device. Figure 2B is a plan view showing a lower conductive layer, a lower conductive pattern, and a word line connection pattern of a semiconductor device. Figure 2Cis a plan view showing a source / drain pattern, a lower active contact, an upper active contact, a lower gate contact, an upper gate contact, and a gate electrode of a semiconductor device. Figure 2D is a plan view showing upper conductive lines and bit lines of a semiconductor device. Figure 2E is along FIG. 2A to FIG. 2D A cross-sectional view taken along line AA'. Figure 2F is along FIG. 2A to FIG. 2D A cross-sectional view taken along line BB'. Figure 2G is along FIG. 2A to FIG. 2D A cross-sectional view taken along line CC'.

[0034] Reference Figures 2A to 2G , the semiconductor device may include a first lower insulating layer 110. The first lower insulating layer 110 may have a plate-like structure extending parallel to the first direction D1 and the second direction D2. The first direction D1 and the second direction D2 may not be parallel to each other. In an embodiment, the first direction D1 and the second direction D2 may be horizontal directions orthogonal to each other. The first lower insulating layer 110 may include an insulating material.

[0035] The first word line WL1 and the second word line WL2 may be disposed in the first lower insulating layer 110. The first word line WL1 and the second word line WL2 may extend in the first direction D1. The first word line WL1 and the second word line WL2 may be spaced apart from each other in the second direction D2. The first word line WL1 and the second word line WL2 may include a conductive material.

[0036] The second lower insulating layer 120 may be disposed on the first lower insulating layer 110. The second lower insulating layer 120 may include an insulating material.

[0037] The word line connection pattern WLC may be disposed in the second lower insulating layer 120. The word line connection pattern WLC may be surrounded by the second lower insulating layer 120. A plurality of word line connection patterns WLC may contact the first word line WL1. A plurality of word line connection patterns WLC may contact the second word line WL2. The bottom surface of the word line connection pattern WLC may contact the top surface of the first word line WL1 or the top surface of the second word line WL2. The word line connection pattern WLC may penetrate the second lower insulating layer 120 along a third direction D3. The third direction D3 may not be parallel to the first direction D1 and the second direction D2. In an embodiment, the third direction D3 may be a vertical direction orthogonal to the first direction D1 and the second direction D2. The word line connection pattern WLC may include a conductive material.

[0038] The lower conductive layer LCL, the lower conductive pattern LCP and the insulating pattern IP may be disposed on the second lower insulating layer 120. A pair of lower conductive patterns LCP may be surrounded by one of the insulating patterns IP. The pair of lower conductive patterns LCP may penetrate one of the insulating patterns IP along the third direction D3. The bottom surface of the lower conductive pattern LCP may contact the top surface of the word line connection pattern WLC. In an embodiment, the plane area of ​​the lower conductive pattern LCP may be greater than the plane area of ​​the word line connection pattern WLC. The lower conductive pattern LCP may include a conductive material. The insulating pattern IP may include an insulating material.

[0039] The lower conductive layer LCL may be disposed to surround the insulating pattern IP and the lower conductive pattern LCP. The bottom surface of the lower conductive layer LCL may contact the top surface of the second lower insulating layer 120. The lower conductive layer LCL may include a first lower conductive part LCL1, a second lower conductive part LCL2, a third lower conductive part LCL3, a fourth lower conductive part LCL4, a fifth lower conductive part LCL5, and a sixth lower conductive part LCL6. The lower conductive layer LCL may include a conductive material.

[0040] The first lower conductive part LCL1 may be disposed between the insulating patterns IP adjacent to each other in the second direction D2. The second lower conductive part LCL2 and the third lower conductive part LCL3 may be spaced apart from each other in the second direction D2, with the insulating pattern IP interposed therebetween. The fourth lower conductive part LCL4 may connect the first lower conductive part LCL1, the second lower conductive part LCL2, and the third lower conductive part LCL3 to each other. The fourth lower conductive part LCL4 may extend in the second direction D2. The fourth lower conductive part LCL4 may be disposed between the insulating patterns IP adjacent to each other in the first direction D1. The fifth lower conductive part LCL5 may be disposed between the insulating patterns IP adjacent to each other in the second direction D2. The sixth lower conductive part LCL6 may connect the second lower conductive part LCL2, the third lower conductive part LCL3, and the fifth lower conductive part LCL5 to each other. The sixth lower conductive part LCL6 may extend in the second direction D2. The sixth lower conductive part LCL6 may be disposed between the insulating patterns IP adjacent to each other in the first direction D1. The fourth lower conductive part LCL4 and the sixth lower conductive part LCL6 may be spaced apart from each other in the first direction D1 with the insulating pattern IP interposed therebetween. One insulating pattern IP and two lower conductive patterns LCP may be surrounded by the second lower conductive part LCL2, the third lower conductive part LCL3, the fourth lower conductive part LCL4, and the sixth lower conductive part LCL6.

[0041] The lengths of the fourth and sixth lower conductive portions LCL4 and LCL6 in the second direction D2 may be greater than the lengths of the first, second, third and fifth lower conductive portions LCL1, LCL2, LCL3 and LCL5 in the second direction D2.

[0042] For convenience of description, the lower conductive layer is described as several lower conductive parts (e.g., first to sixth lower conductive parts LCL1, LCL2, LCL3, LCL4, LCL5 and LCL6), but the lower conductive parts (e.g., first to sixth lower conductive parts LCL1, LCL2, LCL3, LCL4, LCL5 and LCL6) can be provided in the form of a single object without any interface therebetween.

[0043] The lower active contact portion LAC may be disposed on the lower conductive layer LCL. The bottom surface of the lower active contact portion LAC may contact the top surface of the lower conductive layer LCL. The width of the lower active contact portion LAC may decrease as the vertical height increases. The width of the lower active contact portion LAC may decrease as the distance from the lower conductive layer LCL increases. The lower active contact portion LAC may include a conductive material.

[0044] A filling insulating layer FL may be provided. The filling insulating layer FL may be provided on at least one of the lower conductive layer LCL, the lower conductive pattern LCP, and the insulating pattern IP. The lower active contact portion LAC may penetrate the filling insulating layer FL along the third direction D3. The filling insulating layer FL may extend along the second direction D2. The filling insulating layers FL may be arranged to be spaced apart from each other in the first direction D1. The filling insulating layer FL may include an insulating material. For example, the filling insulating layer FL may be formed of or include at least one nitride material.

[0045] A lower pattern LP may be provided. In an embodiment, a plurality of lower patterns LP may be provided on each filling insulating layer FL. The lower patterns LP provided on each filling insulating layer FL may be arranged to be spaced apart from each other in the second direction D2. In an embodiment, the lower pattern LP may be formed of or include at least one of an insulating material and a semiconductor material.

[0046] A device isolation layer ST may be provided. The lower active contact LAC and the filling insulating layer FL may penetrate the device isolation layer ST along the third direction D3. The device isolation layer ST may include an insulating material. For example, the device isolation layer ST may be formed of or include at least one oxide material.

[0047] A lower gate contact LGC may be provided. The lower gate contact LGC may be provided on the lower conductive pattern LCP. The bottom surface of the lower gate contact LGC may contact the top surface of the lower conductive pattern LCP. The lower gate contact LGC may penetrate the filling insulating layer FL and the device isolation layer ST along the third direction D3. The lower gate contact LGC may include a conductive material.

[0048] The lower gate contact LGC may include a first contact P1 on the lower conductive pattern LCP, and a second contact P2 and a third contact P3 on the first contact P1. The second contact P2 and the third contact P3 may be spaced apart from each other in the first direction D1. The first contact P1 may connect the second contact P2 and the third contact P3 to each other. A portion of the device isolation layer ST may be disposed between the second contact P2 and the third contact P3. Each of the second contact P2 and the third contact P3 may overlap with a semiconductor pattern SP to be described below in the third direction D3.

[0049] A source / drain pattern SD may be provided. The source / drain pattern includes a doped semiconductor region used as a source pattern of a transistor or a drain pattern of a transistor. The same source / drain pattern may be a source pattern of one transistor and a drain pattern of another transistor. The source / drain pattern SD may be provided on the lower active contact LAC or the lower pattern LP. The lower active contact LAC may contact the lower portion of the source / drain pattern SD. The source / drain pattern SD may include a semiconductor material. The source / drain pattern SD may be an epitaxial pattern formed by a selective epitaxial growth process.

[0050] A channel structure CH may be provided. The channel structure CH may be provided between source / drain patterns SD adjacent to each other in the second direction D2. Each channel structure CH may include a plurality of semiconductor patterns SP overlapping each other in the third direction D3. The semiconductor patterns SP included in each channel structure CH may be spaced apart from each other in the third direction D3.

[0051] In an embodiment, the semiconductor patterns SP may be formed of or include silicon (Si). For example, each semiconductor pattern SP may be formed of or include crystalline silicon. In an embodiment, the semiconductor patterns SP may be formed of or include silicon-germanium (SiGe).

[0052] A gate electrode GE extending in the first direction D1 may be provided. The gate electrode GE may include a portion between the semiconductor patterns SP. The second contact P2 and the third contact P3 of the lower gate contact LGC may contact the lower portion of the gate electrode GE. The gate electrode GE may include a conductive material. The gate electrode GE and the semiconductor pattern SP may constitute a three-dimensional field effect transistor (e.g., MBCFET or GAAFET).

[0053] The gate insulating layer GI may be provided to separate the gate electrode GE from the channel structure CH. The gate insulating layer GI may cover the top surface, the bottom surface, and the side surface of each semiconductor pattern SP. The gate insulating layer GI may include an insulating material. As an example, the gate insulating layer GI may be formed of or include at least one oxide material.

[0054] A gate dividing layer GD may be provided. The gate dividing layer GD may be interposed between the gate electrodes GE adjacent to each other in the first direction D1. The gate dividing layer GD may separate the gate electrodes GE adjacent to each other in the first direction D1. The gate dividing layer GD may include an insulating material.

[0055] A pair of gate spacers GS may be respectively disposed on opposite side surfaces of the gate electrode GE. The gate spacer GS may extend along the gate electrode GE and in the first direction D1. The top surface of the gate spacer GS may be higher than the top surface of the gate electrode GE. The top surface of the gate spacer GS may be coplanar with the top surface of the interlayer insulating layer 130 to be described below.

[0056] The gate capping pattern GP may be disposed on the gate electrode GE. The gate capping pattern GP may extend along the gate electrode GE and in the first direction D1. The gate capping pattern GP may include an insulating material. For example, the gate capping pattern GP may be formed of or include at least one nitride material.

[0057] The interlayer insulating layer 130 may be disposed on the gate spacer GS and the source / drain pattern SD. The top surface of the interlayer insulating layer 130 may be coplanar with the top surface of the gate capping pattern GP and the top surface of the gate spacer GS. The first upper insulating layer 140 may be disposed on the interlayer insulating layer 130 to cover the gate capping pattern GP. The second upper insulating layer 150 may be disposed on the first upper insulating layer 140. The third upper insulating layer 160 may be disposed on the second upper insulating layer 150. The interlayer insulating layer 130 and the first to third upper insulating layers 140, 150 and 160 may include an insulating material. In an embodiment, the interlayer insulating layer 130 and the first to third upper insulating layers 140, 150 and 160 may be formed of at least one oxide material or include at least one oxide material.

[0058] An upper active contact UAC may be provided. The upper active contact UAC may be provided to penetrate the first upper insulating layer 140. The upper active contact UAC may make contact with an upper portion of the source / drain pattern SD.

[0059] In an embodiment, the source / drain pattern SD may include a metal-semiconductor compound layer that contacts the lower active contact LAC or the upper active contact UAC. For example, the metal-semiconductor compound layer may be formed of at least one of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, or cobalt silicide, or may include at least one of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, or cobalt silicide.

[0060] In an embodiment, each of the upper active contact UAC and the lower active contact LAC may include a conductive pattern and a blocking pattern. The blocking pattern may contact the source / drain pattern SD. The conductive pattern may be spaced apart from the source / drain pattern SD by the blocking pattern. For example, the conductive pattern may include at least one of aluminum, copper, tungsten, molybdenum, or cobalt, and the blocking pattern may include at least one of titanium, tantalum, tungsten, nickel, cobalt, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), or platinum nitride (PtN).

[0061] An upper gate contact UGC may be provided. The upper gate contact UGC may penetrate the first upper insulating layer 140 and the gate capping pattern GP. The upper gate contact UGC may contact the upper portion of the gate electrode GE. The upper gate contact UGC may contact the top surface of the upper active contact UAC. The upper gate contact UGC may include a conductive material.

[0062] A via hole VI may be provided. The via hole VI may penetrate the second upper insulating layer 150 along the third direction D3. A bottom surface of the via hole VI may contact a top surface of the upper active contact UAC. The via hole VI may include a conductive material.

[0063] A first bit line BL1a, a second bit line BL2a, a third bit line BL3a, a fourth bit line BL4a, a first upper conductive line UCL1, and a second upper conductive line UCL2 may be provided. The first to fourth bit lines BL1a, BL2a, BL3a, and BL4a and the first upper conductive line UCL1 and the second upper conductive line UCL2 may penetrate the third upper insulating layer 160 in a third direction D3. Each of the first to fourth bit lines BL1a, BL2a, BL3a, and BL4a and the first upper conductive line UCL1 and the second upper conductive line UCL2 may have a bottom surface contacting a top surface of the via hole VI.

[0064] The first upper conductive line UCL1 may be disposed between the first bit line BL1a and the second bit line BL2a. The second upper conductive line UCL2 may be disposed between the third bit line BL3a and the fourth bit line BL4a. The second and third bit lines BL2a and BL3a may be disposed between the first upper conductive line UCL1 and the second upper conductive line UCL2.

[0065] The first to fourth bit lines BL1a, BL2a, BL3a, and BL4a and the first upper conductive line UCL1 and the second upper conductive line UCL2 may extend in the second direction D2. The first to fourth bit lines BL1a, BL2a, BL3a, and BL4a and the first upper conductive line UCL1 and the second upper conductive line UCL2 may be arranged in the first direction D1 to be spaced apart from each other. The first to fourth bit lines BL1a, BL2a, BL3a, and BL4a and the first upper conductive line UCL1 and the second upper conductive line UCL2 may include a conductive material.

[0066] Source / drain patterns SD, lower active contacts LAC, upper active contacts UAC, gate electrodes GE, lower gate contacts LGC, and upper gate contacts UGC may be disposed between each of the first and second upper conductive lines UCL1 and UCL2 and the lower conductive layer LCL.

[0067] The semiconductor device may include a plurality of SRAM cells SRC. The SRAM cell SRC may include a 6T SRAM cell SRC including a first transistor TR1, a second transistor TR2, a third transistor TR3, a fourth transistor TR4, a fifth transistor TR5, and a sixth transistor TR6.

[0068] The source / drain pattern SD may include first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, and tenth source / drain patterns SD1, SD2, SD3, SD4, SD5, SD6, SD7, SD8, SD9, and SD10.

[0069] The lower active contact portion LAC may include a first lower active contact portion LAC1 in contact with a lower portion of the first source / drain pattern SD1, and a second lower active contact portion LAC2 in contact with a lower portion of the second source / drain pattern SD2. The first source / drain pattern SD1 may be disposed on the first lower active contact portion LAC1. The second source / drain pattern SD2 may be disposed on the second lower active contact portion LAC2. The first and second source / drain patterns SD1 and SD2 and the first and second lower active contacts LAC1 and LAC2 may be electrically connected to the lower conductive layer LCL. The bottom surface of the first lower active contact portion LAC1 may be in contact with the top surface of the first lower conductive portion LCL1. The bottom surface of the second lower active contact portion LAC2 may be in contact with the top surface of the second lower conductive portion LCL2.

[0070] The third to tenth source / drain patterns SD3, SD4, SD5, SD6, SD7, SD8, SD9, and SD10 may be disposed between the first source / drain pattern SD1 and the second source / drain pattern SD2. A distance between one of the third to tenth source / drain patterns SD3, SD4, SD5, SD6, SD7, SD8, SD9, and SD10 and the first source / drain pattern SD1 or the second source / drain pattern SD2 may be smaller than a distance between the first source / drain pattern SD1 and the second source / drain pattern SD2. The third source / drain pattern SD3 may be adjacent to the first source / drain pattern SD1 in the first direction D1.

[0071] The upper active contact portion UAC may include a first upper active contact portion UAC1 in contact with an upper portion of the third source / drain pattern SD3, a second upper active contact portion UAC2 in contact with an upper portion of the fourth source / drain pattern SD4, a third upper active contact portion UAC3 in contact with an upper portion of the fifth source / drain pattern SD5, a fourth upper active contact portion UAC4 in contact with an upper portion of the sixth source / drain pattern SD6, a fifth upper active contact portion UAC5 in contact with upper portions of the seventh source / drain pattern SD7 and the eighth source / drain pattern SD8, and a sixth upper active contact portion UAC6 in contact with upper portions of the ninth source / drain pattern SD9 and the tenth source / drain pattern SD10.

[0072] The third source / drain pattern SD3 and the first upper active contact UAC1 may be electrically connected to the first upper conductive line UCL1 through the via VI. The fourth source / drain pattern SD4 and the second upper active contact UAC2 may be electrically connected to the first upper conductive line UCL1 through the via VI.

[0073] The fifth source / drain pattern SD5 and the third upper active contact UAC3 may be electrically connected to the first bit line BL1a through the via VI. The sixth source / drain pattern SD6 and the fourth upper active contact UAC4 may be electrically connected to the second bit line BL2a through the via VI.

[0074] The upper gate contact UGC may include a first upper gate contact UGC1 in contact with a top surface of the fifth upper active contact UAC5 , and a second upper gate contact UGC2 in contact with a top surface of the sixth upper active contact UAC6 .

[0075] The gate electrode GE may include a first gate electrode GE1 in contact with the first upper gate contact UGC1, and a second gate electrode GE2 in contact with the second upper gate contact UGC2. The seventh source / drain pattern SD7 and the eighth source / drain pattern SD8 and the fifth upper active contact UAC5 may be electrically connected to the first gate electrode GE1 through the first upper gate contact UGC1. The ninth source / drain pattern SD9 and the tenth source / drain pattern SD10 and the sixth upper active contact UAC6 may be electrically connected to the second gate electrode GE2 through the second upper gate contact UGC2.

[0076] The first gate electrode GE1 may be disposed between the fourth source / drain pattern SD4 and the tenth source / drain pattern SD10 and between the second source / drain pattern SD2 and the ninth source / drain pattern SD9. The first gate electrode GE1 may be adjacent to the fourth source / drain pattern SD4 and the tenth source / drain pattern SD10 and the second source / drain pattern SD2 and the ninth source / drain pattern SD9. The second gate electrode GE2 may be disposed between the third source / drain pattern SD3 and the eighth source / drain pattern SD8 and between the first source / drain pattern SD1 and the seventh source / drain pattern SD7. The second gate electrode GE2 may be adjacent to the third source / drain pattern SD3 and the eighth source / drain pattern SD8 and the first source / drain pattern SD1 and the seventh source / drain pattern SD7.

[0077] The gate electrode GE may further include a third gate electrode GE3 between the fifth source / drain pattern SD5 and the seventh source / drain pattern SD7, and a fourth gate electrode GE4 between the sixth source / drain pattern SD6 and the ninth source / drain pattern SD9. The third gate electrode GE3 may be adjacent to the fifth source / drain pattern SD5 and the seventh source / drain pattern SD7. The fourth gate electrode GE4 may be adjacent to the sixth source / drain pattern SD6 and the ninth source / drain pattern SD9.

[0078] The lower gate contact LGC may include a first lower gate contact LGC1 in contact with a lower portion of the third gate electrode GE3, and a second lower gate contact LGC2 in contact with a lower portion of the fourth gate electrode GE4. The third gate electrode GE3 may be electrically connected to the first word line WL1 through the first lower gate contact LGC1, the lower conductive pattern LCP, and the word line connection pattern WLC. The fourth gate electrode GE4 may be electrically connected to the second word line WL2 through the second lower gate contact LGC2, the lower conductive pattern LCP, and the word line connection pattern WLC.

[0079] The first source / drain pattern SD1 and the seventh source / drain pattern SD7 and the second gate electrode GE2 can be used as the source / drain electrode and the gate electrode of the first transistor TR1. The second source / drain pattern SD2 and the ninth source / drain pattern SD9 and the first gate electrode GE1 can be used as the source / drain electrode and the gate electrode of the second transistor TR2. The third source / drain pattern SD3 and the eighth source / drain pattern SD8 and the second gate electrode GE2 can be used as the source / drain electrode and the gate electrode of the third transistor TR3. The fourth source / drain pattern SD4 and the tenth source / drain pattern SD10 and the first gate electrode GE1 can be used as the source / drain electrode and the gate electrode of the fourth transistor TR4. The fifth source / drain pattern SD5 and the seventh source / drain pattern SD7 and the third gate electrode GE3 can be used as the source / drain electrode and the gate electrode of the fifth transistor TR5. The sixth source / drain pattern SD6 and the ninth source / drain pattern SD9 and the fourth gate electrode GE4 can be used as the source / drain electrode and the gate electrode of the sixth transistor TR6.

[0080] In an embodiment, the first transistor TR1 and the second transistor TR2 may be pull-down transistors, the third transistor TR3 and the fourth transistor TR4 may be pull-up transistors, and the fifth transistor TR5 and the sixth transistor TR6 may be transfer gate transistors. In this case, the first source / drain pattern SD1, the second source / drain pattern SD2, the fifth source / drain pattern SD5, the sixth source / drain pattern SD6, the seventh source / drain pattern SD7, and the ninth source / drain pattern SD9 may have a first conductivity type (e.g., n-type), and the third source / drain pattern SD3, the fourth source / drain pattern SD4, the eighth source / drain pattern SD8, and the tenth source / drain pattern SD10 may have a second conductivity type (e.g., p-type) different from the first conductivity type. In addition, the first upper conductive line UCL1 may be used as a power line VDD, and the lower conductive layer LCL may be used as a ground line VSS.

[0081] In an embodiment, the first transistor TR1 and the second transistor TR2 may be pull-up transistors, the third transistor TR3 and the fourth transistor TR4 may be pull-down transistors, and the fifth transistor TR5 and the sixth transistor TR6 may be transfer gate transistors. In this case, the first source / drain pattern SD1, the second source / drain pattern SD2, the fifth source / drain pattern SD5, the sixth source / drain pattern SD6, the seventh source / drain pattern SD7, and the ninth source / drain pattern SD9 may have a first conductivity type (e.g., p-type), and the third source / drain pattern SD3, the fourth source / drain pattern SD4, the eighth source / drain pattern SD8, and the tenth source / drain pattern SD10 may have a second conductivity type (e.g., n-type) different from the first conductivity type. The first upper conductive line UCL1 may be used as a ground line VSS, and the lower conductive layer LCL may be used as a power line VDD.

[0082] The distance between the first upper active contact UAC1 and the second upper active contact UAC2 may be smaller than the distance between the first lower active contact LAC1 and the second lower active contact LAC2. The first lower conductive portion LCL1 may overlap the first lower active contact LAC1, the first source / drain pattern SD1, and the first bit line BL1a in the third direction D3. The second lower conductive portion LCL2 may overlap the second lower active contact LAC2, the second source / drain pattern SD2, and the second bit line BL2a in the third direction D3. The fourth lower conductive portion LCL4 may overlap the first upper conductive portion UCL1, the first upper active contact UAC1, the second upper active contact UAC2, the fifth upper active contact UAC5, and the sixth upper active contact UAC6, the third source / drain pattern SD3, the fourth source / drain pattern SD4, the eighth source / drain pattern SD8, and the tenth source / drain pattern SD10, and the first upper gate contact UGC1 and the second upper gate contact UGC2 in the third direction D3. The first upper conductive line UCL1 may be disposed between the first lower conductive part LCL1 and the second lower conductive part LCL2.

[0083] The first lower gate contact LGC1, the lower conductive pattern LCP and the word line connection pattern WLC connected to each other may overlap the first bit line BL1a in the third direction D3. The second lower gate contact LGC2, the lower conductive pattern LCP and the word line connection pattern WLC connected to each other may overlap the second bit line BL2a in the third direction D3.

[0084] In the semiconductor device, word lines WL1 and WL2 and a lower conductive layer LCL may be disposed under a source / drain pattern SD, and bit lines BL1a, BL2a, BL3a, and BL4a and upper conductive lines UCL1 and UCL2 may be disposed on the source / drain pattern SD. In this case, the degree of freedom in designing interconnection lines may be increased and parasitic capacitance between interconnection lines may be improved.

[0085] In an implementation, since the semiconductor device includes the lower gate contact LGC, the lower conductive pattern LCP, and the word line connection pattern WLC, the gate electrode GE may be electrically connected to the word line WL1 or WL2 under the source / drain pattern SD.

[0086] In an embodiment, the semiconductor device may include a lower conductive layer LCL including lower conductive portions LCL1, LCL2, LCL3, and LCL5 extending in a first direction D1 and lower conductive portions LCL4 and LCL6 extending in a second direction D2, and a lower active contact portion LAC. In this case, the first source / drain pattern SD1 and the second source / drain pattern SD2 spaced apart from each other by a relatively large distance may be electrically connected to the lower conductive layer LCL.

[0087] Figure 3A , Figure 3B , Figure 3C , Figure 4A , Figure 4B , Figure 4C , Figure 5A , Figure 5B , Figure 5C , Fig. 6A , Figure 6B , Fig. 7A , Figure 7B and Figure 7C It shows the manufacturing Figures 2A to 2G A cross-sectional view of a method for a semiconductor device.

[0088] Reference Figure 3A , Figure 3B and Figure 3C The substrate 100 may be patterned to form an active pattern AP. The substrate 100 may be a semiconductor substrate, an insulating substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate. A device isolation layer ST may be formed on the substrate 100.

[0089] The gate spacer GS and the channel structure CH may be formed. The lower pattern LP, the source / drain pattern SD, and the interlayer insulating layer 130 may be formed.

[0090] Reference Figure 4A , Figure 4B and Figure 4C , a gate insulating layer GI, a gate electrode GE, a gate dividing layer GD, and a gate capping pattern GP may be formed.

[0091] A first upper insulating layer 140 may be formed. An upper active contact UAC may be formed. An upper gate contact UGC may be formed. A second upper insulating layer 150 may be formed. A via hole VI may be formed. A third upper insulating layer 160 may be formed. First to fourth bit lines BL1a, BL2a, BL3a, and BL4a and a first upper conductive line UCL1 and a second upper conductive line UCL2 may be formed.

[0092] Reference Figure 5A , Figure 5B and Figure 5C , the substrate 100 may be removed. As an example, the substrate 100 may be removed by at least one of a thinning process and a grinding process. An empty space formed by removing the active pattern AP may be defined as a first cavity CA. The lower pattern LP and the gate insulating layer GI may be exposed through the first cavity CA.

[0093] In an implementation, before removing the substrate 100 , a handle substrate may be formed on the third upper insulating layer 160 .

[0094] Reference Fig. 6A and Figure 6B, a filling insulating layer FL may be formed. Forming the filling insulating layer FL may include: forming an initial filling insulating layer to fill the first cavity CA; and removing a lower portion of the initial filling insulating layer to form the filling insulating layer FL. The initial filling insulating layer may include a lower portion and an upper portion. Each upper portion of the initial filling insulating layer may be disposed in the first cavity CA. As a result of removing the lower portion of the initial filling insulating layer, the upper portions of the initial filling insulating layer may be separated from each other. The separated upper portions of the initial filling insulating layer may be defined as the filling insulating layer FL.

[0095] The preliminary conductive layer pCL may be formed. The forming of the preliminary conductive layer pCL may include: etching some of the filling insulating layer FL and some of the lower pattern LP to form the second cavity CA2; and forming the preliminary conductive layer pCL to fill the second cavity CA2.

[0096] Etching some of the filling insulating layer FL and some of the lower patterns LP may include: forming a mask layer; and etching some of the filling insulating layer FL and some of the lower patterns LP using the mask layer as an etching mask. The preliminary conductive layer pCL may include an upper portion pCL1 disposed in the second cavity CA2 and a lower portion pCL2 connecting the upper portions pCL1 to each other.

[0097] Reference 7A to 7C , the lower portion pCL2 of the initial conductive layer pCL may be removed. Since the lower portion pCL2 of the initial conductive layer pCL is removed, the upper portions pCL1 of the initial conductive layer pCL may be separated from each other. The separated upper portions pCL1 of the initial conductive layer pCL may be defined as the lower active contact portion LAC.

[0098] As a result of removing the lower portion pCL2 of the initial conductive layer pCL, the filling insulating layer FL and the device isolation layer ST may be exposed. The third cavity CA3 may be formed by etching portions of the filling insulating layer FL and the device isolation layer ST. The third cavity CA3 may be formed to expose the gate electrode GE. A lower gate contact LGC may be formed in the third cavity CA3.

[0099] Reference Figures 2A to 2G , an insulating pattern IP, a lower conductive layer LCL, and a lower conductive pattern LCP may be formed. A second lower insulating layer 120 and a word line connection pattern WLC may be formed. A first lower insulating layer 110 and first and second word lines WL1 and WL2 may be formed.

[0100] Fig. 8A and Figure 8B is a cross-sectional view showing an example semiconductor device. In addition to the features to be described below, Fig. 8A and Figure 8B The semiconductor device may have Figures 2A to 2G Similar characteristics of semiconductor devices.

[0101] Reference Fig. 8A and Figure 8B , the filling insulating layer FLb may include an upper portion FL2b and a lower portion FL1b. The lower portion FL1b of the filling insulating layer FLb may connect the upper portions FL2b to each other.

[0102] The insulating pattern IP, the lower conductive layer LCL, and the lower conductive pattern LCP may be spaced apart from the device isolation layer ST by the lower portion FL1b of the filling insulating layer FLb.

[0103] The lower gate contact LGCb may be disposed between the upper portions FL2b of the filling insulating layer FLb. The lower gate contact LGCb may penetrate a portion of the device isolation layer ST disposed between the upper portions FL2b of the filling insulating layer FLb.

[0104] Fig.9A and Fig. 9B is a cross-sectional view showing an example semiconductor device. In addition to the features to be described below, Fig.9A and Fig. 9B The semiconductor device may have Figures 2A to 2G Similar characteristics of semiconductor devices.

[0105] Reference Fig.9A and Fig. 9B , the channel structure CHc may include a semiconductor pattern SP and a lower semiconductor pattern LSP. A bottom surface of the lower semiconductor pattern LSP may contact the filling insulating layer FL. A top surface of the lower semiconductor pattern LSP may contact the gate insulating layer GI. The lower semiconductor pattern LSP may include a semiconductor material.

[0106] The lower gate contact LGCc may overlap the two channel structures CHc in the third direction D3. The width of the lower gate contact LGCc in the first direction D1 may be greater than the distance in the first direction D1 between the two channel structures CHc adjacent to each other in the first direction D1. The lower gate contact LGCc may be disposed to penetrate the lower semiconductor pattern LSP. In an embodiment, an insulating layer may be provided to separate the lower gate contact LGCc from the lower semiconductor pattern LSP.

[0107] Fig. 10A is a plan view showing word lines of an example semiconductor device. Fig. 10B is a plan view illustrating a lower conductive layer, a lower conductive pattern, and a word line connection pattern of an example semiconductor device. Fig. 10C is a plan view showing a source / drain pattern, a lower active contact, an upper active contact, a lower gate contact, an upper gate contact, and a gate electrode of an example semiconductor device. Fig. 10D is a plan view showing an upper conductive line, a bit line, a read word line, and a read bit line of an example semiconductor device.

[0108] Reference Fig. 10A , Fig. 10B , Fig. 10C and Fig. 10D The semiconductor device may include a first lower insulating layer 110d and first and second word lines WL1d and WL2d disposed in the first lower insulating layer 110d. A word line connection pattern WLCd may be disposed on the first and second word lines WL1d and WL2d. A lower conductive pattern LCPd may be disposed on the word line connection pattern WLCd.

[0109] The insulating pattern IPd may be disposed to surround the lower conductive pattern LCPd. The lower conductive layer LCLd may be disposed to surround the insulating pattern IPd. The lower conductive layer LCLd may include: a first lower conductive portion LCL1d disposed between the insulating patterns IPd spaced apart from each other along the second direction D2; a second lower conductive portion LCL2d and a third lower conductive portion LCL3d spaced apart from each other in the second direction D2 with the insulating pattern IPd interposed therebetween; and a fourth lower conductive portion LCL4d and a fifth lower conductive portion LCL5d spaced apart from each other in the first direction D1 with the insulating pattern IPd interposed therebetween. The fourth lower conductive portion LCL4d may connect the first to third lower conductive portions LCL1d, LCL2d, and LCL3d to each other. The fifth lower conductive portion LCL5d may connect the second lower conductive portion LCL2d and the third lower conductive portion LCL3d to each other.

[0110] The semiconductor device may include an SRAM cell SRCd and a read port RPd. The read port RPd may be connected to the SRAM cell SRCd. For example, the read port RPd including the seventh transistor TR7d and the eighth transistor TR8d may be connected to the SRAM cell including the first transistor TR1d, the second transistor TR2d, the third transistor TR3d, the fourth transistor TR4d, the fifth transistor TR5d, and the sixth transistor TR6d. The seventh transistor TR7d may be a pull-down transistor of the read port RPd. The eighth transistor TR8d may be a transmission gate transistor of the read port RPd.

[0111] The source / drain pattern SDd may include a first source / drain pattern SD1d, a second source / drain pattern SD2d, and a third source / drain pattern SD3d. The first source / drain pattern SD1d and the second source / drain pattern SD2d may be source / drain electrodes of the seventh transistor TR7d. The second source / drain pattern SD2d and the third source / drain pattern SD3d may be source / drain electrodes of the eighth transistor TR8d.

[0112] The gate electrode GEd may include a first gate electrode GE1d and a second gate electrode GE2d. The first gate electrode GE1d may be a gate electrode of the seventh transistor TR7d, a gate electrode of the second transistor TR2d, and a gate electrode of the fourth transistor TR4d. The second gate electrode GE2d may be a gate electrode of the eighth transistor TR8d.

[0113] The upper active contact UACd may include a first upper active contact UAC1d and a second upper active contact UAC2d. The first upper active contact UAC1d may be disposed on the second source / drain pattern SD2d. The second upper active contact UAC2d may be disposed on the third source / drain pattern SD3d.

[0114] The first source / drain pattern SD1d can be electrically connected to the lower conductive layer LCLd through the lower active contact LACd. The second gate electrode GE2d can be electrically connected to the read word line RWLd through the upper gate contact UGCd. The third source / drain pattern SD3d can be electrically connected to the read bit line RBLd through the second upper active contact UAC2d and the via Vid.

[0115] The read word line RWLd and the read bit line RBLd may be disposed at the same height as the first bit line BL1d, the second bit line BL2d, and the upper conductive line UCLd.

[0116] Each of the fifth transistor TR5d and the sixth transistor TR6d may be electrically connected to the word line WL1d or WL2d through a lower gate contact LGCd.

[0117] Fig.11A is a plan view showing word lines, dummy lines, and read word lines of an example semiconductor device. Fig. 11B is a plan view illustrating a lower conductive layer, a lower conductive pattern, and a word line connection pattern of an example semiconductor device. Fig. 11C is a plan view showing a source / drain pattern, a lower active contact, an upper active contact, a lower gate contact, an upper gate contact, and a gate electrode of an example semiconductor device. Fig.11D is a plan view showing an upper conductive line, a bit line, a read word line, a read bit line, and a dummy pattern of an example semiconductor device.

[0118] Reference Fig.11A , Fig. 11B , Fig. 11C and Fig.11D, the semiconductor device may include a first word line WL1e, a second word line WL2e, a first read word line RWL1e, a first dummy line DL1e, and a second dummy line DL2e in a first lower insulating layer 110e. The first read word line RWL1e may be disposed between the first word line WL1e and the second word line WL2e. The first word line WL1e and the second word line WL2e and the first read word line RWL1e may be disposed between the first dummy line DL1e and the second dummy line DL2e. The first dummy line DL1e and the second dummy line DL2e, the first word line WL1e and the second word line WL2e, and the first read word line RWL1e may extend along a first direction D1. The first dummy line DL1e and the second dummy line DL2e, the first word line WL1e and the second word line WL2e, and the first read word line RWL1e may be arranged along a second direction D2. The first and second dummy lines DL1e and DL2e, the first and second word lines WL1e and WL2e, and the first read word line RWL1e may be disposed at the same height. The first and second dummy lines DL1e and DL2e, the first and second word lines WL1e and WL2e, and the first read word line RWL1e may be disposed at a height lower than the lower conductive layer LCLe.

[0119] The dummy lines DL1e and DL2e may be formed to improve uniformity of a manufacturing process of the semiconductor device. In an embodiment, the semiconductor device may not include the dummy lines DL1e and DL2e.

[0120] The first word line connection pattern WLC1e may be disposed on each of the first word line WL1e and the second word line WL2e. The first lower conductive pattern LCP1e may be disposed on the first word line connection pattern WLC1e. The second word line connection pattern WLC2e may be disposed on the first read word line RWL1e. The second lower conductive pattern LCP2e may be disposed on the second word line connection pattern WLC2e. The insulating pattern IPe may be disposed to surround the first lower conductive pattern LCP1e and the second lower conductive pattern LCP2e.

[0121] The lower conductive layer LCLe may include: a first lower conductive portion LCL1e, which is arranged between first lower conductive patterns LCP1e spaced apart from each other along the second direction D2; a second lower conductive portion LCL2e and a third lower conductive portion LCL3e, which are spaced apart from each other in the second direction D2, with the first lower conductive pattern LCP1e and the second lower conductive pattern LCP2e interposed therebetween; and a fourth lower conductive portion LCL4e, which is used to connect the first to third lower conductive portions LCL1e, LCL2e and LCL3e to each other.

[0122] The semiconductor device may include a first SRAM cell SRC1e, a second SRAM cell SRC2e, a first read port RP1e, and a second read port RP2e. The first read port RP1e may be connected to the first SRAM cell SRC1e, and the second read port RP2e may be connected to the second SRAM cell SRC2e.

[0123] The first read port RP1e may include a first transistor TR1e and a second transistor TR2e. The second read port RP2e may include a third transistor TR3e and a fourth transistor TR4e. The first transistor TR1e may be a pull-down transistor of the first read port RP1e. The second transistor TR2e may be a transmission gate transistor of the first read port RP1e. The third transistor TR3e may be a pull-down transistor of the second read port RP2e. The fourth transistor TR4e may be a transmission gate transistor of the second read port RP2e.

[0124] The source / drain pattern SDe may include a first source / drain pattern SD1e, a second source / drain pattern SD2e, a third source / drain pattern SD3e, a fourth source / drain pattern SD4e, and a fifth source / drain pattern SD5e. The first source / drain pattern SD1e and the second source / drain pattern SD2e may be source / drain electrodes of the first transistor TR1e. The second source / drain pattern SD2e and the third source / drain pattern SD3e may be source / drain electrodes of the second transistor TR2e. The fourth source / drain pattern SD4e and the fifth source / drain pattern SD5e may be source / drain electrodes of the third transistor TR3e. The third source / drain pattern SD3e and the fifth source / drain pattern SD5e may be source / drain electrodes of the fourth transistor TR4e.

[0125] The gate electrode GEe may include a first gate electrode GE1e, a second gate electrode GE2e, a third gate electrode GE3e, and a fourth gate electrode GE4e. The first gate electrode GE1e may be a gate electrode of a first transistor TR1e. The first gate electrode GE1e may be a gate electrode of a transistor of a first SRAM cell SRC1e. The second gate electrode GE2e may be a gate electrode of a second transistor TR2e. The third gate electrode GE3e may be a gate electrode of a third transistor TR3e. The third gate electrode GE3e may be a gate electrode of a transistor of a second SRAM cell SRC2e. The second gate electrode GE2e may be a gate electrode of a fourth transistor TR4e.

[0126] The upper active contact UACe may include a first upper active contact UAC1e on the second source / drain pattern SD2e, a second upper active contact UAC2e on the third source / drain pattern SD3e, and a third upper active contact UAC3e on the fifth source / drain pattern SD5e.

[0127] The first source / drain pattern SD1e may be electrically connected to the lower conductive layer LCLe through the lower active contact LACEe. The second gate electrode GE2e may be electrically connected to the second lower conductive pattern LCP2e, the second word line connection pattern WLC2e, and the first read word line RWL1e through the lower gate contact LGCe. The third source / drain pattern SD3e may be electrically connected to the read bit line RBLe through the via VIe. The fourth gate electrode GE4e may be electrically connected to the second read word line RWL2e through the upper gate contact UGCe. The fourth source / drain pattern SD4e may be electrically connected to the lower conductive layer LCLe through the lower active contact LACEe.

[0128] The read bit line RBLe, the second read word line RWL2e, and the dummy pattern DPe may be disposed at the same height as the first bit line BL1e, the second bit line BL2e, and the upper conductive line UCLe.

[0129] The dummy pattern DPe may be formed to improve uniformity in a manufacturing process of the semiconductor device. In an embodiment, the semiconductor device may not include the dummy pattern DPe.

[0130] In a semiconductor device, the degree of freedom of interconnection lines can be increased and the parasitic capacitance of the interconnection lines can be improved.

[0131] Although the present disclosure includes many specific implementation details, these should not be interpreted as limiting the scope of possible protection. In a single embodiment, specific features described in the context of independent embodiments in the present disclosure can also be implemented in combination. On the contrary, various features described in the context of a single embodiment can also be implemented independently in multiple embodiments, or in appropriate sub-combinations. In addition, although features may be described above as working in certain combinations and even initially claimed as such, one or more features from a combination can be deleted from the combination in some cases, and the combination can be directed to sub-combinations or variations of sub-combinations.

[0132] While example embodiments of the inventive concepts have been particularly shown and described, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: a first lower active contact; a first source / drain pattern on the first lower active contact; a second lower active contact; a second source / drain pattern on the second lower active contact; a lower conductive layer electrically connected to the first lower active contact and the second lower active contact; a third source / drain pattern and a fourth source / drain pattern between the first source / drain pattern and the second source / drain pattern; a first active contact portion on the third source / drain pattern; a second upper active contact portion on the fourth source / drain pattern; as well as an upper conductive line electrically connected to the first upper active contact portion and the second upper active contact portion, The first to fourth source / drain patterns, the first lower active contact and the second lower active contact, and the first upper active contact and the second upper active contact are disposed between the lower conductive layer and the upper conductive line.

2. The semiconductor device according to claim 1, wherein A distance between the first upper active contact and the second upper active contact is smaller than a distance between the first lower active contact and the second lower active contact.

3. The semiconductor device according to claim 1, wherein The lower conductive layer comprises: a first lower conductive portion, overlapping the first lower active contact portion; a second lower conductive portion overlapping the second lower active contact portion; and a third lower conductive portion, connecting the first lower conductive portion and the second lower conductive portion to each other, Wherein, the upper conductive line overlaps with the third lower conductive portion.

4. The semiconductor device according to claim 3, wherein: The upper conductive line extends along a first direction, and A length of the third lower conductive portion in the first direction is longer than lengths of the first lower conductive portion and the second lower conductive portion in the first direction.

5. The semiconductor device according to claim 3, wherein: The lower conductive layer further comprises: a fourth lower conductive portion connected to the third lower conductive portion; and a fifth lower conductive portion, connecting the second lower conductive portion and the fourth lower conductive portion to each other, wherein the third lower conductive portion and the fifth lower conductive portion are spaced apart from each other, and The second lower conductive portion and the fourth lower conductive portion are spaced apart from each other.

6. The semiconductor device according to claim 5, further comprising: a lower conductive pattern between the third lower conductive portion and the fifth lower conductive portion and between the second lower conductive portion and the fourth lower conductive portion, Wherein, the lower conductive layer surrounds the lower conductive pattern.

7. The semiconductor device according to claim 6, further comprising: a lower gate contact portion on the lower conductive pattern; as well as A gate electrode is on the lower gate contact.

8. A semiconductor device comprising: a first source / drain pattern; a first lower active contact portion contacting a lower portion of the first source / drain pattern; a second source / drain pattern; a second lower active contact portion contacting a lower portion of the second source / drain pattern; a lower conductive layer electrically connected to the first lower active contact and the second lower active contact; a third source / drain pattern; a first upper active contact portion contacting an upper portion of the third source / drain pattern; an upper conductive wire electrically connected to the upper active contact; a fourth source / drain pattern; a second upper active contact portion contacting an upper portion of the fourth source / drain pattern; as well as A first bit line is electrically connected to the second upper active contact portion, Wherein, the lower conductive layer comprises: a first lower conductive portion, contacting the first lower active contact portion; a second lower conductive portion in contact with the second lower active contact portion; and a third lower conductive portion, connecting the first lower conductive portion and the second lower conductive portion to each other, The first lower conductive portion overlaps with the first bit line, and the third lower conductive portion overlaps with the upper conductive line.

9. The semiconductor device according to claim 8, further comprising: The second bit line overlaps with the second lower conductive portion.

10. The semiconductor device according to claim 9, wherein The upper conductive line is disposed between the first bit line and the second bit line.

11. The semiconductor device according to claim 8, wherein The first upper active contact portion overlaps the third lower conductive portion.

12. The semiconductor device according to claim 8, further comprising: a first gate electrode, adjacent to the first source / drain pattern; an upper gate contact portion, contacting an upper portion of the first gate electrode; a second gate electrode, adjacent to the fourth source / drain pattern; as well as The lower gate contact portion contacts the lower portion of the second gate electrode.

13. The semiconductor device according to claim 12, further comprising: a lower conductive pattern in contact with a bottom surface of the lower gate contact portion; as well as an insulating pattern surrounding the lower conductive pattern, The lower conductive layer surrounds the insulating pattern and the lower conductive pattern.

14. The semiconductor device according to claim 13, further comprising: a word line connection pattern in contact with a bottom surface of the lower conductive pattern; as well as A word line contacts a bottom surface of the word line connection pattern.

15. The semiconductor device according to claim 8, wherein The first source / drain pattern, the second source / drain pattern, and the fourth source / drain pattern have a first conductivity type, and The third source / drain pattern has a second conductivity type different from the first conductivity type.

16. The semiconductor device according to claim 8, further comprising: a first gate electrode, adjacent to the second source / drain pattern and the third source / drain pattern; a fifth source / drain pattern, adjacent to the first gate electrode; as well as a third lower active contact portion contacting a lower portion of the fifth source / drain pattern, Wherein, the third lower active contact portion contacts the second lower conductive portion.

17. The semiconductor device according to claim 16, further comprising: a sixth source / drain pattern, adjacent to the fifth source / drain pattern, wherein the first gate electrode is interposed between the sixth source / drain pattern and the fifth source / drain pattern; a second gate electrode, adjacent to the sixth source / drain pattern; as well as A read word line is electrically connected to the second gate electrode.

18. The semiconductor device according to claim 17, wherein: The read word line is disposed at the same height as the first bit line and the upper conductive line.

19. The semiconductor device according to claim 17, wherein: The read word line is disposed at a height lower than the lower conductive layer.

20. A semiconductor device comprising: a first lower insulating layer; A first word line and a second word line are disposed in the first lower insulating layer and extend along a first direction; a second lower insulating layer, on the first lower insulating layer; a first word line connection contact and a second word line connection contact in the second lower insulating layer; a first lower conductive pattern on the first word line connection contact portion; a second lower conductive pattern on the second word line connection contact portion; a first insulating pattern surrounding the first lower conductive pattern; a second insulating pattern surrounding the second lower conductive pattern; a lower conductive layer on the second lower insulating layer; a first lower active contact on the lower conductive layer; a first source / drain pattern on the first lower active contact; a second lower active contact on the lower conductive layer; a second source / drain pattern on the second lower active contact; a first lower gate contact portion, on the first lower conductive pattern; a first gate electrode on the first lower gate contact; a second lower gate contact portion, on the second lower conductive pattern; a second gate electrode on the second lower gate contact; a third source / drain pattern, adjacent to the first gate electrode; a first active contact on the third source / drain pattern; a first bit line electrically connected to the first upper active contact; a fourth source / drain pattern, adjacent to the second gate electrode; a second upper active contact portion on the fourth source / drain pattern; a second bit line electrically connected to the second upper active contact; a fifth source / drain pattern, adjacent to the first source / drain pattern in the first direction; a third active contact portion on the fifth source / drain pattern; a sixth source / drain pattern, adjacent to the second source / drain pattern in the first direction; a fourth upper active contact portion on the sixth source / drain pattern; as well as An upper conductive line is electrically connected to the third upper active contact and the fourth upper active contact.

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