Semiconductor structure, manufacturing method thereof and memory system

Abstract

The invention provides a semiconductor structure, a manufacturing method thereof and a storage system. The method for manufacturing the semiconductor structure comprises the steps that a first semiconductor structure and a second semiconductor structure are bonded, a bonding structure is formed, the first semiconductor structure comprises a storage array, and the bonding structure is located between the first semiconductor structure and the second semiconductor structure; a power line is formed on the side away from the bonding structure, the power line supplies power to the second semiconductor structure, and the second semiconductor structure after power supply controls the storage array.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a semiconductor structure, a method for manufacturing the semiconductor structure, and a storage system. Background Art

[0002] With the rise and development of artificial intelligence, big data, the Internet of Things, mobile communications, mobile devices and cloud storage, the requirements for the storage density of semiconductor structures such as three-dimensional semiconductor memory devices are becoming higher and higher. However, as the storage density of semiconductor structures increases, the number of storage units increases, the size decreases, and the spatial density increases. This makes the number of wirings connected to the storage units increase, and the interference between adjacent wirings becomes more and more serious, which seriously affects the overall performance of the semiconductor structure. Summary of the invention

[0003] The embodiments proposed in this application can solve or partially solve the deficiencies proposed in the above background technology section or other deficiencies in the prior art.

[0004] The present application provides a method for manufacturing a semiconductor structure. The method includes: bonding a first semiconductor structure and a second semiconductor structure to form a bonding structure, wherein the first semiconductor structure includes a storage array, and the bonding structure is located between the first semiconductor structure and the second semiconductor structure; and forming a power line on a side away from the bonding structure, wherein the power line supplies power to the second semiconductor structure, and the second semiconductor structure after power supply controls the storage array.

[0005] In one embodiment, forming a power line on a side away from the bonding structure includes: forming the power line on a side of the first semiconductor structure away from the bonding structure.

[0006] In one embodiment, forming a power line on a side away from the bonding structure includes: forming the power line on a side of the second semiconductor structure away from the bonding structure.

[0007] In one embodiment, the power line is formed on a side of the first semiconductor structure away from the bonding structure, including: forming a conductive plug extending along a first direction in the first semiconductor structure, wherein the first direction is perpendicular to the extension direction of the bonding structure, and the conductive plug is connected to the second semiconductor structure; and forming the power line extending along a second direction and connected to the conductive plug on a side of the first semiconductor structure away from the bonding structure, wherein the second direction is perpendicular to the first direction.

[0008] In one embodiment, forming a conductive plug extending along a first direction in the first semiconductor structure includes: forming a plurality of interconnection contacts extending along the first direction and connected to the memory array and the conductive plug extending along the first direction in the first semiconductor structure.

[0009] In one embodiment, the conductive plug includes a first conductive plug and a second conductive plug, the second conductive plug is close to the interconnection contact, and a power line extending along the second direction and connected to the conductive plug is formed, including: forming an interconnection layer on the interconnection contact and the conductive plug, wherein the interconnection layer includes a first interconnection layer and a second interconnection layer, the first interconnection layer extends along the second direction and is connected to the multiple interconnection contacts and the second conductive plug, and the second interconnection layer is connected to the first conductive plug; forming a first conductive contact on the second interconnection layer; and forming a power line extending along the second direction on the first conductive contact, wherein the power line is connected to the second semiconductor structure via the first conductive contact, the second interconnection layer and the first conductive plug.

[0010] In one embodiment, the conductive plug further includes a third conductive plug, and the interconnect layer further includes a third interconnect layer connected to the third conductive plug, wherein the method further includes: forming a second conductive contact on the third interconnect layer; forming a conductive line on the second conductive contact; and forming a pad lead-out structure on the conductive line, wherein the pad lead-out structure is connected to the second semiconductor structure via the conductive line, the second conductive contact, the third interconnect layer and the third conductive plug.

[0011] In one embodiment, the method includes: forming the first semiconductor structure, including: forming the memory array on a first substrate, wherein the memory array includes transistors and capacitors connected to first ends of the transistors away from the first substrate; forming a second substrate on a side of the memory array away from the first substrate; removing the first substrate and forming a bit line extending along the second direction at a second end of the transistor opposite to the first end; and removing the second substrate to form the first semiconductor structure, wherein the interconnect contact is connected to the capacitor.

[0012] In one embodiment, the transistor includes a semiconductor pillar and a gate structure contacting the semiconductor pillar, and the method includes: forming a contact structure connected to the gate structure, wherein the contact structure is connected to the second semiconductor structure through the bonding structure.

[0013] In one embodiment, the method includes: after bonding the first semiconductor structure and the second semiconductor structure, forming the power line.

[0014] On the other hand, the present application provides a semiconductor structure. The semiconductor structure includes: a first semiconductor structure and a second semiconductor structure bonded to each other, wherein the first semiconductor structure includes a storage array; a bonding structure located between the first semiconductor structure and the second semiconductor structure; and a power line located on a side away from the bonding structure, wherein the power line supplies power to the second semiconductor structure, and the second semiconductor structure after power supply controls the storage array.

[0015] In one embodiment, the power line is located on a side of the first semiconductor structure away from the bonding structure.

[0016] In one embodiment, the power line is located on a side of the second semiconductor structure away from the bonding structure.

[0017] In one embodiment, the power line extends along a second direction, and the semiconductor structure further includes: a first conductive plug connected to the power line, located in the first semiconductor structure and extending along a first direction, wherein the first direction is perpendicular to the second direction, and the power line supplies power to the second semiconductor structure via the first conductive plug.

[0018] In one embodiment, the first semiconductor structure includes: a transistor having a first end away from the bonding structure and a second end opposite to the first end along the first direction; a capacitor including a first electrode, a second electrode, and a dielectric layer located between the first electrode and the second electrode, wherein the first electrode is connected to the first end of the transistor; and a bit line connected to the second end and extending along the second direction.

[0019] In one embodiment, the transistor includes a semiconductor pillar and a gate structure contacting the semiconductor pillar, and the first semiconductor structure includes: a contact structure connected to the gate structure and connected to the second semiconductor structure through the bonding structure.

[0020] In one embodiment, the semiconductor structure includes: a plurality of interconnection contacts extending along the first direction and connected to the second electrode; a second conductive plug adjacent to the first conductive plug and close to the interconnection contact, passing through the first semiconductor structure along the first direction and connected to the second semiconductor structure through the bonding structure; a first interconnection layer extending along the second direction and connected to the plurality of interconnection contacts and the second conductive plug, wherein the second electrode is connected to the second semiconductor structure via the interconnection contact, the first interconnection layer and the second conductive plug.

[0021] In one embodiment, the semiconductor structure includes: a second interconnect layer connected to the first conductive plug; a first conductive contact connected to the second interconnect layer, wherein the power line is located on the first conductive contact and is connected to the second semiconductor structure via the first conductive contact, the second interconnect layer and the first conductive plug.

[0022] In one embodiment, the semiconductor structure includes: a third conductive plug, adjacent to the first conductive plug, passing through the first semiconductor structure along the first direction and connected to the second semiconductor structure through the bonding structure; a third interconnect layer, located on the third conductive plug and connected to the third conductive plug; a second conductive contact, located on the third interconnect layer and connected to the third interconnect layer; a conductive line, located on the second conductive contact and connected to the second conductive contact; and a pad lead-out structure, located on the conductive line and connected to the conductive line, wherein the pad lead-out structure is connected to the second semiconductor structure via the conductive line, the second conductive contact, the third interconnect layer and the third conductive plug.

[0023] On the other hand, the present application provides a storage system, which includes at least one three-dimensional memory, each three-dimensional memory including the semiconductor structure as described above; and a controller coupled to the semiconductor structure for controlling the three-dimensional memory to store data.

[0024] In one or more embodiments of the present application, by forming a power line on a side away from the bonding structure, it is possible to increase the wiring methods of the power line, improve the wiring freedom of the power line, and reduce the wiring length of the power line, which is beneficial to reducing the overall size of the semiconductor structure. It is also possible to reduce the coupling phenomenon between the power line and other conductive wiring (such as bit line wiring), and improve the sensing margin of related components (such as bit lines). BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Other features, purposes and advantages of the present application will become more apparent through the following detailed description of non-limiting embodiments in conjunction with the accompanying drawings. In the accompanying drawings:

[0026] Figure 1 is a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present application;

[0027] Figure 2 is a partial structural schematic diagram of a second semiconductor structure provided according to an exemplary embodiment of the present application;

[0028] Figure 3 is a partial structural schematic diagram of a first semiconductor structure provided according to an exemplary embodiment of the present application;

[0029] like Figures 4 to 6 A process step diagram for forming a first semiconductor structure according to an exemplary embodiment of the present application;

[0030] Figure 7 is a partial structural schematic diagram of a bonding structure formed by bonding a first semiconductor structure and a second semiconductor structure according to an exemplary embodiment of the present application;

[0031] Figure 8 is a schematic diagram of a structure for forming a power line according to an exemplary embodiment of the present application; and

[0032] Fig. 9 is an exemplary block diagram of a system having a storage system according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0033] In order to better understand the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application, and do not limit the scope of the present application in any way.

[0034] It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another feature, and do not represent any limitation on the features, especially do not represent any order of precedence. Therefore, without departing from the teaching of this application, the first semiconductor structure discussed in this application may also be referred to as the second semiconductor structure, the first direction may also be referred to as the second direction, the third direction, and vice versa.

[0035] In the drawings, the thickness, size and shape of the components have been slightly adjusted for ease of illustration. The drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation, not as terms of degree, and are intended to account for the inherent deviations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0036] In addition, in this document, when describing that one part is located "on" another part, for example, the meaning of "on", "above" and "over" should be interpreted in the broadest manner, so that "on" not only means "directly on something", but also includes the meaning of "on something" with intervening features or layers in between, and "above" or "over" does not absolutely mean being above based on the direction of gravity, nor does it only mean the meaning of "on something" or "above something", but also includes the meaning of "on something" or "over something" with no intervening features or layers in between (i.e., directly on something).

[0037] It should also be understood that expressions such as "include", "including", "have", "contain" and / or "comprising" are open rather than closed expressions in this specification, which indicate the presence of the stated features, elements and / or components, but do not exclude the presence of one or more other features, elements, components and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0038] This document is described with reference to schematic diagrams of exemplary embodiments. The exemplary embodiments disclosed herein should not be construed as limited to the specific shapes and sizes shown, but include various equivalent structures that can achieve the same functions and shape and size deviations caused by, for example, manufacturing. The positions shown in the drawings are schematic in nature and are not intended to limit the positions of the components.

[0039] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0040] As used in this article, the term "layer" refers to a material portion including an area with a height. A layer can be an area of ​​a uniform or non-uniform continuous structure, whose height is less than the height of the continuous structure. For example, a layer can be located between the top surface and the bottom surface of the continuous structure or between any set of horizontal planes therebetween. A layer can extend horizontally, vertically and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, above it and / or below it. A layer can include multiple layers.

[0041] In addition, in the present application, when “connected” or “coupled” is used, it may indicate that the corresponding components are in direct contact or indirect contact, unless otherwise clearly defined or can be inferred from the context.

[0042] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. In addition, unless explicitly limited or contradictory to the context, the specific steps included in the method described in this application are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0043] Figure 1 is a flow chart of a method 1000 of fabricating a semiconductor structure according to an exemplary embodiment of the present application.

[0044] like Figure 1 As shown, the method 1000 for manufacturing a semiconductor structure may include: S1100, bonding a first semiconductor structure and a second semiconductor structure to form a bonding structure, wherein the first semiconductor structure includes a memory array, and the bonding structure is located between the first semiconductor structure and the second semiconductor structure; and S1200, forming a power line on a side away from the bonding structure, wherein the power line supplies power to the second semiconductor structure, and the second semiconductor structure after power supply controls the memory array. Steps S1100 and S1200 will be described in detail below.

[0045] In the exemplary embodiment of the present application, Figure 7 As shown, the first semiconductor structure 1100 and the second semiconductor structure 1200 may be bonded to form a bonding structure 1300 , wherein the first semiconductor structure 1100 may include a memory array 1110 , and the bonding structure 1300 may be located between the first semiconductor structure 1100 and the second semiconductor structure 1200 .

[0046] In the exemplary embodiment of the present application, Figure 2 As shown, the second semiconductor structure 1200 may include a third substrate 1210 and a peripheral circuit 1220 extending into the third substrate 1210 . .

[0047] The material of the third substrate 1210 may include at least one of single crystal silicon, polycrystalline silicon, single crystal germanium, group III-V compound semiconductor materials, group II-VI compound semiconductor materials, or other semiconductor materials known in the art.

[0048] The peripheral circuit 1220 (also referred to as the control and sensing circuit) may include any suitable digital, analog and / or mixed signal circuits for facilitating the operation of the memory cell array. For example, the peripheral circuit 1220 may include one or more of a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), an input / output (I / O) circuit, a charge pump, a voltage source or generator, a current or voltage reference, any portion (e.g., a subcircuit) of the above functional circuits, or any active or passive component of the circuit (e.g., a peripheral transistor, a diode, a resistor, or a capacitor). For example, the peripheral circuit 1220 may include a plurality of peripheral transistors 1221. The source, drain, and channel of the peripheral transistor 1221 may be located in the third substrate 1210, and the gate of the peripheral transistor 1221 may be located on the third substrate 1210.

[0049] Exemplarily, the second semiconductor structure 1200 may further include trench isolation (eg, shallow trench isolation (STI)) formed on or in the third substrate 1210 .

[0050] Exemplarily, the second semiconductor structure 1200 may further include a peripheral interconnect layer 1230 located on the peripheral circuit 1220 to transmit electrical signals to and from the peripheral circuit 1220. The peripheral interconnect layer 1230 may include a plurality of interconnect structures (also referred to as "contact structures"), wherein the interconnect structure may include lateral interconnect lines and interconnect contacts. The peripheral interconnect layer 1230 may also include one or more dielectric layers for separating the plurality of interconnect lines and / or interconnect contacts. That is, the peripheral interconnect layer 1230 may include interconnect lines and interconnect contacts in a plurality of dielectric layers. Exemplarily, the peripheral circuits 1220 may be coupled to each other through the interconnect structures in the peripheral interconnect layer 1230. The material of the interconnect structure in the peripheral interconnect layer 1230 may include a conductive material, such as including but not limited to tungsten (W), copper (Cu), aluminum (Al), doped silicon, silicide, or any combination thereof. The dielectric layer may be formed of a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant material layer, or any combination thereof.

[0051] Exemplarily, the second semiconductor structure 1200 may further include a second bonding layer 1240 located on the peripheral interconnect layer 1230. The second bonding layer 1240 may include a plurality of second bonding contacts 1241 and a dielectric isolating the second bonding contacts 1241. The second bonding contacts 1241 may include a conductive material, such as copper (Cu). The remaining area of ​​the second bonding layer 1240 may be formed with a dielectric material (e.g., silicon oxide). The second bonding contacts 1241 and the surrounding dielectric in the second bonding layer 1240 may be used for hybrid bonding.

[0052] In the exemplary embodiment of the present application, Figure 3 As shown, the first semiconductor structure 1100 may include a memory array 1110 (including transistors 1111 and capacitors 1112 ) and a bit line 1120 .

[0053] The memory array 1110 may include a plurality of memory cells such as DRAM memory cells. Each memory cell may include a capacitor 1112 for storing a data bit as a positive charge or a negative charge and one or more transistors 1111 (also referred to as a pass transistor 1111) for controlling (e.g., switching and selecting) access to the memory cell.

[0054] The transistor 1111 may be a vertical transistor, which may include a semiconductor pillar 100 and a gate structure 200 in contact with the semiconductor pillar 100. The semiconductor pillar 100 may be used to form an active region of multiple channels in the vertical transistor 1111. The gate structure 200 may be used to connect to a peripheral circuit 1220 (located in the second semiconductor structure) to achieve transmission of electrical signals between the gate structure 200 and the peripheral circuit 1220.

[0055] The semiconductor column 100 may extend along the first direction Z. The semiconductor column 100 may have a cubic shape to expose its four side walls. It should be understood that the semiconductor column 100 may have any suitable three-dimensional shape, such as a polyhedral shape or a cylindrical shape. That is, the cross section of the semiconductor column 100 in a plan view (e.g., in the second direction X-third direction Y plane, where the first direction Z, the second direction X and the third direction Y intersect each other) may have a square shape, a rectangular shape (or a trapezoidal shape), a circular shape (or an elliptical shape) or any other suitable shape. The material of the semiconductor column 100 may include at least one of single crystal silicon, polycrystalline silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials or other semiconductor materials known in the art.

[0056] The gate structure 200 may be located on the sidewall of the semiconductor pillar 100 and may extend along the third direction Y. The gate structure 200 may include a gate dielectric layer 210 and a gate layer 220. The gate dielectric layer 210 may be located on the sidewall of the semiconductor pillar 100. The gate layer 220 may be located on the surface of the gate dielectric layer 210. The gate dielectric layer 210 may include any suitable dielectric material, for example, silicon oxide, silicon nitride, silicon oxynitride, or a high dielectric constant material layer. For example, the gate dielectric layer 210 may include silicon oxide, i.e., gate oxide. The gate layer 220 may include any suitable conductive material, such as polysilicon, metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), metal compound (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.) or silicide. For example, the gate layer 220 may include doped polysilicon, i.e., gate polysilicon. In some embodiments, the gate layer 220 includes a plurality of conductive layers, such as a W layer on a TiN layer.

[0057] For example, the gate structure 200 may be located on at least one sidewall of the semiconductor pillar 100, that is, the semiconductor pillar 100 may be at least partially surrounded by the gate structure 200. For example, the semiconductor pillar 100, the gate dielectric layer 210, and the gate layer 220 may be radially arranged in this order from the center of the vertical transistor 1111. For example, the gate dielectric layer 210 may surround and contact the semiconductor pillar 100. The gate layer 220 may surround and contact the gate dielectric layer 210. It should be understood that Figure 3The situation in which the gate structure 200 is located on one sidewall of the semiconductor pillar 100 is only an example and is not specifically limited.

[0058] In one embodiment of the present application, the gate structure 200 may be located on multiple sidewalls of the semiconductor column 100, that is, adjacent semiconductor columns 100 along the second direction X may be spaced apart by the gate structure 200. At this time, the semiconductor column 100 and the gate structure 200 may be used together to form a multi-gate transistor (for example, a gate-all-around (GAA) transistor, a tri-gate transistor, or a dual-gate transistor). The multi-gate transistor may have a larger gate control area to achieve better channel control with a smaller subthreshold swing. During the cut-off state, the leakage current of the multi-gate transistor may also be significantly reduced due to the complete depletion of the channel. Therefore, the use of a multi-gate transistor may achieve better speed (saturated drain current) / leakage current performance.

[0059] In another embodiment of the present application, the first semiconductor structure 1100 may further include an isolation structure 1113. The gate structure 200 and the isolation structure 1113 may be respectively located on two opposite side walls of the semiconductor column 100, that is, adjacent semiconductor columns 100 along the second direction X may be spaced apart by the gate structure 200 or the isolation structure 1113. At this time, the semiconductor column 100 and the gate structure 200 may be used together to form a single-gate transistor. Exemplarily, the single-gate transistors adjacent to each other along the first direction may be arranged in a mirror-symmetrical manner. By providing a single-gate transistor, the present application can significantly increase the density of the semiconductor column 100 in the first direction and reduce the difficulty of the manufacturing process. In addition, the mirror-symmetrical single-gate transistor may have a larger process window, which is conducive to reducing the spacing between the bit line 1120, the word line and the transistor 1111 formed subsequently.

[0060] It should be understood that the "mirror symmetry" defined in the present application is not a strict definition, and mirror symmetry can be approximately understood as approximately mirror symmetry. In actual processes, the non-mirror symmetry caused by process errors and / or other factors will not have a practical impact on the semiconductor structure provided by the present application, and also falls within the scope of protection of the present application.

[0061] By way of example, the isolation structure 1113 may include an isolation conductive layer 410 and an isolation dielectric layer 420 surrounding the isolation conductive layer 410. The material of the isolation conductive layer 410 may include, but is not limited to, metal materials such as tungsten W, copper Cu, titanium nitride TiN, etc. The material of the isolation dielectric layer 420 may include, but is not limited to, silicon oxide.

[0062] Exemplarily, the first semiconductor structure 1100 may further include a lead-out structure (not shown) connected to the isolation structure 1113. In the present application, the lead-out structure may be grounded or a certain fixed potential may be applied to the lead-out structure, so that the isolation structure 1113 may electrically insulate adjacent semiconductor pillars 100 and reduce coupling between adjacent transistors 1111.

[0063] Exemplarily, the transistor 1111 may have a first end and a second end opposite to each other along the first direction Z, wherein the first end of the transistor 1111 (such as the first end of the semiconductor column 100) may have a first doped region 110, and the second end of the transistor 1111 (such as the second end of the semiconductor column 100) may have a second doped region 120. The first doped region 110 and the second doped region 120 may be the source and the drain of the semiconductor column 100, respectively. The source and the drain may be doped with any suitable P-type dopant (e.g., boron (B) or gallium (Ga)) or any suitable N-type dopant (e.g., phosphorus (P) or arsenic (As)). The source and the drain may be separated by the gate structure 200 in the first direction Z. That is, the gate structure 200 is vertically formed between the source and the drain. When a gate voltage applied to gate layer 220 of gate structure 200 is higher than a threshold voltage of vertical transistor 1111 (including gate structure 200 and semiconductor pillar 100 ), one or more channels of vertical transistor 1111 may be vertically formed in semiconductor pillar 100 between a source and a drain.

[0064] The capacitor 1112 may be connected to the first end of the semiconductor column 100, such as being connected to the first doped region 110 (e.g., a source region). The capacitor 1112 may include a first electrode 310 connected to the first doped region 110, a capacitor dielectric layer 320 in contact with the first electrode 310, and a second electrode 330 in contact with the capacitor dielectric layer 320. The capacitor 1112 may include, but is not limited to, planar capacitors, stacked capacitors, multi-fin capacitors, cylindrical capacitors, trench capacitors, or first substrate-plate capacitors. Exemplarily, the capacitor 1112 may be a vertical capacitor, in which the first electrode 310, the capacitor dielectric layer 320, and the second electrode 330 are stacked along a first direction Z, and the capacitor dielectric layer 320 may be sandwiched between the first electrode 310 and the second electrode 330.

[0065] The bit line 1120 may be connected to the second end of the semiconductor pillar 100, such as the second doped region 120, and may extend along the second direction X. The word line may be coupled to the gate structure of the transistor 1111 to turn the transistor 1111 on or off. The bit line 1120 may be coupled to the second doped region 120 (e.g., the drain region) of the transistor 1111, and may function as a path for charging or discharging the capacitor 1112.

[0066] By way of example, the first semiconductor structure 1100 may further include an interconnect layer 1130 located on the memory array 1110 and connected to the bit line 1120. The interconnect layer 1130 may include an interconnect structure (also referred to as a “contact structure”) in a plurality of dielectric layers to electrically connect to the memory cell through the bit line 1120.

[0067] Exemplarily, the first semiconductor structure 1100 may further include a first bonding layer 1140 located on the interconnect layer 1130. The first bonding layer 1140 may include a plurality of first bonding contacts 1141 and a dielectric isolating the first bonding contacts 1141. The first bonding contacts 1141 may include a conductive material, such as Cu. The remaining area of ​​the first bonding layer 1140 may be formed of a dielectric material (e.g., silicon oxide). The first bonding contacts 1141 and the surrounding dielectric in the first bonding layer 1140 may be used for hybrid bonding.

[0068] like Figures 4 to 6 As shown, the present application provides a process step diagram for forming a first semiconductor structure 1100. It should be understood that although the present application provides a process for forming a first semiconductor structure 1100, the process is not a necessary step for implementing the present application. The present application can manufacture a semiconductor structure based on the existing process for forming the first semiconductor structure 1100. In addition, the process for forming the first semiconductor structure 1100 provided in the present application is only used as an example and is not specifically limited. In the actual process, the process for forming the first semiconductor structure 1100 can be reasonably set according to actual needs.

[0069] For example, Figure 4 As shown, a memory array 1110 may be formed on a first substrate 1150 , wherein the memory array 1110 includes a transistor 1111 and a capacitor 1112 connected to a first end of the transistor 1111 away from the first substrate 1150 .

[0070] The first substrate 1150 may be used to support the memory array 1110 thereon, and may be removed in a subsequent process. The material of the first substrate 1150 includes at least one of single crystal silicon, polycrystalline silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art. Exemplarily, the first substrate 1150 may be formed by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0071] For example, Figure 5As shown, the second substrate 1160 may be formed on a side of the memory array 1110 away from the first substrate 1150. For example, the second substrate 1160 may be bonded to the surface of the memory array 1110 away from the first substrate 1150 by a bonding process. For example, the second substrate 1160 and the memory array 1110 may be bonded by any suitable bonding process (e.g., anodic bonding, melt bonding, transfer bonding, adhesive bonding, eutectic bonding, etc.). In the present application, the second substrate 1160 may be bonded to the memory array 1110 by bonding the second substrate 1160 to the memory array 1110. Figure 5 The structure shown is flipped 180° before subsequent processing.

[0072] Figure 6 For the general Figure 5 A schematic diagram of a structure in which the structure is flipped 180° and then thinned. In an exemplary embodiment of the present application, Figure 6 As shown, the first substrate 1150 may be removed, and a bit line 1120 extending along a second direction X may be formed at a second end of the transistor 1111 opposite to the first end.

[0073] For example, a planarization process (eg, CMP) and / or an etching process may be used to remove the first substrate 1150 to expose the second doping region 120 of the semiconductor pillar 100 , wherein the bit line 1120 may be connected to the second doping region 120 .

[0074] By way of example, an interconnection layer 1130 connected to the bit line 1120 may be formed on the memory array 1110. The interconnection layer 1130 may include a plurality of interconnection structures, such as a bit line contact 1131 connected to the bit line 1120 and a word line contact 1132 connected to the word line. By way of example, the peripheral circuit 1220 in the second semiconductor structure 1200 may include a word line driver / row decoder coupled to the word line contact 1132 and / or a bit line driver / column decoder coupled to the bit line contact 1131.

[0075] Exemplarily, the interconnect structure in the interconnect layer 1130 may include a conductive material deposited by one or more thin film deposition processes (including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, or any combination thereof). The manufacturing process for forming the interconnect may also include photolithography, chemical mechanical polishing (CMP), wet / dry etching, or any other suitable process. The dielectric layer may include a dielectric material deposited using one or more thin film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof).

[0076] For example, a first bonding layer 1140 may be formed on the interconnection layer 1130. The first bonding layer 1140 may include a plurality of first bonding contacts 1141 and a dielectric for isolating the first bonding contacts 1141, wherein the first bonding contacts 1141 may be connected to an interconnection structure (such as a bit line contact 1131 and / or a word line contact 1132) in the interconnection layer 1130.

[0077] Exemplarily, a dielectric layer (e.g., a dielectric layer) may be deposited on the surface of the interconnect layer 1130 by one or more thin film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). Then, a contact hole passing through the dielectric layer may be first patterned by using a patterning process (e.g., photolithography and dry / wet etching of a dielectric material in the dielectric layer) to form a first bonding contact 1141 passing through the dielectric layer and contacting the interconnect structure in the interconnect layer 1130. The contact hole may be filled with a conductor (e.g., Cu). In some embodiments, filling the contact hole includes depositing a barrier layer, an adhesion layer, and / or a seed layer before depositing the conductor.

[0078] In the exemplary embodiment of the present application, Figure 7 As shown, the first semiconductor structure 1100 and the second semiconductor structure 1200 may be bonded to form a bonding structure 1300 , wherein the bonding structure 1300 may be located between the first semiconductor structure 1100 and the second semiconductor structure 1200 .

[0079] For example, the first bonding layer 1140 in the first semiconductor structure 1100 and the second bonding layer 1240 in the second semiconductor structure 1200 may be bonded face to face to form a bonding structure 1300, wherein the bonding structure 1300 may include the first bonding layer 1140 and the second bonding layer 1240. After bonding, the first bonding contact 1141 and the second bonding contact 1241 may be in contact at the bonding interface.

[0080] By way of example, the bit line 1120 may be coupled to the peripheral circuit 1220 in the second semiconductor structure 1200 through the bit line contact 1131 in the interconnect layer 1130, the first bonding contact 1141 in the first bonding layer 1140, the second bonding contact 1241 in the second bonding layer 1240, and the interconnect structure in the peripheral interconnect layer 1230. Similarly, the word line may be coupled to the peripheral circuit 1220 in the second semiconductor structure 1200 through the word line contact 1132 in the interconnect layer 1130, the first bonding contact 1141 in the first bonding layer 1140, the second bonding contact 1241 in the second bonding layer 1240, and the interconnect structure in the peripheral interconnect layer 1230. By way of example, the word line contact 1132 may be understood as a contact structure connected to the gate structure 200, wherein the contact structure may be connected to the second semiconductor structure 1200 through the bonding structure 1300.

[0081] For example, Figure 7 As shown, after the first semiconductor structure 1100 and the second semiconductor structure 1200 are bonded, the second substrate 1160 may be removed. For example, the second substrate 1160 may be removed by using a planarization process (eg, CMP) and / or an etching process.

[0082] In the exemplary embodiment of the present application, Figure 8 As shown, a power line 1700 may be formed on a side away from the bonding structure 1300, wherein the power line 1700 may supply power to the second semiconductor structure 1200, and the second semiconductor structure 1200 after power supply may control the memory array 1110. For example, the power line 1700 may be formed after the first semiconductor structure 1100 and the second semiconductor structure 1200 are bonded.

[0083] In an exemplary embodiment of the present application, Figure 8 As shown, forming a power line 1700 on a side away from the bonding structure 1300 may include: forming the power line 1700 on a side of the first semiconductor structure 1100 away from the bonding structure 1300. For example, a conductive plug 1420 extending along a first direction Z may be formed in the first semiconductor structure 1100, wherein the first direction Z is perpendicular to the extension direction of the bonding structure 1300, and the conductive plug 1420 may be connected to the second semiconductor structure 1200; and forming a power line 1700 extending along a second direction X and connected to the conductive plug 1420 on a side of the first semiconductor structure 1100 away from the bonding structure 1300.

[0084] For example, a plurality of interconnection contacts 1410 extending along the first direction Z and connected to the memory array 1110 and a conductive plug 1420 extending along the first direction Z may be formed in the first semiconductor structure 1100 .

[0085] The interconnection contact 1410 may be connected to the second electrode 330 of the capacitor 1112 in the memory array 1110. In the present application, the first electrode 310 of each capacitor 1112 may be coupled to the first doped region 110 of the corresponding vertical transistor 1111 in the memory cell. The second electrodes 330 of the plurality of capacitors 1112 may be commonly coupled to the same voltage terminal or a common ground terminal. For example, the interconnection contact 1410 may be used to couple the second electrodes 330 of the plurality of capacitors 1112 to the peripheral circuit 1220 or directly to the ground.

[0086] The conductive plug 1420 may be located at one side of the memory array 1110 along the second direction X, and is used to couple the subsequently formed power line 1700 and the pad lead-out structure 1800 to the peripheral circuit 1220 in the second semiconductor structure 1200. Specifically, a plurality of conductive plugs 1420 extending along the first direction Z may be formed at one side of the memory array 1110 along the second direction X. For example, the conductive plug 1420 may include a first conductive plug 1421 connected to the subsequently formed power line 1700, a second conductive plug 1422 close to the interconnection contact 1410 and connected to the second electrode 330, and a third conductive plug 1423 connected to the subsequently formed pad lead-out structure 1800.

[0087] In the exemplary embodiment of the present application, Figure 8 As shown, an interconnection layer 1500 may be formed on the interconnection contacts 1410 and the conductive plugs 1420. The interconnection layer 1500 may include a first interconnection layer 1510, a second interconnection layer 1520, and a third interconnection layer 1530. For example, the first interconnection layer 1510 may extend along the second direction X and be connected to a plurality of interconnection contacts 1410 and a second conductive plug 1422, wherein the second electrodes 330 of a plurality of capacitors 1112 may be coupled to a peripheral circuit 1220 in the second semiconductor structure 1200 that can provide a certain voltage via the interconnection contacts 1410, the first interconnection layer 1510, and the second conductive plug 1422. The second interconnection layer 1520 may be connected to the first conductive plug 1421. The third interconnection layer 1530 may be connected to the third conductive plug 1423.

[0088] In the exemplary embodiment of the present application, Figure 8 As shown, the first conductive contact 1610 may be formed on the second interconnect layer 1520. For example, in the process of forming the first conductive contact 1610, the second conductive contact 1620 may also be formed on the third interconnect layer 1530.

[0089] For example, a power line 1700 extending along the second direction X may be formed on the first conductive contact 1610. The power line 1700 may be connected to the second semiconductor structure 1200 via the first conductive contact 1610, the second interconnect layer 1520, and the first conductive plug 1421. The power line 1700 may supply power to the second semiconductor structure 1200, and the second semiconductor structure 1200 after supplying power may control the memory array 1110.

[0090] In the present application, the side of the first semiconductor structure 1100 away from the bonding structure 1300 has a larger space. By forming the power line 1700 on the side of the first semiconductor structure 1100 away from the bonding structure 1300, the power line 1700 can be formed in a larger space. In this way, the wiring mode of the power line 1700 can be increased, the wiring freedom of the power line 1700 can be improved, and the wiring length of the power line 1700 can be reduced, which is conducive to reducing the overall size of the semiconductor structure. The coupling phenomenon between the power line 1700 and other conductive wiring (such as bit line wiring) can also be reduced, and the sensing margin of related components (such as bit line 1200) can be improved.

[0091] Exemplarily, in the process of forming the power line 1700, a conductive line 1710 may also be formed on the second conductive contact 1620. The power line 1700 and the conductive line 1710 may be located in the same layer. The power line 1700 and the conductive line 1710 may include conductive materials, including but not limited to W, Cu, Al, doped silicon, silicide, or any combination thereof.

[0092] For example, a pad lead-out structure 1800 may be formed on the conductive line 1710. The pad lead-out structure 1800 may be connected to the second semiconductor structure 1200 via the conductive line 1710, the second conductive contact 1620, the third interconnect layer 1530, and the third conductive plug 1423. The pad lead-out structure 1800 may transmit electrical signals between the semiconductor structure and an external circuit.

[0093] Specifically, a pad lead-out interconnection layer may be formed on the conductive line 1710, and then a pad lead-out structure 1800 may be formed that passes through the pad lead-out interconnection layer and extends to the conductive line 1710. The pad lead-out structure 1800 may include a conductive material, including but not limited to W, Cu, Al, doped silicon, silicide, or any combination thereof. The pad lead-out interconnection layer may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant material layer, or any combination thereof.

[0094] In another exemplary embodiment of the present application, forming the power line 1700 on a side away from the bonding structure 1300 may include: forming the power line 1700 on a side of the second semiconductor structure 1200 away from the bonding structure 1300. It should be understood that the process of forming the power line 1700 on the side of the second semiconductor structure 1200 away from the bonding structure 1300 is similar to the process of forming the power line 1700 on the side of the first semiconductor structure 1100 away from the bonding structure 1300. To avoid redundancy, the present application will not introduce the process of forming the power line 1700 on the side of the second semiconductor structure 1200 away from the bonding structure 1300.

[0095] In the present application, the side of the second semiconductor structure 1200 away from the bonding structure 1300 has a larger space. By forming the power line 1700 on the side of the second semiconductor structure 1200 away from the bonding structure 1300, the space for forming the power line 1700 can also be larger. In this way, the wiring mode of the power line 1700 can be increased, the wiring freedom of the power line 1700 can be improved, and the wiring length of the power line 1700 can be reduced, which is conducive to reducing the overall size of the semiconductor structure. The coupling phenomenon between the power line 1700 and other conductive wiring (such as bit line wiring) can also be reduced, and the sensing margin of related components (such as bit line 1200) can be improved.

[0096] Figure 8 is a schematic structural diagram of a semiconductor structure according to an exemplary embodiment of the present application.

[0097] The semiconductor structure may include a first semiconductor structure 1100 and a second semiconductor structure 1200 bonded to each other, a bonding structure 1300 , and a power line 1700 .

[0098] The second semiconductor structure 1200 may include a third substrate 1210 and a peripheral circuit 1220 extending into the third substrate 1210 .

[0099] The material of the third substrate 1210 may include at least one of single crystal silicon, polycrystalline silicon, single crystal germanium, group III-V compound semiconductor materials, group II-VI compound semiconductor materials, or other semiconductor materials known in the art.

[0100] The peripheral circuit 1220 (also referred to as the control and sensing circuit) may include any suitable digital, analog and / or mixed signal circuits for facilitating the operation of the memory cell array. For example, the peripheral circuit 1220 may include one or more of a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), an input / output (I / O) circuit, a charge pump, a voltage source or generator, a current or voltage reference, any portion (e.g., a subcircuit) of the above functional circuits, or any active or passive component of the circuit (e.g., a peripheral transistor, a diode, a resistor, or a capacitor). For example, the peripheral circuit 1220 may include a plurality of peripheral transistors 1221. The source, drain, and channel of the peripheral transistor 1221 may be located in the third substrate 1210, and the gate of the peripheral transistor 1221 may be located on the third substrate 1210.

[0101] Exemplarily, the second semiconductor structure 1200 may further include trench isolation (eg, shallow trench isolation (STI)) formed on or in the third substrate 1210 .

[0102] Exemplarily, the second semiconductor structure 1200 may further include a peripheral interconnect layer 1230 located on the peripheral circuit 1220 to transmit electrical signals to and from the peripheral circuit 1220. The peripheral interconnect layer 1230 may include a plurality of interconnect structures (also referred to as "contact structures"), wherein the interconnect structure may include lateral interconnect lines and interconnect contacts. The peripheral interconnect layer 1230 may also include one or more dielectric layers for separating the plurality of interconnect lines and / or interconnect contacts. That is, the peripheral interconnect layer 1230 may include interconnect lines and interconnect contacts in a plurality of dielectric layers. Exemplarily, the peripheral circuits 1220 may be coupled to each other through the interconnect structures in the peripheral interconnect layer 1230. The material of the interconnect structure in the peripheral interconnect layer 1230 may include a conductive material, such as including but not limited to tungsten (W), copper (Cu), aluminum (Al), doped silicon, silicide, or any combination thereof. The dielectric layer may be formed of a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant material layer, or any combination thereof.

[0103] The first semiconductor structure 1100 may include a memory array 1110 (including transistors 1111 and capacitors 1112) and a bit line 1120. The memory array 1110 may include a plurality of memory cells such as DRAM memory cells. Each memory cell may include a capacitor 1112 for storing a data bit as a positive charge or a negative charge and one or more transistors 1111 (also referred to as a pass transistor 1111) for controlling (e.g., switching and selecting) access to the memory cell.

[0104] The transistor 1111 may be a vertical transistor, which may include a semiconductor pillar 100 and a gate structure 200 in contact with the semiconductor pillar 100. The semiconductor pillar 100 may be used to form an active region of multiple channels in the vertical transistor 1111. The gate structure 200 may be used to connect to a peripheral circuit 1220 (located in the second semiconductor structure) to achieve transmission of electrical signals between the gate structure 200 and the peripheral circuit 1220.

[0105] The semiconductor column 100 may extend along the first direction Z. The semiconductor column 100 may have a cubic shape to expose its four side walls. It should be understood that the semiconductor column 100 may have any suitable three-dimensional shape, such as a polyhedral shape or a cylindrical shape. That is, the cross section of the semiconductor column 100 in a plan view (e.g., in the second direction X-third direction Y plane, where the first direction Z, the second direction X and the third direction Y intersect each other) may have a square shape, a rectangular shape (or a trapezoidal shape), a circular shape (or an elliptical shape) or any other suitable shape. The material of the semiconductor column 100 may include at least one of single crystal silicon, polycrystalline silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials or other semiconductor materials known in the art.

[0106] The gate structure 200 may be located on the sidewall of the semiconductor pillar 100 and may extend along the third direction Y. The gate structure 200 may include a gate dielectric layer 210 and a gate layer 220. The gate dielectric layer 210 may be located on the sidewall of the semiconductor pillar 100. The gate layer 220 may be located on the surface of the gate dielectric layer 210. The gate dielectric layer 210 may include any suitable dielectric material, for example, silicon oxide, silicon nitride, silicon oxynitride, or a high dielectric constant material layer. For example, the gate dielectric layer 210 may include silicon oxide, i.e., gate oxide. The gate layer 220 may include any suitable conductive material, such as polysilicon, metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), metal compound (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.) or silicide. For example, the gate layer 220 may include doped polysilicon, i.e., gate polysilicon. In some embodiments, the gate layer 220 includes a plurality of conductive layers, such as a W layer on a TiN layer.

[0107] For example, the gate structure 200 may be located on at least one sidewall of the semiconductor pillar 100, that is, the semiconductor pillar 100 may be at least partially surrounded by the gate structure 200. For example, the semiconductor pillar 100, the gate dielectric layer 210, and the gate layer 220 may be radially arranged in this order from the center of the vertical transistor 1111. For example, the gate dielectric layer 210 may surround and contact the semiconductor pillar 100. The gate layer 220 may surround and contact the gate dielectric layer 210. It should be understood that Figure 3 The situation in which the gate structure 200 is located on one sidewall of the semiconductor pillar 100 is only an example and is not specifically limited.

[0108] In one embodiment of the present application, the gate structure 200 may be located on multiple sidewalls of the semiconductor column 100, that is, adjacent semiconductor columns 100 along the second direction X may be spaced apart by the gate structure 200. At this time, the semiconductor column 100 and the gate structure 200 may be used together to form a multi-gate transistor (for example, a gate-all-around (GAA) transistor, a tri-gate transistor, or a dual-gate transistor). The multi-gate transistor may have a larger gate control area to achieve better channel control with a smaller subthreshold swing. During the cut-off state, the leakage current of the multi-gate transistor may also be significantly reduced due to the complete depletion of the channel. Therefore, the use of a multi-gate transistor may achieve better speed (saturated drain current) / leakage current performance.

[0109] In another embodiment of the present application, the first semiconductor structure 1100 may further include an isolation structure 1113. The gate structure 200 and the isolation structure 1113 may be respectively located on two opposite side walls of the semiconductor column 100, that is, adjacent semiconductor columns 100 along the second direction X may be spaced apart by the gate structure 200 or the isolation structure 1113. At this time, the semiconductor column 100 and the gate structure 200 may be used together to form a single-gate transistor. Exemplarily, the single-gate transistors adjacent to each other along the first direction may be arranged in a mirror-symmetrical manner. By providing a single-gate transistor, the present application can significantly increase the density of the semiconductor column 100 in the first direction and reduce the difficulty of the manufacturing process. In addition, the mirror-symmetrical single-gate transistor may have a larger process window, which is conducive to reducing the spacing between the bit line 1120, the word line and the transistor 1111 formed subsequently.

[0110] It should be understood that the "mirror symmetry" defined in the present application is not a strict definition, and mirror symmetry can be approximately understood as approximately mirror symmetry. In actual processes, the non-mirror symmetry caused by process errors and / or other factors will not have a practical impact on the semiconductor structure provided by the present application, and also falls within the scope of protection of the present application.

[0111] By way of example, the isolation structure 1113 may include an isolation conductive layer 410 and an isolation dielectric layer 420 surrounding the isolation conductive layer 410. The material of the isolation conductive layer 410 may include, but is not limited to, metal materials such as tungsten W, copper Cu, titanium nitride TiN, etc. The material of the isolation dielectric layer 420 may include, but is not limited to, silicon oxide.

[0112] Exemplarily, the first semiconductor structure 1100 may further include a lead-out structure (not shown) connected to the isolation structure 1113. In the present application, the lead-out structure may be grounded or a certain fixed potential may be applied to the lead-out structure, so that the isolation structure 1113 may electrically insulate adjacent semiconductor pillars 100 and reduce coupling between adjacent transistors 1111.

[0113] Exemplarily, the transistor 1111 may have a first end and a second end opposite to each other along the first direction Z, wherein the first end of the transistor 1111 (such as the first end of the semiconductor column 100) may have a first doped region 110, and the second end of the transistor 1111 (such as the second end of the semiconductor column 100) may have a second doped region 120. The first doped region 110 and the second doped region 120 may be the source and the drain of the semiconductor column 100, respectively. The source and the drain may be doped with any suitable P-type dopant (e.g., boron (B) or gallium (Ga)) or any suitable N-type dopant (e.g., phosphorus (P) or arsenic (As)). The source and the drain may be separated by the gate structure 200 in the first direction Z. That is, the gate structure 200 is vertically formed between the source and the drain. When a gate voltage applied to gate layer 220 of gate structure 200 is higher than a threshold voltage of vertical transistor 1111 (including gate structure 200 and semiconductor pillar 100 ), one or more channels of vertical transistor 1111 may be vertically formed in semiconductor pillar 100 between a source and a drain.

[0114] The capacitor 1112 may be connected to the first end of the semiconductor column 100, such as being connected to the first doped region 110 (e.g., a source region). The capacitor 1112 may include a first electrode 310 connected to the first doped region 110, a capacitor dielectric layer 320 in contact with the first electrode 310, and a second electrode 330 in contact with the capacitor dielectric layer 320. The capacitor 1112 may include, but is not limited to, planar capacitors, stacked capacitors, multi-fin capacitors, cylindrical capacitors, trench capacitors, or first substrate-plate capacitors. Exemplarily, the capacitor 1112 may be a vertical capacitor, in which the first electrode 310, the capacitor dielectric layer 320, and the second electrode 330 are stacked along a first direction Z, and the capacitor dielectric layer 320 may be sandwiched between the first electrode 310 and the second electrode 330.

[0115] The bit line 1120 may be connected to the second end of the semiconductor pillar 100, such as the second doped region 120, and may extend along the second direction X. The word line may be coupled to the gate structure of the transistor 1111 to turn the transistor 1111 on or off. The bit line 1120 may be coupled to the second doped region 120 (e.g., the drain region) of the transistor 1111, and may function as a path for charging or discharging the capacitor 1112.

[0116] By way of example, the first semiconductor structure 1100 may further include an interconnect layer 1130 located on the memory array 1110 and connected to the bit line 1120. The interconnect layer 1130 may include an interconnect structure (also referred to as a “contact structure”) in a plurality of dielectric layers to electrically connect to the memory cell through the bit line 1120.

[0117] The bonding structure 1300 may be located between the first semiconductor structure 1100 and the second semiconductor structure 1200. The bonding structure 1300 may include a first bonding layer 1140 located on the interconnect layer 1130 and a second bonding layer 1240 located on the peripheral interconnect layer 1230. The first bonding layer 1140 may include a plurality of first bonding contacts 1141 and a dielectric isolating the first bonding contacts 1141. The second bonding layer 1240 may include a plurality of second bonding contacts 1241 and a dielectric isolating the second bonding contacts 1241. The first bonding contacts 1141 and the second bonding contacts 1241 may contact at a bonding interface. The first bonding contacts 1141 and the second bonding contacts 1241 may include a conductive material, such as Cu. The remaining area of ​​the first bonding layer 1140 and / or the second bonding contacts 1241 may be formed of a dielectric material (e.g., silicon oxide).

[0118] The power line 1700 may be located on a side away from the bonding structure 1300, wherein the power line 1700 may supply power to the second semiconductor structure 1200, and the second semiconductor structure 1200 after supplying power may control the memory array 1110. In one embodiment of the present application, the power line 1700 may be located on a side of the first semiconductor structure 1100 away from the bonding structure 1300. Of course, in another embodiment of the present application, the power line 1700 may be located on a side of the second semiconductor structure 1200 away from the bonding structure 1300.

[0119] In the present application, the side of the first semiconductor structure 1100 away from the bonding structure 1300 has a larger space. By forming the power line 1700 on the side of the first semiconductor structure 1100 away from the bonding structure 1300, the power line 1700 can be formed in a larger space. In this way, the wiring mode of the power line 1700 can be increased, the wiring freedom of the power line 1700 can be improved, and the wiring length of the power line 1700 can be reduced, which is conducive to reducing the overall size of the semiconductor structure. The coupling phenomenon between the power line 1700 and other conductive wiring (such as bit line wiring) can also be reduced, and the sensing margin of related components (such as bit line 1200) can be improved.

[0120] Exemplarily, the semiconductor structure may further include a first conductive plug 1421 connected to the power line 1700. The first conductive plug 1421 may be located in the first semiconductor structure 1100 and extend along a first direction Z, wherein the first direction Z is perpendicular to the second direction X, and the power line 1700 supplies power to the second semiconductor structure 1200 via the first conductive plug 1421.

[0121] In the exemplary embodiment of the present application, the semiconductor structure may further include a contact structure (such as a word line contact 1132) and a bit line contact 1131. The contact structure may be connected to the gate structure 200 and may be connected to the second semiconductor structure 1200 through the bonding structure 1300. For example, the word line may be coupled to the peripheral circuit 1220 in the second semiconductor structure 1200 through the word line contact 1132 in the interconnect layer 1130, the first bonding contact 1141 in the first bonding layer 1140, the second bonding contact 1241 in the second bonding layer 1240, and the interconnect structure in the peripheral interconnect layer 1230. Similarly, the bit line 1120 may be coupled to the peripheral circuit 1220 in the second semiconductor structure 1200 through the bit line contact 1131 in the interconnect layer 1130, the first bonding contact 1141 in the first bonding layer 1140, the second bonding contact 1241 in the second bonding layer 1240, and the interconnect structure in the peripheral interconnect layer 1230.

[0122] In the exemplary embodiment of the present application, the semiconductor structure may further include a plurality of interconnection contacts 1410 , a second conductive plug 1422 , and a first interconnection layer 1510 within the first semiconductor structure 1100 .

[0123] The interconnection contacts 1410 may extend along the first direction Z and be connected to the memory array 1110. For example, the plurality of interconnection contacts 1410 may be connected to the second electrodes 330 of the capacitors 1112 in the memory array 1110. The second conductive plug 1422 may be adjacent to the first conductive plug 1421 and close to the interconnection contact 1410. The second conductive plug 1422 may pass through the first semiconductor structure 1100 along the first direction Z and be connected to the second semiconductor structure 1200 through the bonding structure 1300. The first interconnection layer 1510 may extend along the second direction X and be connected to the plurality of interconnection contacts 1410 and the second conductive plug 1422.

[0124] In the present application, the first electrode 310 of each capacitor 1112 may be coupled to the first doped region 110 of the corresponding vertical transistor 1111 in the memory cell. The second electrodes 330 of the plurality of capacitors 1112 may be commonly coupled to the same voltage terminal or a common ground terminal. The interconnection contact 1410 may be used to couple the second electrodes 330 of the plurality of capacitors 1112 to the peripheral circuit 1220 or directly to the ground. Specifically, the second electrodes 330 of the plurality of capacitors 1112 may be connected to the second semiconductor structure 1200 via the interconnection contact 1410, the first interconnection layer 1510, and the second conductive plug 1422.

[0125] In the exemplary embodiment of the present application, the semiconductor structure may further include a second interconnect layer 1520 and a first conductive contact 1610. The second interconnect layer 1520 may be connected to the first conductive plug 1421. The first conductive contact 1610 may be connected to the second interconnect layer 1520. The power line 1700 may be located on the first conductive contact 1610 and may be connected to the second semiconductor structure 1200 via the first conductive contact 1610, the second interconnect layer 1520, and the first conductive plug 1421.

[0126] In the exemplary embodiment of the present application, the semiconductor structure may further include a third conductive plug 1423, a third interconnect layer 1530, a second conductive contact 1620, a conductive line 1710, and a pad lead-out structure 1800. The third conductive plug 1423 may be adjacent to the first conductive plug 1421, may pass through the first semiconductor structure 1100 along the first direction Z, and may be connected to the second semiconductor structure 1200 through the bonding structure 1300. The third interconnect layer 1530 may be located on the third conductive plug 1423 and connected to the third conductive plug 1423. The second conductive contact 1620 may be located on the third interconnect layer and connected to the third interconnect layer. The conductive line 1710 may be located on the second conductive contact 1620 and connected to the second conductive contact 1620. The pad lead-out structure 1800 may be located on the conductive line 1710 and connected to the conductive line 1710 , wherein the pad lead-out structure 1800 is connected to the second semiconductor structure 1200 via the conductive line 1710 , the second conductive contact 1620 , the third interconnect layer 1530 and the third conductive plug 1423 .

[0127] The power line 1700 and the conductive line 1710 may be located in the same level. The pad lead-out structure 1800 may transmit electrical signals between the semiconductor structure and the external circuit. The power line 1700, the conductive line 1710 and the pad lead-out structure 1800 may include conductive materials, including but not limited to W, Cu, Al, doped silicon, silicide or any combination thereof. The pad lead-out interconnect layer may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant material layer or any combination thereof.

[0128] Since the contents and structures involved in the method 1000 for manufacturing a semiconductor structure described above may be fully or partially applicable to the semiconductor structure described herein, the contents related or similar thereto will not be described in detail herein.

[0129] Although the exemplary structure and method of making the semiconductor structure are described herein, it is understood that one or more features may be omitted, replaced or added from the method of making the semiconductor structure. In addition, the illustrated layers and materials thereof are merely exemplary.

[0130] Fig. 9is a block diagram of a system 10 having a storage system 12 according to an exemplary embodiment of the present application.

[0131] The system 10 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device (the electronic device having the storage system 12 located therein). Fig. 9 As shown, the system 10 may include a host 18 and a storage system 12, the storage system 12 having one or more three-dimensional memories 14 and a controller 16. The host 18 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system-on-chip (SoC), such as an application processor (AP). The host 18 may be configured to send or receive data to or from the three-dimensional memory 14.

[0132] The three-dimensional memory 14 may include a semiconductor structure described in any embodiment of the present application. According to some embodiments, the controller 16 is coupled to the three-dimensional memory 14 and the host 18, and is configured to control the three-dimensional memory 14. The controller 16 may manage data stored in the three-dimensional memory 14 and communicate with the host 18. For example, the controller 16 may communicate with an external device (e.g., the host 18) according to a specific communication protocol.

[0133] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of disclosure involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other.

Claims

1. A method for manufacturing a semiconductor structure, It is characterized in that include: Bonding a first semiconductor structure and a second semiconductor structure to form a bonding structure, wherein the first semiconductor structure includes a memory array, and the bonding structure is located between the first semiconductor structure and the second semiconductor structure; and A power line is formed on a side away from the bonding structure, wherein the power line supplies power to the second semiconductor structure, and the second semiconductor structure after power supply controls the storage array.

2. The method according to claim 1, It is characterized in that A power line is formed on a side away from the bonding structure, comprising: The power line is formed on a side of the first semiconductor structure away from the bonding structure.

3. The method according to claim 1, It is characterized in that A power line is formed on a side away from the bonding structure, comprising: The power line is formed on a side of the second semiconductor structure away from the bonding structure.

4. The method according to claim 2, It is characterized in that Forming the power line on a side of the first semiconductor structure away from the bonding structure includes: forming a conductive plug extending along a first direction in the first semiconductor structure, wherein the first direction is perpendicular to an extending direction of the bonding structure, and the conductive plug is connected to the second semiconductor structure; and The power line extending along a second direction and connected to the conductive plug is formed on a side of the first semiconductor structure away from the bonding structure, wherein the second direction is perpendicular to the first direction.

5. The method according to claim 4, It is characterized in that Forming a conductive plug extending along a first direction in the first semiconductor structure, comprising: A plurality of interconnection contacts extending along the first direction and connected to the memory array and the conductive plug extending along the first direction are formed in the first semiconductor structure.

6. The method according to claim 5, It is characterized in that The conductive plug includes a first conductive plug and a second conductive plug, the second conductive plug is close to the interconnection contact, and forms a power line extending along a second direction and connected to the conductive plug, including: forming an interconnection layer on the interconnection contacts and the conductive plugs, wherein the interconnection layer comprises a first interconnection layer and a second interconnection layer, the first interconnection layer extends along the second direction and is connected to the plurality of interconnection contacts and the second conductive plugs, and the second interconnection layer is connected to the first conductive plugs; forming a first conductive contact on the second interconnect layer; and A power line extending along the second direction is formed on the first conductive contact, wherein the power line is connected to the second semiconductor structure via the first conductive contact, the second interconnect layer and the first conductive plug.

7. The method according to claim 6, It is characterized in that The conductive plug further includes a third conductive plug, and the interconnect layer further includes a third interconnect layer connected to the third conductive plug, wherein the method further includes: forming a second conductive contact on the third interconnect layer; forming a conductive line on the second conductive contact; and A pad lead-out structure is formed on the conductive line, wherein the pad lead-out structure is connected to the second semiconductor structure via the conductive line, the second conductive contact, the third interconnect layer and the third conductive plug.

8. The method according to claim 5, It is characterized in that The method comprises: forming the first semiconductor structure, comprising: forming the memory array on a first substrate, wherein the memory array comprises transistors and capacitors connected to first ends of the transistors away from the first substrate; forming a second substrate on a side of the storage array away from the first substrate; removing the first substrate, and forming a bit line extending along the second direction at a second end of the transistor opposite to the first end; and The second substrate is removed to form the first semiconductor structure, wherein the interconnection contact is connected to the capacitor.

9. The method according to claim 8, It is characterized in that The transistor includes a semiconductor pillar and a gate structure in contact with the semiconductor pillar, and the method includes: A contact structure connected to the gate structure is formed, wherein the contact structure is connected to the second semiconductor structure through the bonding structure.

10. The method according to any one of claims 1 to 9, It is characterized in that The method comprises: After bonding the first semiconductor structure and the second semiconductor structure, the power line is formed.

11. A semiconductor structure, It is characterized in that include: a first semiconductor structure and a second semiconductor structure bonded together, wherein the first semiconductor structure comprises a memory array; a bonding structure located between the first semiconductor structure and the second semiconductor structure; as well as A power line is located at a side away from the bonding structure, wherein the power line supplies power to the second semiconductor structure, and the second semiconductor structure after power supply controls the storage array.

12. The semiconductor structure according to claim 11, It is characterized in that The power line is located at a side of the first semiconductor structure away from the bonding structure.

13. The semiconductor structure according to claim 11, It is characterized in that The power line is located at a side of the second semiconductor structure away from the bonding structure.

14. The semiconductor structure according to claim 12, It is characterized in that The power line extends along a second direction, and the semiconductor structure further includes: A first conductive plug connected to the power line is located in the first semiconductor structure and extends along a first direction, wherein the first direction is perpendicular to the second direction, and the power line supplies power to the second semiconductor structure via the first conductive plug.

15. The semiconductor structure according to claim 14, It is characterized in that The first semiconductor structure comprises: a transistor having a first end away from the bonding structure and a second end opposite to the first end along the first direction; a capacitor comprising a first electrode, a second electrode, and a dielectric layer between the first electrode and the second electrode, wherein the first electrode is connected to the first terminal of the transistor; The bit line is connected to the second end and extends along the second direction.

16. The semiconductor structure according to claim 15, It is characterized in that The transistor includes a semiconductor column and a gate structure contacting the semiconductor column, and the first semiconductor structure includes: A contact structure is connected to the gate structure and is connected to the second semiconductor structure through the bonding structure.

17. The semiconductor structure according to claim 15, It is characterized in that The semiconductor structure comprises: a plurality of interconnection contacts extending along the first direction and connected to the second electrode; a second conductive plug, adjacent to the first conductive plug and close to the interconnection contact, passing through the first semiconductor structure along the first direction and connected to the second semiconductor structure through the bonding structure; The first interconnection layer extends along the second direction and is connected to the plurality of interconnection contacts and the second conductive plugs, wherein the second electrode is connected to the second semiconductor structure via the interconnection contacts, the first interconnection layer and the second conductive plugs.

18. The semiconductor structure according to claim 14, It is characterized in that The semiconductor structure comprises: a second interconnect layer connected to the first conductive plug; A first conductive contact is connected to the second interconnect layer, wherein the power line is located on the first conductive contact and is connected to the second semiconductor structure via the first conductive contact, the second interconnect layer and the first conductive plug.

19. The semiconductor structure according to claim 17, It is characterized in that The semiconductor structure comprises: a third conductive plug, adjacent to the first conductive plug, passing through the first semiconductor structure along the first direction and connected to the second semiconductor structure through the bonding structure; a third interconnection layer, located on the third conductive plug and connected to the third conductive plug; a second conductive contact, located on the third interconnect layer and connected to the third interconnect layer; a conductive line, located on the second conductive contact and connected to the second conductive contact; and A pad lead-out structure is located on the conductive line and connected to the conductive line, wherein the pad lead-out structure is connected to the second semiconductor structure via the conductive line, the second conductive contact, the third interconnect layer and the third conductive plug.

20. A storage system, It is characterized in that include: At least one three-dimensional memory, each of the three-dimensional memory comprising a semiconductor structure as claimed in any one of claims 11 to 19; as well as The controller is coupled to the semiconductor structure and is used for controlling the three-dimensional memory to store data.

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