Storage device and working method thereof

Abstract

A novel storage device is provided. A first cell array having a plurality of memory cells and a second cell array having a plurality of memory cells are disposed to overlap each other. Two bit lines included in the first bit line pair are electrically connected to a portion of the memory cells included in the first cell array and a portion of the memory cells included in the second cell array, respectively. Two bit lines included in the second bit line pair are electrically connected to a portion of the memory cells included in the first cell array and a portion of the memory cells included in the second cell array, respectively. In the first cell array, one of the two bit lines included in the second bit line pair has a region overlapping a portion of the first bit line pair, and in the second cell array, the other of the two bit lines included in the second bit line pair has a region overlapping a portion of the first bit line pair.

Claims

1. A storage device, include: a first sense amplifier; a second sense amplifier, adjacent to the first sense amplifier; a first cell array including a plurality of first memory cells, the first cell array being disposed above the first sense amplifier and the second sense amplifier; a second cell array including a plurality of second storage cells, the second cell array being disposed above the first cell array; a first bit line and a second bit line, each electrically connected to the first sense amplifier; as well as a third bit line and a fourth bit line, each electrically connected to the second sense amplifier, The area of ​​the first unit array overlaps with the area of ​​the second unit array. The region of the first cell array includes: The first group; a second group, adjacent to the first group; The third group is adjacent to the second group; a fourth group, adjacent to the second group and the third group; a fifth group, adjacent to the fourth group; and The sixth group, adjacent to the fifth group, The first group to the sixth group each include one or more first memory cells, and the region of the second cell array includes: Group 7; An eighth group, adjacent to the seventh group; A ninth group, adjacent to the eighth group; a tenth group, adjacent to the eighth group and the ninth group; an eleventh group, adjacent to the tenth group; and The twelfth group, adjacent to the eleventh group, The seventh to twelfth groups each include one or more second memory cells, the first bit line includes a first portion electrically connected to the first group, a second portion electrically connected to the third group, and a third portion electrically connected to the ninth group, The second bit line includes a first portion electrically connected to the second group, a second portion electrically connected to the seventh group, and a third portion electrically connected to the eighth group. The third bit line includes a first portion electrically connected to the fourth group, a second portion electrically connected to the sixth group, and a third portion electrically connected to the twelfth group. The fourth bit line includes a first portion electrically connected to the fifth group, a second portion electrically connected to the tenth group, and a third portion electrically connected to the eleventh group. Furthermore, the first portion of the third bit line is adjacent to the second portion of the first bit line and the first portion of the second bit line.

2. A storage device, include: a first sense amplifier; a second sense amplifier, adjacent to the first sense amplifier; a first cell array including a plurality of first memory cells, the first cell array being disposed above the first sense amplifier and the second sense amplifier; a second cell array including a plurality of second storage cells, the second cell array being disposed above the first cell array; a first bit line and a second bit line, each electrically connected to the first sense amplifier; as well as a third bit line and a fourth bit line, each electrically connected to the second sense amplifier, The area of ​​the first unit array overlaps with the area of ​​the second unit array. The region of the first cell array includes: The first group; a second group, adjacent to the first group; The third group is adjacent to the second group; a fourth group, adjacent to the third group; a fifth group, adjacent to the fourth group; and The sixth group, adjacent to the fifth group, The first group to the sixth group each include one or more first memory cells, and the region of the second cell array includes: Group 7; An eighth group, adjacent to the seventh group; A ninth group, adjacent to the eighth group; The tenth group is adjacent to the ninth group; an eleventh group, adjacent to the tenth group; and The twelfth group is adjacent to the eleventh group. The seventh group to the twelfth group each include one or more second memory cells, the first bit line is electrically connected to the first group, the third group, and the ninth group, the second bit line is electrically connected to the second group, the seventh group, and the eighth group, and the third bit line is electrically connected to the fourth group, the sixth group, and the twelfth group. The fourth bit line is electrically connected to the fifth group, the tenth group, and the eleventh group, The first part of the fourth group is adjacent to the second group, The second part of the fourth group is adjacent to the third group, The first part of the tenth group is adjacent to the eighth group, Furthermore, the second portion of the tenth group is adjacent to the ninth group.

3. The storage device according to claim 1 or 2, wherein the fourth group includes two or more first storage units, And the tenth group includes two or more second storage units.

4. The storage device according to claim 1 or 2, The first memory cells each have a first transistor and a first capacitor element, And each of the second memory cells has a second transistor and a second capacitor.

5. The storage device according to claim 4, The first transistor and the second transistor each include an oxide semiconductor in a semiconductor layer.

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