A semiconductor structure, a semiconductor memory and a method for manufacturing a semiconductor structure

Abstract

The application relates to the technical field of semiconductors, in particular to a semiconductor structure, a semiconductor memory and a preparation method of the semiconductor structure. The semiconductor structure comprises, from bottom to top, a substrate, an insulating layer and a control gate layer; the control gate layer comprises a floating gate area and an erase gate area which are arranged at intervals along a first direction, and a tunnel oxide layer is filled between the floating gate area and the erase gate area; the first direction is a direction perpendicular to the thickness direction of the substrate; the floating gate area comprises a floating gate and a control gate which are arranged from bottom to top; the thickness of the tunnel oxide layer between the floating gate and the erase gate area is greater than the thickness of the corresponding floating gate area of the insulating layer, so that the electrons during the erase operation and the write operation are realized through different oxide layer channels, the erase voltage is small, and the reliability of the semiconductor structure can be improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure, a semiconductor memory, and a method for fabricating the semiconductor structure. Background Technology

[0002] Memory is a container capable of holding certain data. It is typically used as a memory device in a computer system to store programs and data. Classified by storage medium, memory includes semiconductor memory, magnetic memory, and laser memory. Among these, semiconductor memory has become a research hotspot in related fields due to its advantages such as high integration, large capacity, small size, and fast access speed.

[0003] Please see Figure 1 The diagram illustrates the structure of a conventional semiconductor memory. The semiconductor memory includes, from bottom to top, a substrate, a gate oxide layer, a floating gate, a dielectric layer, and a control gate. During a write operation, a voltage is applied to the control gate, causing electrons to pass through the gate oxide layer and enter the floating gate. During an erase operation, a voltage is applied to the substrate, causing electrons to pass through the gate oxide layer and be drawn out of the floating gate. However, since electrons pass through this planar gate oxide layer during both write and erase operations in the aforementioned conventional memory device, repeated electron penetration can easily damage the gate oxide layer, leading to reduced reliability. Summary of the Invention

[0004] To address the aforementioned technical problems, this application discloses a semiconductor structure comprising a substrate, an insulating layer, and a control gate layer stacked sequentially from bottom to top.

[0005] The control gate layer includes a floating gate region and an erase gate region spaced apart along a first direction, with a tunneling oxide layer filling the space between the floating gate region and the erase gate region; the first direction is perpendicular to the thickness direction of the substrate.

[0006] The floating gate area includes floating gates and control gates arranged from bottom to top;

[0007] The thickness of the tunneling oxide layer between the floating gate and the erase gate region is greater than the thickness of the corresponding floating gate region of the insulating layer.

[0008] Furthermore, the floating grid includes opposing first and second sides; the first and second sides are arranged along a first direction; the second side is close to the erasure grid area;

[0009] The distance between the second side and the side of the control gate closest to the second side is greater than the distance between the first side and the side of the control gate closest to the first side;

[0010] Furthermore, the floating gate includes a first floating gate region, a second floating gate region, and a third floating gate region that are sequentially arranged and connected along a first direction;

[0011] The second floating gate area corresponds to the position of the control gate;

[0012] The width of the first floating gate region is greater than the width of the third floating gate region, or the width of the first floating gate region is less than the width of the third floating gate region.

[0013] Furthermore, the top of the second floating gate region is at a preset distance from the top of the first floating gate region and the top of the third floating gate region, respectively.

[0014] Furthermore, it includes two floating gate areas;

[0015] The erase grid area is located between two floating grid areas.

[0016] Furthermore, the erasure gate area includes a first structure, a second structure, and a third structure arranged and connected sequentially from bottom to top;

[0017] The width of the first structure is smaller than the width of the third structure;

[0018] The width of the second structure gradually increases along the direction of arrangement;

[0019] An interlayer dielectric layer is provided between the floating gate and the control gate; the interlayer dielectric layer and the second structure are located in the same plane.

[0020] Furthermore, the pierced oxide layer includes a connected first oxide structure and a second oxide structure;

[0021] The first oxide structure is located between the floating gate and the erasure gate;

[0022] The second oxide structure is located between the control gate and the erase gate, and the second oxide structure is a composite structure.

[0023] Furthermore, the thickness of the first oxide structure is greater than the thickness of the first region of the insulating layer; the first region is the region corresponding to the projection of the floating gate onto the insulating layer.

[0024] Furthermore, the control gate layer also includes word lines that are arranged along the first direction and have a preset interval from the floating gate area;

[0025] A gap oxide layer is filled between the floating gate area and the word line; the thickness of the gap oxide layer is greater than the thickness of the first oxide structure.

[0026] The first side is close to the letter line.

[0027] On the other hand, a method for fabricating a semiconductor structure is also disclosed, which includes the following steps:

[0028] An initial semiconductor structure is provided; the initial semiconductor structure includes a substrate, an insulating layer and an initial control gate layer stacked sequentially from bottom to top; the initial control gate layer includes a floating gate material layer and a control gate located on the floating gate material layer; sidewalls are respectively provided on opposite sides of the control gate;

[0029] The initial semiconductor structure is patterned to remove the preset area of ​​the floating gate material layer, and a floating gate is formed on the insulating layer to obtain the intermediate semiconductor structure; the control gate is located on the floating gate.

[0030] A first oxide layer and an erase gate region are sequentially formed on the surface of the intermediate semiconductor structure to obtain the target semiconductor structure; the erase gate region and the floating gate are spaced apart along a first direction; the first direction is a direction perpendicular to the thickness direction of the substrate; a tunneling oxide layer is filled between the floating gate region and the erase gate region; the thickness of the tunneling oxide layer between the floating gate and the erase gate region is greater than the thickness of the corresponding floating gate region of the insulating layer.

[0031] Furthermore, a second oxide layer is provided on the surface of the initial control gate layer; the initial control gate layer includes two control gates spaced apart along a first direction; the initial semiconductor structure is patterned to remove a predetermined area of ​​the floating gate material layer, and a floating gate is formed on the insulating layer to obtain an intermediate semiconductor structure, including:

[0032] The initial semiconductor structure is patterned to remove the second oxide layer in the first preset region on the initial control gate layer; the first preset region is located on the side of the control gate away from the erase gate blanking area; the erase gate blanking area is the area between the two control gates;

[0033] Remove the floating gate material layer in the first preset region and the floating gate material layer in the erased gate blank region to form a floating gate on the insulating layer, thereby obtaining an intermediate semiconductor structure.

[0034] Furthermore, a first oxide layer and an erase gate region are formed on the surface of the intermediate semiconductor structure to obtain the target semiconductor structure, including:

[0035] A first oxide layer is formed on the surface of the intermediate semiconductor structure;

[0036] Conductive material is deposited in a first predetermined region to form word lines on an insulating layer; simultaneously, conductive material is deposited in an erase gate blank area to form an erase gate region on an insulating layer, thereby obtaining the target semiconductor structure.

[0037] On the other hand, a semiconductor memory is also disclosed, the memory device including the semiconductor structure described above.

[0038] On the other hand, an electronic device is also disclosed, which includes the aforementioned semiconductor memory.

[0039] By adopting the above technical solution, the semiconductor structure provided in this application has the following beneficial effects:

[0040] The semiconductor structure includes a substrate, an insulating layer, and a control gate layer stacked sequentially from bottom to top. The control gate layer includes a floating gate region and an erase gate region spaced apart along a first direction, with a tunneling oxide layer filling the space between the floating gate region and the erase gate region. The first direction is perpendicular to the thickness direction of the substrate. The floating gate region includes a floating gate and a control gate arranged from bottom to top. During subsequent write operations, electrons enter the floating gate through the insulating layer below the floating gate. During erase operations, electrons are drawn out of the floating gate through the tunneling oxide layer. Write and erase operations are achieved through different oxide layer channels, thereby reducing the number of electron penetrations through the insulating layer and effectively improving the lifetime of the semiconductor structure.

[0041] Furthermore, the thickness of the tunneling oxide layer between the floating gate and the erase gate region is greater than the thickness of the corresponding floating gate region of the insulating layer. This allows the tunneling oxide layer between the floating gate and the erase gate to be thicker than the insulating layer. This structure allows for the use of a smaller voltage during the erase operation and also improves the reliability of the electron penetration channel. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 This is a schematic diagram of the structure of a semiconductor memory in the prior art;

[0044] Figure 2 This is a schematic diagram of the first semiconductor structure provided in the embodiments of this application;

[0045] Figure 3 This is a schematic diagram of the second semiconductor structure provided in the embodiments of this application;

[0046] Figure 4 This is a schematic diagram of the third semiconductor structure provided in the embodiments of this application;

[0047] Figure 5 This is a schematic diagram of the fabrication process of a semiconductor structure provided in an embodiment of this application;

[0048] Figure 6 This is a schematic diagram of an initial semiconductor structure provided in an embodiment of this application;

[0049] Figure 7This is a schematic diagram of the initial semiconductor structure after the second oxide layer of the first preset region has been removed, according to an embodiment of this application.

[0050] Figure 8 This is a schematic diagram of an intermediate semiconductor structure provided in an embodiment of this application;

[0051] Figure 9 This is a schematic diagram of the initial semiconductor structure after ion implantation into a preset region, provided in an embodiment of this application.

[0052] Figure 10 This is a schematic diagram of another intermediate semiconductor structure provided in an embodiment of this application.

[0053] The following is supplementary explanation of the attached figures:

[0054] 1-Substrate; 2-Insulating layer; 3-Control gate layer; 4-Floating gate region; 401-Floating gate; 4011-First floating gate region; 4012-Second floating gate region; 4013-Third floating gate region; 402-Control gate; 5-Erase gate region; 501-First structure; 502-Second structure; 503-Third structure; 6-Tunnel oxide layer; 601-First oxide structure; 602-Second oxide structure; 7-Interlayer dielectric layer; 8-Word line; 9-Interval oxide layer; 10-Floating gate material layer; 11-Second oxide layer; 12-First preset region; 13-Erase gate blank area; 14-Word line low-resistance region; 15-Source line low-resistance region. Detailed Implementation

[0055] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0056] The term "an embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of this application. In the description of this application, it should be understood that the terms "upper," "lower," "top," "bottom," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. Moreover, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein.

[0057] For the purposes of the detailed description below, it should be understood that the invention may take various alternative variations and sequences of steps unless expressly stated otherwise. Furthermore, except in any operational instance, or otherwise indicated, all figures representing the amounts of ingredients used, for example, in the specification and claims, should be understood to be modified in all cases by the term “about.” Therefore, unless indicated to the contrary, the numerical parameters set forth in the following specification and appended claims are approximations varying with the desired performance to be obtained according to the invention. It is not at all an attempt to limit the application of the doctrine of equivalents to the scope of the claims; each numerical parameter should be interpreted at least according to the number of significant figures reported and by applying ordinary rounding techniques.

[0058] Although the numerical ranges and parameters illustrating the broad scope of the invention are approximate, the values ​​listed in the specific examples are reported as precisely as possible. However, any numerical value inherently contains some error that is necessarily caused by the standard deviation found in their respective test measurements.

[0059] When a numerical range is disclosed herein, the range is considered continuous and includes the minimum and maximum values ​​of the range, as well as every value between the minimum and maximum values. Furthermore, when the range refers to an integer, it includes every integer between the minimum and maximum values ​​of the range. Additionally, when multiple ranges are provided to describe a feature or characteristic, the ranges may be combined. In other words, unless otherwise specified, all ranges disclosed herein should be understood to include any and all subranges to which they are included. For example, a specified range from “1 to 10” should be considered to include any and all subranges between the minimum value 1 and the maximum value 10. Exemplary subranges of the range 1 to 10 include, but are not limited to, 1 to 6.1, 3.5 to 7.8, 5.5 to 10, etc.

[0060] pass Figure 1 As can be seen from the prior art semiconductor memory shown, the semiconductor memory includes at least a substrate, a gate oxide layer, a floating gate, a dielectric layer, and a control gate arranged sequentially from bottom to top. By applying a voltage to the control gate, electrons are allowed to pass through the gate oxide layer and enter the floating gate, realizing the write operation; by applying a voltage to the substrate, electrons are drawn out of the floating gate through the gate oxide layer, realizing the erase operation. Specifically, during the erase operation, when a voltage of 10.5V is applied to the substrate and a voltage of -8.8V is applied to the control gate, the current on the gate oxide layer corresponding to the offset voltage (i.e., the erase voltage) of 19.3V is approximately 90A. Obviously, applying a large erase voltage can easily cause side breakdown problems. However, if the erase voltage is reduced, it may result in incomplete erasure of the device, leading to read failure. Therefore, designing a semiconductor memory that can reduce the erase voltage while ensuring clean erasure has become one of the urgent problems to be solved. Furthermore, since electrons in the existing memory devices are transmitted through the planar gate oxide layer for both write and erase operations, repeated electron penetration can easily damage the gate oxide layer, thereby reducing its reliability.

[0061] For this purpose, please refer to Figure 2 The diagram shows a schematic of a semiconductor structure provided in an embodiment of this application. The semiconductor structure includes a substrate 1, an insulating layer 2, and a control gate layer 3 stacked sequentially from bottom to top. The control gate layer 3 includes a floating gate region 4 and an erase gate region 5 spaced apart along a first direction, with a tunneling oxide layer 6 filling the space between the floating gate region 4 and the erase gate region 5. The first direction is perpendicular to the thickness direction of the substrate 1. The floating gate region 4 includes a floating gate 401 and a control gate 402 arranged from bottom to top. The thickness of the tunneling oxide layer 6 between the floating gate 401 and the erase gate region 5 is greater than the thickness of the corresponding floating gate 401 region of the insulating layer 2. This allows electrons to be drawn out of the floating gate 401 through the tunneling oxide layer 6, rather than the insulating layer 2, during erase / write operations. This dual-channel structure improves the reliability of the device. Optionally, the first direction may refer to... Figure 2 In the x-direction, the thickness direction of substrate 1 can refer to... Figure 2 In the y-direction; in this embodiment, the first direction can specifically refer to the positive x-axis direction, and the thickness direction of the substrate 1 can specifically refer to the positive y-axis direction.

[0062] In one specific embodiment, the floating gate 401 includes a first side and a second side opposite to each other; the first side and the second side are arranged along a first direction; the second side is close to the erase gate region 5; the distance between the second side and the side of the control gate 402 closest to the second side is greater than the distance between the first side and the side of the control gate 402 closest to the first side; that is, by designing the floating gate 401 as an asymmetrical structure, i.e., the area close to the erase gate region 5 is wider, the tunneling oxide layer 6 between the floating gate 401 and the erase gate can be designed to be thicker than the insulating layer 2. Since the tunneling oxide layer 6 is a two-dimensional structure distributed along the y-direction, it will have electric field strength in two directions. Under the same applied voltage, the electric field strength can be stronger. Therefore, even if the tunneling oxide layer 6 is designed to be thicker, the erasure effect under a lower erase voltage can be achieved. Moreover, a thicker tunneling oxide layer 6 can also improve the reliability of the structure and reduce channel damage.

[0063] In one specific embodiment, when given Figure 2 The semiconductor structure shown can be erased by applying an erase voltage of 12V. At this time, the tunneling oxide layer 6 between the floating gate 401 and the erase gate region 5 experiences a current of approximately 130A. This current is transmitted through the aforementioned... Figure 1 Based on the erase test results of the existing semiconductor memory shown (erase voltage of 19.3V), the semiconductor structure provided in this application can achieve erasure at a lower erase voltage.

[0064] In some feasible embodiments, please refer to Figure 3 The floating gate 401 includes a first floating gate region 4011, a second floating gate region 4012, and a third floating gate region 4013 arranged and connected sequentially along a first direction. The second floating gate region 4012 corresponds to the position of the control gate 402. The first floating gate region 4011 is close to the erase gate region 5, and the width of the first floating gate region 4011 is greater than the width of the third floating gate region 4013. Optionally, the width of the second floating gate region 4012 is equal to the width of the control gate 402. Since the widths of the regions on both sides of the second floating gate region 4012 of the floating gate 401 are unequal, an asymmetrical structure is formed, thereby forming an oxide layer with a bent structure between the erase gate region 5 and the floating gate 401, which can improve the reliability of the structure while reducing the erase voltage. In some other feasible embodiments, when the region close to the erase gate region 5 is defined as the third floating gate region 4013, the width of the first floating gate region 4011 is smaller than the width of the third floating gate region 4013.

[0065] In some feasible embodiments, the top of the second floating gate region 4012 is at a predetermined distance from the top of the first floating gate region 4011 and the top of the third floating gate region 4013, respectively. This results in the second floating gate region 4012 being higher than the first floating gate region 4011 and the second floating gate region 4012 by a certain height, specifically formed during the fabrication of the sidewalls on both sides of the control gate 402. For example... Figure 3 As shown, the sidewall can be an ON structure, i.e., silicon oxide layer / silicon nitride layer, with an oxide layer disposed near the control gate 402, or an ONO structure, i.e., silicon oxide layer / silicon nitride layer / silicon oxide layer.

[0066] In this embodiment, an isolation protective layer is further provided on the control gate 402. The material of this isolation protective layer can be one or a composite structure of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbon oxide, and its thickness can range from 800 to 900 angstroms. Specifically, the thickness of this isolation protective layer can be 800 angstroms, 810 angstroms, 820 angstroms, 830 angstroms, 840 angstroms, 850 angstroms, 860 angstroms, 870 angstroms, 880 angstroms, 890 angstroms, and 900 angstroms. Optionally, such as... Figure 2 As shown, the isolation and protective layer can be a composite structure of silicon oxide layer / silicon nitride layer / silicon oxide layer.

[0067] In some feasible embodiments, please refer to Figure 2 The semiconductor structure includes two floating gate regions 4; an erase gate region 5 is located between the two floating gate regions 4. Optionally, the two floating gate regions 4 may be, but are not limited to, mirror images of each other along the central axis of the erase gate region 5.

[0068] In some feasible embodiments, please refer to Figure 3 The erase gate region 5 includes a first structure 501, a second structure 502, and a third structure 503 arranged sequentially from bottom to top. The width of the first structure 501 is smaller than the width of the third structure 503; the width of the second structure 502 gradually increases along the arrangement direction. Specifically, the cross-section of the second structure 502 can be an inverted trapezoid, and the first structure 501 and the third structure 503 can be rectangular, such as a rectangle or a square, depending on the actual device performance and size requirements. Optionally, an interlayer dielectric layer 7 is provided between the floating gate 401 and the control gate 402. The material of the interlayer dielectric layer 7 can be one or any composite structure of silicon oxide, silicon nitride, silicon oxynitride, and silicon oxide containing carbon, and its thickness can range from 130 to 180 angstroms. The specific thickness of the interlayer dielectric layer 7 can be 130 angstroms, 140 angstroms, 150 angstroms, 160 angstroms, 170 angstroms, and 180 angstroms. Optionally, such as... Figure 3 As shown, the interlayer dielectric layer 7 can be a composite structure of silicon oxide layer / silicon nitride layer / silicon oxide layer. Optionally, the interlayer dielectric layer 7 and the second structure 502 are located in the same plane.

[0069] In some feasible embodiments, the tunnel oxide layer 6 includes a connected first oxide structure 601 and a second oxide structure 602; the first oxide structure 601 is located between the floating gate 401 and the erase gate; the second oxide structure 602 is located between the control gate 402 and the erase gate, and the second oxide structure 602 is a composite structure. Optionally, the first oxide structure 601 can be a single-layer structure of a material, such as silicon oxide, and its thickness can range from 110 to 150 angstroms. Specific implementations of the first oxide structure 601 can have thicknesses of 110 angstroms, 120 angstroms, 130 angstroms, 140 angstroms, and 150 angstroms. Optionally, the second oxide structure 602 can be a composite structure of any of the following: silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide oxides.

[0070] In some feasible embodiments, the thickness of the first oxide structure 601 is greater than the thickness of the first region of the insulating layer 2; the first region is the area corresponding to the projection of the floating gate 401 onto the insulating layer 2. During a write operation, electrons enter the floating gate 401 through the first region, while during an erase operation, electrons are drawn out of the floating gate 401 by the first oxide structure 601. Therefore, the above-mentioned thickness setting method in this embodiment can effectively improve the reliability of the structure. Optionally, the insulating layer 2 can specifically be a silicon oxide material, and the thickness range of the first region can be 80-100 angstroms. The specific implementation thickness of the first region can be 80 angstroms, 850 angstroms, 900 angstroms, 950 angstroms, and 100 angstroms.

[0071] In some feasible embodiments, please continue to refer to Figure 3 The control gate layer 3 further includes word lines 8 arranged along a first direction and spaced at a predetermined interval from the floating gate region 4; an interstitial oxide layer 9 is filled between the floating gate region 4 and the word lines 8; the thickness of the interstitial oxide layer 9 is greater than the thickness of the first oxide structure 601; the first side is close to the word lines 8. Optionally, the interstitial oxide layer 9 can be a silicon oxide layer or a silicon nitride layer. Optionally, the thickness of the interstitial oxide layer 9 can be in the range of 200–260 angstroms, and the specific thickness of the interstitial oxide layer 9 can be 200 angstroms, 210 angstroms, 220 angstroms, 230 angstroms, 240 angstroms, and 260 angstroms. The thickness of the interstitial oxide layer 9 is greater than the thickness of the first oxide structure 601. Optionally, if the control gate layer 3 includes two floating gate areas 4, it also includes two corresponding word lines 8. The arrangement of the two word lines 8, the two floating gate areas 4 and the erase gate area 5 along the first direction is one word line 8, one floating gate area 4, one erase gate area 5, another floating gate area 4 and another word line 8. The overall structure can be a mirror structure of the central axis of the erase gate area 5.

[0072] In this embodiment, the first oxide structure 601 is a silicon oxide layer with a thickness of 130 angstroms, and the second oxide structure 602 is a composite structure of silicon oxide / silicon nitride / silicon oxide. The interlayer dielectric layer 7 between the floating gate 401 and the control gate 402 is a composite structure of silicon oxide / silicon nitride / silicon oxide. The sidewalls on both sides of the control gate 402 can be composite structures of silicon oxide / silicon nitride / silicon oxide, wherein the sidewall of the control gate 402 near the erase gate is the upper second oxide structure 602; the outer silicon oxide layer in the sidewall of the control gate 402 near the word line 8 belongs to the aforementioned interstitial oxide layer 9. An isolation protective layer is also provided on the control gate 402, which is a composite structure of silicon oxide / silicon nitride / silicon oxide. The first region of insulating layer 2 has a thickness of 90 angstroms. Insulating layer 2 also includes a second region and a third region. The second region refers to the area where the erase gate is projected onto insulating layer 2. The thickness of the second region can range from 280 to 350 angstroms, and the specific implementation thickness of the second region can be 280 angstroms, 290 angstroms, 300 angstroms, 310 angstroms, 320 angstroms, 330 angstroms, and 350 angstroms. The thickness of the second region is greater than that of the first region. Designing the second region to be thicker can prevent the erase voltage from affecting the low-resistance region 15 of the source line during the erase operation, so that the erase voltage applied to the erase gate region 5 can only be applied to the floating gate 401. The third region refers to the area where the word line 8 is projected onto insulating layer 2. The thickness of the third region can range from 10 to 30 angstroms, and the specific implementation thickness of the third region can be 10 angstroms, 15 angstroms, 20 angstroms, 25 angstroms, and 30 angstroms. The thickness of the third region is determined based on the type of device to be fabricated. For example, if a 1.5V semiconductor memory device is being fabricated, the third region will be thinner. It can also be for 3.3V, 5V, and 12V device types. In fact, the semiconductor structure provided in this application also includes peripheral structures, namely logic regions. The semiconductor structure described above is mainly the control region. In actual fabrication, certain structures of the control region and logic region are fabricated integrally, such as the third region of the insulating layer 2. The thickness of the oxide layer required for the device corresponding to the third region and the logic region is consistent.

[0073] It is understandable that the sidewalls on both sides of the control gate 402 are composite structures of silicon oxide / silicon nitride / silicon oxide layers. Because silicon nitride layers have better chemical stability and a higher K value, this type of sidewall structure can have a large capacitance even when fabricated thinly, making it less prone to breakdown. This is beneficial for reducing the size of the structure and its application in highly integrated devices. To further ensure the above effects, the bottom of the silicon nitride layer can be designed to be lower than the bottom of the control layer. Specifically, when the interlayer dielectric layer 7 is a composite structure of silicon oxide / silicon nitride / silicon oxide layers, the bottom of the silicon nitride layer on the sidewall is lower than the bottom of the silicon nitride layer in the interlayer dielectric layer 7.

[0074] In the embodiments of this application, please refer to Figure 4 The semiconductor structure also includes a word line low-resistance region 14 and a source line low-resistance region 15. The source line low-resistance region 15 is located in the region near the top of the substrate 1 and corresponds to the erase gate region 5. It is used to connect to the source. When there are two word lines 8, there are also two word line low-resistance regions 14. Each word line 8 corresponds to a word line 8 low-resistance region below it. The word line low-resistance region 14 is located in the region near the top of the substrate 1. Both the word line low-resistance region 14 and the source line low-resistance region 15 can be obtained by ion doping a predetermined region.

[0075] In this embodiment, the control gate layer 3 further includes bit lines, which are located on the side of the word line 8 and are filled with an oxide layer between them.

[0076] The semiconductor structure described above includes a laterally spaced floating gate region 4 and an erase gate region 5, with a tunneling oxide layer 6 filling the space between the floating gate region 4 and the erase gate region 5. The floating gate region 4 includes a floating gate 401 and a control gate 402 arranged from bottom to top. This allows electrons to penetrate different channels during subsequent erase and write operations, reducing the number of electron penetrations through the insulating layer 2 and effectively improving the lifetime of the semiconductor structure. Furthermore, by designing the tunneling oxide layer 6 between the floating gate 401 and the erase gate to be thicker than the insulating layer 2, a smaller voltage can be used during the erase operation, while also improving the reliability of the electron penetration channel.

[0077] Please see Figure 5 This application discloses a method for fabricating a semiconductor structure, which includes the following steps:

[0078] S501: Provide an initial semiconductor structure; the initial semiconductor structure includes a substrate 1, an insulating layer 2 and an initial control gate layer 3 stacked sequentially from bottom to top; the initial control gate layer 3 includes a floating gate material layer 10 and a control gate 402 located on the floating gate material layer 10; sidewalls are respectively provided on opposite sides of the control gate 402.

[0079] In the embodiments of this application, please refer to Figure 3 The diagram illustrates a schematic of an initial semiconductor structure provided in an embodiment of this application. The initial semiconductor structure can refer to a structure for which partial fabrication has been completed, such as the control gate 402. The fabrication method involved in this application is primarily a large-plate forming process, i.e., a process of fabricating multiple devices of the same specifications on a whole wafer. The examples provided in this application... Figure 6This corresponds to the control region of a semiconductor memory. In reality, a semiconductor memory also includes a logic region. This application primarily focuses on the fabrication of the various layers of the control region; therefore, the fabrication of the logic region will not be described in detail here. During the large-plate forming process, the floating gate material layer 10 of the initial semiconductor structure will form multiple control structures with preset intervals, such as... Figure 6 As shown, each control structure includes a control gate 402 and oxide layers located below and above the control gate 402. The oxide layer below the control gate 402 can be called an interlayer dielectric layer 7, and the material of the interlayer dielectric layer 7 can be one or a composite structure of silicon oxide, silicon nitride, silicon oxynitride, and carbon-containing silicon oxide. The oxide layer above the control gate 402 can be called an isolation protective layer, and the material of the isolation protective layer can be one or a composite structure of silicon oxide, silicon nitride, silicon oxynitride, and carbon-containing silicon oxide.

[0080] In this embodiment, a second oxide layer 11 is provided on the surface of the initial control gate layer 3. The material of the second oxide layer 11 can be any one of silicon oxide, silicon nitride, silicon oxynitride, and carbon-containing silicon oxide. Optionally, the initial control gate layer 3 includes two control gates 402 spaced apart along a first direction. The first direction is a direction perpendicular to the thickness direction of the substrate, such as... Figure 6 As shown, the first direction can refer to the positive x-axis direction.

[0081] In this embodiment, the material of the floating gate material layer 10 may include polysilicon, silicon nitride, or a conductive nanocrystalline material. The material of the control gate layer 3 may include polysilicon, silicon nitride, or a conductive nanocrystalline material. The material of the word line 8 may include polysilicon.

[0082] In this embodiment, the sidewall can be an ON structure, i.e., a silicon oxide layer / silicon nitride layer, with an oxide layer disposed near the control gate 402, or an ONO structure, i.e., a silicon oxide layer / silicon nitride layer / silicon oxide layer.

[0083] S503: The initial semiconductor structure is patterned to remove the preset area of ​​the floating gate material layer 10, and a floating gate 401 is formed on the insulating layer 2 to obtain an intermediate semiconductor structure; the control gate 402 is located on the floating gate 401.

[0084] In this embodiment, the floating gate 401 includes a first side and a second side opposite to each other; the first side and the second side are arranged along a first direction; the second side is close to the erase gate region 5; the distance between the second side and the side of the control gate 402 closest to the second side is greater than the distance between the first side and the side of the control gate 402 closest to the first side; that is, by designing the floating gate 401 as an asymmetrical structure, i.e., the area close to the erase gate region 5 is wider, the tunneling oxide layer 6 between the floating gate 401 and the erase gate in the subsequent fabrication process can be designed to be thicker than the insulating layer 2, which allows a smaller voltage to be used when performing the erasure operation, and also improves the reliability of the electron penetration channel.

[0085] In some feasible embodiments, step S503, patterning the initial semiconductor structure to remove a preset area of ​​the floating gate material layer 10 and forming a floating gate 401 on the insulating layer 2 to obtain an intermediate semiconductor structure, may include: patterning the initial semiconductor structure to remove the second oxide layer 11 of the first preset area 12 on the initial control gate layer 3; the first preset area 12 is located on the side of the control gate 402 away from the erase gate blank area 13; the erase gate blank area 13 is the area between the two control gates 402; removing the floating gate material layer 10 of the first preset area 12 and the floating gate material layer 10 of the erase gate blank area 13 to form a floating gate 401 on the insulating layer 2 to obtain an intermediate semiconductor structure. Specifically, wet etching, dry etching, or a combination of both can be used to remove the second oxide layer 11 of the first preset area 12. The following describes the wet etching process for removing the second oxide layer 11 of the first preset region 12: First, a photoresist is formed on the surface of the initial semiconductor structure. Specifically, a spin-coating method can be used to form a uniformly thick photoresist on the surface of the initial semiconductor structure. A mask with a preset pattern is then placed above the initial semiconductor structure. Depending on the properties of the photoresist, a suitable mask needs to be selected. For example, positive photoresist can be removed by a developing solution after exposure, while negative photoresist is the opposite. This application example demonstrates the etching method for positive photoresist. As shown in Figure 7, the black area of ​​the mask represents the patterned area, through which light cannot pass. The white area represents the blank area, through which light can pass and react with the photoresist to solidify. After exposing the photoresist according to the preset exposure parameters, development and solution etching are performed sequentially to obtain the desired result. Figure 7 In the structure shown, the second oxide layer 11, from which the photoresist has been removed, can be removed by the corresponding etching solution. In fact, during the etching process, the solution also etches a portion of the silicon nitride layer near the first preset region 12, resulting in the width of the silicon nitride layer near the first preset region 12 being smaller than that of the silicon nitride layer on the other side of the control gate 402.

[0086] Further, the residual photoresist is removed. At this point, the first sidewall of the control gate 402 is a three-layer composite structure of silicon oxide / silicon nitride / silicon oxide. The first sidewall is close to the erased blank area, which is the area between the two control gates 402. The second sidewall of the control gate 402, opposite to the first sidewall, is a two-layer composite structure of silicon oxide / silicon nitride. After etching the floating gate material layer 10 in the erased blank area and the floating gate material layer 10 in the two first preset areas 12, an asymmetric floating gate 401 can be formed, resulting in an intermediate semiconductor structure (such as...). Figure 8 (The structure shown).

[0087] In some feasible embodiments, while etching the floating gate material layer 10 in the erased blank area, the second oxide layer 11 disposed on the floating gate material layer 10 is also removed. That is, the floating gate material layer 10 in the first preset area 12 and the erased blank area are etched simultaneously. In other feasible embodiments, the floating gate material layer 10 in the erased blank area can be etched first, and then the floating gate material layer 10 in the two first preset areas 12 can be etched. Alternatively, the floating gate material layer 10 in the two first preset areas 12 can be etched first, and then the floating gate material layer 10 in the erased blank area can be etched. While etching the floating gate material layer 10 in the erased blank area, the second oxide layer 11 disposed on the floating gate material layer 10 is also removed. The remaining second oxide layer 11 can be removed as needed later. Depending on the etching process, the etching of the aforementioned floating gate material layer 10 can specifically include the following embodiments. In some feasible embodiments, a masked dry etching process can be used to remove the floating gate material layer 10 in the erased blank area and the floating gate material layer 10 in the two first preset areas 12, which requires first forming a barrier layer on the surface of the intermediate semiconductor. In other feasible embodiments, a maskless dry etching process can be used to remove the floating gate material layer 10 in the erased blank area and the floating gate material layer 10 in the two first preset areas 12. The maskless dry etching process means that during etching, it is not necessary to form photoresist on the surface of the intermediate semiconductor, and therefore, exposure and development steps are not required, thus improving etching efficiency. In other feasible embodiments, a combination of dry etching and wet etching can be used to remove the floating gate material layer 10 in the erased blank area and the floating gate material layer 10 in the two first preset areas 12; for example, the second oxide layer 11 in the erased blank area can be removed first by dry etching, and then the floating gate material layer 10 in the erased blank area and the floating gate material layer 10 in the two first preset areas 12 can be removed by wet etching.

[0088] In this embodiment of the application, after step S501, the method further includes: performing a first ion implantation on a predetermined region facing the substrate 1 to form a word line low-resistivity region 14 in the substrate 1, thereby obtaining... Figure 9The structure shown. The first implantation surface can be the surface of the second oxide layer 11 in the second preset region, which is a groove region located away from the erased blank area. Optionally, the ion type for ion implantation can be P-type ions or N-type ions. N-type ions can be elements corresponding to Group V, such as phosphorus, arsenic, or antimony; P-type ions can include boron ions, boron-fluorine ions, or indium ions.

[0089] In this embodiment of the application, after step S503, the method further includes: performing a second ion implantation from a predetermined region facing the substrate 1 to form a low-resistivity source line region 15 in the substrate 1, resulting in... Figure 10 The structure shown. The second implantation surface can be the surface of the second oxide layer 11 in the erased blank area. Optionally, the ion type for ion implantation can be P-type ions or N-type ions. N-type ions can be elements corresponding to Group V, such as phosphorus, arsenic, or antimony; P-type ions can include boron ions, boron-fluorine ions, or indium ions. Optionally, the second ion implantation process can also be performed between steps S501 and S503, which can be performed before, after, or simultaneously with the first ion implantation.

[0090] S505: A first oxide layer and an erase gate region 5 are sequentially formed on the surface of the intermediate semiconductor structure to obtain the target semiconductor structure; the erase gate region 5 and the floating gate 401 are spaced apart along a first direction; the first direction is a direction perpendicular to the thickness direction of the substrate; a tunnel oxide layer 6 is filled between the floating gate region 4 and the erase gate region 5; the thickness of the tunnel oxide layer 6 between the floating gate 401 and the erase gate region 5 is greater than the thickness of the corresponding floating gate 401 region of the insulating layer 2.

[0091] In some feasible embodiments, the specific implementation of forming a first oxide layer and an erase gate region 5 on the surface of the intermediate semiconductor structure in step S505 to obtain the target semiconductor structure may include: forming a first oxide layer on the surface of the intermediate semiconductor structure; depositing conductive material in a first predetermined region 12 to form word lines 8 on the insulating layer 2; and simultaneously depositing conductive material in the erase gate blank region 13 to form an erase gate region 5 on the insulating layer 2, thereby obtaining the target semiconductor structure (e.g., ...). Figure 3 (Structure shown). Optionally, the conductive material can be the same material as the control gate layer 3, specifically including polycrystalline silicon, silicon nitride, or conductive nanocrystalline materials. Optionally, the deposition process can be molecular beam epitaxy or chemical vapor deposition, etc. Optionally, after the conductive material is deposited, the conductive material located on top of the entire intermediate semiconductor structure will be connected into a single sheet, so it is necessary to remove the excess conductive material by grinding, etching, or a combination of both, ultimately forming a structure like... Figure 3The target semiconductor structure shown, namely the conductive material of the first preset region 12 and the conductive material left after erasure, are independent structures.

[0092] It should be noted that the process of preparing the target semiconductor structure from the intermediate semiconductor structure also includes the preparation of the logic region, and, if necessary, the preparation of the bit lines, resulting in the following structure, which includes a substrate 1, an insulating layer 2, and a control gate layer 3 stacked sequentially from bottom to top; the control gate layer 3 includes two bit lines, two floating gate regions 4, two word lines 8, and an erase gate region 5 spaced apart along a first direction, with a tunneling oxide layer 6 filling the space between the floating gate regions 4 and the erase gate regions 5; the first direction is perpendicular to the thickness direction of the substrate 1; the floating gate regions 4 include a floating gate 401 and a control gate 402 arranged from bottom to top; the arrangement of the two bit lines, two word lines 8, two floating gate regions 4, and erase gate regions 5 along the first direction is one bit line, one word line 8, one floating gate region 4, one erase gate region 5, another floating gate region 4, another word line 8, and another bit line. The bit line and word line 8, word line 8 and floating gate area 4, and floating gate area 4 and erase gate area 5 are all filled with an oxide layer. The oxide layer can be one or a composite structure of silicon oxide, silicon nitride, silicon oxynitride and carbon-containing silicon oxide.

[0093] By performing the first and second ion implantations on substrate 1 as described above, a word line low-resistivity region 14 and a source line low-resistivity region 15 can be formed in substrate 1, thereby obtaining... Figure 4 The target semiconductor structure is shown. The source line low resistance region 15 is located in the region near the top of the substrate 1 and corresponds to the erase gate region 5. It is used to connect to the source. When there are two word lines 8, there are also two word line low resistance regions 14. Each word line 8 corresponds to a word line 8 low resistance region below it, and the word line low resistance region 14 is located in the region near the top of the substrate 1.

[0094] The thickness of the layers in a semiconductor structure has been mentioned in the above description of the semiconductor structure, and will not be repeated in the description of the semiconductor structure fabrication method.

[0095] When the semiconductor structure prepared by the above method is subsequently erased and written, electrons penetrate through different channels, which reduces the number of electron penetrations in the insulating layer 2 and effectively improves the lifetime of the semiconductor structure. In addition, by asymmetric etching of the floating gate 401, an asymmetric floating gate 401 is obtained, which enables the erasure operation to be performed with a smaller erasure voltage, further improving the reliability of the structure.

[0096] This application also provides a semiconductor memory, which includes the semiconductor structure described above. The semiconductor structure includes a laterally spaced floating gate region 4 and an erase gate region 5, with a tunneling oxide layer 6 filling the space between them. Both the floating gate region 4 and the erase gate region 5 are located on an insulating layer 2 on a substrate 1. This allows electrons to pass through different oxide layer channels during erase and write operations, thereby improving the reliability of the semiconductor structure. Furthermore, the thickness of the tunneling oxide layer is greater than the thickness of the insulating layer 2 region corresponding to the floating gate 401, enabling the semiconductor structure to perform erase operations using a smaller erase voltage. Therefore, this memory device also has similar advantages.

[0097] This application provides an electronic device, which includes the semiconductor memory described above.

[0098] The electronic devices described in this application can be any electronic product or device such as smartphones, desktop computers, tablets, laptops, digital assistants, augmented reality (AR) / virtual reality (VR) devices, smart voice interaction devices, smart home appliances, smart wearable devices, and in-vehicle terminal devices.

[0099] The electronic device described in this application includes the aforementioned semiconductor memory, which comprises the aforementioned semiconductor structure. This semiconductor structure includes a laterally spaced floating gate region 4 and an erase gate region 5, with a tunneling oxide layer 6 filling the space between them. Both the floating gate region 4 and the erase gate region 5 are located on an insulating layer 2 on a substrate 1. Therefore, electrons during erase and write operations are transmitted through different oxide layer channels, thereby improving the reliability of the semiconductor structure. Furthermore, the thickness of the tunneling oxide layer is greater than the thickness of the insulating layer 2 region corresponding to the floating gate 401, allowing the semiconductor structure to perform erase operations using a smaller erase voltage. Therefore, this electronic device also possesses similar advantages.

[0100] It should be noted that the order of the embodiments described above is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. Furthermore, specific embodiments have been described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps described in the claims can be performed in a different order than that shown in the embodiments and still achieve the desired result. Additionally, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0101] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the device embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0102] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0103] The above description is only an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A semiconductor structure, characterized in that, It includes a substrate, an insulating layer, and a control gate layer stacked sequentially from bottom to top; The control gate layer includes a floating gate region and an erase gate region spaced apart along a first direction, with a tunneling oxide layer filling the space between the floating gate region and the erase gate region; the first direction is a direction perpendicular to the thickness direction of the substrate. The floating gate area includes floating gates and control gates arranged from bottom to top; The thickness of the tunneling oxide layer between the floating gate and the erasure gate region is greater than the thickness of the insulating layer in the region corresponding to the floating gate; The erasure grid area includes a first structure, a second structure, and a third structure arranged and connected from bottom to top; The width of the first structure is smaller than the width of the third structure; The width of the second structure gradually increases along the direction of the arrangement; An interlayer dielectric layer is provided between the floating gate and the control gate; the interlayer dielectric layer and the second structure are located on the same plane.

2. The semiconductor structure according to claim 1, characterized in that, The floating grid includes a first side and a second side opposite to each other; the first side and the second side are arranged along the first direction; the second side is close to the erasure grid area; The distance between the second side and the side of the control gate closest to the second side is greater than the distance between the first side and the side of the control gate closest to the first side.

3. The semiconductor structure according to claim 2, characterized in that, The floating grid includes a first floating grid region, a second floating grid region, and a third floating grid region that are sequentially arranged and connected along the first direction; The second floating gate region corresponds to the position of the control gate; The width of the first floating gate region is greater than the width of the third floating gate region, or the width of the first floating gate region is less than the width of the third floating gate region.

4. The semiconductor structure according to claim 3, characterized in that, The top of the second floating gate region is at a predetermined distance from the top of the first floating gate region and the top of the third floating gate region, respectively.

5. The semiconductor structure according to claim 1, characterized in that, Includes two of the aforementioned floating gate regions; The erasure gate area is located between the two floating gate areas.

6. The semiconductor structure according to claim 3, characterized in that, The tunneling oxide layer includes a first oxide structure and a second oxide structure; The first oxide structure is located between the floating gate and the erasure gate; The second oxide structure is located between the control gate and the erase gate, and the second oxide structure is a composite structure.

7. The semiconductor structure according to claim 6, characterized in that, The thickness of the first oxide structure is greater than the thickness of the first region of the insulating layer; the first region is the region corresponding to the projection of the floating gate onto the insulating layer.

8. The semiconductor structure according to claim 6, characterized in that, The control gate layer also includes word lines that are arranged along the first direction and have a preset interval from the floating gate area; A gap oxide layer is filled between the floating gate area and the word line; the thickness of the gap oxide layer is greater than the thickness of the first oxide structure. The first side is close to the letter line.

9. A method for fabricating a semiconductor structure, characterized in that, Includes the following steps: An initial semiconductor structure is provided; the initial semiconductor structure includes a substrate, an insulating layer and an initial control gate layer stacked sequentially from bottom to top; the initial control gate layer includes a floating gate material layer and a control gate located on the floating gate material layer; sidewalls are respectively provided on opposite sides of the control gate; The initial semiconductor structure is patterned to remove a predetermined area of ​​the floating gate material layer, and a floating gate is formed on the insulating layer to obtain an intermediate semiconductor structure. The control gate is located on the floating gate; A first oxide layer and an erase gate region are sequentially formed on the surface of the intermediate semiconductor structure to obtain the target semiconductor structure; the erase gate region and the floating gate are spaced apart along a first direction; the first direction is a direction perpendicular to the thickness direction of the substrate; a tunneling oxide layer is filled between the floating gate and the erase gate region; the thickness of the tunneling oxide layer between the floating gate and the erase gate region is greater than the thickness of the region of the insulating layer corresponding to the floating gate; The erasure grid area includes a first structure, a second structure, and a third structure arranged and connected from bottom to top; The width of the first structure is smaller than the width of the third structure; The width of the second structure gradually increases along the direction of the arrangement; An interlayer dielectric layer is provided between the floating gate and the control gate; the interlayer dielectric layer and the second structure are located on the same plane.

10. The preparation method according to claim 9, characterized in that, The surface of the initial control gate layer is provided with a second oxide layer; the initial control gate layer includes two control gates spaced apart along the first direction; the initial semiconductor structure is patterned to remove a predetermined area of ​​the floating gate material layer, and a floating gate is formed on the insulating layer to obtain an intermediate semiconductor structure, including: The initial semiconductor structure is patterned to remove the second oxide layer in a first preset region on the initial control gate layer; the first preset region is located on the side of the control gate away from the erase gate blanking area; the erase gate blanking area is the region between the two control gates; Remove the floating gate material layer in the first preset area and the floating gate material layer in the erased gate blank area to form a floating gate on the insulating layer, thereby obtaining the intermediate semiconductor structure.

11. The preparation method according to claim 10, characterized in that, The formation of a first oxide layer and an erase gate region on the surface of the intermediate semiconductor structure to obtain the target semiconductor structure includes: The first oxide layer is formed on the surface of the intermediate semiconductor structure; Conductive material is deposited in the first preset region to form word lines on the insulating layer; simultaneously, conductive material is deposited in the erase gate blank area to form an erase gate area on the insulating layer, thereby obtaining the target semiconductor structure.

12. A semiconductor memory, characterized in that, Includes the semiconductor structure as described in any one of claims 1 to 8.

13. An electronic device, characterized in that, The electronic device includes the semiconductor memory as described in claim 12.

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