Semiconductor device and electronic system including the same

Abstract

Provided are a semiconductor device and an electronic system including the same, the semiconductor device may include: a peripheral circuit structure including a first bonding pad connected to a peripheral circuit on a semiconductor substrate; and a cell array structure including a second bonding pad bonded to the first bonding pad. The cell array structure may include: a partition structure penetrating the stack structure; a vertical channel pattern penetrating the stack structure; a source conductive pattern on the stacked structure, the source conductive pattern being connected to the vertical channel pattern; an upper dielectric layer covering the source conductive pattern; and an upper via penetrating the upper dielectric layer. The stacked structure may include interlayer dielectric layers and conductive patterns vertically alternately stacked. The separation structure may include a stop pattern on the dielectric pattern. The source conductive pattern may be in contact with a top surface of the stop pattern. An upper via may be connected to the source conductive pattern on the stop pattern.

Description

Technical Field

[0001] The inventive concept relates to a semiconductor device and an electronic system including the semiconductor device. Background Art

[0002] In an electronic system that requires data storage, it may be necessary to have a semiconductor device that can store a large amount of data. Therefore, research has been conducted to increase the data storage capacity of semiconductor devices. For example, as a method of increasing the data storage capacity of semiconductor devices, it has been proposed that semiconductor devices include three-dimensionally arranged memory cells instead of two-dimensionally arranged memory cells. Summary of the invention

[0003] Some embodiments of the inventive concept provide a semiconductor device having improved reliability and increased integration.

[0004] Some embodiments of the inventive concept provide an electronic system including a semiconductor device.

[0005] Aspects of the inventive concept are not limited to the above-mentioned contents, and other aspects not mentioned above will be clearly understood by those skilled in the art from the following description.

[0006] According to some embodiments of the inventive concept, a semiconductor device may include: a semiconductor substrate; a peripheral circuit structure including a plurality of peripheral circuits on the semiconductor substrate and a plurality of first bonding pads connected to the plurality of peripheral circuits; and a cell array structure including a plurality of second bonding pads bonded to the plurality of first bonding pads. The cell array structure may include: a stack structure; a separation structure penetrating the stack structure; a plurality of vertical channel patterns penetrating the stack structure; a source conductive pattern located on the stack structure, the source conductive pattern connected to the plurality of vertical channel patterns; an upper dielectric layer covering the source conductive pattern; and an upper via penetrating the upper dielectric layer. The stack structure may include a plurality of interlayer dielectric layers and a plurality of conductive patterns stacked vertically alternately. The separation structure may include a dielectric pattern and a stop pattern located on the dielectric pattern. The source conductive pattern may be in contact with a top surface of the stop pattern, and on the stop pattern, the upper via may be connected to the source conductive pattern.

[0007] According to some embodiments of the inventive concept, a semiconductor device may include: a semiconductor substrate; a peripheral circuit structure, the peripheral circuit structure including a plurality of peripheral circuits on the semiconductor substrate and a plurality of first bonding pads connected to the plurality of peripheral circuits; and a cell array structure, the cell array structure including a plurality of second bonding pads bonded to the plurality of first bonding pads. The cell array structure may include: a plurality of partition structures extending along a first direction; a stack structure located between the plurality of partition structures, the stack structure including a plurality of interlayer dielectric layers and a plurality of conductive patterns stacked vertically and alternately; a source conductive pattern located on the stack structure; a plurality of vertical channel patterns penetrating the stack structure and connected to the source conductive pattern; a plurality of bit lines extending along a second direction intersecting the first direction, while crossing the stack structure and connected to the plurality of vertical channel patterns; an upper dielectric layer covering the source conductive pattern; an upper via penetrating the upper dielectric layer and connected to the source conductive pattern; and a wiring pattern located on the upper dielectric layer and connected to the upper via. Each of the plurality of partition structures may include a dielectric pattern, a stop pattern, and a spacer, the stop pattern being located on the dielectric pattern and adjacent to the source conductive pattern. The spacer may surround the dielectric pattern and at least a portion of the stop pattern. A vertical length of the stop pattern may be smaller than a vertical length of the dielectric pattern.

[0008] According to some embodiments of the inventive concept, an electronic system may include: a semiconductor device including a peripheral circuit structure and a cell array structure located on the peripheral circuit structure; and a controller electrically connected to the semiconductor device through an input / output pad, the controller being configured to control the semiconductor device. The peripheral circuit structure may include: a plurality of peripheral circuits integrated on a semiconductor substrate; and a plurality of first bonding pads connected to the plurality of peripheral circuits. The cell array structure may include a plurality of second bonding pads bonded to the plurality of first bonding pads. The cell array structure may include: a stacking structure; a separation structure penetrating the stacking structure; a plurality of vertical channel patterns penetrating the stacking structure; a source conductive pattern located on the stacking structure, the source conductive pattern connected to the plurality of vertical channel patterns; an upper dielectric layer covering the source conductive pattern; and an upper via penetrating the upper dielectric layer. The stacking structure may include a plurality of interlayer dielectric layers and a plurality of conductive patterns vertically alternately stacked. The separation structure may include a dielectric pattern and a stop pattern on the dielectric pattern. The source conductive pattern may be in contact with a top surface of the stop pattern. On the stop pattern, the upper via may be connected to the source conductive pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 A simplified schematic diagram illustrating an electronic system including a semiconductor device according to some embodiments of the inventive concept is illustrated.

[0010] Figure 2 A simplified perspective view showing an electronic system including a semiconductor device according to some embodiments of the inventive concept is illustrated.

[0011] Figure 3 and Figure 4 Illustrated are simplified cross-sectional views showing semiconductor packages according to some embodiments of the inventive concept.

[0012] Figure 5 Illustrated are plan views showing semiconductor devices according to some embodiments of the inventive concept.

[0013] Fig. 6A Shown along Figure 5 A cross-sectional view taken along line AA' of FIG. 1 illustrates a semiconductor device according to some embodiments of the inventive concept.

[0014] Figure 6B Shown along Figure 5 A cross-sectional view taken along line BB' of FIG. 1 is shown, illustrating a semiconductor device according to some embodiments of the inventive concept.

[0015] Fig. 7A The diagram shows Fig. 6A Magnified view of section P1.

[0016] FIG. 7B to FIG. 7E An enlarged cross-sectional view showing a portion P1 according to some embodiments of the inventive concept is shown.

[0017] Figure 8 The diagram shows Fig. 6A Magnified view of portion P2.

[0018] Figures 9 to 11 , Fig. 12A , Fig. 12B , Fig. 12C and Figures 13 to 23 Shown along Figure 5 A cross-sectional view taken along line AA' of FIG. 1 illustrates a method for manufacturing a semiconductor device according to some embodiments of the inventive concept.

[0019] FIG. 24A to FIG. 24C Illustrated are cross-sectional views showing a method of forming a separation structure in fabricating a semiconductor device according to some embodiments of the inventive concept.

[0020] FIG. 25A to FIG. 25D Illustrated are cross-sectional views showing a method of forming a separation structure in fabricating a semiconductor device according to some embodiments of the inventive concept. DETAILED DESCRIPTION

[0021] Expressions such as "at least one" when preceding a series of elements modify the entire series of elements, rather than the individual elements in the series. For example, "at least one of A, B, and C" and similar language (e.g., "at least one selected from the group consisting of A, B, and C," "at least one of A, B, or C") can be interpreted as only A, only B, only C, or any combination of two or more of A, B, and C, such as ABC, AB, BC, and AC.

[0022] When the terms "approximately" or "substantially" are used in conjunction with a numerical value in this specification, the associated numerical value is intended to include manufacturing or operating tolerances (e.g., ±10%) around the stated numerical value. Moreover, when the words "approximately" and "substantially" are used in conjunction with geometric shapes, it is intended that the accuracy of the geometric shape is not required, but the range of the shape is within the disclosed range. Further, regardless of whether a numerical value or shape is modified as "approximately" or "substantially", it should be understood that these numerical values ​​and shapes should be interpreted as including manufacturing or operating tolerances (e.g., ±10%) around the stated numerical value or shape. When a range is specified, the range includes all values ​​therebetween, such as increments of 0.1%.

[0023] Some embodiments of the inventive concept will be described below with reference to the accompanying drawings.

[0024] Figure 1 A simplified schematic diagram illustrating an electronic system including a semiconductor device according to some embodiments of the inventive concept is shown.

[0025] refer to Figure 1 , the electronic system 1000 according to some embodiments of the inventive concept may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The electronic system 1000 may be a storage device including a single or multiple semiconductor devices 1100, or may be an electronic device including the storage device. For example, the electronic system 1000 may be a solid state drive (SSD) device, a universal serial bus (USB), a computing system, a medical device, or a communication device, each of which includes a single or multiple semiconductor devices 1100.

[0026] The semiconductor device 1100 may be a nonvolatile memory device, such as a NAND flash memory device. The semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. In some embodiments, the first structure 1100F may be disposed on the side of the second structure 1100S.

[0027] The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S may be a memory cell structure including a bit line BL, a common source line CSL, a word line WL, a first gate upper line UL1 and a second gate upper line UL2, a first gate lower line LL1 and a second gate lower line LL2, and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0028] In the second structure 1100S, each of the memory cell strings CSTR may include lower transistors LT1 and LT2 adjacent to a common source line CSL, upper transistors UT1 and UT2 adjacent to a bit line BL, and a memory cell transistor MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. According to embodiments, the number of the lower transistors LT1 and LT2 and the number of the upper transistors UT1 and UT2 may be variously changed.

[0029] In some embodiments, the upper transistors UT1 and UT2 may include string selection transistors, and the lower transistors LT1 and LT2 may include ground selection transistors. The gate lower lines LL1 and LL2 may be gate electrodes of the lower transistors LT1 and LT2, respectively. The word line WL may be a gate electrode of the memory cell transistor MCT, and the gate upper lines UL1 and UL2 may be gate electrodes of the upper transistors UT1 and UT2, respectively.

[0030] In some embodiments, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground selection transistor LT2 connected in series. The upper transistors UT1 and UT2 may include a string selection transistor UT1 and an upper erase control transistor UT2 connected in series. One or both of the lower erase control transistor LT1 and the upper erase control transistor UT2 may be used to perform an erase operation that uses a gate induced drain leakage (GIDL) phenomenon to erase data stored in the memory cell transistor MCT.

[0031] The common source line CSL, the first and second gate lower lines LL1 and LL2, the word lines WL, and the first and second gate upper lines UL1 and UL2 may be electrically connected to the decoder circuit 1110 through the first connection line 1115 extending from the first structure 1100F to the second structure 1100S. The bit line BL may be electrically connected to the page buffer 1120 through the second connection line 1125 extending from the first structure 1100F to the second structure 1100S.

[0032] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 may perform a control operation on at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The logic circuit 1130 may control the decoder circuit 1110 and the page buffer 1120. The semiconductor device 1100 may communicate with the controller 1200 through an input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 may be electrically connected to the logic circuit 1130 through an input / output connection line 1135 extending from the first structure 1100F to the second structure 1100S.

[0033] Although not shown, the first structure 1100F may include a voltage generator. The voltage generator may generate a program voltage, a read voltage, a pass voltage, and a verification voltage required to operate the memory cell string CSTR. The program voltage may be relatively higher (e.g., about 20V to about 40V) than the read voltage, the pass voltage, and the verification voltage.

[0034] In some embodiments, the first structure 1100F may include a high voltage transistor and a low voltage transistor. The decoder circuit 1110 may include a pass transistor connected to the word line WL of the memory cell string CSTR. The pass transistor may include a high voltage transistor that can withstand a high voltage such as a programming voltage applied to the word line WL in a programming operation. The page buffer 1120 may also include a high voltage transistor that can withstand a high voltage.

[0035] The controller 1200 may include a processor 1210 , a NAND controller 1220 , and a host interface 1230 . In some embodiments, the electronic system 1000 may include a plurality of semiconductor devices 1100 , and in this case, the controller 1200 may control the plurality of semiconductor devices 1100 .

[0036] The processor 1210 may control the overall operation of the electronic system 1000 including the controller 1200. The processor 1210 may operate based on desired and / or alternatively predetermined firmware, and may control the NAND controller 1220 to access the semiconductor device 1100. The NAND controller 1220 may include a NAND interface 1221 that handles communication with the semiconductor device 1100. The NAND interface 1221 may be used to transmit therethrough a control command for controlling the semiconductor device 1100, data intended to be written on the memory cell transistors MCT of the semiconductor device 1100, and / or data intended to be read from the memory cell transistors MCT of the semiconductor device 1100. The host interface 1230 may provide the electronic system 1000 with communication with an external host. When a control command is received from an external host through the host interface 1230, the semiconductor device 1100 may be controlled by the processor 1210 in response to the control command.

[0037] Figure 2 A simplified perspective view illustrating an electronic system including a semiconductor device according to some embodiments of the inventive concept is shown.

[0038] refer to Figure 2 , an electronic system 2000 according to some embodiments of the inventive concept may include a main board 2001, and may further include a controller 2002 mounted on the main board 2001, at least one semiconductor package 2003, and a dynamic random access memory (DRAM) 2004. The semiconductor package 2003 and the DRAM 2004 may be connected to the controller 2002 through a wiring pattern 2005 formed on the main board 2001.

[0039] The mainboard 2001 may include a connector 2006 including a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may be changed based on the communication interface between the electronic system 2000 and the external host. In some embodiments, the electronic system 2000 may communicate with the external host through one or more interfaces, such as a universal serial bus (USB), a peripheral component interconnect express (PCI-Express), a serial advanced technology attachment (SATA), and an M-PHY for universal flash storage (UFS). In some embodiments, the electronic system 2000 may operate using power supplied from an external host through the connector 2006. The electronic system 2000 may also include a power management integrated circuit (PMIC), and the power supplied from the external host is distributed to the controller 2002 and the semiconductor package 2003 through the power management integrated circuit.

[0040] The controller 2002 may write data to the semiconductor package 2003 , may read data from the semiconductor package 2003 , or may increase the operation speed of the electronic system 2000 .

[0041] The DRAM 2004 may be a buffer memory that reduces the speed difference between an external host and the semiconductor package 2003 used as a data storage space. The DRAM 2004 included in the electronic system 2000 may operate as a cache memory and may provide a space for temporary data storage in the control operation of the semiconductor package 2003. When the DRAM 2004 is included in the electronic system 2000, the controller 2002 may include not only a NAND controller for controlling the semiconductor package 2003 but also a DRAM controller for controlling the DRAM 2004.

[0042] The semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include: a package substrate 2100; a semiconductor chip 2200 located on the package substrate 2100; an adhesive layer 2300 disposed on the bottom surface of the semiconductor chip 2200; a connection structure 2400 electrically connecting the semiconductor chip 2200 to the package substrate 2100; and a mold layer 2500 located on the package substrate 2100 and covering the semiconductor chip 2200 and the connection structure 2400.

[0043] The package substrate 2100 may be a printed circuit board including the upper pads 2130. Each of the semiconductor chips 2200 may include one or more input / output pads 2210. The input / output pads 2210 may correspond to Figure 1 The input / output pads 1101 are provided. Each of the semiconductor chips 2200 may include a stack structure 3210 and a vertical structure 3220. According to some embodiments of the inventive concept, each of the semiconductor chips 2200 may include a semiconductor device described later.

[0044] In some embodiments, the connection structure 2400 may be a bonding wire that electrically connects the input / output pad 2210 to the upper pad 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other in a bonding wire manner and may be electrically connected to the upper pad 2130 of the package substrate 2100. In some embodiments, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other through a connection structure such as through silicon vias (TSV) instead of the connection structure 2400 shaped like a bonding wire.

[0045] In some embodiments, the controller 2002 and the semiconductor chip 2200 may be included in a single package. For example, the controller 2002 and the semiconductor chip 2200 may be mounted on an interposer substrate different from the main board 2001 and may be connected to each other through wiring lines formed on the interposer substrate.

[0046] Figure 3 and Figure 4 Illustrated are simplified cross-sectional views showing semiconductor packages according to some embodiments of the inventive concept. Figure 3 and Figure 4 Each depicted Figure 2 The example of a semiconductor package shown conceptually shows Figure 2 The semiconductor package shown is a cross section taken along line II'.

[0047] refer to Figure 3 The printed circuit board can be used as a package substrate 2100 of the semiconductor package 2003. The package substrate 2100 may include: a package substrate body 2120; an upper pad (see Figure 2 2130), the upper pads are disposed on the top surface of the package substrate body 2120; lower pads 2125, the lower pads are disposed or exposed on the bottom surface of the package substrate body 2120; and internal lines 2135, the upper pads 2130 and the lower pads 2125 are electrically connected to each other in the package substrate body 2120 through the internal lines 2135. The upper pads 2130 can be electrically connected to the connection structure 2400. The lower pads 2125 can be connected to the wiring pattern 2005 of the main board 2001 in the electronic system 2000 through the conductive connector 2800, as shown in FIG. Figure 2 shown.

[0048] Each of the semiconductor chips 2200 may include a semiconductor substrate 3010, and may also include a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010. The first structure 3100 may include a peripheral circuit region including a peripheral wiring line 3110. The second structure 3200 may include: a source structure 3205; a stacked structure 3210, the stacked structure 3210 being located on the source structure 3205; a vertical structure 3220 and a partition structure 3230, the vertical structure 3220 and the partition structure 3230 running through the stacked structure 3210; a bit line 3240, the bit line 3240 being electrically connected to the vertical structure 3220; and a cell contact plug, the cell contact plug being electrically connected to a corresponding word line of the stacked structure 3210 (see Figure 1 The partition structure 3230 may correspond to the first partition structure, the second partition structure, and the third partition structure (see Figure 5 The source structure 3205 may correspond to a source conductive pattern (see CST of FIG. 6 ) to be discussed below.

[0049] Each of the semiconductor chips 2200 may include one or more through-wiring lines 3245 extending into the second structure 3200 and electrically connected to the peripheral wiring lines 3110 of the first structure 3100. The through-wiring lines 3245 may be disposed outside the stacked structure 3210, and may also be disposed to penetrate the stacked structure 3210. Each of the semiconductor chips 2200 may also include one or more input / output pads electrically connected to the peripheral wiring lines 3110 of the first structure 3100 (see Figure 2 2210).

[0050] refer to Figure 4 In the semiconductor package 2003A, each semiconductor chip 2200 may include: a semiconductor substrate 4010; a first structure 4100 located on the semiconductor substrate 4010; and a second structure 4200 disposed on the first structure 4100 and wafer-bonded to the first structure 4100.

[0051] The first structure 4100 may include a peripheral circuit region including a peripheral wiring line 4110 and a first bonding structure 4150. The second structure 4200 may include: a source structure 4205; a stacked structure 4210 located between the source structure 4205 and the first structure 4100; a vertical structure 4220 and a partition structure 4230, the vertical structure 4220 and the partition structure 4230 penetrating the stacked structure 4210; and a second bonding structure 4250 electrically connected to a corresponding word line of the stacked structure 4210 (see Figure 1 For example, the second bonding structure 4250 may be electrically connected to the corresponding vertical structure 4220 through the bit line 4240 electrically connected to the vertical structure 4220, and connected to the corresponding word line through the cell contact plug electrically connected to the word line WL (see Figure 1 The first bonding structure 4150 of the first structure 4100 may be bonded to the second bonding structure 4250 while being in contact with the second bonding structure 4250 of the second structure 4200. The first bonding structure 4150 and the second bonding structure 4250 may have bonding portions thereof formed of, for example, copper (Cu).

[0052] The partition structure 4230 may correspond to the first partition structure, the second partition structure, and the third partition structure (see Figure 5The source structure 4205 may correspond to a source conductive pattern (see CST of FIG. 6 ) to be discussed below. Each of the semiconductor chips 2200 may further include an input / output pad (see FIG. 6 ) electrically connected to the peripheral wiring line 4110 of the first structure 4100. Figure 2 2210).

[0053] Figure 3 or Figure 4 The semiconductor chips 2200 may be electrically connected to each other through a connection structure 2400 shaped like a bonding wire. Figure 3 or Figure 4 In a semiconductor package of the semiconductor chips 2200, the semiconductor chips 2200 may be electrically connected to each other through a connection structure 3265 or 4265 including a through electrode such as a through silicon via (TSV).

[0054] Figure 3 The first structure 3100 and Figure 4 The first structure 4100 may correspond to a peripheral circuit structure to be discussed in the following embodiments, and Figure 3 The second structure 3200 and Figure 4 The second structure 4200 may correspond to a cell array structure which will be discussed in the following embodiments.

[0055] Figure 5 Illustrated are plan views showing semiconductor devices according to some embodiments of the inventive concept. Fig. 6A Shown along Figure 5 A cross-sectional view taken along line AA' of FIG. 1 illustrates a semiconductor device according to some embodiments of the inventive concept. Figure 6B Shown along Figure 5 A cross-sectional view taken along line BB' of FIG. 1 is shown, illustrating a semiconductor device according to some embodiments of the inventive concept. 7A to 7E The diagram shows Fig. 6A Magnified view of section P1. Figure 8 The diagram shows Fig. 6A Magnified view of portion P2.

[0056] refer to Figure 5 , Fig. 6A and Figure 6B , a semiconductor device according to some embodiments of the inventive concept may include a peripheral circuit structure PS located on a semiconductor substrate 200 and a cell array structure CS located on the peripheral circuit structure PS.

[0057] According to some embodiments, since the cell array structure CS is bonded to the peripheral circuit structure PS, the cell capacity per unit area of ​​the semiconductor device according to the inventive concept can be improved. In addition, since the peripheral circuit structure PS and the cell array structure CS are separately manufactured and then bonded to each other, the peripheral circuit PTR described later can be limited and / or prevented from being damaged due to various heat treatment processes, and therefore, the reliability and electrical characteristics of the semiconductor device can be improved.

[0058] The peripheral circuit structure PS may include: a semiconductor substrate 200; a peripheral circuit PTR that controls a memory cell array; and peripheral interlayer dielectric layers 210 and 220 that cover the peripheral circuit PTR. The peripheral circuit PTR may be integrated on the top surface of the semiconductor substrate 200. A surface dielectric layer 201 may be provided on the bottom surface of the semiconductor substrate 200.

[0059] The semiconductor substrate 200 may be, for example, a silicon substrate, a silicon germanium substrate, a germanium substrate, or a single crystal epitaxial layer grown on a single crystal silicon substrate. The semiconductor substrate 200 may have a top surface parallel to a first direction D1 and a second direction D2, the second direction D2 intersecting the first direction D1 and being perpendicular to a third direction D3. The first direction D1, the second direction D2, and the third direction D3 may be directions orthogonal to each other.

[0060] The peripheral circuit PTR may be a row decoder and a column decoder, a page buffer, and a control circuit. For example, the peripheral circuit PTR may include an NMOS transistor and a PMOS transistor. The peripheral circuit line PLP may be electrically connected to the peripheral circuit PTR through a peripheral contact plug PCP.

[0061] The peripheral contact plugs PCP may each have a width in the first direction D1 or the second direction D2, and, for example, the width may increase in the third direction D3. The peripheral contact plugs PCP and the peripheral circuit lines PLP may include a conductive material such as metal.

[0062] Peripheral interlayer dielectric layers 210 and 220 may be disposed on the top surface of the semiconductor substrate 200. On the semiconductor substrate 200, the peripheral interlayer dielectric layers 210 and 220 may cover the peripheral circuit PTR, the peripheral contact plug PCP, and the peripheral circuit line PLP. The peripheral contact plug PCP and the peripheral circuit line PLP may be electrically connected to the peripheral circuit PTR. The peripheral interlayer dielectric layers 210 and 220 may include one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a low-k dielectric layer.

[0063] The first bonding pad BP1 may be disposed in the uppermost peripheral interlayer dielectric layer 220. The uppermost peripheral interlayer dielectric layer 220 may not cover the top surface of the first bonding pad BP1. The top surface of the uppermost peripheral interlayer dielectric layer 220 may be substantially coplanar with the top surface of the first bonding pad BP1. The first bonding pad BP1 may be electrically connected to the peripheral circuit PTR through the peripheral circuit line PLP and the peripheral contact plug PCP.

[0064] The cell array structure CS may be disposed on the peripheral circuit structure PS. The cell array structure CS of the semiconductor device may include a cell array region CAR and first and second connection regions CNR1 and CNR2, and the first connection region CNR1 may be located between the cell array region CAR and the second connection region CNR2 along the first direction D1.

[0065] The cell array structure CS may include a memory cell array including memory cells arranged in three dimensions. The cell array structure CS may include a source conductive pattern CST, a stack structure ST, a first vertical structure VS1 and a second vertical structure VS2, a bit line BL, a cell contact plug CPLG, a peripheral contact plug PPLG, and an input / output contact plug IOPLG.

[0066] The stack structure ST of the cell array structure CS may be provided in plural. Figure 5 When viewed in the plan view shown, the plurality of stacked structures ST may extend along the first direction D1 and may be spaced apart from each other along the second direction D2. For ease of discussion, the following will focus on a single stacked structure ST, and the following description may also apply to other stacked structures ST.

[0067] The stack structure ST may include conductive patterns GE1 and GE2 and interlayer dielectric layers ILD1 and ILD2 alternately stacked along a third direction D3 (or a vertical direction) perpendicular to the first direction D1 and the second direction D2 .

[0068] An etch stop layer EST may be disposed on the stack structure ST. The etch stop layer EST may cover a top surface of the stack structure ST and may contact the uppermost first interlayer dielectric layer ILD1. For example, the etch stop layer EST may include polysilicon.

[0069] In some embodiments, the conductive patterns GE1 and GE2 may include: a first erase gate pattern and a second erase gate pattern, which are adjacent to the source conductive pattern CST; a ground selection gate pattern, which is located on the second erase gate pattern; a plurality of unit gate patterns, which are stacked on the ground selection gate pattern; and a string selection gate pattern, which is located on the topmost unit gate pattern.

[0070] The conductive patterns GE1 and GE2 of the stack structure ST may be stacked to have an inverted stepped structure on the first connection region CNR1. For example, the lengths of the conductive patterns GE1 and GE2 along the first direction D1 increase as the distances of the conductive patterns GE1 and GE2 from the peripheral circuit structure PS increase.

[0071] Each of the conductive patterns GE1 and GE2 may have a pad portion on the first connection region CNR1. The pad portions of the conductive patterns GE1 and GE2 may be located at positions horizontally and vertically different from each other. The cell contact plugs CPLG may be coupled to the pad portions of the conductive patterns GE1 and GE2, respectively.

[0072] In some embodiments, the stack structure ST may include a first stack structure ST1 and a second stack structure ST2 located below the first stack structure ST1. The first stack structure ST1 may include alternately stacked first interlayer dielectric layers ILD1 and first conductive patterns GE1, and the second stack structure ST2 may include alternately stacked second interlayer dielectric layers ILD2 and second conductive patterns GE2.

[0073] The second stack structure ST2 may be disposed between the first stack structure ST1 and the peripheral circuit structure PS. For example, the second stack structure ST2 may be disposed on the bottom surface of the lowest first interlayer dielectric layer among the first interlayer dielectric layers ILD1 included in the first structure ST1. Although the uppermost second interlayer dielectric layer among the second interlayer dielectric layers ILD2 included in the second stack structure ST2 contacts the lowest first interlayer dielectric layer among the first interlayer dielectric layers ILD1 included in the first stack structure ST1, the inventive concept is not limited thereto, and a single dielectric layer may be disposed between the uppermost second conductive pattern among the second conductive patterns GE2 included in the second stack structure ST2 and the lowest first conductive pattern among the first conductive patterns GE1 included in the first stack structure ST1.

[0074] A lowermost second conductive pattern among the second conductive patterns GE2 included in the second stacked structure ST2 may have a minimum length along the first direction D1 , and an uppermost first conductive pattern among the first conductive patterns GE1 included in the first stacked structure ST1 may have a maximum length along the first direction D1 .

[0075] The first conductive pattern GE1 and the second conductive pattern GE2 may include, for example, at least one selected from a doped semiconductor (e.g., doped silicon), a metal (e.g., tungsten, molybdenum, nickel, copper, or aluminum), a conductive metal nitride (e.g., titanium nitride or tantalum nitride), and a transition metal (e.g., titanium or tantalum). The first interlayer dielectric layer ILD1 and the second interlayer dielectric layer ILD2 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, and a low-k dielectric. For example, the first interlayer dielectric layer ILD1 and the second interlayer dielectric layer ILD2 may include high-density plasma (HDP) oxide or tetraethylorthosilicate (TEOS).

[0076] According to some embodiments, the semiconductor device may be a vertical NANF flash memory device, and in this case, the first conductive pattern GE1 and the second conductive pattern GE2 of the semiconductor device may be used as reference patterns. Figure 1 Discussed are gate lower lines LL1 and LL2, word lines WL, and gate upper lines UL1 and UL2.

[0077] The planarized dielectric layers 110a and 110b may cover the stepped end (or pad portion) of the stacked structure ST. The planarized dielectric layers 110a and 110b may have a substantially flat top surface. The planarized dielectric layers 110a and 110b may include a single dielectric layer or a plurality of stacked dielectric layers. For example, the planarized dielectric layers 110a and 110b may include a first planarized dielectric layer 110a covering the stepped structure of the first stacked structure ST1 and a second planarized dielectric layer 110b covering the stepped structure of the second stacked structure ST2. The planarized dielectric layers 110a and 110b may have substantially flat top and bottom surfaces. Top surfaces of the planarized dielectric layers 110 a and 110 b may be substantially coplanar with the etch stop layer EST on the stack structure ST, and bottom surfaces of the planarized dielectric layers 110 a and 110 b may be substantially coplanar with the lowermost interlayer dielectric layer ILD2 of the stack structure ST.

[0078] The source conductive pattern CST may be disposed on the uppermost first interlayer dielectric layer ILD1 of the first stacked structure ST1. The source conductive pattern CST may correspond to Figure 3 The source structure of 3205 and Figure 4The source conductive pattern CST may have a uniform thickness. The source conductive pattern CST may extend in the first direction D1 and the second direction D2 on the cell array region CAR and the first connection region CNR1. When viewed in the first direction D1, the length of the source conductive pattern CST may be greater than the length of the uppermost first conductive pattern GE1 of the first stacked structure ST1.

[0079] The source conductive pattern CST may cover the first vertical structure VS1 and the separation structures SS1 and SS2 to be discussed below. For example, upper portions of the first vertical structure VS1 and the separation structures SS1 and SS2 may protrude from the stack structure ST, and the source conductive pattern CST may have a uniform or substantially uniform thickness covering the protruding upper portions.

[0080] In some embodiments, the source conductive pattern CST may include at least one selected from polysilicon, a doped semiconductor (e.g., doped silicon), a metal (e.g., tungsten, copper, or aluminum), a conductive metal nitride (e.g., titanium nitride or tantalum nitride), and a transition metal (e.g., titanium or tantalum).

[0081] On the second connection region CNR2, an upper conductive pattern CP may be disposed on the top surface of the first planarized dielectric layer 110a and may be located at a level substantially the same as that of the source conductive pattern CST. The upper conductive pattern CP may include the same conductive material as that of the source conductive pattern CST. The input / output contact plug IOPLG may be connected to the input / output pad IOPAD through the upper via VA.

[0082] On the cell array region CAR, a plurality of first vertical structures VS1 may penetrate the stacked structure ST to be connected to the source conductive pattern CST. When viewed in a plan view, the first vertical structures VS1 may be arranged in a straight line or in a zigzag manner along one direction. On the first connection region CNR1, a second vertical structure VS2 may penetrate the stacked structure ST.

[0083] On the first connection region CNR1, the second vertical structure VS2 may penetrate ends (or pad portions) of the first and second conductive patterns GE1 and GE2. The second vertical structure VS2 may have substantially the same structure as the first vertical structure VS1 and may include the same material as that of the first vertical structure VS1.

[0084] The second vertical structure VS2 may be different from the first vertical structure VS1 in terms of planar shape and size. The top surfaces of the second vertical structures VS2 may have a circular shape, an elliptical shape, a bar shape, or any other suitable shape, respectively. The second vertical structure VS2 may be disposed to surround the cell contact plug CPLG. When the top surface of the second vertical structure VS2 has an elliptical shape, the main axis of the second vertical structure VS2 may be disposed in different directions on the pad portion of each of the first conductive pattern GE1 and the second conductive pattern GE2. A plurality of second vertical structures VS2 may be disposed between adjacent cell contact plugs CPLG.

[0085] In some embodiments, each of the first vertical structures VS1 may be disposed in a vertical channel hole penetrating the stack structure ST. The vertical channel hole may include a first vertical channel hole penetrating the first stack structure ST1, and may further include a second vertical channel hole penetrating the second stack structure ST2 and connected to the first vertical channel hole.

[0086] Each of the first vertical structures VS1 may include a first vertical extension in the first vertical channel hole and a second vertical extension in the second vertical channel hole. The first vertical extension and the second vertical extension may be a single structure extending continuously without a boundary. The first vertical extension may have a sidewall whose slope is consistent from its lower portion to its upper portion. Similarly, the second vertical extension may have a sidewall whose slope is consistent from its lower portion to its upper portion. For example, the width of each of the first vertical extension and the second vertical extension along the first direction D1 or the second direction D2 may decrease as the distance from the semiconductor substrate 200 increases. The first vertical extension and the second vertical extension may have different diameters at their connecting portions. A step difference may be provided at the connecting portion where the first vertical extension and the second vertical extension are connected to each other.

[0087] However, the inventive concept is not limited thereto, and unlike what is shown, each of the first vertical structures VS1 may have three or more vertical extensions having step differences at two or more boundaries. Alternatively, each of the first vertical structures VS1 may have a flat sidewall without a step difference.

[0088] refer to Figure 5 , Fig. 6A , Figure 6B and Fig. 7A , a first interlayer dielectric layer 120 may be disposed under the planarized dielectric layers 110a and 110b and the stacked structure ST. The first interlayer dielectric layer 120 may cover a bottom surface of the first vertical structure VS1.

[0089] The first, second, and third separation structures SS1, SS2, and SS3 may penetrate the first interlayer dielectric layer 120, the planarized dielectric layers 110a and 110b, and the stack structure ST. Each of the first, second, and third separation structures SS1, SS2, and SS3 may include a stop pattern STP, a dielectric pattern DL, and a spacer SP.

[0090] The dielectric pattern DL may be disposed on the second interlayer dielectric layer 130, and the stop pattern STP may be disposed on the dielectric pattern DL. The dielectric pattern DL and the stop pattern STP may be disposed along a vertical direction (or a third direction D3), and an upper portion of the stop pattern STP may protrude from the etch stop layer EST. For example, a top surface STPb of the stop pattern STP may be located at a level higher than that of the top surface of the etch stop layer EST, and an upper portion of the stop pattern STP may be covered with a source conductive pattern CST.

[0091] The spacer SP may surround the outer lateral surface of the dielectric pattern DL and the outer lateral surface of the stop pattern STP. The top surface of the dielectric pattern DL may be in contact with the bottom surface STPa of the stop pattern STP, and the spacer SP may be disposed between the dielectric pattern DL and the stacked structure ST and between the stop pattern STP and the stacked structure ST. The top surface of the spacer SP may be coplanar with the top surface of the etch stop layer EST. For example, the stop pattern STP may include at least one selected from amorphous silicon, polysilicon, and metal, and the dielectric pattern DL may include at least one selected from silicon oxide, silicon nitride, and silicon germanium (SiGe). The spacer SP may include silicon oxide or silicon oxynitride.

[0092] The stop pattern STP may be disposed only in a portion of each of the separation structures SS1, SS2, and SS3. For example, the stop pattern STP may be positioned on an upper portion of each of the separation structures SS1, SS2, and SS3. The stop pattern STP may have a bottom surface STPa and a top surface STPb that are opposite to each other in a third direction D3, and the top surface STPb of the stop pattern STP may be adjacent to the source conductive pattern CST. The bottom surface STPa of the stop pattern STP may be located at a level higher than that of the bottom surface of the stacked structure ST. The vertical length of the stop pattern STP may be less than the vertical length of the dielectric pattern DL. The vertical length of each of the stop pattern STP and the dielectric pattern DL may refer to the length in the third direction D3.

[0093] When the stop pattern STP is positioned on the upper portion of each of the separation structures SS1, SS2, and SS3, the stop pattern STP may be used as a stopper in the process of patterning the upper dielectric layer 310 to form an upper via VA as discussed below. For example, when a hole penetrating the upper dielectric layer 310 is formed to form the upper via VA, the stop pattern STP may be used to limit and / or prevent the dielectric patterns DL of the separation structures SS1, SS2, and SS3 from being overetched.

[0094] According to some embodiments, the bottom surface STPa of the stop pattern STP may be located at a level higher than the levels of the conductive patterns GE1 and GE2 and the top surface of the conductive pattern GE1 most adjacent to the source conductive pattern CST among the conductive patterns GE1 and GE2. Therefore, a sufficient interval may be ensured between the stop pattern STP and the conductive patterns GE1 and GE2, and even when the stop pattern STP includes a metal, the stop pattern STP and the conductive patterns GE1 and GE2 may be less electrically affected by each other.

[0095] Compared to other dielectric materials, amorphous silicon or polycrystalline silicon may be relatively more susceptible to thermal deformation, and when heat is applied to the separation structures SS1, SS2, and SS3 filled with only amorphous silicon or polycrystalline silicon, large thermal deformation may occur to cause a warpage phenomenon. In contrast, according to some embodiments of the inventive concept, the stop pattern STP may be provided only in a portion of each of the separation structures SS1, SS2, and SS3, and thus even when the stop pattern STP includes amorphous silicon or polycrystalline silicon, the warpage phenomenon may be at least partially restricted and / or prevented.

[0096] The first separation structures SS1 may extend from the cell array region CAR toward the first connection region CNR1 along the first direction D1 and may be spaced apart from each other in a second direction D2 intersecting the first direction D1. In some embodiments, the stacked structure ST may be disposed between the first separation structures SS1 adjacent to each other in the second direction D2.

[0097] The second separation structure SS2 may penetrate the stacked structure ST on the cell array region CAR. The second separation structure SS2 may be disposed between the first separation structures SS1. When viewed in the first direction D1, the length of the second separation structure SS2 may be less than the length of the first separation structure SS1. Alternatively, a plurality of second separation structures SS2 may be disposed between the first separation structures SS1.

[0098] On the first connection region CNR1, the third separation structure SS3 may penetrate the planarized dielectric layers 110a and 110b and the stacked structure ST while being spaced apart from the first separation structure SS1 and the second separation structure SS2 in the first direction D1. The third separation structure SS3 may extend along the first direction D1. The third separation structures SS3 may be spaced apart from each other in the first direction D1 and the second direction D2.

[0099] A bit line conductive pad may be formed on the lower end of the first vertical structure VS1, and an upper bit line contact plug BCTa may penetrate the first interlayer dielectric layer 120 and the second interlayer dielectric layer 130 to contact the bit line conductive pad. The bit line conductive pad may include a semiconductor material not doped with impurities, a semiconductor material doped with impurities, or a conductive material. A lower bit line contact plug BCTb may penetrate the third interlayer dielectric layer 140 to couple to the upper bit line contact plug BCTa.

[0100] On the first connection region CNR1, the cell contact plug CPLG may penetrate the first interlayer dielectric layer 120, the second interlayer dielectric layer 130, and the third interlayer dielectric layer 140 and the planarized dielectric layers 110a and 110b to be coupled to the pad portions of the first conductive pattern GE1 and the second conductive pattern GE2, respectively. The vertical length of the cell contact plug CPLG decreases as the distance from the cell array region CAR decreases. The cell contact plug CPLG may have bottom surfaces thereof substantially coplanar with each other.

[0101] On the second connection region CNR2 , the peripheral contact plug PPLG and the input / output contact plug IOPLG may penetrate the first, second, and third interlayer dielectric layers 120 , 130 , and 140 and the planarized dielectric layers 110 a and 110 b to be coupled to the upper conductive pattern CP.

[0102] Each of the cell contact plug CPLG, the peripheral contact plug PPLG, and the input / output contact plug IOPLG may include a barrier metal layer including a conductive metal nitride (eg, titanium nitride or tantalum nitride) and a metal layer including a metal (eg, tungsten, titanium, or tantalum).

[0103] On the cell array region CAR, the bit line BL may be disposed on the third interlayer dielectric layer 140. The bit line BL may extend in the second direction D2 while running across the stack structure ST. The bit line BL may be electrically connected to the first vertical structure VS1 through the upper bit line contact plug BCTa and the lower bit line contact plug BCTb.

[0104] On the first connection region CNR1 , a first lower conductive line LCLa may be disposed under the third interlayer dielectric layer 140 so as to be coupled to the cell contact plug CPLG.

[0105] On the second connection region CNR2 , the second lower conductive line LCLb may be disposed under the third interlayer dielectric layer 140 , thereby being coupled to the peripheral contact plug PPLG and the input / output contact plug IOPLG.

[0106] A fourth interlayer dielectric layer 150 may be disposed under the third interlayer dielectric layer 140 , and the bit lines BL and the first and second lower conductive lines LCLa and LCLb may be disposed in the fourth interlayer dielectric layer 150 .

[0107] A fifth interlayer dielectric layer 160 may be disposed under the fourth interlayer dielectric layer 150, and a first upper conductive line UCLa and a second upper conductive line UCLb may be disposed in the fifth interlayer dielectric layer 160. On the cell array region CAR, the first upper conductive line UCLa may be electrically connected to the bit line BL. On the first connection region CNR1 and the second connection region CNR2, the second upper conductive line UCLb may be electrically connected to the first lower conductive line LCLa and the second lower conductive line LCLb.

[0108] The first lower conductive line LCLa and the second lower conductive line LCLb and the first upper conductive line UCLa and the second upper conductive line UCLb may include at least one selected from metal (e.g., tungsten, copper, or aluminum), conductive metal nitride (e.g., titanium nitride or tantalum nitride), and transition metal (e.g., titanium or tantalum). For example, the first lower conductive line LCLa and the second lower conductive line LCLb may be formed of tungsten having a relatively high resistivity, and the first upper conductive line UCLa and the second upper conductive line UCLb may be formed of copper having a relatively low resistivity.

[0109] The sixth interlayer dielectric layer 170 may be disposed under the fifth interlayer dielectric layer 160, and the second bonding pad BP2 may be disposed in the sixth interlayer dielectric layer 170. The second bonding pad BP2 may be electrically connected to the first upper conductive line UCLa and the second upper conductive line UCLb. The second bonding pad BP2 may be formed of aluminum, copper, or tungsten.

[0110] The second bonding pad BP2 may be electrically and physically connected to the first bonding pad BP1 using a bonding method. For example, the second bonding pad BP2 may be in direct contact with the first bonding pad BP1.

[0111] The second bonding pad BP2 may include the same metal material as those of the first bonding pad BP1. The second bonding pad BP2 may have substantially the same shape, width, and area as those of the first bonding pad BP1.

[0112] The upper dielectric layer 310 may cover the source conductive pattern CST and the upper conductive pattern CP. An upper via VA penetrating the upper dielectric layer 310 may be disposed on the source conductive pattern CST and the upper conductive pattern CP. The upper via VA may be disposed on the source conductive pattern CST, or may penetrate the source conductive pattern CST, or may penetrate the source conductive pattern CST to contact the top surface STPb of the stop pattern STP of the separation structures SS1, SS2, and SS3.

[0113] A wiring pattern PAD and an input / output pad IOPAD may be disposed on the upper dielectric layer 310. A capping dielectric layer 320 may be disposed on the upper dielectric layer 310, and the capping dielectric layer 320 may cover the wiring pattern PAD and the input / output pad IOPAD.

[0114] The capping dielectric layer 320 and the passivation layer 340 may be sequentially formed on the front surface of the upper dielectric layer 310. The capping dielectric layer 320 may include, for example, a silicon nitride layer or a silicon oxynitride layer. The passivation layer 340 may include a polyimide-based material such as photosensitive polyimide (PSPI).

[0115] The capping dielectric layer 320 and the passivation layer 340 may have a pad opening OP exposing a portion of the input / output pad IOPAD.

[0116] FIG. 7B to FIG. 7E An enlarged cross-sectional view showing a portion P1 according to some embodiments of the inventive concept is illustrated. For simplicity of explanation, detailed descriptions of technical features identical to those of the semiconductor device discussed above may be omitted, and differences thereof will be described.

[0117] refer to Figure 5 , Fig. 6A and Figure 7B , the stop pattern STP and the dielectric pattern DL may vary in their shapes. For example, the bottom surface STPa of the stop pattern STP may have a concave portion, and the concave portion may be concave upward. The top surface of the dielectric pattern DL may be in contact with the concave portion. For example, the top surface of the dielectric pattern DL may have a convex protruding shape.

[0118] refer to Figure 5 , Fig. 6A and Figure 7C , the stop pattern STP may be disposed to be spaced apart from the upper via VA without contacting the upper via. For example, the stop pattern STP and the upper via VA may be spaced apart from each other via the source conductive pattern CST.

[0119] refer to Figure 5 , Fig. 6A and Fig.7DThe stop pattern STP may include a first stop pattern STP1 and a second stop pattern STP2. The first stop pattern STP1 may be disposed on the dielectric pattern DL, and the second stop pattern STP2 may be interposed between the first stop pattern STP1 and the source conductive pattern CST on the dielectric pattern DL. The second stop pattern STP2 may surround the top surface and the lateral surface of the first stop pattern STP1.

[0120] The second stop pattern STP2 may include a low-k dielectric material and may have a dielectric constant less than that of the first stop pattern STP1. Therefore, the second stop pattern STP2 having a low dielectric constant may surround the top surface and the lateral surface of the first stop pattern STP1, and the electrical interference between the first conductive pattern GE1 and the first stop pattern STP1 may be reduced.

[0121] refer to Figure 5 , Fig. 6A and Fig. 7E , the spacer SP may have a relatively large width W1. In this case, the spacer SP may ensure a distance between the stop pattern STP and the first conductive pattern GE1, and thus the bottom surface STPa of the stop pattern STP may be located at a level lower than that of the bottom surface of at least one of the first conductive patterns GE1. Therefore, the stop pattern STP may have a relatively large height H1. The width W1 of the spacer SP may refer to a thickness in a direction parallel to the top surface of the stack structure ST (e.g., the first direction D1 or the second direction D2), and the height H1 of the stop pattern STP may refer to a distance from the top surface STPb of the stop pattern STP to the bottom surface STPa of the stop pattern STP in a vertical direction (e.g., the third direction D3).

[0122] refer to Figure 5 , Fig. 6A and Figure 8 The first vertical structure VS1 may extend in a third direction D3 perpendicular to the top surface of the semiconductor substrate 200 to penetrate the stack structure ST and be connected to the source conductive pattern CST.

[0123] Each of the first vertical structures VS1 may include a vertical channel pattern VP, a data storage pattern DSP, and a vertical dielectric pattern VI.

[0124] For example, the vertical channel pattern VP may have a macaroni shape or a pipe shape with its top and bottom ends closed. The vertical channel pattern VP may have an inner sidewall defining an inner space and an outer sidewall adjacent to the stacked structure ST. The vertical channel pattern VP may surround the outer sidewall of the vertical dielectric pattern VI, and a portion of the vertical channel pattern VP may be disposed between the source conductive pattern CST and the vertical dielectric pattern VI.

[0125] The vertical channel pattern VP may include a semiconductor material such as silicon (Si), germanium (Ge), or a mixture thereof. The vertical channel pattern VP including a semiconductor material may be used as a channel of the upper transistors UT1 and UT2, the memory cell transistor MCT, and the lower transistors LT1 and LT2, all of which are referenced Figure 1 discuss.

[0126] The vertical channel pattern VP may be connected to the source conductive pattern CST. For example, the vertical channel pattern VP may have an upper portion protruding from the etch stop layer EST, and the protruding upper portion of the vertical channel pattern VP may be covered by the source conductive pattern CST. The top surface of the vertical channel pattern VP may be located at a higher level than the top surface of the etch stop layer EST.

[0127] The data storage pattern DSP may extend in the third direction D3 and surround the outer sidewall of the vertical channel pattern VP. For example, the top surface of the data storage pattern DSP may be located at a level lower than the level of the top surface of the vertical channel pattern VP, and may be coplanar with the top surface of the etching stop layer EST. The data storage pattern DSP may have a macaroni or tubular shape with its top end open. The data storage pattern DSP may be formed by a single thin layer or a plurality of thin layers. In some embodiments of the inventive concept, the data storage pattern DSP may include a tunneling dielectric layer TIL, a charge storage layer CIL, and a blocking dielectric layer BLK constituting a data storage layer of a NAND flash memory device. For example, the charge storage layer CIL may be a trap dielectric layer, a floating gate electrode, or a dielectric layer including conductive nanodots.

[0128] Figures 9 to 11 , Fig. 12A , Fig. 12B , Fig. 12C and Figures 13 to 23 Shown along Figure 5 A cross-sectional view taken along line AA' of FIG. 1 illustrates a method for manufacturing a semiconductor device according to some embodiments of the inventive concept.

[0129] refer to Figure 5 and Fig. 9 , a lowermost dielectric layer EILD, an etch stop layer EST, and a first mold structure ML1 may be formed on the first substrate 100 .

[0130] The formation of the first mold structure ML1 may include forming a first thin layer structure (not shown) in which first interlayer dielectric layers ILD1 and first sacrificial layers SL1 are vertically alternately stacked and repeatedly performing a patterning process on the first thin layer structure. Therefore, the first mold structure ML1 may have a stepped structure on the first connection region CNR1.

[0131] The lowermost dielectric layer EILD, the etch stop layer EST, the first interlayer dielectric layer ILD1 and the first sacrificial layer SL1 may be deposited by using one of thermal chemical vapor deposition (CVD), plasma enhanced CVD, physical CVD processes and atomic layer deposition (ALD).

[0132] The etch stop layer EST may be formed of a material different from that of the lowermost dielectric layer EILD, and unlike the lowermost dielectric layer EILD, the etch stop layer EST may be etch-resistant. For example, the etch stop layer EST may be formed of polysilicon, while the lowermost dielectric layer EILD may be formed of silicon oxide.

[0133] In the first mold structure ML1, the first sacrificial layer SL1 may be formed of a material that can be etched with an etching selectivity relative to the first interlayer dielectric layer ILD1. For example, the first sacrificial layer SL1 may be formed of a dielectric material different from the dielectric material of the first interlayer dielectric layer ILD1. For example, the first sacrificial layer SL1 may be formed of a silicon nitride layer, and the first interlayer dielectric layer ILD1 may be formed of a silicon oxide layer.

[0134] After forming the first mold structure ML1 , a first planarized dielectric layer 110 a may be formed to cover the stepped structure of the first mold structure ML1 .

[0135] The second mold structure ML2 may be formed on the first mold structure ML1. According to some embodiments, before forming the second mold structure ML2, a vertical sacrificial pattern (not shown) penetrating the first mold structure ML1 may be formed.

[0136] The formation of the second mold structure ML2 may be substantially the same as the formation of the first mold structure ML1 discussed above. For example, the formation of the second mold structure ML2 may include forming a second thin layer structure (not shown) in which the second interlayer dielectric layer ILD2 and the second sacrificial layer SL2 are vertically alternately stacked on the first mold structure ML1, and repeatedly performing a patterning process on the second thin layer structure. Therefore, the second mold structure ML2 may have a stepped structure on the first connection region CNR1.

[0137] The second sacrificial layer SL2 may include the same material as that of the first sacrificial layer SL1, and may have a thickness substantially the same as that of the first sacrificial layer SL1. The second sacrificial layer SL2 may be formed of a dielectric material different from the dielectric material of the second interlayer dielectric layer ILD2. The second sacrificial layer SL2 may be formed of the same material as that of the first sacrificial layer SL1. For example, the second sacrificial layer SL2 may be formed of a silicon nitride layer, and the second interlayer dielectric layer ILD2 may be formed of a silicon oxide layer.

[0138] After forming the second mold structure ML2, a second planarized dielectric layer 110b may be formed to cover the stepped structure of the second mold structure ML2. The first planarized dielectric layer 110a and the second planarized dielectric layer 110b may constitute the planarized dielectric layers 110a and 110b.

[0139] The vertical channel hole may be formed to penetrate the first and second mold structures ML1 and ML2 and expose the first substrate 100. When a vertical sacrificial pattern (not shown) is formed in the first mold structure ML1, the formation of the vertical channel hole may include removing the vertical sacrificial pattern to expose the first substrate 100.

[0140] When forming the vertical channel hole, on the first connection region CNR1 , a dummy channel hole may be formed to penetrate portions of the planarized dielectric layers 110 a and 110 b and the first and second mold structures ML1 and ML2 .

[0141] The formation of the vertical channel hole may include forming a hard mask pattern on the second molding structure ML2, and anisotropically etching the first molding structure ML1 and the second molding structure ML2 using the hard mask pattern as an etching mask. The anisotropic etching process for forming the vertical channel hole may expose the top surface of the first substrate 100, and the top surface of the first substrate 100 exposed by the vertical channel hole may be recessed to a certain depth. In addition, in the anisotropic etching process for forming the vertical channel hole, the depth of the recess of the first substrate 100 may be changed according to the position of the vertical channel hole.

[0142] Thereafter, the first vertical structure VS1 may be formed in the vertical channel hole on the cell array region CAR, and the second vertical structure VS2 may be formed in the dummy channel hole on the first connection region CNR1.

[0143] The formation of the first vertical channel structure VS1 and the second vertical channel structure VS2 may include sequentially depositing a data storage layer and a vertical channel layer in the vertical channel hole, and etching and planarizing the data storage layer and the vertical channel layer.

[0144] A chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process can be used to deposit a data storage layer having a uniform thickness on the bottom surface and inner sidewalls of the vertical channel hole. The data storage layer may include a blocking dielectric layer, a charge storage layer, and a tunneling dielectric layer sequentially stacked in the vertical channel hole. A chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process can be used to deposit a vertical channel layer having a uniform thickness on the data storage layer. After forming the data storage layer and the vertical channel layer, the vertical channel hole can be filled with a gap-filling dielectric layer. Therefore, as described above with reference to Figure 8 As discussed, the data storage pattern DSP, the vertical channel pattern VP, and the vertical dielectric pattern VI may be formed in each vertical channel hole.

[0145] Thereafter, a bit line conductive pad may be formed on the top end of the vertical channel pattern VP. The bit line conductive pad may be a region doped with impurities or may be formed of a conductive material. The bit line conductive pad may have its top surface coplanar with the top surface of the uppermost second interlayer dielectric layer ILD2.

[0146] refer to Figure 5 and Fig.10 , a first interlayer dielectric layer 120 may be formed on the second planarized dielectric layer 110 b to cover top surfaces of the first and second vertical structures VS1 and VS2 .

[0147] The first and second mold structures ML1 and ML2 may be patterned to form trenches CH1. The trenches CH1 may penetrate the first and second mold structures ML1 and ML2, the etch stop layer EST, and the lowermost dielectric layer EILD, and may additionally penetrate a portion of the first substrate 100.

[0148] A process of replacing the first sacrificial layer SL1 of the first mold structure ML1 and the second sacrificial layer SL2 of the second mold structure ML2 with the first conductive pattern GE1 and the second conductive pattern GE2 may be performed. Thus, a stack structure ST may be formed on the first substrate 100 .

[0149] The process of replacing the first sacrificial layer SL1 and the second sacrificial layer SL2 with the first conductive pattern GE1 and the second conductive pattern GE2 may include isotropically etching the first sacrificial layer SL1 and the second sacrificial layer SL2 by using an etching recipe having an etching selectivity relative to the first and second interlayer dielectric layers ILD1 and ILD2, the first and second vertical structures VS1 and VS2, and the first substrate 100.

[0150] refer to Fig.11 and FIG. 12A to FIG. 12C , separation structures SS1 and SS2 may be formed in the trench CH1 .

[0151] For example, refer to Figure 5 and Fig.11 , a spacer layer SP' may be formed on the first interlayer dielectric layer 120 and the trench CH1, and the spacer layer SP' may conformally cover the top surface of the first interlayer dielectric layer 120 and the bottom surface and inner wall of the trench CH1. For example, the spacer layer SP' may be formed by using chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0152] refer to Fig. 12A , a stop layer STP' may be formed on the spacer layer SP'. The stop layer STP' may fill the trench CH1. For example, the trench CH1 may be filled with the stop layer STP' using a chemical vapor deposition (CVD) process. The stop layer STP' may include at least one selected from amorphous silicon, polysilicon, and metal.

[0153] refer to Fig. 12B , a portion of the stop layer STP' may be etched to form a stop pattern STP. For example, the stop layer STP' may be etched back to leave a portion of the stop layer STP' while removing the remaining portion of the stop layer STP' so that the stop pattern STP may be formed in the lower portion of the trench CH1. The top surface of the stop pattern STP may be located at a level lower than that of the bottom surface of the lowermost first conductive pattern among the first conductive patterns GE1.

[0154] refer to Fig. 12C , the dielectric pattern DL may fill the trench CH1 in which the stop pattern STP is formed. For example, the dielectric pattern DL may be formed by forming a dielectric layer filling the trench CH1 in which the stop pattern STP is formed using chemical vapor deposition (CVD), and then performing a planarization process on the dielectric layer to expose the first interlayer dielectric layer 120. The planarization process may remove a portion of the spacer layer SP' on the first interlayer dielectric layer 120, and may form a spacer SP. The planarization process may include, for example, a chemical mechanical polishing (CMP) process or an etch-back process.

[0155] refer to Figure 5 and Fig.13 , after forming the stack structure ST and the separation structures SS1 and SS2, a second interlayer dielectric layer 130 may be formed on the first interlayer dielectric layer 120. Afterwards, an upper bit line contact plug BCTa may be formed to penetrate the first interlayer dielectric layer 120 and the second interlayer dielectric layer 130, thereby being coupled to the first vertical structure VS1. The upper bit line contact plug BCTa may contact the bit line conductive pad of the first vertical structure VS1. The bit line conductive pad may be formed of a semiconductor material not doped with impurities, a semiconductor material doped with impurities, or a conductive material.

[0156] refer to Figure 5 and Fig.14 , a third interlayer dielectric layer 140 may be formed on the second interlayer dielectric layer 130, and a lower bit line contact plug BCTb may be formed to penetrate the third interlayer dielectric layer 140 so as to be coupled to the upper bit line contact plug BCTa. In addition, a cell contact plug CPLG, a peripheral contact plug PPLG, and an input / output contact plug IOPLG may be formed on the first connection region CNR1 and the second connection region CNR2. On the second connection region CNR2, the peripheral contact plug PPLG and the input / output contact plug IOPLG may be formed by forming a contact hole penetrating the first interlayer dielectric layer 120, the second interlayer dielectric layer 130, and the third interlayer dielectric layer 140 and the planarized dielectric layers 110a and 110b to expose the first substrate 100, and then filling the contact hole with a conductive material.

[0157] The bit line BL may be formed on the third interlayer dielectric layer 140. The bit line BL may be connected to the upper bit line contact plug BCTa and the lower bit line contact plug BCTb.

[0158] On the first connection region CNR1 and the second connection region CNR2, a first lower conductive line and a second lower conductive line connected to the cell contact plug CPLG may be formed (see Figure 6B of LCLa and LCLb).

[0159] refer to Figure 5 and Fig.15 , a fourth interlayer dielectric layer 150, a fifth interlayer dielectric layer 160, and a sixth interlayer dielectric layer 170 may be formed to be stacked on the third interlayer dielectric layer 140, and a first upper conductive line and a second upper conductive line may be formed on the third interlayer dielectric layer 140 (see Figure 6B The first upper conductive line UCLa and UC1b are connected to the bit line BL. Figure 6B CNR1 and CNR2), a second upper conductive line can be formed (see Figure 6B UCLb), and the second upper conductive line (see Figure 6B UCLb) can be connected to the first lower conductive line and the second lower conductive line (see Figure 6B of LCLa and LCLb).

[0160] A second bonding pad BP2 may be formed in the sixth interlayer dielectric layer 170, and the second bonding pad BP2 may be connected to the first upper conductive wire and the second upper conductive wire (see Figure 6B of UCLa and UCLb).

[0161] The first upper conductive line and the second upper conductive line may be formed using a damascene process (see Figure 6B The second bonding pad BP2 may have its top surface substantially coplanar with the top surface of the sixth interlayer dielectric layer 170.

[0162] refer to Figure 5 and Fig.16 , a peripheral circuit structure PS including a peripheral circuit PTR formed on a second substrate 200 may be prepared.

[0163] For example, the formation of the peripheral circuit structure PS may include: forming a device isolation layer defining an active area in the second substrate 200; forming a peripheral circuit PTR on the active area on the second substrate 200; forming a peripheral contact plug PCP, a peripheral circuit line PLP, and a first bonding pad BP1 electrically connected to the peripheral circuit PTR; and forming peripheral interlayer dielectric layers 210 and 220 covering the peripheral contact plug PCP, the peripheral circuit line PLP and the first bonding pad BP1.

[0164] The second substrate 200 may include, for example, at least one selected from silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenic (GaAs), indium gallium arsenic (InGaAs), aluminum gallium arsenic (AlGaAs), and mixtures thereof. In this specification, the second substrate 200 may correspond to a semiconductor substrate.

[0165] Row and column decoders, page buffers, and control circuits may be formed as peripheral circuits PTR on the second substrate 200. The peripheral circuits PTR may include metal oxide semiconductor (MOS) transistors each of which uses the second substrate 200 as a channel.

[0166] The peripheral interlayer dielectric layers 210 and 220 may include a single dielectric layer covering the peripheral circuit PTR or a plurality of stacked dielectric layers covering the peripheral circuit PTR. For example, the peripheral interlayer dielectric layers 210 and 220 may include a plurality of lower dielectric layers and an etch stop layer between the lower dielectric layers. The peripheral interlayer dielectric layers 210 and 220 may include one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a low-k dielectric layer.

[0167] The peripheral contact plug PCP may penetrate portions of the peripheral interlayer dielectric layers 210 and 220 to be connected with the peripheral circuit PTR. The peripheral circuit line PLP may be formed by depositing a conductive layer and patterning the conductive layer.

[0168] The first bonding pad BP1 may be formed in the uppermost peripheral interlayer dielectric layer 220 of the peripheral interlayer dielectric layers 210 and 220. The first bonding pad BP1 may be electrically connected to the peripheral circuit PTR through the peripheral contact plug PCP and the peripheral circuit line PLP.

[0169] A damascene process may be used to form the first bonding pad BP1. The first bonding pad BP1 may have its top surface substantially coplanar with the top surface of the uppermost peripheral interlayer dielectric layer 220. In the following description, the phrase "substantially coplanar with" may mean that a planarization process can be performed. The planarization process may include, for example, a chemical mechanical polishing (CMP) process or an etch-back process.

[0170] The cell array structure CS formed on the first substrate 100 may be bonded to the peripheral circuit structure PS formed on the second substrate 200. Therefore, the first bonding pad BP1 of the peripheral circuit structure PS may be bonded to the second bonding pad BP2 of the cell array structure CS, and the uppermost interlayer dielectric layer 170 on the first substrate 100 may be bonded to the uppermost peripheral interlayer dielectric layer 220 on the second substrate 200.

[0171] When the first bonding pad BP1 and the second bonding pad BP2 are bonded to each other, the cell array structure CS may be turned upside down. For example, the first substrate 100 of the cell array structure CS may be positioned at the top position, and the stepped structure of the stack structure ST may be disposed upside down.

[0172] refer to Figure 5 and Fig.17 After bonding between the first bonding pad BP1 and the second bonding pad BP2, the first substrate 100 may be removed. The first substrate 100 may be removed by a grinding process, a planarization process, a dry etching process, and / or a wet etching process. Removal of the first substrate 100 may expose the top surface of the uppermost interlayer dielectric layer ILD1 of the stacked structure ST and the first planarized dielectric layer (see Figure 6B In addition, the removal of the first substrate 100 may cause the data storage layer of the first vertical structure VS1 to protrude from the uppermost interlayer dielectric layer ILD1. At the same time, the peripheral contact plug PPLG and the input / output contact plug IOPLG may be exposed.

[0173] refer to Figure 5 and Fig.18 , an upper portion of the data storage layer protruding from the uppermost interlayer dielectric layer ILD1 may be removed to expose a top surface of the vertical channel layer and top surfaces of the separation structures SS1 and SS2 .

[0174] An isotropic etching process may be performed on the upper portion of the data storage layer protruding from the top surface of the uppermost interlayer dielectric layer ILD1. Thus, the upper portion of the vertical channel layer may be exposed, and a data storage pattern having opposite ends opened thereat may be formed (see Figure 8 DSP).

[0175] The isotropic etching process performed on the data storage layer can use an isotropic etching process with respect to the vertical channel pattern (see Figure 8 The isotropic etching process of the data storage layer may include sequentially isotropically etching the blocking dielectric layer, the charge storage layer, and the tunneling dielectric layer.

[0176] For example, the isotropic etching process may include a first etching process for etching a portion of the blocking dielectric layer, a second etching process for etching a portion of the charge storage layer, and a third etching process for etching a portion of the tunnel dielectric layer. An etchant including hydrofluoric acid or sulfuric acid may be used in the first etching process and the third etching process, and an etchant including phosphoric acid may be used in the second etching process. Figure 8 A top surface of the DSP) may have a profile that changes according to etching recipes of the first etching process, the second etching process, and the third etching process.

[0177] refer to Fig.19 , a source conductive pattern CST may be deposited on the etch stop layer EST. The source conductive pattern CST may be conformally deposited to cover the top surface of the etch stop layer EST, the top surface of the stop pattern STP, and the vertical channel layer. The source conductive pattern CST may include at least one selected from polysilicon, a doped semiconductor (e.g., doped silicon), a metal (e.g., tungsten, copper, or aluminum), a conductive metal nitride (e.g., titanium nitride or tantalum nitride), and a transition metal (e.g., titanium or tantalum).

[0178] refer to Fig. 20 , an upper dielectric layer 310 may be formed on the source conductive patterns CST.

[0179] refer to Figure 5 and Fig.21 , the upper dielectric layer 310 may be patterned to form a contact hole CH2 exposing the source conductive pattern CST. During the formation of the contact hole CH2, a portion of the source conductive pattern CST may be etched. According to some embodiments of the inventive concept, even if the source conductive pattern CST is etched, the stop pattern STP may be disposed under the source conductive pattern CST, and thus the dielectric pattern DL may be suppressed from being additionally overetched.

[0180] refer to Figure 5 and Fig. 22, an upper via VA may be formed on the stop pattern STP. The formation of the upper via VA may include: forming a metal barrier layer covering the bottom surface and inner wall of the contact hole CH2; filling a conductive material on the metal barrier layer; and performing a planarization process to expose the top surface of the upper dielectric layer 310.

[0181] refer to Figure 5 , Figure 6B and Fig.23 , a wiring pattern PAD and an input / output pad IOPAD may be formed on the upper dielectric layer 310. The input / output pad IOPAD may be connected to the input / output contact plug IOPLG through an upper via VA penetrating the upper dielectric layer 310.

[0182] After forming the input / output pad IOPAD, a capping dielectric layer 320, a protective layer 330, and a passivation layer 340 may be sequentially formed. The capping dielectric layer 320 may include, for example, a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. The protective layer 330 may include, for example, a silicon nitride layer or a silicon oxynitride layer. The passivation layer 340 may include, for example, a polyimide-based material, such as photosensitive polyimide (PSPI). The passivation layer 340 may be formed on the protective layer 330 using a spin coating process.

[0183] The capping dielectric layer 320 , the protection layer 330 , and the passivation layer 340 may be patterned to form an opening OP exposing a portion of the input / output pad IOPAD.

[0184] FIG. 24A to FIG. 24C Illustrated are cross-sectional views showing a method of forming a separation structure in fabricating a semiconductor device according to some embodiments of the inventive concept. FIG. 25A to FIG. 25D Illustrated are cross-sectional views showing a method of forming a separation structure in fabricating a semiconductor device according to some embodiments of the inventive concept.

[0185] refer to Fig.24A , a stop layer STP' may be formed on the spacer layer SP'. The stop layer STP' may fill only a portion of the trench CH1, and the remaining portion of the trench CH1 may be in an unoccupied state. The stop layer STP' may fill a portion of the trench CH1 along the inner wall and the bottom surface of the trench CH1. For example, the trench CH1 may be filled with the stop layer STP' using a chemical vapor deposition (CVD) process. The stop layer STP' may include at least one selected from amorphous silicon, polycrystalline silicon, and metal.

[0186] refer to Fig. 24B, a portion of the stop layer STP' may be etched to form a stop pattern STP. For example, the stop layer STP' may be etched back to leave a portion of the stop layer STP' while removing the remaining portion of the stop layer STP' so that the stop pattern STP may be formed in the lower portion of the trench CH1. The stop pattern STP may have an exposed top surface STPa including a recessed portion.

[0187] refer to Fig.24C , the dielectric pattern DL may be filled on the stop pattern STP. For example, the dielectric pattern DL may be formed by forming a dielectric layer filling the trench CH1 in which the stop pattern STP is formed using chemical vapor deposition (CVD), and then performing a planarization process (e.g., CMP) on the dielectric layer to expose the first interlayer dielectric layer 120. The planarization process may remove a portion of the spacer layer SP' to form the spacer SP. The planarization process may include, for example, a chemical mechanical polishing (CMP) process or an etch-back process.

[0188] Alternatively, refer to Fig.25A , a first stop layer STP' may be formed on the spacer layer SP'. The first stop layer STP' may fill only a portion of the trench CH1, and the remaining portion of the trench CH1 may be in an unoccupied state. The first stop layer STP' may fill a portion of the trench CH1 along the inner wall and the bottom surface of the trench CH1. For example, the trench CH1 may be filled with the first stop layer STP' using a chemical vapor deposition (CVD) process. The first stop layer STP' may include at least one selected from amorphous silicon, polycrystalline silicon, and metal.

[0189] refer to Fig.25B , a second stop layer STP' may be formed on the spacer layer SP'. The formation of the second stop layer STP' may include etching a portion of the first stop layer STP' and refilling a portion of the trench CH1 with a stop pattern material. The partial etching of the first stop layer STP' may include conformally coating the first stop layer STP' on the inner wall and bottom surface of the trench CH1. The stop pattern material may include at least one selected from amorphous silicon, polycrystalline silicon, and metal.

[0190] refer to Fig.25C , the second stop layer STP" may be etched to form a stop pattern STP. For example, the second stop layer STP" may be dry-etched to leave a portion of the second stop layer STP" and remove the remaining portion of the second stop layer STP", with the result that the stop pattern STP may be formed. The stop pattern STP may have a partially protruding lateral surface STPe.

[0191] refer to Fig.25D, the dielectric pattern DL may be filled on the stop pattern STP. The dielectric pattern DL may be formed by forming a dielectric layer filling the trench CH1 in which the stop pattern STP is formed using chemical vapor deposition (CVD), and then performing a planarization process (e.g., CMP) on the dielectric layer to expose the first interlayer dielectric layer 120. The planarization process may remove a portion of the spacer layer SP' to form the spacer SP. The planarization process may include, for example, a chemical mechanical polishing (CMP) process or an etch-back process.

[0192] According to some embodiments of the inventive concept, in a semiconductor device having a structure in which a cell array structure and a peripheral circuit structure are bonded to each other, the separation structure may include a stop pattern. When a contact hole penetrating an upper dielectric layer provided on the separation structure is formed, the stop pattern may limit and / or prevent over-etching. Moreover, in addition to the stop pattern, the separation structure may include a dielectric pattern. Compared with the stop pattern, the dielectric pattern is less affected by thermal warpage, and thus the process of bonding the cell array structure and the peripheral circuit structure to each other may be satisfactorily performed.

[0193] One or more of the elements disclosed above may be included or implemented in a processing circuit system (such as hardware including logic circuits; hardware / software combinations, such as a processor running software; or combinations thereof). For example, the processing circuit system may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system-on-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0194] Although the present invention has been described in conjunction with some embodiments of the present invention shown in the drawings, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the technical principles and essential features of the present invention. It will be apparent to those skilled in the art that various substitutions, modifications and changes may be made without departing from the scope and principles of the present invention.

Claims

1. A semiconductor device, comprising: Semiconductor substrate; a peripheral circuit structure, the peripheral circuit structure comprising a plurality of peripheral circuits located on the semiconductor substrate and a plurality of first bonding pads connected to the plurality of peripheral circuits; as well as A cell array structure comprising a plurality of second bonding pads bonded to the plurality of first bonding pads, wherein: The cell array structure comprises: Stacked structure, a partition structure, wherein the partition structure penetrates the stacking structure, a plurality of vertical channel patterns, the plurality of vertical channel patterns penetrating the stacked structure, a source conductive pattern located on the stacked structure, the source conductive pattern connected to the plurality of vertical channel patterns, an upper dielectric layer, the upper dielectric layer covering the source conductive pattern, and an upper via, the upper via penetrating the upper dielectric layer, The stack structure includes a plurality of interlayer dielectric layers and a plurality of conductive patterns vertically alternately stacked, The separation structure includes a dielectric pattern and a stop pattern on the dielectric pattern, the source conductive pattern contacts a top surface of the stop pattern, and On the stop pattern, the upper via is connected to the source conductive pattern.

2. The semiconductor device according to claim 1, wherein The upper via contacts a top surface of the stop pattern.

3. The semiconductor device according to claim 1, wherein The stop pattern includes at least one of amorphous silicon, polysilicon, and metal.

4. The semiconductor device according to claim 1, wherein: The dielectric pattern includes at least one of silicon oxide, silicon nitride, and silicon oxynitride.

5. The semiconductor device according to claim 1, wherein A bottom surface of the stop pattern has a level higher than a top surface of one of the plurality of conductive patterns that is most adjacent to the source conductive pattern.

6. The semiconductor device according to claim 1, wherein The bottom surface of the stop pattern includes a recessed portion, and A top surface of the dielectric pattern contacts the recess.

7. The semiconductor device according to claim 1, wherein The stop pattern includes a first stop pattern and a second stop pattern, the first stop pattern is located on the dielectric pattern, the second stop pattern is located between the first stop pattern and the source conductive pattern, and A dielectric constant of the second stop pattern is smaller than a dielectric constant of the first stop pattern.

8. The semiconductor device according to claim 1, wherein The separation structure further includes a spacer located between the dielectric pattern and the stack structure and between the stop pattern and the stack structure.

9. The semiconductor device according to claim 1, further comprising: a data storage pattern surrounding an outer sidewall of a vertical channel pattern among the plurality of vertical channel patterns; as well as A vertical dielectric pattern is located within the vertical channel pattern.

10. The semiconductor device according to claim 9, wherein A level of a contact surface between the vertical channel pattern and the source conductive pattern is different from a level of a contact surface between the source conductive pattern and the data storage pattern.

11. The semiconductor device according to claim 1, further comprising: An etch stop layer is located between the stack structure and the source conductive pattern.

12. The semiconductor device according to claim 11, wherein Upper portions of the plurality of vertical channel patterns and an upper portion of the stop pattern protrude from the etch stop layer.

13. The semiconductor device according to claim 12, wherein: The source conductive pattern has a uniform thickness covering the etch stop layer, upper portions of the plurality of vertical channel patterns, and an upper portion of the stop pattern.

14. A semiconductor device, comprising: Semiconductor substrate; a peripheral circuit structure, the peripheral circuit structure comprising a plurality of peripheral circuits on the semiconductor substrate and a plurality of first bonding pads connected to the plurality of peripheral circuits; as well as A cell array structure comprising a plurality of second bonding pads bonded to the plurality of first bonding pads, wherein: The cell array structure comprises: A plurality of partition structures extending along a first direction; a stacking structure located between the plurality of separation structures, the stacking structure comprising a plurality of interlayer dielectric layers and a plurality of conductive patterns vertically alternately stacked; a source conductive pattern, wherein the source conductive pattern is located on the stacked structure; a plurality of vertical channel patterns, the plurality of vertical channel patterns penetrating the stack structure and connected to the source conductive pattern; a plurality of bit lines extending in a second direction intersecting the first direction while crossing the stack structure and connected to the plurality of vertical channel patterns; an upper dielectric layer, the upper dielectric layer covering the source conductive pattern; an upper via penetrating the upper dielectric layer and connected to the source conductive pattern; and a wiring pattern located on the upper dielectric layer and connected to the upper via, Each of the plurality of separation structures includes a dielectric pattern, a stop pattern, and a spacer, wherein the stop pattern is located on the dielectric pattern and adjacent to the source conductive pattern, and the spacer surrounds the dielectric pattern and at least a portion of the stop pattern, and A vertical length of the stop pattern is smaller than a vertical length of the dielectric pattern.

15. The semiconductor device according to claim 14, wherein: The stop pattern includes at least one of amorphous silicon, polysilicon, and metal.

16. The semiconductor device according to claim 14, wherein: The dielectric pattern includes at least one of silicon oxide, silicon nitride, and silicon oxynitride.

17. The semiconductor device according to claim 14, wherein: The upper via contacts a top surface of the stop pattern.

18. The semiconductor device according to claim 14, wherein: A bottom surface of the stop pattern has a level higher than a top surface of one of the plurality of conductive patterns that is most adjacent to the source conductive pattern.

19. The semiconductor device according to claim 14, wherein: The stop pattern includes a first stop pattern and a second stop pattern, The first stop pattern is located on the dielectric pattern, The second stop pattern is located between the first stop pattern and the source conductive pattern. A dielectric constant of the second stop pattern is smaller than a dielectric constant of the first stop pattern.

20. An electronic system, comprising: A semiconductor device, comprising a peripheral circuit structure and a cell array structure located on the peripheral circuit structure; as well as A controller electrically connected to the semiconductor device through an input / output pad, the controller being configured to control the semiconductor device, wherein The peripheral circuit structure includes: a plurality of peripheral circuits, the plurality of peripheral circuits are integrated on a semiconductor substrate; and a plurality of first bonding pads, the plurality of first bonding pads are connected to the plurality of peripheral circuits, The cell array structure includes a plurality of second bonding pads bonded to the plurality of first bonding pads, The cell array structure comprises: Stacked structure; a partition structure, wherein the partition structure penetrates the stacking structure; a plurality of vertical channel patterns, wherein the plurality of vertical channel patterns penetrate the stack structure; a source conductive pattern located on the stacked structure, the source conductive pattern being connected to the plurality of vertical channel patterns; an upper dielectric layer, the upper dielectric layer covering the source conductive pattern; and an upper via, the upper via penetrating the upper dielectric layer, The stack structure includes a plurality of interlayer dielectric layers and a plurality of conductive patterns vertically alternately stacked, The separation structure includes a dielectric pattern and a stop pattern on the dielectric pattern, the source conductive pattern contacts a top surface of the stop pattern, and On the stop pattern, the upper via is connected to the source conductive pattern.

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