Semiconductor package

Abstract

A semiconductor package includes: a plurality of first semiconductor chips sequentially stacked in a vertical direction and connected to each other via a plurality of first through electrodes, each of the plurality of first semiconductor chips having a first width in a horizontal direction; a second semiconductor chip under the plurality of first semiconductor chips and connected to the plurality of first semiconductor chips via a plurality of second through electrodes, the second semiconductor chip having a second width in the horizontal direction, the second width being greater than the first width; a redistribution layer under the second semiconductor chip, the redistribution layer having a third width in the horizontal direction, the third width being substantially equal to the second width; and a plurality of first connection bumps located between the second semiconductor chip and the redistribution layer.

Description

Technical Field

[0001] Example embodiments of the present disclosure relate generally to semiconductor integrated circuits, and more particularly to semiconductor packages including stacked semiconductor chips or dies and methods of manufacturing the semiconductor packages. Background Art

[0002] Semiconductor packages are becoming more compact, and at the same time, performance such as capacity and speed are increasing. In semiconductor systems, when relatively high bandwidth is required, high bandwidth memory (HBM) devices can be used. Conventional HBM devices can be implemented using microbumps (uBumps) with small size and pitch, and relatively expensive silicon interposers are used to mount conventional HBM devices. Therefore, there may be a problem of increased manufacturing costs for the entire system.

[0003] The information disclosed in the background technology section has been known or obtained by the inventor before or during the process of implementing the embodiments of the present application, or is technical information obtained in the process of implementing the embodiments. Therefore, it may contain information that does not constitute prior art known to the public. Summary of the invention

[0004] One or more example embodiments provide a semiconductor package that can effectively reduce system manufacturing costs.

[0005] One or more example embodiments also provide a method of manufacturing a semiconductor package.

[0006] Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments.

[0007] According to one aspect of example embodiments, a semiconductor package includes: a plurality of first semiconductor chips, the plurality of first semiconductor chips are sequentially stacked in a vertical direction, at least one of the plurality of first semiconductor chips includes a plurality of first through-electrodes connecting the plurality of first semiconductor chips to each other, each of the plurality of first semiconductor chips having a first width in a horizontal direction; a second semiconductor chip, the second semiconductor chip is located below the plurality of first semiconductor chips, the second semiconductor chip includes a plurality of second through-electrodes connecting the second semiconductor chip to the plurality of first semiconductor chips, the second semiconductor chip having a second width in a horizontal direction greater than the first width; a redistribution layer, the redistribution layer is located below the second semiconductor chip, the redistribution layer has a third width in a horizontal direction substantially equal to the second width; a plurality of first connection bumps, the plurality of first connection bumps are located between the second semiconductor chip and the redistribution layer and connect the second semiconductor chip to the redistribution layer, each of the plurality of first connection bumps having a first size; and a plurality of second connection bumps, the plurality of second connection bumps are located below the redistribution layer and connect the redistribution layer to an external device, each of the plurality of second connection bumps having a second size greater than the first size.

[0008] According to one aspect of an example embodiment, a semiconductor package includes: a first semiconductor device; a plurality of second semiconductor devices, wherein the first semiconductor device is configured to control the plurality of second semiconductor devices; and a connection substrate, the first semiconductor device and the plurality of second semiconductor devices being disposed on the connection substrate, wherein each of the plurality of second semiconductor devices includes: a plurality of first semiconductor chips sequentially stacked in a vertical direction, at least one of the plurality of first semiconductor chips including a plurality of first through electrodes connecting the plurality of first semiconductor chips to each other, each of the plurality of first semiconductor chips having a first width in a horizontal direction; a second semiconductor chip, the second semiconductor chip being located below the plurality of first semiconductor chips, the second semiconductor chip being disposed below the plurality of first semiconductor chips, The conductor chip includes a plurality of second through-electrodes connecting the second semiconductor chip to the plurality of first semiconductor chips, the second semiconductor chip having a second width greater than the first width in the horizontal direction; a redistribution layer, the redistribution layer being located below the second semiconductor chip, the redistribution layer having a third width substantially equal to the second width in the horizontal direction; a plurality of first connection bumps, the plurality of first connection bumps being located between the second semiconductor chip and the redistribution layer and connecting the second semiconductor chip to the redistribution layer, each of the plurality of first connection bumps having a first size; and a plurality of second connection bumps, the plurality of second connection bumps being located below the redistribution layer and connecting the redistribution layer to an external device, each of the plurality of second connection bumps having a second size greater than the first size.

[0009] According to one aspect of example embodiments, a method for manufacturing a semiconductor package includes: making a plurality of first semiconductor chips and a second semiconductor chip, each of the plurality of first semiconductor chips having a first width in a horizontal direction, and the second semiconductor chip having a second width greater than the first width in the horizontal direction; sequentially stacking the plurality of first semiconductor chips and the second semiconductor chips in a vertical direction, at least one of the plurality of first semiconductor chips including a plurality of first through electrodes connecting the plurality of first semiconductor chips to each other, and the second semiconductor chip including a plurality of second through electrodes connecting the second semiconductor chip to the plurality of first semiconductor chips; forming a plurality of first connection bumps under the second semiconductor chip, each of the plurality of first connection bumps having a first size; forming a redistribution layer under the second semiconductor chip, the redistribution layer having a third width substantially equal to the second width in a horizontal direction; and forming a plurality of second connection bumps under the redistribution layer, each of the plurality of second connection bumps having a second size greater than the first size, wherein the plurality of first connection bumps and the plurality of second connection bumps are connected via the redistribution layer, wherein the second semiconductor chip and the redistribution layer are connected via the plurality of first connection bumps, and wherein the semiconductor package is connected to an external device via the plurality of second connection bumps.

[0010] According to one aspect of an example embodiment, a semiconductor package includes: a first dynamic random access memory (DRAM) chip, the first dynamic random access memory (DRAM) chip having a first width in a horizontal direction; a plurality of second DRAM chips, the plurality of second DRAM chips being sequentially stacked in a vertical direction below the first DRAM chip, at least one of the plurality of second DRAM chips including a plurality of first through electrodes connecting the plurality of second DRAM chips to each other and to the first DRAM chip, each of the plurality of second DRAM chips having a second width in a horizontal direction substantially equal to the first width; a buffer chip, the buffer chip being located below the plurality of second DRAM chips, the buffer chip including a plurality of second through electrodes connected to the first DRAM chip and the plurality of second DRAM chips, the buffer chip having a third width in a horizontal direction greater than the first width; a redistribution layer, the redistribution layer being located below the buffer chip, the redistribution layer having a fourth width in a horizontal direction substantially equal to the third width; a plurality of first connection bumps, the plurality of first connection bumps being located between the buffer chip and the redistribution layer and connected to the plurality of A second through-electrode and a redistribution layer, each of the plurality of first connection bumps has a first size; a plurality of second connection bumps, the plurality of second connection bumps are located below the redistribution layer and connected to the redistribution layer, each of the plurality of second connection bumps has a second size greater than the first size; and an encapsulant, the encapsulant encapsulates the first DRAM chip, the plurality of second DRAM chips and the buffer chip, the encapsulant covers the side surface of the first DRAM chip, the side surface of the plurality of second DRAM chips, and at least a portion of the upper surface of the buffer chip, wherein the number of the plurality of second connection bumps is less than the number of the plurality of first connection bumps, wherein a first number of first connection bumps among the plurality of first connection bumps are respectively connected to a second number of second connection bumps among the plurality of second connection bumps via the redistribution layer, wherein the first DRAM chip, the plurality of second DRAM chips and the buffer chip are electrically connected to an external device via the first number of first connection bumps, the redistribution layer and the second number of second connection bumps, and wherein a third number of first connection bumps among the plurality of first connection bumps are floated without being connected to the redistribution layer, the plurality of second connection bumps and the external device. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects, features and advantages of certain example embodiments of the present disclosure will be more readily understood from the following description in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a cross-sectional view illustrating a semiconductor package according to one or more example embodiments;

[0013] Figure 2A , Figure 2B , Figure 2C and Figure 3 is a diagram illustrating a semiconductor package according to one or more example embodiments;

[0014] Figure 4A , Figure 4B , Figure 4C , Figure 4D and Figure 4E is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to one or more example embodiments;

[0015] Figure 5 , Figure 6 and Figure 7 is a cross-sectional view illustrating a semiconductor package according to one or more example embodiments;

[0016] Figure 8 is a perspective view showing a semiconductor package according to one or more example embodiments;

[0017] Fig. 9 is a block diagram illustrating a semiconductor system according to one or more example embodiments;

[0018] Fig.10 is a block diagram illustrating an example of a memory chip included in a semiconductor system according to one or more example embodiments; and

[0019] Fig.11 is a block diagram illustrating an electronic system according to one or more example embodiments. DETAILED DESCRIPTION

[0020] Hereinafter, an exemplary embodiment of the present disclosure will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the accompanying drawings, and their redundant descriptions will be omitted. The embodiments described herein are exemplary embodiments, and therefore, the present disclosure is not limited thereto and may be implemented in various other forms.

[0021] As used herein, expressions such as "at least one of" when preceding a list of elements modify the entire list of elements and do not modify the individual elements of the list. For example, the expression "at least one of a, b, and c" should be understood to include: only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0022] It should be understood that when an element or layer is referred to as being "on," "above," "on," "below," "below," "connected to," or "coupled to" another element or layer, it can be directly on, above, on, below, below, below, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being directly "on," "above," "directly on," "below," "below," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers.

[0023] Figure 1 is a cross-sectional view illustrating a semiconductor package according to one or more example embodiments.

[0024] exist Figure 1 In the figure, two directions substantially parallel to the first surface (e.g., top surface) of the substrate (e.g., semiconductor substrate or packaging substrate) and intersecting each other are referred to as the first direction X (e.g., the first horizontal direction) and the second direction Y (e.g., the second horizontal direction). In addition, the direction substantially perpendicular to the first surface of the substrate is referred to as the third direction Z (e.g., the vertical direction). For example, the first direction X and the second direction Y may be substantially perpendicular to each other. For example, the third direction Z may be substantially perpendicular to both the first direction X and the second direction Y. Further, the direction indicated by the arrow in the figure and the opposite direction thereof are considered to be the same direction. The definitions of the first direction X, the second direction Y, and the third direction Z are the same in the subsequent figures.

[0025] refer to Figure 1 , the semiconductor package 10 may include a plurality of first semiconductor chips 100, 200 and 300, a second semiconductor chip 400, a plurality of first connection bumps 500, a redistribution layer 600, and a plurality of second connection bumps 700. The semiconductor package 10 may also include a plurality of connection structures 150, 250, 350 and 450, a plurality of insulating layers 160, 260, 360, 460 and 560, and an encapsulant 800. The semiconductor chip may be referred to as a semiconductor die, the connection bump may be referred to as a conductive bump, a solder bump, a solder ball or an electrical connection structure, and the encapsulant may be referred to as a sealing member.

[0026] The plurality of first semiconductor chips 100, 200, and 300 may be sequentially stacked in a vertical direction (eg, in a third direction Z) and may be electrically connected to each other via a plurality of first through electrodes 210 and 310. For ease of explanation, Figure 11 and 2 , three first semiconductor chips 100 , 200 , and 300 are shown, however, the number of the first semiconductor chips 100 , 200 , and 300 is not limited thereto. For example, the semiconductor package 10 may include two first semiconductor chips or four or more first semiconductor chips stacked in a vertical direction.

[0027] In some example embodiments, at least some of the plurality of first semiconductor chips 100, 200, and 300 may include a plurality of first through electrodes 210 and 310. For example, the first semiconductor chip 200 may include the first through electrodes 210, and the first semiconductor chip 300 may include the first through electrodes 310. For example, the first semiconductor chip 100, which is the uppermost first semiconductor chip among the plurality of first semiconductor chips 100, 200, and 300, may not include a through electrode. The first semiconductor chips 100 and 200 may be electrically connected via the first through electrodes 210, and the first semiconductor chips 200 and 300 may be electrically connected via the first through electrodes 310.

[0028] The second semiconductor chip 400 may be disposed or arranged below the plurality of first semiconductor chips 100, 200, and 300, and may be electrically connected to the plurality of first semiconductor chips 100, 200, and 300 via the plurality of second through electrodes 410. For example, the second semiconductor chip 400 may include the plurality of second through electrodes 410. For ease of explanation, Figure 1 One second semiconductor chip 400 is shown in FIG. 1 , however, the number of the second semiconductor chips 400 is not limited thereto. For example, the semiconductor package 10 may include two or more second semiconductor chips stacked in a vertical direction.

[0029] In some example embodiments, each of the plurality of first semiconductor chips 100, 200, and 300 may include a first semiconductor layer, and the second semiconductor chip 400 may include a second semiconductor layer. The plurality of first through electrodes 210 and 310 may penetrate the first semiconductor layer in a vertical direction (e.g., in a third direction Z), and the plurality of second through electrodes 410 may penetrate the second semiconductor layer in a vertical direction (e.g., in a third direction Z). For example, the first through electrode 210 may be formed to penetrate the first semiconductor layer included in the first semiconductor chip 200, and the first through electrode 310 may be formed to penetrate the first semiconductor layer included in the first semiconductor chip 300. For example, the plurality of first through electrodes 210 and 310 and the second through electrode 410 may be through silicon vias (TSVs) formed by penetrating a silicon substrate.

[0030] The redistribution layer 600 may be disposed or arranged below the second semiconductor chip 400. For example, the redistribution layer 600 may include a plurality of vias 640, a plurality of wirings 650, and a plurality of insulating layers 660. The plurality of vias 640 and the plurality of wirings 650 may be used to redistribute or rewire pads of the first semiconductor chips 100, 200, and 300 and the second semiconductor chip 400, or for electrical connection with the connection bumps 500 and 700. The plurality of insulating layers 660 may electrically insulate at least some of the plurality of wirings 650.

[0031] The plurality of first connection bumps 500 may be formed or disposed between the second semiconductor chip 400 and the redistribution layer 600, and may electrically connect the second semiconductor chip 400 with the redistribution layer 600. For example, the plurality of first connection bumps 500 may be or may include micro bumps.

[0032] A plurality of second connection bumps 700 may be formed or disposed under the redistribution layer 600, and may electrically connect the redistribution layer 600 to an external device (e.g., another semiconductor package and / or another semiconductor device located outside the semiconductor package 10). For example, the plurality of second connection bumps 700 may be or may include bumps having a size greater than that of the microbumps, which will be referred to in detail in the following description. Figure 2B Give a description.

[0033] The plurality of first connection bumps 500 and the plurality of second connection bumps 700 may be electrically connected to each other through the redistribution layer 600. The first semiconductor chips 100, 200, 300, the second semiconductor chip 400, and the redistribution layer 600 may be electrically connected to each other through the plurality of first connection bumps 500. The semiconductor package 10 (e.g., the first semiconductor chips 100, 200, 300, the second semiconductor chip 400, and the redistribution layer 600) may be electrically connected to an external device through the plurality of second connection bumps 700.

[0034] In some example embodiments, the number of the plurality of second connection bumps 700 may be equal to the number of the plurality of first connection bumps 500. For example, the plurality of first connection bumps 500 may be electrically connected to the plurality of second connection bumps 700, respectively, via the redistribution layer 600. For ease of explanation, Figure 1 8. Eight first connection bumps 500 and eight second connection bumps 700 are shown in FIG. 1, however, the number of the first connection bumps 500 and the number of the second connection bumps 700 are not limited thereto.

[0035] The connection structure 150 may be electrically connected to the first through-electrode 210 so that the first semiconductor chips 100 and 200 are electrically connected to each other through the connection structure 150, and the insulating layer 160 may electrically insulate the connection structure 150. The connection structure 250 may be electrically connected to the first through-electrodes 210 and 310 so that the first semiconductor chips 200 and 300 are electrically connected to each other through the connection structure 250, and the insulating layer 260 may electrically insulate the connection structure 250. The connection structure 350 may be electrically connected to the first through-electrode 310 and the second through-electrode 410 so that the first semiconductor chip 300 and the second semiconductor chip 400 are electrically connected to each other through the connection structure 350, and the insulating layer 360 may electrically insulate the connection structure 350. The connection structure 450 may be electrically connected to the second through-electrode 410 and the first connection bump 500 so that the second semiconductor chip 400 and the first connection bump 500 are electrically connected to each other through the connection structure 450, and the insulating layer 460 may electrically insulate the connection structure 450. The insulating layer 560 may electrically insulate the first connecting bump 500 .

[0036] In some example embodiments, when a plurality of first connection bumps 500 are formed between the second semiconductor chip 400 and the redistribution layer 600, the second semiconductor chip 400 and the redistribution layer 600 may be spaced apart from each other in a vertical direction (e.g., in a third direction Z). In other words, the lower surface of the second semiconductor chip 400 (e.g., the connection structure 450 and the insulating layer 460) and the upper surface of the redistribution layer 600 may be spaced apart from each other by a certain distance. An air layer may be formed between the second semiconductor chip 400 and the redistribution layer 600 instead of the insulating layer 560 that electrically insulates the first connection bumps 500.

[0037] The encapsulant 800 may encapsulate or seal the plurality of first semiconductor chips 100, 200, and 300 and the second semiconductor chip 400. For example, the encapsulant 800 may be formed to expose the upper surface of the first semiconductor chip 100, which is the uppermost first semiconductor chip among the plurality of first semiconductor chips 100, 200, and 300. For example, the encapsulant 800 may directly contact the side surfaces of the plurality of first semiconductor chips 100, 200, and 300 and directly contact at least a portion of the upper surface of the second semiconductor chip 400. For example, the upper surface of the semiconductor package 10 may be formed by the upper surface of the encapsulant 800 and the upper surface of the first semiconductor chip 100. However, example embodiments are not limited thereto.

[0038] In some example embodiments, the plurality of first semiconductor chips 100, 200, and 300 and the second semiconductor chip 400 may be semiconductor chips of different types. Figure 8 , Fig. 9 and Fig.10As described, the plurality of first semiconductor chips 100, 200, and 300 may be or may include memory chips storing data (e.g., dynamic random access memory (DRAM) chips), the second semiconductor chip 400 may be a buffer chip controlling the operation of the memory chips, and the semiconductor package 10 may be a high bandwidth memory (HBM) device. However, example embodiments are not limited thereto.

[0039] Although the upper portion (or top portion), the lower portion (or bottom portion), the upper surface (or top surface), the lower surface (or bottom surface), etc. are based on Figure 1 The structure of the semiconductor package 10 shown in FIG. 1 is described, but example embodiments are not limited thereto. For example, when the semiconductor package 10 is turned over during a manufacturing process, the upper and lower portions described above may be reversed, and the upper and lower surfaces described above may be reversed.

[0040] Figure 2A , Figure 2B , Figure 2C and Figure 3 FIG. 1 is a diagram showing a semiconductor package according to one or more example embodiments. Figure 1 Descriptions of duplicate or overlapping descriptions.

[0041] refer to Figure 2A , each of the plurality of first semiconductor chips 100, 200, and 300 may have a first width W1 in a horizontal direction (e.g., in the first direction X), the second semiconductor chip 400 may have a second width W2 greater than the first width W1 in the horizontal direction (e.g., in the first direction X), and the redistribution layer 600 may have a second width W2 in the horizontal direction (e.g., in the first direction X). In other words, the second semiconductor chip 400 and the redistribution layer 600 may have the same width in the horizontal direction, and the plurality of first semiconductor chips 100, 200, and 300 may have a width smaller than that of the second semiconductor chip 400 and the redistribution layer 600 in the horizontal direction.

[0042] The size of the semiconductor package 10 may be determined as a second width W2, which represents the size of the second semiconductor chip 400 and the redistribution layer 600. In this example, even if the redistribution layer 600 is additionally formed or provided, the size of the semiconductor package 10 may not increase and may be maintained.

[0043] although Figure 2AAn example in which the horizontal direction is the first direction X is shown, but example embodiments are not limited thereto. For example, each of the plurality of first semiconductor chips 100, 200, and 300 may have a first length in the second direction Y, and each of the second semiconductor chip 400 and the redistribution layer 600 may have a second length greater than the first length in the second direction Y. In this example, the size of the semiconductor package 10 may be determined as the second length, which represents the size of the second semiconductor chip 400 and the redistribution layer 600.

[0044] refer to Figure 2B , each of the plurality of first connection bumps 500 may have a first size S1, and each of the plurality of second connection bumps 700 may have a second size S2 that is larger than the first size S1. In other words, the size of the plurality of first connection bumps 500 may be smaller than the plurality of second connection bumps 700. For example, the first size S1 may be the diameter of each of the plurality of first connection bumps 500, and the second size S2 may be the diameter of each of the plurality of second connection bumps 700. Although the first size S1 and the second size S2 are Figure 2B , but the dimensions S1 and S2 are not limited thereto, and the first dimension S1 and the second dimension S2 may refer to the width of the bump, the height of the bump, the area of ​​the bump, and other parameters that will indicate the size difference. For example, each of the first dimension S1 and the second dimension S2 may be expressed as a radius, an area, etc.

[0045] In some example embodiments, the first size S1 may be greater than about 1 μm and less than or equal to about 25 μm. In some example embodiments, the second size S2 may be greater than about 25 μm.

[0046] refer to Figure 2C , the distance between two adjacent connection bumps in the plurality of first connection bumps 500 may be a first distance D1, and the distance between two adjacent connection bumps in the plurality of second connection bumps 700 may be a second distance D2, the second distance D2 being longer than the first distance D1. In other words, the distance between adjacent first connection bumps 500 may be smaller than the distance between adjacent second connection bumps 700. For example, the first distance D1 may be the distance between the centers of two adjacent connection bumps in the first connection bumps 500, and the second distance D2 may be the distance between the centers of two adjacent connection bumps in the second connection bumps 700, but other reference points between adjacent connection bumps may be used to indicate the difference in distance. Each of the first distance D1 and the second distance D2 may be referred to as a pitch.

[0047] In some example embodiments, the first distance D1 may be greater than about 1 μm and less than or equal to about 55 μm. In some example embodiments, the second distance D2 may be greater than about 55 μm.

[0048] As reference Figure 2B and Figure 2C As described, when the second connecting bumps 700 having a larger size than the first connecting bumps 500 and a larger distance between adjacent bumps than the first connecting bumps 500 are used, electrical connection between the semiconductor package 10 and an external device may be relatively easily achieved.

[0049] refer to Figure 3 , in a top view or on a plane, a plurality of first connecting bumps 500 may be arranged adjacent to a center C of the semiconductor package 10, and a plurality of second connecting bumps 700 may be regularly or uniformly arranged in an entire region (eg, the second region ER) of the semiconductor package 10.

[0050] For example, the plurality of first connection bumps 500 may be disposed in the first region CR where the plurality of first semiconductor chips 100, 200, and 300 are formed. For example, the plurality of first connection bumps 500 may be arranged in a relatively narrow first range in the first direction X and in a relatively wide second range in the second direction Y. Figure 3 As shown, in some embodiments, in the first region CR, the plurality of first connection bumps 500 may be arranged such that a greater number of connection bumps extend along the vertical direction (Y direction) and a smaller number of connection bumps extend along the horizontal direction (X direction). Figure 3 As shown, the plurality of first connection bumps 500 may be arranged in two columns and eight rows. However, example embodiments are not limited thereto, and the arrangement of the plurality of first connection bumps 500 in the first region may be determined differently according to example embodiments. Alternatively, some of the plurality of first connection bumps 500 may be disposed in a region other than the first region CR (e.g., a region ER surrounding the first region).

[0051] For example, a plurality of second connection bumps 700 may be disposed in the second region ER where the second semiconductor chip 400 and the redistribution layer 600 are formed. For example, in a top view or on a plane, the first region CR may be included in the second region ER. For example, a plurality of second connection bumps 700 may be uniformly disposed at regular distances in the first direction X and the second direction Y. That is, in a top view, a plurality of second connection bumps 700 may be arranged around the second region ER and spaced apart at equal or substantially equal distances both vertically and horizontally. When a plurality of second connection bumps 700 are regularly or uniformly arranged, the semiconductor package 10 and an external device may be stably electrically connected without deviation or bias.

[0052] The semiconductor package according to the example embodiment may include a redistribution layer 600 for redistributing a plurality of first connection bumps 500, and may include a plurality of second connection bumps 700 formed below the redistribution layer 600. The second semiconductor chip 400 and the redistribution layer 600 may have the same or substantially the same width in the horizontal direction, and thus the occupied area of ​​the semiconductor package 10 may not increase and may be maintained. In addition, each second connection bump 700 may have a second size S2 larger than each first connection bump 500, and the distance between two adjacent second connection bumps 700 may be greater than the distance between two adjacent first connection bumps 500. Therefore, the electrical connection between the semiconductor package 10 and the external device may be relatively easy to achieve. Therefore, the semiconductor package 10 may be mounted on a relatively low-priced interposer or package substrate, and the manufacturing cost of the system including the semiconductor package 10 may be effectively reduced.

[0053] Figure 4A , Figure 4B , Figure 4C , Figure 4D and Figure 4E is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to one or more example embodiments.

[0054] refer to Figure 4A , the second semiconductor chip 400 including a plurality of second through electrodes 410 formed by penetrating the second semiconductor chip 400 may be fabricated or manufactured, and the carrier 50 may be attached to a lower portion of the second semiconductor chip 400 .

[0055] In some example embodiments, the second semiconductor chip 400 may include a semiconductor element such as silicon or germanium (Ge), and / or may include a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). For example, the second semiconductor chip 400 may have a silicon-on-insulator (SOI) structure. For example, the second semiconductor chip 400 may include a conductive region (e.g., a well doped with impurities or a structure doped with impurities). For example, the second semiconductor chip 400 may include various element isolation structures such as a shallow trench isolation (STI) structure.

[0056] In some example embodiments, the second semiconductor chip 400 may include various types of active elements and / or passive elements. For example, the second semiconductor chip 400 may include a field effect transistor (FET) such as a planar FET or a FinFET, and may include logic elements such as AND, OR, or NOT, a system large scale integration (LSI), a complementary metal oxide semiconductor (CMOS) imaging sensor (CIS), a micro-electromechanical system (MEMS), etc.

[0057] In some example embodiments, the second semiconductor chip 400 may include an interlayer insulating layer and a multilayer wiring layer located on the above-mentioned elements. For example, the interlayer insulating layer may include silicon oxide or silicon nitride. For example, the multilayer wiring layer may include multilayer wiring and / or vertical contact. For example, the multilayer wiring layer may connect the elements of the second semiconductor chip 400 to each other, may connect the elements to the conductive region of the second semiconductor chip 400, and / or may connect the elements to the second through electrode 410 and / or the pad.

[0058] In some example embodiments, a plurality of through vias penetrating the second semiconductor chip 400 may be formed, and a plurality of second through electrodes 410 may be formed in the plurality of through vias. For example, a plurality of through vias may be formed using a mechanical drill, a laser drill, or the like. For example, the plurality of second through electrodes 410 may be formed by a plating process. For example, the plating process may be a subtractive process, an additive process, a semi-additive process (SAP), a modified semi-additive process (MSAP), or the like.

[0059] In some example embodiments, the material of the plurality of second through electrodes 410 may be a conductive material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, each of the plurality of second through electrodes 410 may be completely filled with a conductive material, or a conductive material may be formed along a wall of a corresponding through via in the plurality of through vias. In addition, each of the plurality of second through electrodes 410 may have any known shape, such as an hourglass shape, a cylindrical shape, and the like.

[0060] In some example embodiments, each of the plurality of second through electrodes 410 may include a conductive plug and a barrier layer surrounding the conductive plug. For example, the conductive plug may include a metal material, such as tungsten (W), titanium (Ti), aluminum (Al) and / or copper (Cu). For example, the conductive plug may be formed by a plating process, a physical vapor deposition (PVD) process, or a chemical vapor deposition (CVD) process. For example, the barrier layer may include an insulating barrier layer and / or a conductive barrier layer. For example, the insulating barrier layer may be formed by an oxide film, a nitride film, a carbide film, a polymer, and / or a combination thereof. For example, a conductive barrier layer may be disposed between the insulating barrier layer and the conductive plug. For example, the conductive barrier layer may include, for example, a metal compound, such as tungsten nitride (WN), titanium nitride (TiN), and / or tantalum nitride (TaN). For example, the barrier layer may be formed by a PVD process or a CVD process.

[0061] In some example embodiments, the carrier 50 may include a support substrate and an adhesive material for attaching the second semiconductor chip 400 to the support substrate.

[0062] In some example embodiments, the second semiconductor chip 400 may be fabricated first, and then the carrier 50 may be attached to the second semiconductor chip 400. However, example embodiments are not limited thereto.

[0063] refer to Figure 4B , a plurality of first semiconductor chips 100 , 200 , and 300 including a plurality of first through electrodes 210 and 310 formed by penetrating the first semiconductor layer may be fabricated or manufactured, and the plurality of first semiconductor chips 100 , 200 , and 300 may be stacked on the second semiconductor chip 400 .

[0064] The first semiconductor chips 100, 200 and 300 and the plurality of first through electrodes 210 and 310 may have characteristics substantially the same as or similar to those of the second semiconductor chip 400 and the plurality of second through electrodes 410, respectively, and thus redundant descriptions thereof may be omitted. For example, the first semiconductor chips 100, 200 and 300 may include memory elements such as DRAM, static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), phase change random access memory (PRAM), resistive random access memory (RRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), etc.

[0065] In some example embodiments, the connection structures 150, 250, and 350 may be formed by a reflow process or the like, and then the plurality of first semiconductor chips 100, 200, and 300 and the second semiconductor chip 400 may be electrically connected to each other via the connection structures 150, 250, and 350. For example, the connection structures 150, 250, and 350 may include tin (Sn) or an alloy containing tin (e.g., Sn-Ag-Cu). For example, the connection structures 150, 250, and 350 may be micro bumps that are smaller than the first connection bumps 500.

[0066] In some example embodiments, a plurality of first semiconductor chips 100, 200 and 300 and a second semiconductor chip 400 may be stacked using a bonding scheme. For example, a pad may be formed on the lower surface of the first semiconductor chip 100 and the upper surface of the first semiconductor chip 200, and then the first semiconductor chips 100 and 200 may be stacked by electrically or physically connecting the pads to each other. For example, the pad may be formed of copper (Cu), and the bonding scheme may be a Cu-Cu bonding scheme. In addition, the first semiconductor chips 200 and 300 may be stacked in the same manner, and the first semiconductor chip 300 and the second semiconductor chip 400 may be stacked in the same manner.

[0067] In some example embodiments, the insulating layers 160, 260, and 360 may include an insulating material, such as silicon oxide. In some example embodiments, the insulating layers 160, 260, and 360 may also include an adhesive material, such as an epoxy resin material. For example, an adhesive material may be filled between the plurality of first semiconductor chips 100, 200, and 300 and the second semiconductor chip 400 to strengthen the gap between the plurality of first semiconductor chips 100, 200, and 300 and the second semiconductor chip 400.

[0068] In some example embodiments, the plurality of first semiconductor chips 100, 200, and 300 may be sequentially stacked first, and then the plurality of first semiconductor chips 100, 200, and 300 may be stacked on the second semiconductor chip 400. In other example embodiments, the plurality of first semiconductor chips 100, 200, and 300 may be sequentially stacked on the second semiconductor chip 400. However, example embodiments are not limited thereto.

[0069] refer to Figure 4C , an encapsulant 800 may be formed to encapsulate the plurality of first semiconductor chips 100, 200, and 300 and the second semiconductor chip 400. The encapsulant 800 may encapsulate or protect the plurality of first semiconductor chips 100, 200, and 300 and the second semiconductor chip 400, and may provide an insulating region.

[0070] In some example embodiments, the encapsulant 800 may include an insulating material. For example, the insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a thermosetting resin or a thermoplastic resin impregnated with an inorganic filler in a core material such as glass fiber (or glass cloth or glass fabric). For example, the insulating material may be a prepreg, Ajinomoto Build up Film (ABF), FR-4, Bismaleimide Triazine (BT), etc. Alternatively, the material of the encapsulant 800 is not particularly limited, but may be, for example, a photoimageable encapsulant (PIE).

[0071] In some example embodiments, the encapsulation form of the encapsulant 800 is not particularly limited. Figure 4C As shown, the encapsulant 800 may cover the side surfaces of the first semiconductor chips 100, 200, and 300, and at least a portion of the upper surface of the second semiconductor chip 400. For example, the encapsulant 800 may be formed to expose the upper surface of the first semiconductor chip 100, which is the uppermost first semiconductor chip among the plurality of first semiconductor chips 100, 200, and 300. For example, through a planarization process, the upper surface of the encapsulant 800 may be substantially coplanar with the upper surface of the first semiconductor chip 100. For example, the planarization process may be performed through a chemical mechanical polishing (CMP) process.

[0072] refer to Figure 4D , the carrier 50 may be removed, and a plurality of first connection bumps 500 may be formed under the second semiconductor chip 400 .

[0073] The connection structure 450 and the insulating layer 460 between the second semiconductor chip 400 and the plurality of first connection bumps 500 may have characteristics substantially the same as or similar to those of the connection structures 150 , 250 and 350 and the insulating layers 160 , 260 and 360 , respectively, and thus redundant descriptions thereof may be omitted.

[0074] In some example embodiments, the plurality of first connection bumps 500 may be formed of a conductive material, such as solder, etc. However, example embodiments are not limited thereto, and the material of each of the plurality of first connection bumps 500 may be changed. For example, the plurality of first connection bumps 500 may be pads, balls, pins, etc. For example, the plurality of first connection bumps 500 may be formed as a multilayer or single-layer structure. In an example in which the first connection bump 500 is formed as a multilayer structure, the first connection bump 500 may include a copper (Cu) column and solder. In an example in which the first connection bump 500 is formed as a single-layer structure, the first connection bump 500 may include tin-silver solder, copper (Cu), etc. However, this is only an example, and the first connection bump 500 is not limited thereto. For example, the number, spacing, arrangement form, etc. of the plurality of first connection bumps 500 are not particularly limited, but may be fully modified according to the design details of those skilled in the art.

[0075] refer to Figure 4E , a redistribution layer 600 may be formed under the second semiconductor chip 400 and the plurality of first connection bumps 500 .

[0076] The insulating layer 560 between the second semiconductor chip 400 and the redistribution layer 600 may have characteristics substantially the same as or similar to those of the insulating layers 160 , 260 , 360 , and 460 , and thus a redundant description thereof may be omitted.

[0077] In some example embodiments, the uppermost insulating layer among the plurality of insulating layers 660 in the redistribution layer 600 may be formed by a lamination process or any known application process. Vias may then be formed in the uppermost insulating layer by a photolithography process. For example, some vias 640 and some wirings 650 may then be formed in or on the uppermost insulating layer by a plating process. In a similar manner, the remaining insulating layers 660, the remaining vias 640, and the remaining wirings 650 may then be sequentially formed.

[0078] In some example embodiments, the plurality of insulating layers 660 may include an insulating material. For example, the insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a thermosetting resin or a thermoplastic resin impregnated with an inorganic filler in a core material such as glass fiber. For example, the insulating material may be prepreg, ABF, FR-4, BT, etc.

[0079] In some example embodiments, at least a portion of the plurality of insulating layers 660 may include a photosensitive insulating material, such as a photoimageable dielectric (PID) resin. For example, at least a portion of the plurality of insulating layers 660 may be a photosensitive insulating layer. In an example where the insulating layer 660 has a photosensitive property, the insulating layer 660 may be formed to have a smaller thickness, and a fine pitch of the via 640 may be more easily achieved. For example, the insulating layer 660 may be a photosensitive insulating layer including an insulating resin and an inorganic filler. In an example where the insulating layer 660 is multilayered, the materials of the insulating layers 660 may be the same as each other or may also be different from each other. In an example where the insulating layer 660 is multilayered, the insulating layers 660 may be integrated with each other according to the process so that the boundaries between them may also be unclear.

[0080] In some example embodiments, the lowest insulating layer among the plurality of insulating layers 660 may be a passivation layer. The passivation layer may protect the semiconductor package 10 from external physical damage and / or chemical damage. For example, the passivation layer may include an insulating resin and an inorganic filler, but may not include glass fiber. For example, the passivation layer may be formed by ABF. However, example embodiments of the passivation layer are not limited thereto. For example, the passivation layer may also be formed by PID, solder resist, etc. For example, the passivation layer may be formed by any known lamination process, hardening process, etc.

[0081] In some example embodiments, the plurality of vias 640 and the plurality of wirings 650 may include a conductive material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, each of the plurality of vias 640 may be a filled via formed by filling a through hole with a metal material, or a conformal via having a metal material formed on an inner wall of the through hole.

[0082] In some example embodiments, the redistribution layer 600 may perform various functions according to design. For example, the redistribution layer 600 may include a ground pattern, a power pattern, and a signal pattern. The signal pattern may include a communication path for transmitting various signals (e.g., a data signal, etc.), except for the ground pattern and the power pattern.

[0083] Thereafter, a plurality of second connection bumps 700 may be formed under the redistribution layer 600 , and thus the manufacturing process of the semiconductor package 10 may be completed.

[0084] Although Figure 4A , Figure 4B , Figure 4C , Figure 4D and Figure 4EThe process of manufacturing a semiconductor package 10 is shown, but the exemplary embodiment is not limited thereto. For example, when a semiconductor package 10 includes three first semiconductor chips 100, 200, and 300 as shown in the figure, a plurality of first semiconductor chips 100 may be manufactured at one time (or at one time) on a single wafer, a plurality of first semiconductor chips 200 may be manufactured at one time on a single wafer, a plurality of first semiconductor chips 300 may be manufactured at one time on a single wafer, and a plurality of second semiconductor chips 400 may be manufactured at one time on a single wafer, by referring to Figure 4A , Figure 4B , Figure 4C , Figure 4D and Figure 4E The described series of processes may manufacture a plurality of semiconductor packages 10 at a time using four wafers, and then the plurality of semiconductor packages 10 may be separated into individual semiconductor packages 10 through a dicing process.

[0085] Figure 5 , Figure 6 and Figure 7 is a cross-sectional view showing a semiconductor package according to an example embodiment. Figure 1 Description of aspects that are the same or similar to the aspects of FIG.

[0086] refer to Figure 5 , the semiconductor package 20 may include a plurality of first semiconductor chips 100, 200, and 300, a second semiconductor chip 400, a plurality of first connection bumps 500, a redistribution layer 602, and a plurality of second connection bumps 702. The semiconductor package 20 may also include a plurality of connection structures 150, 250, 350, and 450, a plurality of insulating layers 160, 260, 360, 460, and 560, and an encapsulant 800.

[0087] Except that the configurations of the redistribution layer 602 and the plurality of second connection bumps 702 are partially changed, the semiconductor package 20 may be similar to Figure 1 The semiconductor packages 10 are substantially the same.

[0088] In some example embodiments, the number of the plurality of second connection bumps 702 may be less than the number of the plurality of first connection bumps 500. For example, the number of the plurality of first connection bumps 500 may be twice the number of the plurality of second connection bumps 702. In other words, the number of the plurality of second connection bumps 702 may be half the number of the plurality of first connection bumps 500.

[0089] In some example embodiments, the plurality of first connection bumps 500 may include a first connection bump 502 and a first connection bump 504. The first connection bumps 502 of the plurality of first connection bumps 500 may be electrically connected to the plurality of second connection bumps 702, respectively, via the redistribution layer 602. The first connection bumps 504 of the plurality of first connection bumps 500 may be floated without being electrically connected to the plurality of second connection bumps 702. The redistribution layer 602 may be implemented to electrically connect the first connection bumps 502 of the plurality of first connection bumps 500 to the plurality of second connection bumps 702, respectively. Figure 5 As shown, the number of the first connection bumps 502 may be four, and there may be four second connection bumps 702, so that the first connection bumps 502 are respectively (i.e., one-to-one) connected to the second connection bumps 702. In addition, the number of the first connection bumps 504 may be four, and these first connection bumps 504 may be floated without being electrically connected to the plurality of second connection bumps 702. Therefore, for the plurality of first connection bumps 500, the first connection bumps 502 connected to the connection bumps 702 and the first connection bumps 504 floated without being electrically connected to the plurality of second connection bumps 702 may alternate.

[0090] In some example embodiments, the first connection bump 502 of the plurality of first connection bumps 500 may be an odd-numbered connection bump among the plurality of first connection bumps 500 , and the first connection bump 504 of the plurality of first connection bumps 500 may be an even-numbered connection bump among the plurality of first connection bumps 500 .

[0091] In some example embodiments, the semiconductor package 20 may be an HBM device, and the plurality of first connection bumps 500 and the plurality of second connection bumps 702 may be electrically connected to data input / output (I / O) pads of the plurality of first semiconductor chips 100, 200, and 300 as DRAM chips. For example, the plurality of first connection bumps 500 may include first data I / O bumps electrically connected to the data I / O pads, the plurality of second connection bumps 702 may include second data I / O bumps electrically connected to the data I / O pads, and the number of the first data I / O bumps and the number of the second data I / O bumps may be 1024 and 512, respectively.

[0092] However, example embodiments are not limited thereto. For example, the plurality of first connection bumps 500 and the plurality of second connection bumps 702 may include first address bumps and second address bumps connected to address pads of the plurality of first semiconductor chips 100, 200, and 300, respectively, and the number of the first address bumps may be twice the number of the second address bumps. For another example, the plurality of first connection bumps 500 and the plurality of second connection bumps 702 may include first command bumps and second command bumps connected to command pads of the plurality of first semiconductor chips 100, 200, and 300, respectively, and the number of the first command bumps may be twice the number of the second command bumps.

[0093] refer to Figure 6 , the semiconductor package 25 may include a plurality of first semiconductor chips 100, 200, and 300, a second semiconductor chip 400, a plurality of first connection bumps 500, a redistribution layer 604, and a plurality of second connection bumps 704. The semiconductor package 25 may also include a plurality of connection structures 150, 250, 350, and 450, a plurality of insulating layers 160, 260, 360, 460, and 560, and an encapsulant 800.

[0094] Except that the configurations of the redistribution layer 604 and the plurality of second connection bumps 704 are partially changed, the semiconductor package 25 may be similar to Figure 1 The redistribution layer 604 and the plurality of second connection bumps 704 may be respectively connected to Figure 5 The redistribution layer 602 and the plurality of second connection bumps 702 in FIG. 7 are similar, and thus redundant descriptions thereof may be omitted.

[0095] In some example embodiments, the number of the plurality of second connection bumps 704 may be smaller than the number of the plurality of first connection bumps 500 . For example, the number of the plurality of first connection bumps 500 may be twice the number of the plurality of second connection bumps 704 .

[0096] In some example embodiments, the plurality of first connection bumps 500 may include first connection bumps 506, which may be electrically connected to the plurality of second connection bumps 704, respectively, via the redistribution layer 604. The plurality of first connection bumps 500 may include first connection bumps 508, which may be floated without being electrically connected to the plurality of second connection bumps 704. The redistribution layer 604 may be implemented to electrically connect the first connection bumps 506 of the plurality of first connection bumps 500 to the plurality of second connection bumps 704, respectively. Figure 6 As shown, the number of the first connection bumps 500 may be eight, and the first connection bumps 506 may include the first four first connection bumps 506 electrically connected to the second connection bumps 704 respectively, and the last four first connection bumps 508 may be floated without being electrically connected to the plurality of second connection bumps 704 .

[0097] In some example embodiments, the first connection bump 506 among the plurality of first connection bumps 500 may be a connection bump of the left half among the plurality of first connection bumps 500 , and the first connection bump 508 among the plurality of first connection bumps 500 may be a connection bump of the right half among the plurality of first connection bumps 500 .

[0098] refer to Figure 7 , the semiconductor package 30 may include a plurality of first semiconductor chips 100, 200, and 300, a second semiconductor chip 400, a plurality of first connection bumps 500, a redistribution layer 606, and a plurality of second connection bumps 706. The semiconductor package 25 may also include a plurality of connection structures 150, 250, 350, and 450, a plurality of insulating layers 160, 260, 360, 460, and 560, and an encapsulant 800.

[0099] Except that the configurations of the redistribution layer 606 and the plurality of second connection bumps 706 are partially changed, the semiconductor package 30 may be similar to Figure 1 The redistribution layer 606 and the plurality of second connection bumps 706 may be respectively connected to Figure 5 and Figure 6 The redistribution layers 602 and 604 and the plurality of second connection bumps 702 and 704 in FIG. 1 are similar, and thus redundant descriptions thereof may be omitted.

[0100] In some example embodiments, the number of the plurality of second connection bumps 706 may be less than the number of the plurality of first connection bumps 500. For example, the number of the plurality of first connection bumps 500 may be four times the number of the plurality of second connection bumps 706. In other words, the number of the plurality of second connection bumps 706 may be one quarter the number of the plurality of first connection bumps 500.

[0101] In some example embodiments, the plurality of first connection bumps 500 may include first connection bumps 512, which may be electrically connected to the plurality of second connection bumps 706, respectively, via the redistribution layer 606. The plurality of first connection bumps 500 may include first connection bumps 514, which may be floated without being electrically connected to the plurality of second connection bumps 706. The redistribution layer 606 may be implemented to electrically connect the first connection bumps 512 of the plurality of first connection bumps 500 to the plurality of second connection bumps 706, respectively. That is, as Figure 7As shown, the number of the second connection bumps 706 is two. The number of the first connection bumps 512 may be two, and the two first connection bumps 512 may be electrically connected to two second connection bumps in the plurality of second connection bumps 706, respectively. The number of the first connection bumps 514 may be six, and these first connection bumps 514 may be floated without being electrically connected to the plurality of second connection bumps 706.

[0102] exist Figure 5 , Figure 6 and Figure 7 In the illustrated example embodiment, the number of first connection bumps in the plurality of first connection bumps 500, and the number of connection bumps in the plurality of second connection bumps 700, 702, 704, and 706 are shown as specific numbers, but these depictions are exemplary and not exclusive. A person of ordinary skill in the art will understand from the disclosure herein that the number of connection bumps may vary without departing from the scope of the present disclosure.

[0103] In some example embodiments, the semiconductor package 30 may be an HBM device, and the plurality of first connection bumps 500 and the plurality of second connection bumps 706 may be electrically connected to the data I / O pads of the plurality of first semiconductor chips 100, 200, and 300 as DRAM chips. For example, the plurality of first connection bumps 500 may include first data I / O bumps, the plurality of second connection bumps 706 may include second data I / O bumps, and the number of the first data I / O bumps and the number of the second data I / O bumps may be 1024 and 256, respectively. However, example embodiments are not limited thereto. For example, the plurality of first connection bumps 500 and the plurality of second connection bumps 706 may include address bumps and / or command bumps.

[0104] although Figure 5 and Figure 6 An example is shown in which half of the plurality of first connection bumps 500 are connected to the plurality of second connection bumps 702 and 704, and the remaining half of the plurality of first connection bumps 500 are not connected to the second connection bumps 702 and 704, and although Figure 7 An example is shown in which one quarter of the plurality of first connection bumps 500 are connected to the second connection bumps 706, and the remaining three quarters of the plurality of first connection bumps 500 are not connected to the plurality of second connection bumps 706, but example embodiments are not limited thereto. For example, among the plurality of first connection bumps 500, the first arbitrary number of connection bumps may be classified into the first group, and the remaining connection bumps may be classified into the second group, and then only the connection bumps of the first group may be electrically connected to the second connection bumps.

[0105] In some example embodiments, the first semiconductor chips 100, 200 and 300 and / or the second semiconductor chip 400 may include: a component for driving only the first connection bumps 502, 506 and 512 electrically connected to the second connection bumps 702, 704 and 706, and for preventing the first connection bumps 504, 508 and 514 not electrically connected to the second connection bumps 702, 704 and 706 from being driven. For example, the first semiconductor chips 100, 200 and 300 and / or the second semiconductor chip 400 may further include a selection circuit for selecting a communication path. For example, when sending and / or receiving signals, data, etc. via the first connection bumps 502, 506 and 512, the selection circuit may maintain the communication path. For example, when transmitting and / or receiving signals, data, etc. via first connection bumps 504, 508, and 514, the selection circuit may change the communication path to use first connection bumps 502, 506, and 512 instead of first connection bumps 504, 508, and 514. For example, the selection circuit may include a switch, a multiplexer, etc.

[0106] Figure 8 is a perspective view illustrating a semiconductor package according to one or more example embodiments.

[0107] refer to Figure 8 , the semiconductor package 900 may include a first semiconductor device ( SD1 ) 910 , a plurality of second semiconductor devices ( SD2 ) 920 , and a connection substrate 930 .

[0108] The first semiconductor device 910 may control the overall operation of the semiconductor package 900. The plurality of second semiconductor devices 920 may be controlled by the first semiconductor device 910. The first semiconductor device 910 and the plurality of second semiconductor devices 920 may be mounted on a connection substrate 930. The first semiconductor device 910 and the plurality of second semiconductor devices 920 may be electrically connected to each other via the connection substrate 930.

[0109] Each of the plurality of second semiconductor devices 920 may be a semiconductor device according to the reference Figures 1 to 7A semiconductor package of an example embodiment described. For example, each of the plurality of second semiconductor devices 920 may include a first semiconductor chip and a second semiconductor chip, which are semiconductor chips of different types and are stacked in a vertical direction. For example, each of the plurality of second semiconductor devices 920 may include a redistribution layer having the same width as the second semiconductor chip in the horizontal direction, the width being greater than the width of another semiconductor chip, as described above. For example, each of the plurality of second semiconductor devices 920 may include a first connection bump between the second semiconductor chip and the redistribution layer, and a second connection bump below the redistribution layer, the second connection bump being larger than the first connection bump and connected to the first connection bump via the redistribution layer. The second semiconductor chip and the redistribution layer may have the same width in the horizontal direction, and thus the occupied area of ​​each of the plurality of second semiconductor devices 920 may not increase and may be maintained. A second connection bump having a relatively large size and pitch may be used, so that the electrical connection between each of the plurality of second semiconductor devices 920 and the connection substrate 930 may be relatively easily achieved.

[0110] In some example embodiments, the first semiconductor device 910 and the plurality of second semiconductor devices 920 may be semiconductor devices of different types. For example, the first semiconductor device 910 may be a logic semiconductor device that performs a data processing function, and the plurality of second semiconductor devices 920 may be memory semiconductor devices that perform a data storage function.

[0111] In some example embodiments, the connection substrate 930 may be or may include a connector implemented at a relatively lower price than a silicon interposer.

[0112] In some example embodiments, the connection substrate 930 may be a silicon-free interposer. For example, the connection substrate 930 may be a glass interposer. For example, the glass interposer may include a through glass via (TGV) formed by penetrating a glass substrate, and the first semiconductor device 910 and the plurality of second semiconductor devices 920 may be electrically connected to each other through the TGV.

[0113] In some example embodiments, the connection substrate 930 may be a package base substrate. For example, the connection substrate 930 may be a printed circuit board (PCB) substrate. For example, the PCB substrate may be a multilayer circuit board having vias and various circuits therein, and the first semiconductor device 910 and the plurality of second semiconductor devices 920 may be electrically connected to each other through the vias.

[0114] In some example embodiments, when the connection substrate 930 is a silicon-free interposer, the semiconductor package 900 may further include a package base substrate on which the connection substrate 930 including the first semiconductor device 910 and the plurality of second semiconductor devices 920 are mounted.

[0115] In semiconductor systems, HBM devices can be utilized when relatively high bandwidth is required.

[0116] In the semiconductor package 900 according to the example embodiment, the first semiconductor device 910 and the plurality of second semiconductor devices 920 may be electrically connected to each other using a relatively inexpensive connection substrate 930 (e.g., a PCB substrate or a glass interposer) instead of a silicon interposer. The plurality of second semiconductor devices 920 may be connected in a manner similar to that of a reference semiconductor device. Figures 1 to 7 The semiconductor package of the described example embodiment is implemented in the form of a semiconductor package, and thus the second semiconductor device 920 can have the same footprint as a conventional HBM device, and has a larger bump size and a larger bump pitch than a conventional HBM device. Therefore, the semiconductor package 900 can be easily connected to the connection substrate 930, and the manufacturing cost of the semiconductor package 900 can be effectively reduced.

[0117] Fig. 9 is a block diagram illustrating a semiconductor system according to one or more example embodiments.

[0118] refer to Fig. 9 , the semiconductor system 1000 may include a logic semiconductor device 1100 and a memory semiconductor device 1200. The semiconductor system 1000 may correspond to Figure 8 A semiconductor package 900 is provided.

[0119] The logic semiconductor device 1100 may correspond to Figure 8 The first semiconductor device 910 in the embodiment of the present invention may include a memory controller 1110. For example, the logic semiconductor device 1100 may be or may include a device operating as a host (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system on chip (SoC), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.).

[0120] The memory semiconductor device 1200 may correspond to Figure 8 The second semiconductor device 920 in the embodiment may include a buffer chip 1210 and a plurality of memory chips 1220. For example, the memory semiconductor device 1200 may correspond to Figure 1 The semiconductor package 10 of FIG. 1 , and the buffer chip 1210 and the plurality of memory chips 1220 may correspond to Figure 1The memory semiconductor device 1200 may include a second semiconductor chip 400 and a plurality of first semiconductor chips 100, 200, and 300. For example, the memory semiconductor device 1200 may be an HBM device, and the plurality of memory chips 1220 may be DRAM chips.

[0121] The memory semiconductor device 1200 may be controlled by the memory controller 1110. For example, based on a request from the logic semiconductor device 1100, the memory controller 1110 may store (e.g., write or program) data into the memory semiconductor device 1200, or may retrieve (e.g., read or sense) data from the memory semiconductor device 1200. For example, the memory controller 1110 may send command, address, and control signals to the memory semiconductor device 1200, may exchange data signals with the memory semiconductor device 1200, and may provide a power supply voltage to the memory semiconductor device 1200.

[0122] In a structure in which a plurality of memory chips 1220 are connected to one memory controller 1110, the output impedance of the memory controller 1110 may be quite large, and thus a problem may occur in which a signal output from the memory controller 1110 cannot correctly reach or arrive at the plurality of memory chips 1220. In order to solve the above problem, a structure in which the memory controller 1110 and the plurality of memory chips 1220 are connected via a buffer chip 1210 may be applied, adopted, or taken, so that the buffer chip 1210 can drive a signal received from the memory controller 1110 and can correctly transmit the signal to the memory chip 1220.

[0123] In some example embodiments, as shown in FIG. Figure 5 , Figure 6 and Figure 7 As described, when only some of the first connection bumps 502 , 506 , and 512 are electrically connected to the second connection bumps 702 , 704 , and 706 , the buffer chip 1210 may include a selection circuit for selecting a communication path, and / or each of the plurality of memory chips 1220 may include a selection circuit.

[0124] Fig.10 is a block diagram illustrating an example of a memory chip included in a semiconductor system according to one or more example embodiments.

[0125] refer to Fig.10, the memory chip 1500 may include a control logic circuit 1510, an address register 1520, a bank control logic circuit 1530, a row address multiplexer 1540, a refresh counter 1545, a column address latch 1550, a row decoder 1560, a column decoder 1570, a memory cell array 1600, a sense amplifier unit 1585, an I / O gating circuit 1590, and a data I / O buffer 1595. For example, the memory chip 1500 may be one of various volatile memory chips such as a DRAM chip.

[0126] The memory cell array 1600 may include a first memory bank array 1610 to an eighth memory bank array 1680. The row decoder 1560 may include first memory bank row decoders 1560a to an eighth memory bank row decoder 1560h connected to the first memory bank array 1610 to the eighth memory bank array 1680, respectively. The column decoder 1570 may include first memory bank column decoders 1570a to an eighth memory bank column decoder 1570h connected to the first memory bank array 1610 to the eighth memory bank array 1680, respectively. The sense amplifier unit 1585 may include first memory bank sense amplifiers 1585a to an eighth memory bank sense amplifier 1585h connected to the first memory bank array 1610 to the eighth memory bank array 1680, respectively.

[0127] The first memory bank array 1610 to the eighth memory bank array 1680, the first memory bank row decoder 1560a to the eighth memory bank row decoder 1560h, the first memory bank column decoder 1570a to the eighth memory bank column decoder 1570h, and the first memory bank sense amplifier 1585a to the eighth memory bank sense amplifier 1585h may form the first memory bank to the eighth memory bank. Each of the first memory bank array 1610 to the eighth memory bank array 1680 may include a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC at intersections of the word lines WL and the bit lines BL.

[0128] although Fig.10 Memory chip 1500 is shown as including eight memory banks (and eight memory bank arrays, eight row decoders, etc.), but memory chip 1500 may include any number of memory banks (e.g., one, two, four, eight, sixteen, or thirty-two memory banks, or any number between one and thirty-two, etc.).

[0129] The address register 1520 may be received from a memory controller (eg, Fig. 9The memory controller 1110 in the embodiment receives an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR. The address register 1520 can provide the received bank address BANK_ADDR to the bank control logic circuit 1530, can provide the received row address ROW_ADDR to the row address multiplexer 1540, and can provide the received column address COL_ADDR to the column address latch 1550.

[0130] The bank control logic circuit 1530 may generate a bank control signal in response to the bank address BANK_ADDR. One of the first bank row decoder 1560a to the eighth bank row decoder 1560h corresponding to the bank address BANK_ADDR may be activated in response to the bank control signal, and one of the first bank column decoder 1570a to the eighth bank column decoder 1570h corresponding to the bank address BANK_ADDR may be activated in response to the bank control signal.

[0131] The row address multiplexer 1540 may receive a row address ROW_ADDR from the address register 1520 and may receive a refresh row address REF_ADDR from the refresh counter 1545. The row address multiplexer 1540 may selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 1540 may be applied to the first to eighth bank row decoders 1560a to 1560h.

[0132] The activated one of the first to eighth bank row decoders 1560a to 1560h may decode the row address RA output from the row address multiplexer 1540, and may activate a word line WL corresponding to the row address RA in the corresponding bank array. For example, the activated bank row decoder may generate a word line driving voltage, and may apply the word line driving voltage to the word line WL corresponding to the row address RA.

[0133] The column address latch 1550 may receive a column address COL_ADDR from the address register 1520 and may temporarily store the received column address COL_ADDR. In some example embodiments, in a burst mode, the column address latch 1550 may generate a column address incremented from the received column address COL_ADDR. The column address latch 1550 may apply the temporarily stored or generated column address to the first to eighth bank column decoders 1570a to 1570h.

[0134] An activated one of the first to eighth bank column decoders 1570 a to 1570 h may decode the column address COL_ADDR output from the column address latch 1550 and may control the I / O gating circuit 1590 to output data corresponding to the column address COL_ADDR.

[0135] The I / O gating circuit 1590 may include a circuit configured to gate input / output data. The I / O gating circuit 1590 may also include a read data latch configured to store data output from the first memory array 1610 to the eighth memory array 1680, and may also include a write control device for writing data to the first memory array 1610 to the eighth memory array 1680.

[0136] The data DAT read from one of the first memory bank array 1610 to the eighth memory bank array 1680 may be sensed by a sense amplifier connected to the memory bank array from which the data DAT is to be read, and may be stored in a read data latch. The data DAT stored in the read data latch may be provided to a memory controller via a data I / O buffer 1595. The data DAT to be written into one of the first memory bank array 1610 to the eighth memory bank array 1680 may be provided from the memory controller to the I / O gating circuit 1590 via the data I / O buffer 1595, and the I / O gating circuit 1590 may write the data DAT into that memory bank array through a write driver.

[0137] The control logic circuit 1510 may control the operation of the memory chip 1500. For example, the control logic circuit 1510 may generate a control signal for the memory chip 1500 to perform a write operation and / or a read operation. The control logic circuit 1510 may include a command decoder 1511 that decodes a command CMD received from a memory controller, and a mode register 1512 that sets an operation mode of the memory chip 1500. In some example embodiments, the operations described herein as being performed by the control logic circuit 1510 may be performed by a processing circuit. For example, the command decoder 1511 may generate a control signal corresponding to the command CMD by decoding a write enable signal, a row address strobe signal, a column address strobe signal, a chip select signal, etc.

[0138] A command pad for receiving a command CMD, an address pad for receiving an address ADDR, and a data pad for exchanging data DAT may be electrically connected to Figure 1 The first connecting bump 500 and the second connecting bump 700 are provided in FIG.

[0139] In some example embodiments, as shown in FIG. Figure 5 , Figure 6 and Figure 7 As described, when only some of the first connection bumps 502, 506, and 512 are electrically connected to the second connection bumps 702, 704, and 706, and when each memory chip includes a selection circuit for selecting a communication path, the selection circuit may be connected to a data pad or a command / address pad.

[0140] Fig.11 is a block diagram illustrating an electronic system according to one or more example embodiments.

[0141] Reference Fig.11 , the electronic system 4000 includes at least one processor 4100, a communication module 4200, a display / touch module 4300, a storage device 4400, and a memory device 4500. For example, the electronic system 4000 may be any mobile system or any computing system.

[0142] The processor 4100 may control the operation of the electronic system 4000. For example, the processor 4100 may run an operating system and at least one application to provide an Internet browser, a game, a video, etc. The communication module 4200 may be controlled by the processor 4100 and may perform wireless or wired communication with an external system. The display / touch module 4300 may display data processed by the processor 4100 and / or may receive data through a touch panel. The storage device 4400 may store user data. The memory device 4500 may temporarily store data for processing the operation of the electronic system 4000.

[0143] At least a portion of the electronic system 4000 may be implemented in the form of a semiconductor package according to example embodiments. For example, the memory device 4500 may be implemented in the form of a semiconductor package according to reference Figures 1 to 7 The example embodiments described herein are implemented in the form of a semiconductor package, and the processor 4100 and the memory device 4500 may be implemented in the form of a semiconductor package according to the reference Figure 8 The described example embodiments are implemented in the form of a semiconductor package.

[0144] Although reference Figure 8 A semiconductor package including a logic semiconductor device and a memory semiconductor device and having a 2.5-dimensional (2.5D) stack structure is described, but example embodiments are not limited thereto.

[0145] In some example embodiments, the semiconductor package according to example embodiments may be a lower semiconductor package or an upper semiconductor package constituting a package on package (PoP) type semiconductor package.

[0146] In some example embodiments, the semiconductor package according to the example embodiments may be a semiconductor package having a three-dimensional (3D) stacked structure. In a semiconductor package having a 3D stacked structure, the distance between semiconductor devices (or chips) may be reduced by vertically stacking several semiconductor devices that are the same or different from each other. For example, a semiconductor device may have corresponding through electrodes, thereby shortening the time it takes for data to be transferred to other semiconductor devices. A semiconductor package having a 3D stacked structure may include various types of semiconductor devices freely arranged therein, thereby increasing the processing speed of data between semiconductor devices.

[0147] In some example embodiments, the semiconductor package according to the example embodiments may be a wafer-level package (WLP), and may be a fan-out wafer-level package (FOWLP) in which package connection terminals or external connection pads are located outside the area of ​​the semiconductor chip or a fan-in wafer-level package (FINWLP) in which package connection terminals or external connection pads are located inside the area of ​​the semiconductor chip.

[0148] In some example embodiments, the semiconductor package according to the example embodiments may be a chip-last fan-out semiconductor package in which an interposer or a connection substrate is formed and then at least one semiconductor device is mounted on the interposer or the connection substrate. In other example embodiments, the semiconductor package according to the example embodiments may be a chip-first semiconductor package in which at least one semiconductor device is mounted on a tape, the periphery of the semiconductor device is surrounded by a molding layer, and then an interposer or a connection substrate is connected to the semiconductor device. In some example embodiments, the semiconductor package according to the example embodiments may be a fan-out panel level package (FOPLP).

[0149] In some example embodiments, a semiconductor package according to example embodiments may include a plurality of semiconductor devices, and the semiconductor package according to example embodiments may be a system-in-package (SIP) in which a plurality of semiconductor devices of different types are electrically connected to each other to operate as a single system.

[0150] Example embodiments may be applied to various electronic devices and systems including semiconductor packages. For example, example embodiments may be applied to systems such as personal computers (PCs), server computers, data centers, workstations, mobile phones, smart phones, tablet computers, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable game consoles, music players, camcorders, video players, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, drones, cars, etc.

[0151] The foregoing is illustrative of example embodiments and should not be construed as limiting thereof. Although some example embodiments have been described, those skilled in the art will readily appreciate that many modifications in the example embodiments are possible without materially departing from the novel teachings and advantages of the example embodiments. Therefore, all such modifications are intended to be included within the scope of the example embodiments as defined in the claims. Therefore, it should be understood that the foregoing is illustrative of various example embodiments and should not be construed as limiting to the specific example embodiments disclosed, and modifications to the disclosed example embodiments as well as other example embodiments are intended to be included within the scope of the appended claims.

Claims

1. A semiconductor package, comprising: a plurality of first semiconductor chips, the plurality of first semiconductor chips being sequentially stacked in a vertical direction, at least one of the plurality of first semiconductor chips comprising a plurality of first through electrodes connecting the plurality of first semiconductor chips to each other, each of the plurality of first semiconductor chips having a first width in a horizontal direction; a second semiconductor chip, the second semiconductor chip being located below the plurality of first semiconductor chips, the second semiconductor chip comprising a plurality of second through electrodes connecting the second semiconductor chip to the plurality of first semiconductor chips, the second semiconductor chip having a second width in the horizontal direction greater than the first width; a redistribution layer, the redistribution layer being located below the second semiconductor chip, the redistribution layer having a third width in the horizontal direction substantially equal to the second width; a plurality of first connection bumps, the plurality of first connection bumps being located between the second semiconductor chip and the redistribution layer and connecting the second semiconductor chip with the redistribution layer, each of the plurality of first connection bumps having a first size; as well as A plurality of second connection bumps are disposed under the redistribution layer and connect the redistribution layer with an external device, each of the plurality of second connection bumps having a second size greater than the first size.

2. The semiconductor package according to claim 1, wherein: A first distance between two adjacent first connection bumps among the plurality of first connection bumps is smaller than a second distance between two adjacent second connection bumps among the plurality of second connection bumps.

3. The semiconductor package according to claim 1, wherein: The number of the second connection bumps is smaller than the number of the first connection bumps.

4. The semiconductor package according to claim 3, wherein: The number of the plurality of first connection bumps is twice the number of the plurality of second connection bumps.

5. The semiconductor package according to claim 3, wherein: The number of the plurality of first connection bumps is four times the number of the plurality of second connection bumps.

6. The semiconductor package according to claim 1, wherein: A first number of first connection bumps among the plurality of first connection bumps are respectively connected to a second number of second connection bumps among the plurality of second connection bumps via the redistribution layer; and A third number of first connection bumps among the plurality of first connection bumps are floated without being connected to the plurality of second connection bumps.

7. The semiconductor package according to claim 1, wherein: The number of the second connection bumps is equal to the number of the first connection bumps.

8. The semiconductor package according to claim 7, wherein: The plurality of first connection bumps are respectively connected to the plurality of second connection bumps via the redistribution layer.

9. The semiconductor package according to claim 1, wherein: In a plan view, the plurality of first connecting bumps are arranged adjacent to a center of the semiconductor package, and the plurality of second connecting bumps are uniformly arranged around the semiconductor package.

10. The semiconductor package according to claim 1, further comprising: An encapsulant encapsulates the plurality of first semiconductor chips and the second semiconductor chip.

11. The semiconductor package according to claim 10, wherein: The encapsulant directly contacts side surfaces of the plurality of first semiconductor chips and directly contacts at least a portion of an upper surface of the second semiconductor chip.

12. The semiconductor package according to claim 1, wherein The plurality of first semiconductor chips include an uppermost first semiconductor chip and a remaining number of first semiconductor chips, wherein the plurality of first through electrodes penetrate the remaining number of first semiconductor chips, and The plurality of second through electrodes penetrate the second semiconductor chip.

13. The semiconductor package according to claim 12, wherein: None of the plurality of first through electrodes penetrates the uppermost first semiconductor chip among the plurality of first semiconductor chips.

14. The semiconductor package according to claim 1, wherein The plurality of first semiconductor chips and the second semiconductor chip are semiconductor chips of different types.

15. The semiconductor package according to claim 14, wherein: The plurality of first semiconductor chips include a dynamic random access memory chip configured to store data, wherein the second semiconductor chip includes a buffer chip configured to control the operation of the dynamic random access memory chip, and Wherein, the semiconductor package is a high bandwidth memory device.

16. A semiconductor package, comprising: a first semiconductor device; a plurality of second semiconductor devices, wherein the first semiconductor device is configured to control the plurality of second semiconductor devices; and a connection substrate on which the first semiconductor device and the plurality of second semiconductor devices are disposed, Wherein, each of the plurality of second semiconductor devices comprises: a plurality of first semiconductor chips sequentially stacked in a vertical direction, at least one of the plurality of first semiconductor chips comprising a plurality of first through electrodes connecting the plurality of first semiconductor chips to each other, each of the plurality of first semiconductor chips having a first width in a horizontal direction; a second semiconductor chip located below the plurality of first semiconductor chips, the second semiconductor chip including a plurality of second through electrodes connecting the second semiconductor chip to the plurality of first semiconductor chips, the second semiconductor chip having a second width in the horizontal direction greater than the first width; a redistribution layer located below the second semiconductor chip, the redistribution layer having a third width in the horizontal direction substantially equal to the second width; a plurality of first connection bumps, the plurality of first connection bumps being located between the second semiconductor chip and the redistribution layer and connecting the second semiconductor chip with the redistribution layer, each of the plurality of first connection bumps having a first size; and A plurality of second connection bumps are disposed under the redistribution layer and connect the redistribution layer with an external device, each of the plurality of second connection bumps having a second size greater than the first size.

17. The semiconductor package according to claim 16, wherein: The connection substrate includes a silicon-free interposer.

18. The semiconductor package according to claim 16, wherein: The connection substrate includes a printed circuit board substrate.

19. The semiconductor package according to claim 16, wherein: The first semiconductor device includes a logic semiconductor device configured to perform a data processing function, and The plurality of second semiconductor devices include memory semiconductor devices configured to perform a data storage function.

20. A semiconductor package, comprising: A first dynamic random access memory chip, wherein the first dynamic random access memory chip has a first width in a horizontal direction; a plurality of second dynamic random access memory chips, the plurality of second dynamic random access memory chips being sequentially stacked in a vertical direction below the first dynamic random access memory chip, at least one of the plurality of second dynamic random access memory chips comprising a plurality of first through electrodes, the plurality of first through electrodes connecting the plurality of second dynamic random access memory chips to each other and to the first dynamic random access memory chip, each of the plurality of second dynamic random access memory chips having a second width in the horizontal direction substantially equal to the first width; a buffer chip located below the plurality of second dynamic random access memory chips, the buffer chip comprising a plurality of second through electrodes connected to the first dynamic random access memory chip and the plurality of second dynamic random access memory chips, the buffer chip having a third width in the horizontal direction that is greater than the first width; a redistribution layer located below the buffer chip, the redistribution layer having a fourth width in the horizontal direction substantially equal to the third width; a plurality of first connection bumps, the plurality of first connection bumps being located between the buffer chip and the redistribution layer and connected to the plurality of second through-electrodes and the redistribution layer, each of the plurality of first connection bumps having a first size; a plurality of second connection bumps, the plurality of second connection bumps being located under the redistribution layer and connected to the redistribution layer, each of the plurality of second connection bumps having a second size greater than the first size; as well as an encapsulant, wherein the encapsulant encapsulates the first dynamic random access memory chip, the plurality of second dynamic random access memory chips and the buffer chip, and the encapsulant covers a side surface of the first dynamic random access memory chip, a side surface of the plurality of second dynamic random access memory chips and at least a portion of an upper surface of the buffer chip, wherein the number of the plurality of second connecting protrusions is less than the number of the plurality of first connecting protrusions; wherein a first number of first connecting bumps among the plurality of first connecting bumps are respectively connected to a second number of second connecting bumps among the plurality of second connecting bumps via the redistribution layer, wherein the first dynamic random access memory chip, the plurality of second dynamic random access memory chips, and the buffer chip are electrically connected to an external device through the first number of first connection bumps, the redistribution layer, and the second number of second connection bumps, and Wherein, a third number of first connection bumps among the plurality of first connection bumps are floated without being connected to the redistribution layer, the plurality of second connection bumps, and the external device.

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