3D super-junction high-voltage-resistant high-heat-dissipation HEMT device and preparation method thereof

Abstract

The invention provides a 3D super-junction high-voltage-resistant high-heat-dissipation HEMT device and a preparation method thereof, and belongs to the field of semiconductor devices. The HEMT device comprises a substrate, an electron channel layer, a barrier layer, a hole channel layer and a p-type semiconductor layer which are sequentially stacked from bottom to top. The upper surface of the p-type semiconductor layer is provided with a first electrode. And first grooves which are periodically distributed are formed in the p-type semiconductor layer and the hole channel layer. An opening of the first groove is located on the upper surface of the p-type semiconductor layer, and the bottom of the first groove is located in the hole channel layer or located on the upper surface of the barrier layer. The inner wall and the bottom of the first groove are provided with a first dielectric layer, and the interior is filled with p-type diamond. The p-type diamond is in contact with the first electrode. And the electron channel layer, the barrier layer and the hole channel layer form a double heterojunction. In the HEMT device structure, a polarized super junction and a pn super junction are combined to form a 3D super junction structure, so that the breakdown voltage and the heat dissipation performance of the HEMT device are remarkably improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a 3D superjunction high-voltage and high-heat dissipation HEMT device and a preparation method thereof. Background Art

[0002] When voltage is applied to HEMT (high electron mobility transistor) devices, local electric field concentration will occur, resulting in the overall voltage resistance performance of HEMT devices being not high enough. Taking GaN HEMT (gallium nitride high electron mobility transistor) devices as an example, although the breakdown electric field strength of GaN is 3MV / cm, it is difficult for power devices with GaN HEMT structure to achieve high voltage resistance performance exceeding 1000V. Especially when the device is in the off state, as the drain voltage continues to increase, the depletion region under the gate expands to the drain side, resulting in a higher electric field peak at the edge of the gate. This phenomenon of gate electric field concentration causes the electric field in the electron channel where the gate is located to reach the critical breakdown electric field prematurely, resulting in premature breakdown of the device, and is also prone to "current collapse" phenomenon.

[0003] In order to increase the breakdown voltage of HEMT devices, field plate (FP) technology is usually used to make the electric field in the channel uniform. However, although the field plate formed on the gate can suppress the phenomenon of electric field concentration to a certain extent, it is difficult to completely eliminate the phenomenon of electric field concentration. Therefore, the field plate technology has limited effect on improving the breakdown voltage of the device.

[0004] In order to make the electric field distribution in the channel more uniform, a polarized superjunction (PSJ) structure is introduced in the prior art. Taking GaN HEMT as an example, the specific measures include: forming a GaN / AlGaN / GaN heterojunction in the channel region. Then, AlGaN spontaneously polarizes to generate a two-dimensional hole gas (2DHG) near the GaN interface above AlGaN, and a two-dimensional electron gas (2DEG) near the GaN interface below AlGaN. When the device is turned off, 2DHG and 2DEG are depleted, the electric field strength in the entire PSJ region becomes uniform, and the electric field from the drain to the gate can be evenly distributed. By increasing the length of the PSJ part (corresponding to the channel length), the breakdown voltage can be increased. This scheme is also applicable to gallium oxide (Ga 2 O 3)-based HEMT devices. This solution uses undoped GaN and p-type GaN layers to fully cover the surface of the device barrier layer to ensure the number of two-dimensional hole gases, but it is very difficult to achieve p-type doping for gallium oxide. Moreover, as the voltage of the device increases further, the high heat generation problem becomes more severe, especially the thermal conductivity of gallium oxide is very poor, which is far from meeting the heat dissipation requirements of gallium oxide transistors in high-power scenarios. In addition, the unintentionally doped layers in the device structure (such as unintentionally doped GaN layers, Ga 2 O 3 The presence of unintentionally doped layers and p-type semiconductor layers (e.g., p-type GaN layers) will introduce a large-area planar capacitor, which will significantly reduce the frequency characteristics of the device. Moreover, due to the presence of unintentionally doped layers and p-type semiconductor layers, the gate's ability to regulate the two-dimensional electron gas is affected, and the gate control capability is reduced. Summary of the invention

[0005] In view of the above technical problems, the present invention provides a 3D superjunction high-voltage and high-heat dissipation HEMT device. The HEMT device structure has a double heterojunction formed by an electron channel layer, a barrier layer, and a hole channel layer, and also has a pn junction formed by a p-type diamond and a hole channel layer, so that the HEMT device is a device with a 3D superjunction structure, which significantly improves the breakdown voltage of the device. At the same time, due to the ultra-high thermal conductivity of p-type diamond, the HEMT device also has excellent heat dissipation performance.

[0006] Specifically, the present invention adopts the following technical solutions to achieve the above purpose: A 3D superjunction high-voltage and high-heat dissipation HEMT device comprises a substrate, an electron channel layer, a barrier layer, a hole channel layer and a p-type semiconductor layer stacked in sequence from bottom to top, wherein a first electrode is arranged on the upper surface of the p-type semiconductor layer; periodically distributed first grooves are arranged in the p-type semiconductor layer and the hole channel layer, wherein the opening of the first groove is located on the upper surface of the p-type semiconductor layer, and the bottom of the first groove is located in the hole channel layer or on the upper surface of the barrier layer; a first dielectric layer is arranged on the inner wall and the bottom of the first groove, and the interior of the first groove is filled with p-type diamond; the p-type diamond is in contact with the first electrode; the electron channel layer forms a heterojunction with the barrier layer, and the barrier layer forms a heterojunction with the hole channel layer.

[0007] In a preferred embodiment, the first electrode is a gate, and the HEMT device includes a source, a drain, a source field plate and a second dielectric layer; the source and the drain are respectively located on both sides of the upper surface of the barrier layer; the source field plate extends from the upper surface of the source toward the drain and extends to above the p-type semiconductor layer; the second dielectric layer isolates the gate and the source field plate.

[0008] In a further preferred embodiment, the material of the second dielectric layer is at least one of silicon dioxide, aluminum oxide, and silicon nitride.

[0009] In a preferred solution, a second trench is provided in the barrier layer, a third dielectric layer is deposited on the inner wall and bottom of the second trench, and the gate of the HEMT device is provided in the second trench; the first electrode is a base.

[0010] In a further preferred embodiment, the material of the third dielectric layer is aluminum oxide.

[0011] In a further preferred embodiment, the HEMT device includes a source, a drain, a source field plate and a second dielectric layer; the source and the drain are respectively located on both sides of the upper surface of the barrier layer; the source field plate extends from the upper surface of the source toward the drain and extends to above the p-type semiconductor layer; the second dielectric layer isolates the gate and the source field plate and isolates the first electrode and the source field plate.

[0012] In a preferred solution, the first groove is a multi-level groove.

[0013] In a preferred embodiment, a buffer layer is provided between the substrate and the electron channel layer.

[0014] In a further preferred embodiment, the material of the buffer layer is aluminum nitride.

[0015] In a preferred embodiment, the substrate is at least one of a gallium oxide substrate, a silicon carbide substrate, a silicon substrate, and a sapphire substrate.

[0016] In a preferred embodiment, the material of the electron channel layer is unintentionally doped gallium oxide and / or unintentionally doped gallium nitride.

[0017] In a preferred embodiment, the material of the barrier layer is (Al x Ga 1-x ) 2 O 3 、Al y Ga 1-y At least one of N and AlN, wherein 0.15≤x≤0.3, 0.1≤y≤0.3.

[0018] In a preferred embodiment, the material of the hole channel layer is unintentionally doped gallium oxide and / or unintentionally doped gallium nitride.

[0019] In a preferred embodiment, the material of the p-type semiconductor layer is p-type gallium nitride.

[0020] In a preferred solution, the material of the first dielectric layer is aluminum nitride and / or silicon nitride.

[0021] The present invention also provides a method for preparing the 3D super junction high voltage and high heat dissipation HEMT device, comprising the following steps: S1, sequentially growing an electron channel layer, a barrier layer, a hole channel layer and a p-type semiconductor layer on a substrate; S2, etching the p-type semiconductor layer and the hole channel layer to obtain periodically distributed first grooves; S3, depositing a first dielectric layer on the inner wall and bottom of the first trench; then depositing p-type diamond in the first trench; S4. Fabricate a first electrode on the upper surface of the p-type semiconductor layer.

[0022] In a preferred embodiment, before manufacturing the first electrode in step S4, the following steps are included: etching the p-type semiconductor layer and the hole channel layer to expose the barrier layer to obtain a source region and a drain region; manufacturing a source electrode and a drain electrode in the source region and the drain region, respectively; and after step S4, the following steps are included: S5, depositing a second dielectric layer on the upper surface of the structure obtained in step S4, etching the second dielectric layer, forming an electrode lead-out hole on the upper surface of the first electrode, and exposing the source electrode and the drain electrode; S6. Fabricate a source field plate on the upper surface of the second dielectric layer.

[0023] In a preferred embodiment, before making the first electrode in step S4, the following steps are included: etching the p-type semiconductor layer and the hole channel layer to expose the barrier layer to obtain a source region and a drain region; etching a second groove in the barrier layer located in the source region; depositing a third dielectric layer on the inner wall and bottom of the second groove to make a gate in the second groove; making a source electrode and a drain electrode in the source region and the drain region, respectively; after step S4, the following steps are included: S5, depositing a second dielectric layer on the upper surface of the structure obtained in step S4, etching the second dielectric layer, forming electrode lead-out holes on the upper surfaces of the first electrode and the gate, and exposing the source electrode and the drain electrode; S6. Fabricate a source field plate on the upper surface of the second dielectric layer.

[0024] In a further preferred embodiment, a buffer layer is first grown on the substrate, and then the electron channel layer, the barrier layer, the hole channel layer and the p-type semiconductor layer are sequentially grown on the buffer layer.

[0025] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: (1) In the HEMT device structure provided by the present invention, a polarization superjunction structure is formed by a double heterojunction of an electron channel layer, a barrier layer and a hole channel layer, and a pn superjunction is formed by embedding p-type diamond and a hole channel layer. The 3D superjunction formed by the polarization superjunction and the pn superjunction greatly improves the phenomenon of electric field concentration and improves the withstand voltage performance of the device. The p-type semiconductor layer on the top of the HEMT device ensures the supply of holes to ensure the formation of the polarization superjunction.

[0026] (2) The design of inlaying p-type diamond to form a pn superjunction reduces the area of ​​the p-type semiconductor layer and the hole channel layer above the polarized superjunction structure, thereby reducing the planar capacitance introduced by the hole channel layer and the p-type semiconductor layer and improving the frequency characteristics of the device.

[0027] (3) P-type diamond is embedded inside the HEMT device. When the first electrode is the gate, its top is connected to the gate and its bottom is close to the electron channel layer, which enhances the gate's ability to regulate the two-dimensional electron gas.

[0028] (4) Since polycrystalline diamond has an ultra-high thermal conductivity (reaching over 2000 W / (m·k)), filling the HEMT device with polycrystalline diamond greatly improves the device's heat dissipation capability and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A schematic diagram of the three-dimensional structure of a 3D super junction high-voltage and high-heat dissipation HEMT device provided in Example 1 of the present invention; and a schematic diagram of the three-dimensional structure of a 3D super junction high-voltage and high-heat dissipation HEMT device prepared by a preparation method provided in Example 2 of the present invention; Figure 2 for Figure 1 A cross-sectional view of the upper section A; Figure 3 for Figure 1 A cross-sectional view of the upper section B; Figure 4 for Figure 1 A cross-sectional view of the upper section C; Figure 5 A schematic diagram of the three-dimensional structure of another 3D super junction high voltage and high heat dissipation HEMT device provided in Example 1 of the present invention; Figures 6 to 9 A schematic diagram of a process for preparing a 3D super junction high voltage and high heat dissipation HEMT device provided in Example 2 of the present invention; Figures 10-12 A schematic diagram of a partial arrangement of the first trench in the 3D super junction high voltage and high heat dissipation HEMT device structure provided by the present invention; Fig.13A schematic structural diagram of a 3D super junction high voltage and high heat dissipation HEMT device structure in which the first trench is a secondary trench.

[0030] In the figure: 1. substrate; 2. buffer layer; 3. electron channel layer; 4. barrier layer; 5. hole channel layer; 6. p-type semiconductor layer; 7. first electrode; 8. first dielectric layer; 9. p-type diamond; 10. source; 11. drain; 12. source field plate; 13. second dielectric layer; 14. gate; 15. third dielectric layer; 16. first groove; 17. electrode lead-out hole. DETAILED DESCRIPTION

[0031] The following content is combined with the embodiments to clearly and completely describe the technical solution of the present application so that those skilled in the art can fully understand the present application. Obviously, the described embodiments are only some preferred embodiments of the present application, rather than all embodiments. Any equivalent transformation or substitution made to the following implementation modes by those of ordinary skill in the art without creative work belongs to the protection scope of the present application.

[0032] Directional terms described in this application, such as "upper", "lower", "inner", "outer", "bottom", "upper surface", etc., indicate directions or positional relationships based on directions or positional relationships in the drawings of the specification, or directions or positional relationships in which the products of this application are usually placed when in use, and are only for the convenience of describing and understanding the product structure of this application. Therefore, directional terms cannot be understood as limiting this application. In this application, unless otherwise clearly defined, expressions such as "upper", "above", "above", and "upper surface" of a first feature on a second feature indicate that the first feature and the second feature may be in direct contact or indirect contact through an intermediate medium; the first feature may be directly above or obliquely above the second feature, or simply indicate that the first feature is higher in level than the second feature. Expressions such as "lower", "below", "below", and "lower surface" of a first feature on a second feature indicate that the first feature and the second feature may be in direct contact or indirect contact through an intermediate medium; the first feature may be directly below or obliquely below the second feature, or simply indicate that the first feature is lower in level than the second feature. Ordinal numbers used in this application, such as "first", "second", etc., are only used for descriptive purposes to distinguish similar objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. The methods not described in detail in the following embodiments are all conventional methods well known to those skilled in the art.

[0033] Example 1 Reference Figures 1 to 4, a 3D superjunction high-voltage and high-heat dissipation HEMT device, comprising a substrate 1, an electron channel layer 3, a barrier layer 4, a hole channel layer 5 and a p-type semiconductor layer 6 stacked in sequence from bottom to top. A first electrode 7 is provided on the upper surface of the p-type semiconductor layer 6. Periodically distributed first grooves are provided in the p-type semiconductor layer 6 and the hole channel layer 5. The opening of the first groove is located on the upper surface of the p-type semiconductor layer 6, and the bottom is located in the hole channel layer 5 or on the upper surface of the barrier layer 4. A first dielectric layer 8 is provided on the inner wall and bottom of the first groove. The interior of the first groove is filled with p-type diamond 9. The p-type diamond 9 is in contact with the first electrode 7. The electron channel layer 3 forms a heterojunction with the barrier layer 4. The barrier layer 4 forms a heterojunction with the hole channel layer 5.

[0034] In the structure of the above HEMT device, the electron channel layer 3, the barrier layer 4 and the hole channel layer 5 constitute a depletion-type HEMT device with a polarized superjunction. Polarized positive charges and two-dimensional electron gas are formed at the heterojunction interface between the electron channel layer 3 and the barrier layer 4, and polarized negative charges and two-dimensional hole gas are formed at the heterojunction interface between the hole channel layer 5 and the barrier layer 4. When the device is in the off state, the two-dimensional hole gas and two-dimensional electron gas in the horizontal direction are depleted to form a depletion region, leaving only the polarized negative charges at the upper interface where the barrier layer 4 contacts the hole channel layer 5 and the polarized positive charges at the lower interface where the barrier layer 4 contacts the electron channel layer 3. The electric field strength in the depletion region becomes more uniform, thereby significantly improving the breakdown voltage of the device. A p-type semiconductor layer is provided on the upper surface of the hole channel layer 5 to ensure the supply of holes. By etching a first groove in the barrier layer 4 and the hole channel layer 5 and filling the first groove with p-type diamond 9, the embedded p-type diamond strip and the hole channel layer 5 form a pn super junction. Therefore, the above HEMT device structure is a device with a 3D super junction that combines a polarization super junction and a pn super junction. When the HEMT device is in the off state, the pn junction is reverse biased to form a depletion region between the first electrode and the drain, increasing the breakdown voltage of the device. By reducing the area of ​​the p-type semiconductor layer 6, the introduced flat capacitor can be reduced. Since diamond has an ultra-high thermal conductivity (reaching more than 2000W / (m·K)), it can quickly reduce the temperature inside the device and play a role in efficient heat dissipation.

[0035] Continue to refer to Figure 1In a specific HEMT device structure, the first electrode 7 is a gate. The HEMT device also includes a source 10, a drain 11, a source field plate 12, and a second dielectric layer 13. The source 10 and the drain 11 are respectively located on both sides of the upper surface of the barrier layer 4. The source field plate 12 extends from the upper surface of the source 10 toward the drain 11 and extends to the top of the p-type semiconductor layer 6. The second dielectric layer 13 extends from the upper surface of the barrier layer 4 close to the source 10 to the upper surface of the barrier layer 4 close to the drain 11, covering the upper surface of the gate, isolating the gate and the source field plate 12 (in order to facilitate the observation of the structure and distribution of the p-type diamond 9, Figure 1 Only a part of the second dielectric layer 13 is drawn). An electrode lead-out hole 17 is provided on the second dielectric layer 13 located on the upper surface of the first electrode 7. In a HEMT device of this structure, the p-type diamond 9 is in direct contact with the gate (first electrode 7) and is closer to the channel region, which can enhance the gate's control over the channel region. The source field plate 12 can further enhance the device's withstand voltage capability.

[0036] Reference Figure 5 In another specific HEMT device structure, the first electrode 7 is a base. The HEMT device also includes a source 10, a drain 11, a gate 14, and a third dielectric layer 15. The source 10 and the drain 11 are respectively located on both sides of the upper surface of the barrier layer 4. A second groove is provided on the side of the barrier layer 4 close to the source 10, and a third dielectric layer 15 is deposited on the inner wall and bottom of the second groove. The gate 14 is located in the second groove. The HEMT device with this structure is an enhancement-type device. By thinning the thickness of the barrier layer 4 below the gate 14 (the dimension of the barrier layer along the substrate 1 to the barrier layer 4), the polarization effect of the heterojunction can be reduced, thereby depleting the two-dimensional electron gas in the channel. The increased base is electrically connected to the source, which can control the polarization superjunction structure. In addition, the p-type diamond 9 is in contact with the base (the first electrode 7) and the hole channel layer 5 at the same time, and provides holes for the hole channel layer 5 during the process from the device being turned off to being turned on, thereby enhancing the switching characteristics of the device. Furthermore, the HEMT device also includes a source field plate and a second dielectric layer. The source field plate extends from the upper surface of the source 10 toward the drain 11, and extends to the top of the p-type semiconductor layer 6. The second dielectric layer extends from the upper surface of the barrier layer 4 close to the source 10 to the upper surface of the barrier layer 4 close to the drain 11, covering the upper surface of the gate 14 and the first electrode 7 (base). The second dielectric layer isolates the gate 14 and the source field plate, and at the same time, the second dielectric layer also isolates the first electrode 7 and the source field plate. Electrode lead-out holes are provided on the second dielectric layer located on the upper surface of the first electrode 7 and the second dielectric layer located on the upper surface of the gate 14. Similarly, the source field plate can further enhance the voltage resistance of the device.

[0037] Reference Figure 1, in some other specific HEMT device structures, a buffer layer 2 is provided between the substrate 1 and the electron channel layer 3. As an example, the material of the buffer layer 2 is AlN.

[0038] Referring to Fig.13 , in some other specific HEMT device structures, the first trench is a multi-level trench (such as Fig.13 the two-level trench shown in

[0039] ). When the bottom of the first trench is located on the upper surface of the barrier layer 4, the multi-level trench structure can increase the contact area between the p-type diamond and the hole channel layer 5, thereby increasing the heat dissipation capacity of the device. At the same time, the multi-level trench structure can also make the thickness of the first dielectric layer 8 on the inner surface of the first trench more uniform, which is beneficial to the deposition of p-type diamond. The number of levels of the first trench can also be three-level, four-level or other multi-level structures according to the total thickness of the p-type semiconductor layer 6 and the hole channel layer 5 (the dimension in the direction from the substrate 1 to the p-type semiconductor layer 6).

[0040] As an example, the material of the electron channel layer 3 is unintentionally doped gallium oxide or / and unintentionally doped gallium nitride.

[0041] As an example, the material of the barrier layer 4 is (Al x Ga 1-x ) 2 O 3 , Al y Ga 1-y N, AlN, or any combination thereof. Among them, 0.15 ≤ x ≤ 0.3, 0.1 ≤ y ≤ 0.3; for example, x = 0.15, x = 0.16, x = 0.17, x = 0.18, x = 0.2, x = 0.21, x = 0.22, x = 0.25, x = 0.26, x = 0.28, x = 0.3; y = 0.1, y = 0.11, y = 0.13, y = 0.15, y = 0.17, y = 0.18, y = 0.2, y = 0.21, y = 0.22, y = 0.25, y = 0.26, y = 0.28, y = 0.3.

[0042] As an example, the material of the hole channel layer 5 is unintentionally doped gallium oxide or / and unintentionally doped gallium nitride.

[0043] As an example, the material of the p-type semiconductor layer 6 is p-type GaN.

[0044] As an example, the material of the first electrode 7 is at least one of nickel and gold (Ni / Au), platinum and gold (Pt / Au), platinum, titanium and gold (Pt / Ti / Au).

[0045] As an example, the material of the first dielectric layer 8 is aluminum nitride or / and silicon nitride.

[0046] As an example, the p-type diamond 9 is p-type polycrystalline diamond.

[0047] As an example, the material of the source electrode 10 is at least one of Ti / Al / Ti / Au, Ti / Al / Pt / Au, and Ti / Al / Ni / Au.

[0048] As an example, the material of the drain electrode 11 is at least one of Ti / Al / Ti / Au, Ti / Al / Pt / Au, and Ti / Al / Ni / Au.

[0049] As an example, the material of the source field plate 12 is Al.

[0050] As an example, the material of the second dielectric layer 13 is silicon dioxide (SiO 2 )、Alumina(Al 2 O 3 ), any one or a combination of silicon nitride.

[0051] As an example, the material of the gate 14 is at least one of Ni / Au, Pt / Au, and Pt / Ti / Au.

[0052] As an example, the material of the third dielectric layer 15 is aluminum oxide (Al 2 O 3 ).

[0053] As an example, in some HEMT device structures, the material of the electron channel layer 3 is unintentionally doped gallium oxide (u-Ga 2 O 3 ), the material of the barrier layer 4 is (Al x Ga 1-x ) 2 O 3 (0.15≤x≤0.3), the material of the hole channel layer 5 is unintentionally doped gallium oxide (u-Ga 2 O 3 ), the material of the p-type semiconductor layer 6 is p-type GaN. The polarization superjunction structure is composed of u-Ga 2 O 3 、(Al x Ga 1-x ) 2 O 3 ,u-Ga 2 O 3 form.

[0054] As an example, in some other HEMT device structures, the material of the electron channel layer 3 is unintentionally doped gallium nitride (u-GaN), and the material of the barrier layer 4 is Aly Ga 1-y N (0.1≤y≤0.3), the hole channel layer 5 is made of unintentionally doped gallium nitride (u-GaN), and the p-type semiconductor layer 6 is made of p-type GaN. y Ga 1-y N and u-GaN are formed.

[0055] The shape of the first groove is not limited, as long as the p-type diamond 9 contacts the first electrode 7 and the p-type diamond 9 is periodically distributed in the barrier layer 4 and the hole channel layer 5. By adjusting the shape and distribution spacing of the first groove, the withstand voltage performance of the device can be adjusted. As an example, the projection shape of the first groove on the upper surface of the barrier layer 4 is a rectangle, a square, a circle, or a combination thereof. Figures 10-12 The periodic arrangement of the p-type diamond 9 is given as an example. Along the direction from the source 10 to the drain 11, the p-type diamond 9 can be a whole long strip structure (such as Fig.10 and Fig.12 As shown), it can also be divided into multiple intervals (such as Fig.11 In a direction perpendicular to the direction from the source 10 to the drain 11 and perpendicular to the direction from the substrate 1 to the barrier layer 4 (i.e. Fig.10 In the first direction on the upper side), the p-type diamond 9 may be a strip-shaped structure (such as Fig.12 It can also be a combination of long strip structures spaced apart along the first direction and long strip structures extending along the first direction (as shown); Fig.10 as shown).

[0056] Example 2 Reference Figures 1 to 9 , a method for preparing a 3D super junction high voltage and high heat dissipation HEMT device, comprising the following steps: S1. Reference Figure 5 and Figure 6 , an electron channel layer 3 , a barrier layer 4 , a hole channel layer 5 and a p-type semiconductor layer 6 are grown in sequence on the substrate 1 .

[0057] S2, reference Figure 7 , the p-type semiconductor layer 6 and the hole channel layer 5 are partially etched to expose the barrier layer 4 and form periodically distributed long strip-shaped first grooves 16 .

[0058] S3. Combined with reference Figure 1 , 5 , 7, 8, 9, depositing a first dielectric layer 8 with a thickness of 5 to 20 nm on the inner wall and bottom of the first trench 16; and then depositing a p-type diamond 9 inside the first trench 16.

[0059] S4. Combined with reference Figure 1 , 5 9, etch both sides of the p-type semiconductor layer 6 and the hole channel layer 5 to expose the barrier layer 4, and obtain the source region and the drain region. Deposit the first metal on the upper surface of the obtained structure, and make the source 10 and the drain 11 by lift-off process, and anneal to form ohmic contact. After the source 10 and the drain 11 are made, deposit the second metal on the upper surface of the obtained structure and pattern it to form (for example, by metal etching process) the first electrode 7. Figure 1 As shown in , the first electrode 7 is a gate. Figure 5 As shown in FIG. , the first electrode 7 is a base.

[0060] S5. Reference Figures 1 to 4 A second dielectric layer 13 is deposited on the upper surface of the structure obtained in step S4. The second dielectric layer 13 is etched to form an electrode lead-out hole 17 on the upper surface of the first electrode 7, and the source electrode 10 and the drain electrode 11 are exposed.

[0061] S6. Reference Figures 1 to 4 A source field plate 12 is fabricated on the upper surface of the second dielectric layer 13 .

[0062] In other methods for preparing 3D superjunction high-voltage and high-heat dissipation HEMT devices, step S1 also includes the step of growing a buffer layer 2 on the substrate 1. That is, the buffer layer 2, the electron channel layer 3, the barrier layer 4, the hole channel layer 5 and the p-type semiconductor layer 6 are sequentially grown on the substrate 1 (refer to Figures 1 to 4 ).

[0063] In other methods for preparing 3D superjunction high-voltage and high-heat dissipation HEMT devices, after obtaining the source region and the drain region in step S4, the barrier layer 4 located in the source region is etched to obtain a second trench. A third dielectric layer 15 is deposited on the inner wall and bottom of the second trench, and then a gate 14 is made in the second trench (refer to Figure 5 ). A first metal is deposited on the upper surface of the obtained structure, and a source electrode 10 and a drain electrode 11 are produced by a lift-off process, and annealing is performed to form an ohmic contact. After the source electrode 10 and the drain electrode 11 are produced, a second metal is deposited on the upper surface of the obtained structure and patterned to form (for example, by a metal etching process) a first electrode 7. When the second dielectric layer 13 is etched in step S5, electrode lead holes are formed on the upper surface of the first electrode 7 and the upper surface of the gate electrode 14, and the source electrode 10 and the drain electrode 11 are exposed.

[0064] As an example, the method for growing the electron channel layer 3 in step S1 is metal organic chemical vapor deposition (MOCVD) or hydride vapor phase epitaxy (HVPE).

[0065] As an example, the method for growing the barrier layer 4 in step S1 is MOCVD or molecular beam epitaxy (MBE).

[0066] As an example, the method for growing the hole channel layer 5 in step S1 is MOCVD.

[0067] As an example, the method for growing the p-type semiconductor layer 6 in step S1 is MOCVD or MBE.

[0068] As an example, the etching method in step S2 is dry etching or wet etching or a combination of dry and wet etching.

[0069] As an example, the method for depositing the first dielectric layer 8 in step S3 is hydride vapor phase epitaxy (HVPE) or atomic layer deposition (ALD). The deposited first dielectric layer 8 (such as an AlN film or a silicon nitride film) helps the adhesion of the nano-diamond seed crystal, thereby facilitating the growth of the p-type diamond 9. At the same time, it can also protect the p-type semiconductor layer 6 and the hole channel layer 5 around the first trench 16 and the barrier layer 4 at the bottom of the first trench 16.

[0070] As an example, the thickness of the first dielectric layer 8 is 5 nm, 6 nm, 7 nm, 8 nm, . . . 20 nm.

[0071] As an example, the p-type diamond 9 deposited in step S3 is p-type polycrystalline diamond, and the deposition method is chemical vapor deposition (CVD), especially microwave plasma chemical vapor deposition (MPCVD).

[0072] As an example, the method of etching the p-type semiconductor layer 6 and the hole channel layer 5 in step S4 is dry etching or wet etching or a combination of dry and wet etching.

[0073] As an example, the annealing conditions in step S4 are: 2 Or annealing at 400°C ~ 900°C in Ar atmosphere; for example, the annealing temperature is 400°C, 450°C, 470°C, 500°C, 550°C, 600°C ... 900°C.

[0074] As an example, the method of etching the barrier layer 4 is dry etching.

[0075] As an example, the method of depositing the third dielectric layer 15 is plasma enhanced chemical vapor deposition (PECVD) or ALD.

[0076] As an example, the method of manufacturing the gate 14 is electron beam evaporation (E-beam).

[0077] As an example, the method for depositing the second dielectric layer 13 in step S5 is plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD) or ALD.

[0078] As an example, the method of etching the second dielectric layer 13 in step S5 is dry etching.

[0079] As an example, the method for manufacturing the source field plate 12 in step S6 is electron beam evaporation (E-beam).

[0080] The above-described embodiments are only preferred embodiments of the present application and are not intended to limit the scope of protection of the present application. For any person skilled in the art, the present application may have various changes and modifications. Any simple equivalent changes and modifications made based on the scope of protection of the present application and the contents of the specification should be included in the scope of protection of the present application.

Claims

1. A 3D super junction high voltage and high heat dissipation HEMT device, characterized in that: The invention comprises a substrate, an electron channel layer, a barrier layer, a hole channel layer and a p-type semiconductor layer which are stacked in sequence from bottom to top, wherein a first electrode is arranged on the upper surface of the p-type semiconductor layer; periodically distributed first grooves are arranged in the p-type semiconductor layer and the hole channel layer, wherein the opening of the first groove is located on the upper surface of the p-type semiconductor layer, and the bottom of the first groove is located in the hole channel layer or on the upper surface of the barrier layer; a first dielectric layer is arranged on the inner wall and the bottom of the first groove, and the interior of the first groove is filled with p-type diamond; the p-type diamond is in contact with the first electrode; the electron channel layer forms a heterojunction with the barrier layer, and the barrier layer forms a heterojunction with the hole channel layer.

2. The HEMT device according to claim 1, characterized in that: The first electrode is a gate, and the HEMT device includes a source, a drain, a source field plate, and a second dielectric layer; the source and the drain are respectively located on both sides of the upper surface of the barrier layer; The source field plate extends from the upper surface of the source toward the drain and extends to above the p-type semiconductor layer; The second dielectric layer isolates the gate and the source field plate.

3. The HEMT device according to claim 2, characterized in that: The material of the second dielectric layer is at least one of silicon dioxide, aluminum oxide, and silicon nitride.

4. The HEMT device according to claim 1, characterized in that: A second trench is arranged in the barrier layer, a third dielectric layer is deposited on the inner wall and bottom of the second trench, the gate of the HEMT device is arranged in the second trench; and the first electrode is a base.

5. The HEMT device according to claim 4, characterized in that: The material of the third dielectric layer is aluminum oxide; Or / and, the HEMT device comprises a source, a drain, a source field plate and a second dielectric layer; the source and the drain are respectively located on both sides of the upper surface of the barrier layer; The source field plate extends from the upper surface of the source toward the drain and extends to above the p-type semiconductor layer; The second dielectric layer isolates the gate and the source field plate and isolates the first electrode and the source field plate.

6. The HEMT device according to claim 1, characterized in that: The first groove is a multi-level groove; Or / and, a buffer layer is provided between the substrate and the electron channel layer.

7. The HEMT device according to claim 1, characterized in that: The substrate is at least one of a gallium oxide substrate, a silicon carbide substrate, a silicon substrate, and a sapphire substrate; Or / and, the material of the electronic channel layer is unintentionally doped gallium oxide or / and unintentionally doped gallium nitride; Or / and, the material of the hole channel layer is unintentionally doped gallium oxide or / and unintentionally doped gallium nitride.

8. The HEMT device according to claim 1, characterized in that: The material of the barrier layer is (Al x Ga 1-x )2O3、Al y Ga 1-y At least one of N and AlN, wherein 0.15≤x≤0.3, 0.1≤y≤0.3; Or / and, the material of the p-type semiconductor layer is p-type gallium nitride; Or / and, the material of the first dielectric layer is aluminum nitride or / and silicon nitride.

9. The method for preparing a HEMT device according to any one of claims 1 to 8, characterized in that: The following steps are involved: S1, sequentially growing an electron channel layer, a barrier layer, a hole channel layer and a p-type semiconductor layer on a substrate; S2, etching the p-type semiconductor layer and the hole channel layer to obtain periodically distributed first grooves; S3, depositing a first dielectric layer on the inner wall and bottom of the first trench; then depositing p-type diamond in the first trench; S4. Fabricate a first electrode on the upper surface of the p-type semiconductor layer.

10. The preparation method according to claim 9, characterized in that: Before manufacturing the first electrode in step S4, the following steps are included: etching the p-type semiconductor layer and the hole channel layer to expose the barrier layer to obtain a source region and a drain region; manufacturing a source electrode and a drain electrode in the source region and the drain region respectively; after step S4, the following steps are included: S5, depositing a second dielectric layer on the upper surface of the structure obtained in step S4, etching the second dielectric layer, forming an electrode lead-out hole on the upper surface of the first electrode, and exposing the source electrode and the drain electrode; S6, manufacturing a source field plate on the upper surface of the second dielectric layer; or, Before making the first electrode in step S4, the following steps are included: etching the p-type semiconductor layer and the hole channel layer to expose the barrier layer to obtain a source region and a drain region; etching a second groove in the barrier layer located in the source region; depositing a third dielectric layer on the inner wall and bottom of the second groove to make a gate in the second groove; making a source electrode and a drain electrode in the source region and the drain region, respectively; after step S4, the following steps are included: S5, depositing a second dielectric layer on the upper surface of the structure obtained in step S4, etching the second dielectric layer, forming electrode lead-out holes on the upper surfaces of the first electrode and the gate, and exposing the source electrode and the drain electrode; S6. Fabricate a source field plate on the upper surface of the second dielectric layer.

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