Hybrid gate high electron mobility transistor, preparation method and test method thereof

Abstract

The invention discloses a hybrid gate high electron mobility transistor, a preparation method and a test method thereof. The transistor can be configured in a depletion mode or an enhancement mode, and the gate structure is composed of p-GaN semiconductor layers in different proportions. In the preparation process, an inductively coupled plasma reactive ion etching technology is adopted, the gate structure is protected, and defects are reduced. When the device works, driving voltage is applied to the grid electrode, a built-in electric field of the p-GaN / AlGaN / GaN heterojunction is regulated and controlled under bias voltage of the source electrode and the drain electrode, two-dimensional electron gas below the grid electrode is exhausted, and the exhausting degree changes along with the proportion of p-GaN. The two-dimensional electron gas can be recovered by applying the positive bias voltage. The whole preparation process strictly follows the standard gallium nitride technical process, and additional modification is not needed. By means of the design, grid electric leakage can be effectively reduced, stable and adjustable threshold voltage is provided, and flexible regulation and control of the normally-on state and the normally-off state of the device are achieved by adjusting the p-GaN proportion.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor preparation, and in particular to a hybrid gate high electron mobility transistor, a preparation method and a testing method thereof. Background Art

[0002] Currently, direct bandgap gallium nitride semiconductors are one of the most promising candidate materials in the field of power electronics. GaN has excellent material properties, including a high bandgap of up to 2.5×10 7 cm / s electron saturation drift velocity, 3.4eV wide band gap, excellent thermal stability, strong radiation resistance and high breakdown field strength up to 2.2MV / cm. In addition, the spontaneous and piezoelectric polarization effects at the GaN / GaN heterojunction interface can form a high-mobility and high-concentration two-dimensional electron gas (2DEG). In addition, GaN is also compatible with low-cost and highly mature silicon-based semiconductor integrated circuit technology. GaN-based devices have been widely used in next-generation high-power, small-size lasers, radio frequency (RF) and microwave devices, power converters, semiconductor lighting and other fields.

[0003] In a gallium nitride-based high electron mobility transistor (HEMT), when a drain-source voltage (VDS) is applied between the drain and the source, the two-dimensional electron gas is driven by the lateral electric field and transmitted directionally along the heterojunction interface of AlGaN (aluminum gallium nitride) / GaN (gallium nitride), forming an on-current. By adjusting the magnitude of the applied gate voltage, the opening and closing of the 2DEG channel can be effectively controlled, thereby realizing the switching control of the device. However, in the traditional AlGaN / GaN HEMT structure, the 2DEG caused by the polarization effect naturally exists, making the device work in a normally-on mode, which means that the device is always in the on state under zero gate bias, and a negative gate bias must be applied to turn off the device.

[0004] In actual circuit applications, such as startup circuits, in order to achieve the bias function, a depletion-mode (D-mode) device with a negative threshold voltage is usually required to clamp a specific potential. However, although the metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT) in the prior art can achieve threshold voltage (Vth) regulation to a certain extent by adjusting the thickness of the dielectric layer, this method has obvious limitations. Specifically, in order to obtain MIS-HEMT devices with different Vth, dielectric layers of different thicknesses need to be designed separately, and additional mask layers are introduced to define specific Vth regions, which not only increases the process complexity and cost, but also makes mask alignment and process control more difficult. At the same time, the interface state formed during the deposition of the dielectric layer has a significant impact on the device performance, which further leads to a decrease in the uniformity of Vth on the wafer, and the reliability of the device is difficult to guarantee, which limits the promotion of MIS-HEMT in high-reliability and large-scale integration applications. Summary of the invention

[0005] The object of the present invention is to provide a hybrid gate high electron mobility transistor, a preparation method and a test method thereof, so as to realize flexible regulation of the normally-on and normally-off states of the device.

[0006] In order to solve the above technical problems, the present invention provides a hybrid gate high electron mobility transistor, comprising: a substrate; An N-type channel layer, a barrier layer, and a P-type semiconductor layer are sequentially stacked along a first direction, wherein the first direction is a direction from the substrate to the P-type semiconductor layer; The P-type semiconductor layer includes a plurality of sub-P-type semiconductor layers arranged in sequence along a second direction, wherein the plurality of sub-P-type semiconductor layers have different occupancy ratios; and the second direction is a direction from the source to the drain.

[0007] Furthermore, the sub-P-type semiconductor layer includes a plurality of sub-P-type semiconductor layer islands arranged equidistantly along the second direction, wherein an occupancy ratio of the sub-P-type semiconductor layer is in a range greater than 0% and less than 100%.

[0008] Furthermore, the occupancy ratio is: P p-GaN =W p-GaN / W total ; Among them, P p-GaN is the occupancy ratio, W total is the gate width, W p-GaN It is the sum of the widths of all sub-P-type semiconductor layers.

[0009] Further, the sub-P-type semiconductor layer includes a plurality of sub-P-type semiconductor layer islands arranged at equal intervals along the second direction, wherein the occupation ratio of the sub-P-type semiconductor layer ranges from greater than 0% to less than 100%.

[0010] Further, the P-type semiconductor layer includes a plurality of sub-P-type semiconductor layers arranged in sequence along the second direction, wherein the plurality of sub-P-type semiconductor layers have different occupation ratios; the second direction is the direction from the source electrode to the drain electrode.

[0011] Further, the P-type semiconductor layer includes a sub-P-type semiconductor layer with an occupation ratio of 0%, a sub-P-type semiconductor layer with an occupation ratio of 75%, a sub-P-type semiconductor layer with an occupation ratio of 50%, and / or a sub-P-type semiconductor layer with an occupation ratio of 100%.

[0012] Further, it further includes: a passivation electrolyte layer and a Schottky metal layer; The passivation electrolyte layer is disposed in a region on the surface of the barrier layer that is not covered by the P-type semiconductor layer; The Schottky metal layer is disposed on the surface of the P-type semiconductor layer.

[0013] On the other hand, the present invention also discloses a method for manufacturing a hybrid gate high electron mobility transistor, the method including: Providing a substrate; Stacking an N-type channel layer, a barrier layer, and a P-type semiconductor layer on the substrate in sequence; Marking the formation regions of the respective sub-P-type semiconductor layers on the P-type semiconductor layer; Marking the etching regions of the sub-P-type semiconductor layers on the formation regions; Performing plasma etching on the etching regions to form a plurality of the sub-P-type semiconductor layers arranged in sequence along the second direction and having different occupation ratios on the surface of the barrier layer; wherein, the second direction is the direction from the source electrode to the drain electrode; the occupation ratio of the sub-P-type semiconductor layer ranges from greater than 0% to less than 100%.

[0014] Further, performing plasma etching on the etching regions includes: Introducing an etching gas into the reaction chamber; wherein, the etching gas includes boron trichloride and chlorine; the gas flow ratio of the boron trichloride to the chlorine ranges from 1:1 to 3:1; Applying a radio frequency power to the reaction chamber, the radio frequency power being used to ionize the etching gas to form a plasma, and the plasma being used to perform plasma etching treatment on the etching regions; wherein, the radio frequency power ranges from 10 to 15 W.

[0015] Further, the method further includes: Depositing a passivation dielectric layer on the surface of the P-type semiconductor layer and the surface of the barrier layer by an evaporation method; The passivation dielectric layer on the surface of the P-type semiconductor layer is etched.

[0016] Furthermore, the method further comprises: Depositing a Schottky metal layer on the P-type semiconductor layer by an electron beam evaporation coating method, and performing a uniform temperature-raising annealing process on the Schottky metal layer; The growth regions of the source and drain are marked on the passivation dielectric layer, the growth regions are plasma etched to form empty regions, and a metal layer is deposited in the empty regions to form the source and drain.

[0017] On the other hand, the present invention further discloses a method for testing a hybrid gate high electron mobility transistor, the method comprising: Probe operation on HEMT; collecting an electrical signal of the HEMT; Analyzing and processing the electrical signal to obtain electrical test curves of different high electron mobility transistors; It is determined whether the HEMT can realize gate controllability between a normally-off state and a normally-on state according to the electrical test curve.

[0018] Compared with the prior art, the present invention has at least the following beneficial effects: By designing the P-type semiconductor layer as multiple sub-P-type semiconductor layers with different occupancy ratios arranged in the horizontal direction (second direction), the threshold voltage (Vth) of each region of the device can be flexibly adjusted to achieve the integration of enhancement mode (E-mode) and depletion mode (D-mode) HEMTs on the same GaN device. This design does not require the introduction of additional process steps, is compatible with the existing GaN platform, has a simple process, high Vth control accuracy, effectively reduces gate leakage current and improves the reliability and high-voltage tolerance of the device, and is particularly suitable for high-power, high-frequency and high-integration applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a cross-sectional schematic diagram of a HEMT in Embodiment 1 of the present invention; Figure 2 is a top view of a HEMT in which the occupancy ratio of the P-type semiconductor layer is 100% in the first embodiment of the present invention; Figure 3 is a top view of a HEMT in which the occupancy ratio of the P-type semiconductor layer is 75% in the first embodiment of the present invention; Figure 4 It is a top view of a HEMT in which the occupancy ratio of the P-type semiconductor layer is 50% in the first embodiment of the present invention; Figure 5It is a schematic diagram of the preparation process of the hybrid gate high electron mobility transistor in the second embodiment of the present invention; Figure 6 Schematic diagram of the preparation process of the hybrid gate high electron mobility transistor in the second embodiment of the present invention; Figure 7 It is a schematic diagram of another preparation process of the hybrid gate high electron mobility transistor in the second embodiment of the present invention; Figure 8 It is a schematic diagram of another preparation process of the hybrid gate high electron mobility transistor in the second embodiment of the present invention; Fig. 9 It is a schematic diagram of another preparation process of the hybrid gate high electron mobility transistor in the second embodiment of the present invention; Fig.10 It is a schematic diagram of another preparation process of the hybrid gate high electron mobility transistor in the second embodiment of the present invention; Fig.11 It is a schematic diagram of another preparation process of the hybrid gate high electron mobility transistor in the second embodiment of the present invention; Fig.12 is a transmission curve diagram of the first sub-P-type semiconductor, the second sub-P-type semiconductor and the third sub-P-type semiconductor in the third embodiment of the present invention; Fig.13 The output curve diagram of the first sub-P-type semiconductor, the second sub-P-type semiconductor and the third sub-P-type semiconductor in the third embodiment of the present invention; Fig.14 is a breakdown curve diagram of the first sub-P-type semiconductor in the third embodiment of the present invention; Fig.15 is a breakdown curve diagram of the second sub-P-type semiconductor in the third embodiment of the present invention; Fig.16 This is a breakdown curve diagram of the third sub-P-type semiconductor in the third embodiment of the present invention. DETAILED DESCRIPTION

[0020] The hybrid gate high electron mobility transistor, preparation method and test method thereof of the present invention will be described below in conjunction with schematic diagrams, wherein preferred embodiments of the present invention are shown, and it should be understood that those skilled in the art can modify the present invention described herein while still achieving the advantageous effects of the present invention. Therefore, the following description should be understood as being widely known to those skilled in the art, and not as a limitation of the present invention.

[0021] The present invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present invention will become more apparent from the following description and claims. It should be noted that the drawings are in very simplified form and in non-precise proportions, and are only used to facilitate and clearly assist in illustrating the purpose of the embodiments of the present invention.

[0022] Embodiment 1 The inventors found that: in a gallium nitride-based device, when a driving voltage is applied to the gate and it is under source-drain bias stress conditions, the p-GaN layer located in the gate region will generate hot electrons due to carrier acceleration. The hot electrons can be effectively compensated by the hole channel provided in the gate structure, thereby significantly reducing the gate leakage current under gate / drain voltage stress conditions and effectively maintaining the stability of the device threshold voltage (Vth). In addition, the inventors further found that by adjusting the coverage ratio of the p-GaN (P-type doped gallium nitride) layer in the gate structure of the gallium nitride device, the threshold voltage of the device can be precisely controlled, so that the device has adjustable characteristics from the normally off state (Normally-off) to the normally on state (Normally-on), thereby enhancing the flexibility and applicability of the device.

[0023] Please refer to Figure 1 Based on the above findings, this embodiment discloses a hybrid gate high electron mobility transistor (HG-HEMT), including: A substrate 1; an N-type channel layer 2, a barrier layer 3, a P-type semiconductor layer 4, and a Schottky metal layer stacked in sequence along a first direction, wherein the first direction is the direction from the substrate 1 to the P-type semiconductor layer 4. The P-type semiconductor layer 4 includes a plurality of sub-P-type semiconductor layers arranged in sequence along a second direction, wherein the plurality of sub-P-type semiconductor layers have different occupancy ratios; and the second direction is the direction from the source to the drain.

[0024] In this embodiment, after the N-type channel layer 2 is introduced, a heterostructure consisting of the N-type channel layer 2, the barrier layer 3 and the P-type peninsula body layer 4 is formed, and an electrically equivalent PIN junction (P-type-barrier layer-N-type) is formed between the three layers. The built-in electric field of the PIN structure can effectively increase the potential at the heterojunction interface to make it higher than the Fermi level, thereby depleting the 2DEG under the gate, thereby realizing the normally off characteristics of the device. By applying a positive gate bias, the built-in electric field can be overcome, so that the 2DEG can be re-accumulated and restored to conduction. In addition, by designing the P-type semiconductor layer 4 as a plurality of sub-P-type semiconductor layers with different occupancy ratios arranged in the horizontal direction (second direction), the Vth of each region of the device can be flexibly adjusted, and the integration of enhancement mode (E-mode) and depletion mode (D-mode) HEMT (high electron mobility transistor) on the same semiconductor device can be realized. This design does not require the introduction of additional process steps, is compatible with the existing GaN platform, has a simple process, and has high Vth control accuracy. It can effectively reduce gate leakage current and improve the reliability and high voltage tolerance of the device.

[0025] It is understood that Vth in this embodiment refers to the gate voltage when the two-dimensional electron gas in the channel below the gate is just exhausted. When the gate voltage is lower than Vth, the 2DEG in the channel will be completely exhausted, leaving only a very small leakage current. At this time, the device is in the off state.

[0026] The N-type channel layer 2 prepared in this embodiment is composed of GaN material, and the N-type channel layer 2 includes a buffer layer, the thickness of the buffer layer is 5 μm, and the thickness of the N-type channel layer 2 as a whole is 200 nm. It is understandable that those skilled in the art can introduce a buffer layer and / or a transition layer between the N-type channel layer 2 and the substrate 1 according to actual conditions.

[0027] The barrier layer 3 prepared in this embodiment is made of AlGaN material. The specific thickness of the barrier layer 3 is 15 mm. The content of aluminum in the AlGaN material is between 10% and 30%.

[0028] The P-type semiconductor layer 4 prepared in this embodiment is composed of p-GaN doped with Mg (magnesium).

[0029] A p-GaN / AlGaN / GaN heterostructure is formed by introducing a P-type semiconductor layer 4 (p-GaN) between the gate and the AlGaN / GaN heterojunction. The Schottky metal layer and the P-type semiconductor layer 4 form a metal-semiconductor (MS) heterojunction, and the P-type semiconductor layer 4 and the AlGaN / GaN layer form an electrically equivalent PIN (P-type-functional barrier layer 3-N-type) heterojunction structure. Both GaN and AlGaN are III-group nitride semiconductor materials, and a polarization-induced electrostatic field is generated at the heterojunction interface due to the polarization effect. The electrostatic field modulates the band structure and carrier distribution, prompting a large number of electrons to transfer to the AlGaN / GaN interface with lower energy, forming a 2DEG channel extending along the first direction.

[0030] The built-in electric field of the PIN structure can effectively increase the potential at the heterojunction interface to make it higher than the Fermi level of the 2DEG, thereby depleting the 2DEG under the gate and realizing the normally-off characteristic of the device. When a positive gate bias is applied, the built-in electric field can be overcome, causing the depleted 2DEG to re-accumulate and resume conduction, forming a current path. After applying the drain-source bias voltage (VDS), the 2DEG is transmitted directionally along the heterojunction interface under the action of the lateral electric field to complete current conduction. As the control terminal, the gate can effectively control the switching state of the 2DEG channel by adjusting the applied gate voltage, thereby realizing the switching function of the device.

[0031] In this embodiment, the calculation method of the occupancy ratio is: P p-GaN =W p-GaN / Wtotal； Among them, P p-GaN is the occupancy ratio, W total is the gate width, W p-GaN It is the sum of the widths of all sub-P-type semiconductor layers.

[0032] With P p-GaN With the change of (p-GaN proportion), the electrical connection method of the gate will also be different. E-mode HEMT (enhancement mode high electron mobility transistor) uses 100% p-GaN islands, and its gate is composed entirely of p-GaN. The gate voltage controls the opening of the 2DEG channel. D-mode HEMT (depletion mode high electron mobility transistor) uses 0% p-GaN. Its gate structure does not include p-GaN. The gate voltage is applied negatively to control the closing of 2DEG. HG-HEMT (hybrid high electron mobility transistor) uses different proportions of p-GaN islands in the gate design. These islands are filled with other materials to control the effect of gate voltage on the two-dimensional electron gas.

[0033] Please refer to Figure 2-Figure 3 Furthermore, the plurality of sub-P-type semiconductor layers include a plurality of sub-P-type semiconductor layer islands equidistantly arranged along the second direction, wherein an occupancy ratio of the sub-P-type semiconductor layer is in a range greater than 0% and less than 100%.

[0034] In this embodiment, in order to achieve uniformity of electric field distribution and improve the reliability and controllability of the device, the plurality of sub-P-type semiconductor layer islands are preferably arranged equidistantly along the second direction. The equidistant arrangement design can effectively avoid the problem of excessive or weak local electric field, reduce the risk of breakdown, make the 2DEG depletion region evenly distributed, and thus achieve stable and adjustable Vth. At the same time, the equidistant arrangement is conducive to the precise control of process processes such as lithography and etching, improves manufacturing consistency and mass production yield, and further enhances device performance and application reliability.

[0035] Please refer to Figure 4 Furthermore, the P-type semiconductor layer 4 also includes a sub-P-type semiconductor layer with an occupancy ratio of 100%.

[0036] When the occupancy ratio of the sub-P-type semiconductor layer is equal to 100%, the sub-P-type semiconductor layer achieves full coverage in the gate region, and can completely deplete the 2DEG in the N-type channel layer 2, so that the device is in an off state under zero gate-source bias, thereby making the device exhibit E-mode transistor characteristics with Vth greater than 0V.

[0037] Please refer to Figure 5 Furthermore, the P-type semiconductor layer 4 may also include a sub-P-type semiconductor layer with an occupancy ratio of 0%.

[0038] When the proportion of the P-type semiconductor layer is 0%, the gate structure of the device does not contain a P-type semiconductor layer at all, which usually causes the device to operate in D-mode. In this mode, the device is in the on state without applying a gate voltage, and only when a sufficiently negative gate voltage is applied will the 2DEG be depleted and the device will be turned off.

[0039] In a specific embodiment, the P-type semiconductor layer 4 includes three sequentially arranged sub-P-type semiconductor layers, with occupancy ratios of 100%, 75% and 50% respectively.

[0040] Among them, the area with an occupancy ratio of 100% can make the GaN device completely shut down at zero gate bias, improving the stability of the normally-off device; the areas with occupancy ratios of 75% and 50% provide progressive 2DEG compensation capability, making Vth continuously adjustable between positive and negative values, thereby optimizing the performance of the device in different operating modes.

[0041] It is understandable that those skilled in the art can select sub-P-type semiconductor layers with different occupancy ratios according to actual conditions to form a desired gate structure. The number of sub-P-type semiconductor layers can also be selected according to actual conditions to enhance the compensation for 2DEG or adjust Vth to obtain the desired switching characteristics and electrical performance.

[0042] Furthermore, in this embodiment, it also includes a passivation electrolyte layer disposed between the sub-P-type semiconductor layer islands, and the surface of the sub-P-type semiconductor layer islands.

[0043] In a specific embodiment, the P-type semiconductor layer 4 is generally formed of magnesium-doped P-type GaN, and the passivation dielectric layer 5 is composed of AlN. The thickness of the two layers is generally 50-100 nm.

[0044] Furthermore, in this embodiment, a Schottky metal layer 6 is stacked on the surface of the P-type semiconductor layer 4 to form a Schottky contact and a MIS (metal-insulator-semiconductor) gate.

[0045] In a specific embodiment, the thickness of the Schottky metal layer 6 is 5-10 mm.

[0046] Furthermore, in this embodiment, a source 8 and a drain 7 are also included, which are located at two ends of the HEMT and serve as the input and output ends of the current respectively.

[0047] In a specific embodiment, the source electrode 8 and the drain electrode 7 are formed by sequentially stacking TiN (titanium nitride), Al (aluminum), Ti (titanium) and TiN (titanium nitride).

[0048] Embodiment 2 Based on the same inventive concept, this embodiment discloses a method for preparing a hybrid gate HEMT, and the method for preparing the hybrid gate HEMT disclosed in the first embodiment includes: S1. Providing a substrate 1; S2. An N-type channel layer 2, a barrier layer 3 and a P-type semiconductor layer 4 are sequentially stacked on the substrate 1; S3. Marking the formation region of each sub-P-type semiconductor layer on the P-type semiconductor layer 4; S4. marking the etching region of the sub-P-type semiconductor layer on the formation region; S5. Plasma etching is performed on the etching area to form a plurality of sub-P-type semiconductor layers arranged in sequence along the second direction and having different occupancy ratios on the surface of the barrier layer 3; wherein the second direction is the direction from the source to the drain; and the occupancy ratio of the sub-P-type semiconductor layer is in the range of greater than 0% and less than 100%.

[0049] Through the above process flow, etching of gate structures with different proportions is organically integrated with the device preparation process. The prepared HEMT structure can be configured as D-mode or E-mode according to design requirements, and has high voltage tolerance. Its gate structure is composed of P-type semiconductor layers 4 in different proportions, and the threshold voltage Vth is accurately adjusted by the occupancy ratio of the P-type semiconductor layer. Specifically, under the condition of source-drain bias stress, when a driving voltage is applied to the gate, the design of different occupancy ratios can effectively enhance the electric field in the depletion region, improve the carrier depletion efficiency, and then regulate Vth, so that HEMT can flexibly switch between D-mode and normally-off E-mode working states. In addition, under the action of gate / drain voltage stress, the design can effectively reduce the gate leakage current, stabilize the Vth of the device, and improve the reliability and withstand voltage performance of the device. In summary, the present invention helps to form a gallium nitride device with stable physical and chemical properties, facilitates subsequent applications and performance testing, and has good application prospects.

[0050] Please refer to Figure 6 In a specific embodiment of step S2, a P-type silicon substrate 1 is used as a base. An N-type channel layer 2 composed of GaN, a barrier layer 3 composed of AlGaN, and a P-type semiconductor layer 4 composed of p-GaN are epitaxially grown in sequence by MOCVD (metal organic chemical vapor deposition) to form a p-GaN / AlGaN / GaN heterostructure.

[0051] Furthermore, in this embodiment, a mask is applied on the surface of the P-type semiconductor layer 4 and plasma etching is performed to form sub-P-type semiconductor layer islands of different types of devices (for an E-mode HEMT with an occupancy ratio of 100%, a continuous gate structure is formed).

[0052] In step S4, the distances between the etching regions in the same formation region are set to be equal, so as to form a plurality of sub-P-type semiconductor layer islands that are equidistantly distributed along the second direction.

[0053] It should be noted that, for an E-mode HEMT with a duty ratio of 100%, a continuous gate structure is formed, and the S3-S5 steps are not required for this structure.

[0054] It should be further explained that, for a D-mode HEMT with a proportion of 0%, the structure does not need to provide a P-type semiconductor layer 4. At this time, the HEMT is formed by sequentially stacking an N-type channel layer 2, a barrier layer 3 and a passivation layer 4 on a substrate.

[0055] Furthermore, during the preparation of step S5, an etching gas is introduced into the reaction chamber.

[0056] Those skilled in the art can select different etching gases according to actual conditions. Preferably, the etching gas includes boron trichloride and chlorine; the gas flow ratio of the boron trichloride to the chlorine is in the range of 1:1-3:1. Specifically, the benefit of the gas flow ratio of boron trichloride to chlorine being in the range of 1:1 to 3:1 is that it can provide good etching selectivity and controllability. Within this flow ratio range, boron trichloride provides effective etching power, while chlorine helps to increase the etching rate and reduce damage to other materials during the etching process.

[0057] Further, when performing the preparation of step S5, a radio frequency power is applied to the reaction chamber, and the radio frequency power is used to ionize the etching gas to form a plasma, and the plasma is used to perform a plasma etching process on the etching area. Those skilled in the art can select different ranges of radio frequency power according to actual conditions. Preferably, the range of the radio frequency power is 10-15W.

[0058] Under the above-mentioned preferred range of plasma power conditions, the etching selectivity of the P-type semiconductor layer 4 exceeds 20. This means that during the etching process of p-GaN, p-GaN is removed with minimal etching damage to the GaN device.

[0059] Please refer to Figure 7 Further, after completing step S5 and preparing the P-type semiconductor layer 4, a passivation dielectric layer 5 is deposited on the surface of the P-type semiconductor layer 4 and the surface of the barrier layer 3 by evaporation.

[0060] Please refer to Figure 8Furthermore, after the passivation dielectric layer 5 is deposited, the passivation dielectric layer 5 located above the sub-P-type semiconductor layer island is etched away, so that the subsequently arranged Schottky metal layer 6 can directly contact the P-type semiconductor to form a stable Schottky contact and MIS gate electrode.

[0061] Please refer to Fig. 9 Furthermore, after completing the above preparation steps, after depositing the Schottky metal layer 6 on the P-type semiconductor layer 4 by electron beam evaporation coating method, the Schottky metal layer 6 is annealed.

[0062] Specifically, the Schottky metal layer 6 needs to be deposited over the entire gate to simultaneously form a metal / semiconductor Schottky contact and a MIS gate.

[0063] In a specific embodiment, nitrogen is used as the inert gas during the annealing process. Of course, those skilled in the art can also select different inert gases for annealing according to actual conditions, and no specific limitation is made here.

[0064] In another specific embodiment, annealing is performed by uniform temperature rise annealing method, specifically, the inert gas atmosphere is uniformly heated within a preset time. For example, the nitrogen temperature is uniformly raised from 350°C to 400°C within 5 minutes. It is understandable that those skilled in the art can set different annealing times, annealing temperatures and inert gas atmosphere heating rates according to actual conditions, and no specific restrictions are made here.

[0065] The uniform temperature rise annealing method improves the stability of the physical, chemical and electrical properties of the Schottky metal layer 6, making it very suitable for subsequent preparation processes.

[0066] Please refer to Figure 10-11 Furthermore, after the annealing operation is completed, the growth areas of the source 8 and the drain 7 are marked on the passivation dielectric layer, and the growth areas are plasma etched to form empty areas, and metal layers are sequentially deposited in the empty areas.

[0067] In a specific embodiment, chlorine-based ICP-RIE (inductively coupled plasma-reactive ion etching) is used on the passivation dielectric layer 5 and is etched down into the N-type channel layer 2 to form a rectangular groove, and the Schottky metal layer 6 is sequentially deposited in the rectangular groove.

[0068] In another specific embodiment, metals such as TiN (titanium nitride), Al (aluminum), Ti (titanium) and TiN (titanium nitride) are sequentially deposited and annealed in a nitrogen environment to form a source electrode 8 and a drain electrode 7 with ohmic contact. Of course, those skilled in the art can also select different metals to form metal layers according to actual conditions, thereby forming different contact types.

[0069] Embodiment 3 Based on the same inventive concept, this embodiment discloses a test method for a HG-HEMT with an adjustable Vth function, which is intended to evaluate the performance of the HEMT disclosed in Embodiment 1 and Embodiment 2. The specific method is as follows: S1. Perform probe operation on HEMT device; S2. Collecting the electrical signal of the HEMT; S3. Analyzing and processing the electrical signal to obtain electrical test curves of different high electron mobility transistors; S4. Determine whether the high electron mobility transistor can achieve gate controllability between a normally-off state and a normally-on state according to the electrical test curve.

[0070] It can be understood that the probe operation is to physically contact the probe with the specific test points (such as source, drain, gate, etc.) of the HEMT device through a microscope or a probe station to form a test loop. The collection of electrical signals is to obtain the electrical characteristics of the device by measuring and recording the changes in electrical signals (such as voltage, current, etc.) after the probe operation.

[0071] In a specific embodiment of step S1, a microscope is used to perform a probe operation on the HEMT device.

[0072] In a specific embodiment of step S2, a high-power probe station is used to perform electrical testing.

[0073] In a specific embodiment of step S3, a power device analyzer is used to analyze and process the electrical signal of the HEMT device.

[0074] In a specific embodiment of step S4, by evaluating the performance of the device under different temperatures, different gate voltages and different drain voltage stress conditions, it is determined whether the HEMT can effectively reduce gate leakage and maintain a stable Vth, thereby realizing the gate controllable function of the HEMT between the normally-off state and the normally-on state.

[0075] In a specific embodiment, the gate structure of the gallium nitride device involved in the test includes, from top to bottom, a Schottky metal layer 6, a P-type semiconductor layer 4 (composed of p-GaN), a barrier layer 3 (composed of AlGaN), and an N-type channel layer 2 (composed of GaN), and the above four-layer structure together constitutes a double junction structure, including a metal / semiconductor Schottky junction and a p-GaN / AlGaN / GaN heterojunction. In addition, the P-type semiconductor layer 4 includes a first sub-P-type semiconductor layer, a second sub-P-type semiconductor layer, and a third sub-P-type semiconductor layer arranged in sequence along the second direction, wherein the occupancy ratios of the first sub-P-type semiconductor layer, the second sub-P-type semiconductor layer, and the third sub-P-type semiconductor layer are 100%, 75%, and 50%, respectively. Under the stress conditions of applying the drain bias voltage and the gate drive voltage, the P-type semiconductor layer 4 with different occupancy ratios can enhance the electric field in the depletion region, further aggravating the degree of carrier depletion, thereby modulating the Vth of the gallium nitride-based device, realizing the gate adjustable capability of the device between the normally-off state and the normally-on state, while effectively reducing the gate leakage and providing a stable Vth under the gate / drain voltage stress conditions.

[0076] In a specific embodiment, see Fig.12 , under the condition of drain current ID=1μA / mm, the Vth of the three devices (the first sub-P-type semiconductor layer is curve A, the second sub-P-type semiconductor layer is curve B, and the third sub-P-type semiconductor layer is curve C) are +1.5V, -13.6V and -52.9V respectively. The test results show that by adjusting the coverage ratio of the P-type GaN (p-GaN) layer in the gate structure (from 100% to 50%), the device Vth can be adjusted from positive to negative values, thereby realizing the Vth adjustable characteristics of the GaN HEMT device.

[0077] In another specific embodiment, see Fig.13 , a gate voltage V is applied to the first sub-P-type semiconductor layer with an occupancy ratio of 100%. GS = +6V, and apply gate voltage V to the second and third P-type semiconductor layers with occupancy ratios of 75% and 50% respectively. GS =0V, under the above test conditions, the on-resistance (Ron) of the three devices (the first sub-P-type semiconductor layer is curve A, the second sub-P-type semiconductor layer is curve B, and the third sub-P-type semiconductor layer is curve C) are 10.9Ωmm, 18.0Ωmm, and 15.1Ωmm, respectively. The test results show that the HEMT device in the embodiment of the present invention has excellent conduction performance and low on-resistance. For further information, see Figure 14-16The breakdown voltages (BV) of the three devices (the first sub-P-type semiconductor layer is curve A, the second sub-P-type semiconductor layer is curve B, and the third sub-P-type semiconductor layer is curve C) are 920V, 915V, and 913V, respectively. The above results show that the gallium nitride-based device described in the present invention has a high withstand voltage level and good voltage blocking reliability, thus having excellent high-voltage application performance.

[0078] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A hybrid gate high electron mobility transistor, characterized in that include: substrate; An N-type channel layer, a barrier layer, and a P-type semiconductor layer are sequentially stacked along a first direction, wherein the first direction is a direction from the substrate to the P-type semiconductor layer; The P-type semiconductor layer includes a plurality of sub-P-type semiconductor layers arranged in sequence along a second direction, wherein the plurality of sub-P-type semiconductor layers have different occupancy ratios; and the second direction is a direction from the source to the drain.

2. The hybrid gate high electron mobility transistor according to claim 1, wherein: The occupancy ratio is: P p-GaN =W p-GaN / W total ; Among them, P p-GaN is the occupancy ratio, W total is the gate width, W p-GaN It is the sum of the widths of all sub-P-type semiconductor layers.

3. The hybrid gate high electron mobility transistor according to claim 1, wherein: The sub-P-type semiconductor layer includes a plurality of sub-P-type semiconductor layer islands arranged equidistantly along the second direction, wherein an occupancy ratio of the sub-P-type semiconductor layer is in a range of greater than 0% and less than 100%.

4. The hybrid gate high electron mobility transistor according to claim 1, wherein: The P-type semiconductor layer includes a sub-P-type semiconductor layer with an occupancy ratio of 0%, a sub-P-type semiconductor layer with an occupancy ratio of 75%, a sub-P-type semiconductor layer with an occupancy ratio of 50% and / or a sub-P-type semiconductor layer with an occupancy ratio of 100%.

5. The hybrid gate high electron mobility transistor according to claim 1, wherein: Also includes: Passivation electrolyte layer and Schottky metal layer; The passivation electrolyte layer is disposed in a region of the barrier layer surface that is not covered by the P-type semiconductor layer; The Schottky metal layer is arranged on the surface of the P-type semiconductor layer.

6. A method for preparing a hybrid gate high electron mobility transistor, characterized in that: The method comprises: providing a substrate; An N-type channel layer, a barrier layer and a P-type semiconductor layer are sequentially stacked on the substrate; marking formation regions of each sub-P-type semiconductor layer on the P-type semiconductor layer; marking an etching region of the sub-P-type semiconductor layer on the formation region; Plasma etching is performed on the etching area to form a plurality of sub-P-type semiconductor layers arranged in sequence along the second direction and having different occupancy ratios on the surface of the barrier layer; wherein the second direction is the direction from the source to the drain, and the occupancy ratio of the sub-P-type semiconductor layer ranges from greater than 0% to less than 100%.

7. The method for preparing a hybrid gate high electron mobility transistor according to claim 6, characterized in that: Plasma etching the etching area includes: Introducing an etching gas into the reaction chamber; wherein the etching gas comprises boron trichloride and chlorine; and the gas flow ratio of the boron trichloride to the chlorine is in the range of 1:1-3:1; Applying radio frequency power into the reaction chamber, the radio frequency power is used to ionize the etching gas to form plasma, and the plasma is used to perform plasma etching on the etching area; wherein the radio frequency power ranges from 10 to 15W.

8. The method for preparing a hybrid gate high electron mobility transistor according to claim 7, characterized in that: The method further comprises: Depositing a passivation dielectric layer on the surface of the P-type semiconductor layer and the surface of the barrier layer by an evaporation method; The passivation dielectric layer on the surface of the P-type semiconductor layer is etched.

9. The method for preparing a hybrid gate high electron mobility transistor according to claim 8, characterized in that: The method further comprises: Depositing a Schottky metal layer on the P-type semiconductor layer by an electron beam evaporation coating method, and performing a uniform temperature-raising annealing process on the Schottky metal layer; The growth regions of the source and drain are marked on the passivation dielectric layer, the growth regions are plasma etched to form empty regions, and a metal layer is deposited in the empty regions to form the source and drain.

10. A method for testing a hybrid gate high electron mobility transistor, characterized in that: The test method includes: Probe operation on HEMT; collecting electrical signals of the HEMT; Analyzing and processing the electrical signal to obtain electrical test curves of different high electron mobility transistors; It is determined whether the HEMT can realize gate controllability between a normally-off state and a normally-on state according to the electrical test curve.

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