Esd device of ldmosfet structure and manufacturing method, chip

Abstract

The application relates to the field of semiconductor technology and provides an ESD device of an LDMOSFET structure, a manufacturing method and a chip. The device comprises a substrate, a body region, a drift region, a source region, a drain region and a gate structure, the body region is formed on the upper surface of the drift region, and the gate structure is formed in the body region; the source region is connected with a source metal layer, and the drain region is connected with a drain metal layer; the gate structure comprises a gate oxide layer, a polysilicon gate and a polysilicon resistor, the polysilicon gate and the polysilicon resistor are connected with the body region through the gate oxide layer; the polysilicon resistor is connected with the source metal layer, and the body region is connected with the source metal layer; the polysilicon gate is connected with the drain metal layer through an isolation oxide layer, and the polysilicon gate, the isolation oxide layer and the drain metal layer form a capacitor structure. The application is a high-voltage ESD device equivalent to an RC type ESD protection circuit, does not need to increase a resistor and a capacitor outside the MOS device, reduces the area of the device and improves the high-voltage protection capability of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to an ESD device with an LDMOSFET structure, its manufacturing method, and a chip. Background Technology

[0002] ESD (Electrostatic Discharge) refers to the charge transfer caused by objects with different electrostatic potentials approaching or coming into direct contact. When static charge accumulated in the external environment or inside an IC (integrated circuit) chip flows into or out through the chip's pins, the instantaneous ESD current can damage the thick gate oxide and metal lines of the internal components, leading to device failure. With the continuous improvement of VLSI (Very Large Scale Integration) process technology, Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits have entered the ultra-deep submicron stage. The size of MOS devices is constantly shrinking, and the harm of electrostatic discharge (ESD) to integrated circuits is becoming increasingly significant, necessitating ESD protection design for integrated circuits.

[0003] Existing technologies use ESD circuits to protect integrated circuits from electrostatic discharge. Figure 1 This is an RC-type ESD protection circuit employing gate coupling technology. By continuously adjusting the values ​​of capacitor Cn and resistor Rn, a suitable voltage can be coupled to the gate of the NMOS device Mn1 under high ESD stress, thereby reducing the turn-on voltage of the NMOS and achieving electrostatic discharge (ESD) protection. For NMOS and PMOS devices, a high bias voltage coupled to the gate will cause more channel current and a higher electric field, making the thin gate oxide layer more susceptible to damage, and rapidly reducing the robustness of ESD protection. However, in power management chips in the power field, the voltage during ESD discharge can reach several thousand volts or even tens of thousands of volts, making it difficult for this type of ESD circuit to achieve high-voltage ESD protection. Furthermore, this ESD circuit connects capacitors and resistors externally to the NMOS or PMOS device, resulting in a large area occupied by the ESD circuit, which is detrimental to chip miniaturization and integration. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention provides an ESD device with an LDMOSFET structure and a manufacturing method thereof.

[0005] The present invention provides an ESD device with an LDMOSFET structure, comprising: a substrate, a body region, a drift region, a source region, a drain region, and a gate structure, wherein the drift region is formed on the surface of the substrate, the body region is formed on the upper surface of the drift region, the source region is formed on the upper surface of the body region, the drain region is formed on the lower surface of the drift region, and the gate structure is formed within the body region;

[0006] The source region is connected to the source metal layer, and the source metal layer is grounded;

[0007] The drain region is connected to the drain metal layer, and the drain metal layer serves as the input terminal;

[0008] The gate structure includes a gate oxide layer, a polysilicon gate, and a polysilicon resistor, wherein the polysilicon gate and the polysilicon resistor are connected to the body region through the gate oxide layer;

[0009] The polysilicon resistor is connected to the source metal layer, and the body region is connected to the source metal layer;

[0010] The polysilicon gate is connected to the drain metal layer through an isolation oxide layer, and the polysilicon gate, the isolation oxide layer and the drain metal layer constitute a capacitor structure.

[0011] In this embodiment of the invention, the polysilicon gate and the polysilicon resistor are stacked laterally, and the gate oxide layer is vertically disposed along the side of the polysilicon gate and the polysilicon resistor.

[0012] In this embodiment of the invention, the polysilicon gate is made of heavily doped polysilicon, and the doping concentration of ions in the heavily doped polysilicon is 1×10⁻⁶. 20 cm -3 ~1×10 21 cm -3 ;

[0013] The polycrystalline silicon resistor is made of lightly doped polycrystalline silicon, and the doping concentration of ions in the lightly doped polycrystalline silicon is 1×10⁻⁶. 16 cm -3 ~1×10 18 cm -3 .

[0014] In this embodiment of the invention, the polycrystalline silicon resistor is connected to the source metal layer through a first contact terminal.

[0015] In this embodiment of the invention, the body region is connected to the source metal layer via a second contact terminal.

[0016] In this embodiment of the invention, the substrate is an SOI substrate, which includes a substrate silicon layer, an insulating layer, and an active silicon layer.

[0017] The drift region is formed on the upper surface of the active silicon layer;

[0018] The drain region is formed by the active silicon layer.

[0019] In this embodiment of the invention, the drain metal layer is formed on the lower surface of the active silicon layer.

[0020] In this embodiment of the invention, the drain metal layer includes a metal contact terminal, which is connected to the isolation oxide layer, and the metal contact terminal, the isolation oxide layer, and the polysilicon gate constitute a capacitor structure.

[0021] The present invention also provides a method for manufacturing an ESD device with the above-described LDMOSFET structure, comprising:

[0022] An N-type epitaxial layer and a P-type epitaxial layer are formed on the surface of an SOI substrate through two epitaxial processes. The SOI substrate includes a substrate silicon layer, an insulating layer, and an N-type active silicon layer.

[0023] The N-type epitaxial layer, P-type epitaxial layer and SOI substrate are etched until the insulating layer of SOI substrate is exposed to form trenches;

[0024] The trench is filled with oxide, and the oxide is etched to expose the P-type epitaxial layer on the sidewall of the trench.

[0025] The P-type epitaxial layer on the trench sidewall is oxidized to form a gate oxide layer that is connected to the P-type epitaxial layer on the trench sidewall. The remaining N-type epitaxial layer is used as the N-type drift region, and the remaining P-type epitaxial layer is used as the P-type body region.

[0026] Polysilicon is deposited in a trench with a gate oxide layer to form a polysilicon gate and a polysilicon resistor.

[0027] Ion implantation is performed on the surface of the P-type body region to form the source region;

[0028] Remove the substrate silicon layer and insulating layer of the SOI substrate to expose the oxide filling the trench, and use the remaining N-type active silicon layer as the drain region.

[0029] The oxide in the trench is etched to form contact holes, and the remaining oxide in the trench serves as an isolation oxide layer.

[0030] Metal is deposited in the contact holes of the trench and on the surface of the trench to form a drain metal layer, and at the same time, a source metal layer is formed.

[0031] In this embodiment of the invention, an N-type epitaxial layer and a P-type epitaxial layer are formed twice on the surface of an SOI substrate, including:

[0032] N-type silicon is epitaxially grown on the surface of the N-type active silicon layer on the SOI substrate to form an N-type epitaxial layer;

[0033] P-type silicon is epitaxially grown on the surface of an N-type epitaxial layer to form a P-type epitaxial layer.

[0034] In this embodiment of the invention, polysilicon is deposited in a trench with a gate oxide layer to form a polysilicon gate and a polysilicon resistor, including:

[0035] Polysilicon with a first doping concentration of 1×10⁻⁶ is deposited at the bottom of the trench to form a polysilicon gate. 20 cm -3 ~1×10 21 cm -3 ;

[0036] A second doping concentration of polysilicon is deposited on the surface of the polysilicon gate within the trench to form a polysilicon resistor. The second doping concentration is 1×10⁻⁶. 16 cm -3 ~1×10 18 cm -3 .

[0037] In this embodiment of the invention, ion implantation is performed on the surface of the P-type body region to form a source region, including:

[0038] N-type ion implantation is performed on the surface of the P-type body region and the surface of the polysilicon resistor to form the source region and the first contact end.

[0039] P-type ions are implanted onto the surface of the P-type body region to form a second contact end.

[0040] In this embodiment of the invention, forming a source metal layer includes:

[0041] Silicon dioxide is deposited over the body region where the active region, the first contact end, and the second contact end are formed to form an oxide layer;

[0042] The oxide layer is etched to form a contact hole that communicates with the source region, the first contact end, and the second contact end;

[0043] Metal is deposited on the surface of the oxide layer and inside the contact holes to form the source metal layer.

[0044] The present invention also provides a chip comprising the above-described LDMOSFET structure for ESD devices.

[0045] This invention designs an ESD device based on the LDMOSFET structure. By utilizing the high voltage resistance of the LDMOSFET device, a polysilicon resistor and a capacitor structure consisting of a polysilicon gate, an isolation oxide layer, and a drain metal layer are added to the LDMOSFET structure to form a high voltage ESD device equivalent to an RC-type ESD protection circuit. This eliminates the need to add resistors and capacitors outside the MOS device, reduces the area of ​​the ESD device, and improves the high voltage protection capability of the ESD device.

[0046] Other features and advantages of the technical solution of the present invention will be described in detail in the following detailed embodiments section. Attached Figure Description

[0047] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0048] Figure 1 It is an existing gate-coupled RC type ESD protection circuit;

[0049] Figure 2 This is a schematic diagram of the structure of the ESD device with the LDMOSFET structure provided in the embodiment of the present invention;

[0050] Figure 3 This is a flowchart of a method for manufacturing an ESD device with an LDMOSFET structure provided in an embodiment of the present invention;

[0051] Figure 4a This is a schematic diagram of the structure of the N-type epitaxial layer and the P-type epitaxial layer formed in the manufacturing method provided in the embodiments of the present invention;

[0052] Figure 4b This is a schematic diagram of the structure of the trench formed in the manufacturing method provided in the embodiment of the present invention;

[0053] Figure 4c This is a schematic diagram of the structure formed by filling the groove in the manufacturing method provided in the embodiment of the present invention;

[0054] Figure 4d This is a schematic diagram of the structure formed after etching the filling trench in the manufacturing method provided in the embodiment of the present invention;

[0055] Figure 4e This is a schematic diagram of the gate oxide layer formed in the manufacturing method provided in the embodiments of the present invention;

[0056] Figure 4f This is a schematic diagram of the structure of the polysilicon gate and polysilicon resistor formed in the manufacturing method provided in the embodiments of the present invention;

[0057] Figure 4g This is a schematic diagram of the source region formed in the manufacturing method provided in the embodiments of the present invention;

[0058] Figure 4h This is a schematic diagram of the structure of the leak area formed in the manufacturing method provided in the embodiment of the present invention;

[0059] Figure 4i This is a schematic diagram of the structure of the contact hole on the back side formed in the manufacturing method provided in the embodiment of the present invention;

[0060] Figure 4j This is a schematic diagram of the structure of the drain metal layer and the source metal layer formed in the manufacturing method provided in the embodiments of the present invention.

[0061] Explanation of reference numerals in the attached figures

[0062] 101 - Substrate silicon layer, 102 - Insulating layer, 103 - Active silicon layer, 104 - Oxide layer

[0063] 11-Drift region, 12-Bulk region, 13-Gate oxide layer, 14-Polysilicon gate,

[0064] 15-Polycrystalline silicon resistor, 16-Isolation oxide layer, 17-First contact terminal, 18-Second contact terminal,

[0065] 19 - Source region, 20 - Source metal layer, 21 - Drain region, 22 - Drain metal layer, 23 - Metal contact terminal. Detailed Implementation

[0066] To make the technical solutions and advantages of the embodiments of the present invention clearer, the exemplary embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of the present invention can be combined with each other.

[0067] In the description of this invention, it should be understood that the terms "center," "upper," "lower," "front," "rear," "left," "right," "side," "bottom," "surface," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0068] In this invention, unless otherwise explicitly specified and limited, the terms "connected," "interlocked," and "linked" should be interpreted broadly. For example, they can refer to direct connection or indirect connection through an intermediate medium, or they can refer to the internal connection of two elements or the interaction between two elements. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0069] Figure 2 This is a schematic diagram of the ESD device with an LDMOSFET structure provided in an embodiment of the present invention. Figure 2 As shown, the ESD device with an LDMOSFET structure provided in this embodiment includes: a substrate, a body region 12, a drift region 11, a source region 19, a drain region 21, and a gate structure. The drift region 11 is formed on the surface of the substrate, the body region 12 is formed on the upper surface of the drift region 11, the source region 19 is formed on the upper surface of the body region 12, the drain region 21 is formed on the lower surface of the drift region 11, and the gate structure is formed within the body region 12. The source region 19 is connected to the source metal layer 20, which is grounded; the drain region 21 is connected to the drain metal layer 22, which serves as the input terminal. The gate structure includes a gate oxide layer 13, a polysilicon gate 14, and a polysilicon resistor 15. The polysilicon gate 14 and the polysilicon resistor 15 are connected to the body region 12 through the gate oxide layer 13, the polysilicon resistor 15 is connected to the source metal layer 20, and the body region 12 is connected to the source metal layer 20. The polysilicon gate 14 is connected to the drain metal layer 22 through the isolation oxide layer 16. The polysilicon gate 14 and the drain metal layer 22 serve as the two plates of the capacitor, and the isolation oxide layer 16 serves as the dielectric layer between the plates. The polysilicon gate 14, the isolation oxide layer 16 and the drain metal layer 22 constitute the capacitor structure.

[0070] In this embodiment, the polysilicon gate 14 and the polysilicon resistor 15 are horizontally stacked, and the gate oxide layer 13 is vertically disposed along the side ends of the polysilicon gate 14 and the polysilicon resistor 15, and the gate oxide layer 13 is in contact with the sidewalls of the polysilicon gate 14 and the polysilicon resistor 15. The polysilicon gate 14 is made of heavily doped polysilicon, and the doping concentration of ions in the heavily doped polysilicon is 1×10⁻⁶. 20 cm -3 ~1×10 21 cm -3 The polycrystalline silicon resistor 15 is made of lightly doped polycrystalline silicon, with a doping concentration of 1×10⁻⁶ ions. 16 cm -3 ~1×10 18 cm -3 .

[0071] In this embodiment, the polysilicon resistor 15 is connected to the source metal layer 20 through the first contact terminal 17, forming an ohmic contact with the source metal layer 20. The body region 12 is connected to the source metal layer 20 through the second contact terminal 18. The two ends of the first contact terminal 17 adjacent to the source region 19 are covered with oxide layers 104, and the first contact terminal 17 is connected to the source metal layer 20 through metal contact holes between the oxide layers 104 on both sides.

[0072] In an optional embodiment, the substrate is an SOI (Silicon On Insulator) substrate, which includes a substrate silicon layer 101, an insulating layer 102, and an active silicon layer 103. A drift region 11 is formed on the upper surface of the active silicon layer 103, which constitutes the drain region 21 of the device. A drain metal layer 22 is formed on the lower surface of the active silicon layer 103. The drain metal layer 22 includes a metal contact 23, which is connected to an isolation oxide layer 16. The metal contact 23 serves as the lower electrode of the capacitor, and the polysilicon gate 14 serves as the upper electrode of the capacitor. The polysilicon gate 14, the isolation oxide layer 16, and the metal contact 23 constitute a capacitor structure.

[0073] This invention designs an ESD device based on the LDMOSFET structure. By utilizing the high voltage resistance of the LDMOSFET device, a polysilicon resistor and a capacitor structure consisting of a polysilicon gate, an isolation oxide layer, and a drain metal layer are added to the LDMOSFET structure to form a high voltage ESD device equivalent to an RC-type ESD protection circuit. This eliminates the need to add resistors and capacitors outside the MOS device, reduces the area of ​​the ESD device, and improves the high voltage protection capability of the ESD device.

[0074] The present invention also provides a method for manufacturing an ESD device with the above-described LDMOSFET structure. The method uses an SOI substrate, which includes a substrate silicon layer, an insulating layer, and an N-type active silicon layer.

[0075] like Figure 3 As shown, the method includes the following steps:

[0076] S301, an N-type epitaxial layer and a P-type epitaxial layer are formed on the surface of an SOI substrate through two epitaxial processes;

[0077] S302, etching is performed on the N-type epitaxial layer, P-type epitaxial layer and SOI substrate until the insulating layer of SOI substrate is exposed, forming trenches;

[0078] S303, fill the trench with oxide, etch the oxide filling the trench to expose the P-type epitaxial layer on the sidewall of the trench;

[0079] S304, the P-type epitaxial layer on the trench sidewall is oxidized to form a gate oxide layer in contact with the P-type epitaxial layer on the trench sidewall, the remaining N-type epitaxial layer is used as the N-type drift region, and the remaining P-type epitaxial layer is used as the P-type body region.

[0080] S305, polysilicon is deposited in a trench with a gate oxide layer to form a polysilicon gate and a polysilicon resistor;

[0081] S306, ion implantation is performed on the surface of the P-type body region to form the source region;

[0082] S307, remove the substrate silicon layer and insulating layer of the SOI substrate to expose the oxide filling the trench, and the remaining N-type active silicon layer serves as the drain region.

[0083] S308 etches the oxide in the trench to form contact holes, and the remaining oxide in the trench serves as an isolation oxide layer.

[0084] S309, depositing metal in the contact hole of the trench and on the surface of the trench to form a drain metal layer, and simultaneously forming a source metal layer.

[0085] In one specific embodiment, in step S301 above, the SOI substrate includes a substrate silicon layer 101, an insulating layer 102, and an N-type active silicon layer 103. N-type silicon is epitaxially grown on the surface of the N-type active silicon layer 103 of the SOI substrate to form an N-type epitaxial layer (corresponding to the N-type drift region 11). P-type silicon is epitaxially grown on the surface of the N-type epitaxial layer to form a P-type epitaxial layer (corresponding to the P-type body region 12), forming... Figure 4a The structure is shown. The N-type epitaxial layer is used to form the N-type drift region 11, and the P-type epitaxial layer is used to form the P-type body region 12.

[0086] In one specific embodiment, in step S302 above, a thin layer of silicon dioxide (SiO2) is thermally oxidized on the surface of the P-type epitaxial layer, followed by photoresist coating, photolithography, and dry etching of the thin silicon dioxide layer and the underlying P-type epitaxial layer 12, N-type epitaxial layer 11, and N-type active silicon layer 103 until the insulating layer 102 of the SOI substrate is exposed, forming a layer as shown in the figure. Figure 4b The groove shown.

[0087] In one specific embodiment, in step S303 above, the photoresist is removed, and silicon dioxide (SiO2) is filled into the trench using chemical vapor deposition (CVD). Excess SiO2 on the surface is then smoothed using CMP. Since the insulating layer 102 of the SOI substrate is silicon dioxide (SiO2), the SiO2 serving as the insulating layer 102 and the SiO2 filled in the trench together form a structure similar to... Figure 4c The oxide layer 104 is shown. Then, photoresist is coated, photolithography is performed, and dry etching is used to etch the SiO2 within the trench to a depth reaching the thickness of the P-type epitaxial layer 12, completely exposing the P-type epitaxial layer on the trench sidewalls. The photoresist is then removed, forming the layer shown. Figure 4d The structure shown.

[0088] In one specific embodiment, in step S304 above, the P-type epitaxial layer on the trench sidewall is subjected to thermal oxidation treatment to form a vertical gate oxide layer 13 on the trench sidewall, wherein the remaining N-type epitaxial layer serves as the N-type drift region 11, and the remaining P-type epitaxial layer serves as the P-type body region 12, forming as shown in the figure. Figure 4e The structure shown.

[0089] In one specific embodiment, in step S305 above, a low-pressure chemical vapor deposition (LPCVD) method is used to deposit polysilicon with a first doping concentration at the bottom of the trench with the gate oxide layer 13 to form a polysilicon gate 14, and then deposit polysilicon with a second doping concentration on the surface of the polysilicon gate 14 to form a polysilicon resistor 15. The first doping concentration is 1×10⁻⁶. 20 cm -3 ~1×10 21 cm -3 The second doping concentration is 1×10 16 cm -3 ~1×10 18 cm -3 Then, CMP smooths out excess polysilicon on the surface, forming a layer like... Figure 4f The structure shown.

[0090] In one specific embodiment, in step S306 above, SiO2 on the P-type body region 12 is removed by wet process, photolithography is performed to form ion implantation windows on the surface of the P-type body region 12, N-type heavily doped ion implantation and P-type heavily doped ion implantation are performed respectively, then the photoresist is removed and annealing is performed to form as shown in the figure. Figure 4g The N+ and P+ regions are shown. The N+ region on the surface of the P-type body region 12 serves as the source region 19, and the N+ region on the surface of the polysilicon resistor 15 serves as the first contact terminal 17 for ohmic contact between the polysilicon resistor 15 and the subsequent source metal layer. The P+ region on the surface of the P-type body region 12 serves as the second contact terminal 18 for connection between the P-type body region 12 and the subsequent source metal layer.

[0091] In one specific embodiment, in step S307 above, a thick layer of silicon dioxide (SiO2) is deposited above the P-type body region 12, which forms the active region N+, the first contact terminal N+, and the second contact terminal P+, using a chemical vapor deposition (CVD) method to form an oxide layer 104 above the source region. The oxide layer 104 above the source region is etched to form a front-side contact hole, which communicates with the source region N+, the first contact terminal N+, and the second contact terminal P+. Then, the substrate silicon layer 101 and the insulating layer 102 on the back side of the SOI substrate are removed, exposing the SiO2 filling the trench. The remaining N-type active silicon layer 103 serves as the drain region 21, forming... Figure 4h The structure shown.

[0092] In one specific embodiment, in step S308 above, the SiO2 in the trench is photolithographically etched and dry-etched to form the contact hole on the back side. The remaining SiO2 in the trench serves as an isolation oxide layer 16, forming a... Figure 4i The structure shown.

[0093] In one specific embodiment, in step S309 above, metal is deposited in the contact holes on the back side and on the lower surface of the trench to form a drain metal layer 22, while metal is deposited in the contact holes on the front side to form a source metal layer 20, forming as shown in the figure. Figure 4j The structure shown is as follows. In this structure, the metal filled in the contact hole serves as the metal contact terminal 23. The polysilicon gate 14, the isolation oxide layer 16, and the metal contact terminal 23 constitute a capacitor structure, forming an ESD device with an LDMOSFET structure.

[0094] The present invention also provides a chip that includes an ESD device with the above-described LDMOSFET structure, thereby achieving electrostatic protection for the integrated circuit in the chip.

[0095] The optional embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the embodiments of the present invention are not limited to the specific details in the above embodiments. Within the scope of the technical concept of the embodiments of the present invention, various simple modifications can be made to the technical solutions of the embodiments of the present invention, and these simple modifications all fall within the protection scope of the embodiments of the present invention. Furthermore, it should be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. As long as such combination does not violate the spirit of the embodiments of the present invention, it should also be considered as the content disclosed in the embodiments of the present invention.

Claims

1. An ESD device of an LDMOSFET structure, comprising: The substrate, body region, drift region, source region, drain region and gate structure are characterized in that the drift region is formed on the surface of the substrate, the body region is formed on the upper surface of the drift region, the source region is formed on the upper surface of the body region, the drain region is formed on the lower surface of the drift region, and the gate structure is formed in the body region. The source region is connected to a source metal layer, and the source metal layer is grounded. The drain region is connected to a drain metal layer, and the drain metal layer serves as an input terminal. The gate structure comprises a gate oxide layer, a polysilicon gate and a polysilicon resistor, and the polysilicon gate and the polysilicon resistor are connected to the body region through the gate oxide layer. The polysilicon resistor is connected to the source metal layer, and the body region is connected to the source metal layer. The polysilicon gate is connected to the drain metal layer through an isolation oxide layer, and the polysilicon gate, the isolation oxide layer and the drain metal layer form a capacitor structure.

2. The ESD device of the LDMOSFET structure of claim 1, wherein, The polysilicon gate and the polysilicon resistor are arranged in a lateral stack, and the gate oxide layer is arranged vertically along the side ends of the polysilicon gate and the polysilicon resistor.

3. The ESD device of the LDMOSFET structure of claim 1, wherein, The material of the polysilicon gate is heavily doped polysilicon, and the doping concentration of ions in the heavily doped polysilicon is 1x10 20 cm -3 ~1x10 21 cm -3 ; The material of the polysilicon resistor is lightly doped polysilicon, and the doping concentration of ions in the lightly doped polysilicon is 1x10 16 cm -3 ~1x10 18 cm -3 .

4. The ESD device of the LDMOSFET structure of claim 1, wherein, The polysilicon resistor is connected to the source metal layer through a first contact terminal.

5. The ESD device of the LDMOSFET structure of claim 1, wherein, The body region is connected to the source metal layer through a second contact terminal.

6. The ESD device of the LDMOSFET structure of claim 1, wherein, The substrate is an SOI substrate, and the SOI substrate comprises a substrate silicon layer, an insulating layer and an active silicon layer. The drift region is formed on the upper surface of the active silicon layer. The drain region is formed on the lower surface of the active silicon layer.

7. The ESD device of the LDMOSFET structure of claim 6, wherein, The drain metal layer is formed on the lower surface of the active silicon layer.

8. The ESD device of the LDMOSFET structure of claim 7, wherein, The drain metal layer comprises a metal contact terminal, the metal contact terminal is connected to the isolation oxide layer, and the metal contact terminal, the isolation oxide layer and the polysilicon gate form a capacitor structure.

9. A method of fabricating an ESD device of an LDMOSFET structure, characterized by, The method comprises the following steps: forming an N-type epitaxial layer and a P-type epitaxial layer on the surface of an SOI substrate by twice epitaxy, wherein the SOI substrate comprises a substrate silicon layer, an insulating layer and an N-type active silicon layer; etching the N-type epitaxial layer, the P-type epitaxial layer and the SOI substrate until the insulating layer of the SOI substrate is exposed, to form a trench; filling the trench with oxide, and etching the oxide filled in the trench to expose the P-type epitaxial layer on the sidewall of the trench; performing oxidation treatment on the P-type epitaxial layer on the sidewall of the trench to form a gate oxide layer on the sidewall of the trench, the remaining N-type epitaxial layer serving as an N-type drift region, and the remaining P-type epitaxial layer serving as a P-type body region; depositing polysilicon in the trench with the gate oxide layer to form a polysilicon gate and a polysilicon resistor; performing ion implantation on the surface of the P-type body region to form a source region; removing the substrate silicon layer and the insulating layer of the SOI substrate to expose the oxide filled in the trench, and the remaining N-type active silicon layer serving as a drain region; etching the oxide in the trench to form a contact hole, and the remaining oxide in the trench serving as an isolation oxide layer; depositing metal in the contact hole of the trench and on the surface of the trench to form a drain metal layer, and simultaneously forming a source metal layer.

10. The method of claim 9, wherein the LDMOSFET structure is an ESD device. The method comprises the following steps: forming an N-type epitaxial layer and a P-type epitaxial layer on the surface of an SOI substrate by twice epitaxy, wherein the SOI substrate comprises a substrate silicon layer, an insulating layer and an N-type active silicon layer; epitaxially growing N-type silicon on the surface of the N-type active silicon layer of the SOI substrate to form an N-type epitaxial layer; epitaxially growing P-type silicon on the surface of the N-type epitaxial layer to form a P-type epitaxial layer.

11. The method of claim 9, wherein the LDMOSFET structure is an ESD device. Depositing polysilicon in the trench with the gate oxide layer to form a polysilicon gate and a polysilicon resistor, comprising: depositing polysilicon of a first doping concentration at the bottom of the trench to form a polysilicon gate, the first doping concentration being 1 x 10 20 cm -3 ~ 1 x 10 21 cm -3 ; depositing a second dopant concentration of polysilicon on the surface of the polysilicon gate within the trench, the second dopant concentration being 1 x 10 16 cm -3 ~ 1 x 10 18 cm -3 .

12. The method of claim 9, wherein the LDMOSFET structure is an ESD device. Ion implantation on the surface of the P-type body region to form a source region, comprising: N-type ion implantation on the surface of the P-type body region and the surface of the polysilicon resistor to form a source region and a first contact end; P-type ion implantation on the surface of the P-type body region to form a second contact end.

13. The method of claim 12, wherein the LDMOSFET structure is an ESD device. Forming a source metal layer, comprising: Depositing silicon dioxide on the body region with the active region, the first contact end and the second contact end to form an oxide layer; Etching the oxide layer to form a contact hole communicating with the source region, the first contact end and the second contact end; Depositing metal on the surface of the oxide layer and in the contact hole to form a source metal layer.

14. A chip, characterized by The chip comprises an ESD device of the LDMOSFET structure according to any one of claims 1-8.

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