Esd device of ldmosfet structure and manufacturing method, chip

Abstract

The application relates to the field of semiconductor technology and provides an ESD device of an LDMOSFET structure, a manufacturing method and a chip. The device comprises a substrate, a body region, a drift region, a source region, a drain region and a gate structure. The gate structure is formed above the body region and the drift region and comprises a polysilicon gate, an insulating medium layer and a polysilicon resistor which are stacked in sequence from bottom to top. The source region is connected with a source metal layer, and the drain region is connected with a drain metal layer. The polysilicon resistor is connected with the source metal layer through a first contact end, and the body region is connected with the source metal layer through a second contact end. The side surface of the polysilicon gate is provided with a silicon nitride side wall which is connected with the drain metal layer, and the polysilicon gate, the silicon nitride side wall and the drain metal layer form a capacitor structure. The polysilicon resistor and the capacitor structure are connected in parallel, forming a high-voltage ESD device equivalent to an RC type ESD protection circuit, thereby reducing the area of the device and improving the high-voltage protection capability of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to an ESD device with an LDMOSFET structure, its manufacturing method, and a chip. Background Technology

[0002] ESD (Electrostatic Discharge) refers to the charge transfer caused by objects with different electrostatic potentials approaching or coming into direct contact. When static charge accumulated in the external environment or inside an IC (integrated circuit) chip flows into or out through the chip's pins, the instantaneous ESD current can damage the thick gate oxide and metal lines of the internal components, leading to device failure. With the continuous improvement of VLSI (Very Large Scale Integration) process technology, Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits have entered the ultra-deep submicron stage. The size of MOS devices is constantly shrinking, and the harm of electrostatic discharge (ESD) to integrated circuits is becoming increasingly significant, necessitating ESD protection design for integrated circuits.

[0003] Existing technologies use ESD circuits to protect integrated circuits from electrostatic discharge. Figure 1 This is an RC-type ESD protection circuit employing gate coupling technology. By continuously adjusting the values ​​of capacitor Cn and resistor Rn, a suitable voltage can be coupled to the gate of the NMOS device Mn1 under high ESD stress, thereby reducing the turn-on voltage of the NMOS and achieving electrostatic discharge (ESD) protection. For NMOS and PMOS devices, a high bias voltage coupled to the gate will cause more channel current and a higher electric field, making the thin gate oxide layer more susceptible to damage, and rapidly reducing the robustness of ESD protection. However, in power management chips in the power field, the voltage during ESD discharge can reach several thousand volts or even tens of thousands of volts, making it difficult for this type of ESD circuit to achieve high-voltage ESD protection. Furthermore, this ESD circuit connects capacitors and resistors externally to the NMOS or PMOS device, resulting in a large area occupied by the ESD circuit, which is detrimental to chip miniaturization and integration. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention provides an ESD device with an LDMOSFET structure and a manufacturing method thereof.

[0005] The present invention provides an ESD device with an LDMOSFET structure, comprising: a substrate, a body region, a drift region, a source region, a drain region, and a gate structure, wherein the body region and the drift region are formed in the substrate, the source region is formed on the surface of the body region, the drain region is formed on the surface of the drift region, and the gate structure is formed above the body region and the drift region;

[0006] The gate structure includes a polysilicon gate, an insulating dielectric layer, and a polysilicon resistor stacked sequentially from bottom to top;

[0007] The source region is connected to the source metal layer, and the drain region is connected to the drain metal layer;

[0008] The polysilicon resistor is connected to the source metal layer through a first contact terminal, and the body region is connected to the source metal layer through a second contact terminal;

[0009] The polysilicon gate has a silicon nitride sidewall on its side, which is connected to the drain metal layer. The polysilicon gate, silicon nitride sidewall, and drain metal layer constitute a capacitor structure.

[0010] In this embodiment of the invention, the gate structure further includes a gate oxide layer, which is connected to the lower surface of the polysilicon gate.

[0011] In this embodiment of the invention, the upper surface of the polysilicon gate is in contact with the lower surface of the insulating dielectric layer, and the upper surface of the insulating dielectric layer is in contact with the lower surface of the polysilicon resistor;

[0012] The sidewalls of the polysilicon gate, the insulating dielectric layer, and the polysilicon resistor are all connected to the silicon nitride sidewall.

[0013] In this embodiment of the invention, the polysilicon gate is made of heavily doped polysilicon, and the doping concentration of ions in the heavily doped polysilicon is 1×10⁻⁶. 20 cm -3 ~1×10 21 cm -3 ;

[0014] The polycrystalline silicon resistor is made of lightly doped polycrystalline silicon, and the doping concentration of ions in the lightly doped polycrystalline silicon is 1×10⁻⁶. 16 cm -3 ~1×10 18 cm -3 ;

[0015] The insulating dielectric layer is made of undoped polycrystalline silicon or silicon dioxide.

[0016] In this embodiment of the invention, the first contact end is located on the surface of the polysilicon resistor, and the polysilicon resistor is connected to the source metal layer through the first contact end to form an ohmic contact with the source metal layer;

[0017] The second contact end is located on the surface of the body region, and the body region is connected to the source metal layer through the second contact end.

[0018] In this embodiment of the invention, it also includes an N-type well region and a P-type well region, wherein the N-type well region is located below the body region and the drift region;

[0019] An N+ contact terminal is provided on the surface of the N-type well region, and the power supply voltage is connected through the N+ contact terminal;

[0020] A P+ contact terminal is provided on the surface of the P-type well region, and ground is connected through the P+ contact terminal.

[0021] In this embodiment of the invention, a field plate structure is also included, the field plate structure including a shallow trench isolation area formed within the drift area.

[0022] The present invention also provides a method for manufacturing an ESD device with the above-described LDMOSFET structure, comprising:

[0023] Forming bulk regions and drift regions in the substrate;

[0024] A gate oxide layer is formed above the bulk region and the drift region, and a polysilicon gate, an insulating dielectric layer and a polysilicon resistor are sequentially formed on the surface of the gate oxide layer.

[0025] A source region is formed on the surface of the bulk region, a drain region is formed on the surface of the drift region, a first contact terminal is formed on the surface of the polysilicon resistor, and a second contact terminal is formed on the surface of the bulk region.

[0026] Silicon nitride sidewalls are formed on the sides of the polysilicon gate;

[0027] An isolation oxide layer is formed above the body region, the drift region, and the polysilicon resistor, and the isolation oxide layer is etched to form multiple contact holes, which are respectively connected to the source region, the drain region, the first contact terminal, and the second contact terminal.

[0028] Metal is deposited inside the contact hole to form a drain metal layer and a source metal layer.

[0029] In this embodiment of the invention, forming a body region and a drift region in a substrate includes:

[0030] P-type ion implantation and N-type ion implantation are performed on the surface of the substrate, and high-temperature propulsion is carried out to form a P-type bulk region and an N-type drift region.

[0031] In this embodiment of the invention, a polysilicon gate, an insulating dielectric layer, and a polysilicon resistor are sequentially formed on the surface of the gate oxide layer, including:

[0032] A polysilicon gate is formed by depositing a polysilicon gate with a first doping concentration of 1×10⁻⁶ on the surface of the gate oxide layer. 20 cm -3 ~1×10 21 cm -3 ;

[0033] Undoped polysilicon is deposited on the surface of the polysilicon gate to form an insulating dielectric layer;

[0034] A polycrystalline silicon resistor is formed by depositing a second doping concentration of 1×10⁻⁶ on the surface of the insulating dielectric layer. 16 cm -3 ~1×10 18 cm -3 .

[0035] In this embodiment of the invention, a source region is formed on the surface of the body region, a drain region is formed on the surface of the drift region, a first contact terminal is formed on the surface of the polysilicon resistor, and a second contact terminal is formed on the surface of the body region, comprising:

[0036] Photolithography is performed on the surface of the bulk region, the surface of the drift region, and the surface of the polysilicon resistor to form ion implantation windows. N-type ions are implanted into the ion implantation windows to form the source region, the drain region, and the first contact end.

[0037] P-type ions are injected into the ion implantation window in the body region to form a second contact end.

[0038] In this embodiment of the invention, a silicon nitride sidewall is formed on the side of the polysilicon gate, including:

[0039] Silicon nitride is deposited on the sidewalls of the polysilicon gate, insulating dielectric layer, and polysilicon resistor, and then etched to form silicon nitride sidewalls.

[0040] In this embodiment of the invention, depositing metal within the contact hole to form a drain metal layer and a source metal layer includes:

[0041] A metal layer is formed by depositing metal inside the contact hole using a physical vapor deposition process.

[0042] The metal layer is etched to form a drain metal layer and a source metal layer. The source metal layer enables interconnection between the body region, the source region, and the polysilicon resistor.

[0043] In this embodiment of the invention, the method for manufacturing the ESD device with the LDMOSFET structure further includes:

[0044] When the P-type body region and the N-type drift region are formed, the N-type well region and the P-type well region are formed simultaneously.

[0045] Shallow trench isolation zones are formed on the surface of the N-type drift region and the surface of the N-type well region.

[0046] The present invention also provides a chip comprising the above-described LDMOSFET structure for ESD devices.

[0047] This invention designs an ESD device based on the LDMOSFET structure. Utilizing the high-voltage withstand capability of the LDMOSFET, a polysilicon resistor and a capacitor structure consisting of a polysilicon gate, silicon nitride sidewalls, and a drain metal layer are added to the LDMOSFET structure. This forms a high-voltage ESD device equivalent to an RC-type ESD protection circuit, eliminating the need for external resistors and capacitors on the MOSFET, thus reducing the device area and improving its high-voltage protection capability. Furthermore, the stacked arrangement of the polysilicon resistor and polysilicon gate reduces the area occupied by the RC-type gate structure, further minimizing the device area.

[0048] Other features and advantages of the technical solution of the present invention will be described in detail in the following detailed embodiments section. Attached Figure Description

[0049] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0050] Figure 1 It is an existing gate-coupled RC type ESD protection circuit;

[0051] Figure 2 This is a schematic diagram of the structure of the ESD device with the LDMOSFET structure provided in the embodiment of the present invention;

[0052] Figure 3 This is a flowchart of a method for manufacturing an ESD device with an LDMOSFET structure provided in an embodiment of the present invention;

[0053] Figure 4a This is a schematic diagram of the structure of the body region and drift region formed in the manufacturing method provided in the embodiments of the present invention;

[0054] Figure 4b This is a schematic diagram of the shallow trench isolation zone formed in the manufacturing method provided in this embodiment of the invention;

[0055] Figure 4c This is a schematic diagram of the gate structure formed in the manufacturing method provided in the embodiments of the present invention;

[0056] Figure 4d This is a schematic diagram of the source region, drain region, and contact end formed by ion implantation in the manufacturing method provided in this embodiment of the invention;

[0057] Figure 4e This is a schematic diagram of the silicon nitride sidewall formed in the manufacturing method provided in the embodiments of the present invention;

[0058] Figure 4fThis is a schematic diagram of the structure of the isolation oxide layer formed in the manufacturing method provided in the embodiments of the present invention;

[0059] Figure 4g This is a schematic diagram of the source metal layer and drain metal layer formed in the manufacturing method provided in the embodiments of the present invention.

[0060] Explanation of reference numerals in the attached figures

[0061] 10-Substrate, 11-Bulk region, 12-Drift region, 13-Well region, 14-Shallow trench isolation region

[0062] 15 - Gate oxide layer, 16 - Polysilicon gate, 17 - Insulating dielectric layer, 18 - Polysilicon resistor

[0063] 19-Silicon nitride sidewall, 20-First contact terminal, 21-Second contact terminal, 22-Source region, 23-Drain region, 24-Isolation oxide layer, 25-Source metal layer, 26-Drain metal layer. Detailed Implementation

[0064] To make the technical solutions and advantages of the embodiments of the present invention clearer, the exemplary embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of the present invention can be combined with each other.

[0065] In the description of this invention, it should be understood that the terms "center," "upper," "lower," "front," "rear," "left," "right," "side," "bottom," "surface," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0066] In this invention, unless otherwise explicitly specified and limited, the terms "connected," "interlocked," and "linked" should be interpreted broadly. For example, they can refer to direct connection or indirect connection through an intermediate medium, or they can refer to the internal connection of two elements or the interaction between two elements. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0067] Figure 2 This is a schematic diagram of the ESD device with an LDMOSFET structure provided in an embodiment of the present invention. Figure 2 As shown, the ESD device with an LDMOSFET structure provided in this embodiment includes: a substrate 10, a body region 11, a drift region 12, a source region 22, a drain region 23, and a gate structure. The body region 11 and the drift region 12 are formed in the substrate 10, the source region 22 is formed on the surface of the body region 11, the drain region 23 is formed on the surface of the drift region 12, and the gate structure is formed above the body region 11 and the drift region 12. The gate structure includes a polysilicon gate 16, an insulating dielectric layer 17, and a polysilicon resistor 18 stacked sequentially from bottom to top. The source region 22 is connected to the source metal layer 25, which is grounded. The drain region 23 is connected to the drain metal layer 26, which serves as the input terminal. The polysilicon resistor 18 is connected to the source metal layer 25 through a first contact terminal 20, and the body region 11 is connected to the source metal layer 25 through a second contact terminal 21. The polysilicon gate 16 has a silicon nitride sidewall 19 on its side. The silicon nitride sidewall 19 is connected to the drain metal layer 26. The polysilicon gate 16 is connected to the drain metal layer 26 through the silicon nitride sidewall 19. The polysilicon gate 16 and the drain metal layer 26 serve as the two plates of the capacitor, respectively. The silicon nitride sidewall 19 serves as the dielectric layer between the plates. The polysilicon gate 16, the silicon nitride sidewall 19 and the drain metal layer 26 constitute a capacitor structure.

[0068] In this embodiment, the gate structure further includes a gate oxide layer 15, which is connected to the lower surface of the polysilicon gate 16. The upper surface of the polysilicon gate 16 is connected to the lower surface of the insulating dielectric layer 17, and the upper surface of the insulating dielectric layer 17 is connected to the lower surface of the polysilicon resistor 18. The sidewalls of the polysilicon gate 16, the insulating dielectric layer 17, and the polysilicon resistor 18 are all connected to the silicon nitride sidewalls 19. The polysilicon gate 16 is made of heavily doped polysilicon, and the doping concentration of ions in the heavily doped polysilicon is 1×10⁻⁶. 20 cm -3 ~1×10 21 cm -3 The polycrystalline silicon resistor 18 is made of lightly doped polycrystalline silicon, with a doping concentration of 1 × 10⁻⁶ ions. 16 cm -3 ~1×10 18 cm -3The insulating dielectric layer 17 is made of undoped polycrystalline silicon or silicon dioxide.

[0069] In this embodiment, the first contact terminal 20 is located on the surface of the polysilicon resistor 18 and is connected to the source metal layer 25. The polysilicon resistor 18 is connected to the source metal layer 25 through the first contact terminal 20, forming an ohmic contact with the source metal layer 25. The second contact terminal 21 is located on the surface of the body region 11 and is connected to the source metal layer 25. The body region 11 is connected to the source metal layer 25 through the second contact terminal 21. An isolation oxide layer 24 is formed on the surface of the polysilicon resistor 18, a portion of the surface of the drain region 23, and a portion of the surface of the second contact terminal 21, which isolates the source metal layer 25 from the drain metal layer 26.

[0070] In a specific embodiment, a silicon nitride sidewall 19 may be formed only on the right side of the polysilicon gate 16, or a silicon nitride sidewall 19 may be formed only on the right side of the polysilicon gate 16, the insulating dielectric layer 17 and the polysilicon resistor 18, and a silicon nitride sidewall 19 on the left side is not necessary.

[0071] In an optional embodiment, the ESD device of the above-described LDMOSFET structure further includes a well region 13. An N-type well region 13 can be formed below the P-type body region 11 and the N-type drift region 12, and an additional P-type well region 13 can also be provided. An N+ contact is provided on the surface of the left-side N-type well region 13, which is connected to the power supply voltage (VDD). A P+ contact is provided on the surface of the right-side P-type well region 13, which is connected to ground.

[0072] In an optional embodiment, the LDMOSFET structure of the ESD device described above further includes a field plate structure, which includes a shallow trench isolation (STI) region 14 formed on the surface of the N-type drift region 12 and the surface of the N-type well region 13. The field plate structure can improve the breakdown voltage of the ESD device and enhance its high-voltage protection capability.

[0073] This invention designs an ESD device based on the LDMOSFET structure. Utilizing the high-voltage withstand capability of the LDMOSFET, a polysilicon resistor and a capacitor structure consisting of a polysilicon gate, silicon nitride sidewalls, and a drain metal layer are added to the LDMOSFET structure. The polysilicon resistor and capacitor structure are connected in parallel, forming a high-voltage ESD device equivalent to an RC-type ESD protection circuit. This eliminates the need to add resistors and capacitors externally to the MOSFET, reducing the ESD device area and improving its high-voltage protection capability. Furthermore, the stacked arrangement of the polysilicon resistor and polysilicon gate reduces the area occupied by the RC-type gate structure, further reducing the device area.

[0074] The present invention also provides a method for manufacturing an ESD device with the above-described LDMOSFET structure, such as... Figure 3 As shown, the method includes the following steps:

[0075] S301, forming a bulk region and a drift region in the substrate;

[0076] S302, a gate oxide layer is formed above the body region and the drift region, and a polysilicon gate, an insulating dielectric layer and a polysilicon resistor are sequentially formed on the surface of the gate oxide layer;

[0077] S303, a source region is formed on the surface of the body region, a drain region is formed on the surface of the drift region, a first contact terminal is formed on the surface of the polysilicon resistor, and a second contact terminal is formed on the surface of the body region;

[0078] S304, a silicon nitride sidewall is formed on the side of the polysilicon gate;

[0079] S305 forms an isolation oxide layer above the bulk region, drift region, and polysilicon resistor, and etches the isolation oxide layer to form multiple contact holes;

[0080] S306, depositing metal in the contact hole to form a drain metal layer and a source metal layer.

[0081] In one specific embodiment, in step S301 above, a P-type silicon substrate is selected, and the surface of the P-type silicon substrate has a thin oxide layer. P-type ion implantation and N-type ion implantation are performed on the surface of the P-type silicon substrate 10, and high-temperature propagation is carried out to form a structure as shown in the figure. Figure 4a The P-type body region 11 and N-type drift region 12 are shown.

[0082] In an optional embodiment, while forming the P-type body region 11 and the N-type drift region 12, an N-type well region 13 is simultaneously formed below the P-type body region 11 and the N-type drift region 12, as well as a P-type well region 13 on the right side. Then, following the standard STI (shallow trench isolation) process, shallow trench isolation regions 14 are formed on the surface of the N-type drift region 12 and the surface of the N-type well region 13, forming a... Figure 4b The structure shown.

[0083] In one specific embodiment, in step S302 above, a gate oxide layer 15 is formed above the P-type body region 11 and the N-type drift region 12. Then, a low-pressure chemical vapor deposition (LPCVD) method is used to deposit polysilicon with a first doping concentration on the surface of the gate oxide layer 15 to form a polysilicon gate 16. The first doping concentration is 1×10⁻⁶. 20 cm -3 ~1×10 21 cm -3Next, undoped polysilicon is deposited on the surface of the polysilicon gate 16, or silicon dioxide (SiO2) is deposited on the surface of the polysilicon gate 16 to form an insulating dielectric layer 17; then, polysilicon with a second doping concentration of 1×10⁻⁶ is deposited on the surface of the insulating dielectric layer 17 to form a polysilicon resistor 18. 16 cm -3 ~1×10 18 cm -3 , forming as Figure 4c The structure shown.

[0084] In one specific embodiment, in step S303 above, photolithography is performed on the surface of the P-type body region 11, the surface of the N-type drift region 12, and the surface of the polysilicon resistor 18 to form ion implantation windows. N-type ions are implanted into the ion implantation windows, followed by annealing to form the source region N+ on the surface of the P-type body region 11, the drain region N+ on the surface of the N-type drift region 12, and the contact terminal N+ on the surface of the polysilicon resistor 18. P-type ions are implanted into the ion implantation windows of the P-type body region 11 to form the contact terminal P+ on the surface of the P-type body region 11, forming... Figure 4d The structure shown.

[0085] In one specific embodiment, in step S304 above, a low-pressure chemical vapor deposition (LPCVD) method is used. Figure 4d The structure shown is formed by depositing silicon nitride (SiN) on its surface, followed by dry etching of the silicon nitride, retaining the silicon nitride on the sidewalls of the polysilicon gate 16, the insulating dielectric layer 17, and the polysilicon resistor 18, thus forming a structure as shown. Figure 4e The silicon nitride sidewall 19 is shown.

[0086] In one specific embodiment, the N+ contact terminal on the surface of the polysilicon resistor 18 formed in step S303 serves as the first contact terminal 20, and the P+ contact terminal on the surface of the P-type body region 11 serves as the second contact terminal 21. In step S305, silicon dioxide (SiO2) is deposited above the P-type body region 11, the N-type drift region 12, and the polysilicon resistor 18 to form an isolation oxide layer 24. The isolation oxide layer 24 is then etched to form multiple contact holes. These contact holes are respectively connected to the source region 22, the drain region 23, the first contact terminal 20, and the second contact terminal 21, forming a... Figure 4f The structure shown.

[0087] In one specific embodiment, in step S306 above, a physical vapor deposition (PVD) process is used to deposit metal in the contact hole to form a metal layer. The metal layer is then etched to form a source metal layer 25 and a drain metal layer 26. The source metal layer 25 connects the body region 11, the source region 22, and the polysilicon resistor 18 to form a structure as shown in the figure. Figure 4gThe structure shown yields an ESD device with an LDMOSFET structure.

[0088] The present invention also provides a chip that includes an ESD device with the above-described LDMOSFET structure, thereby achieving electrostatic protection for the integrated circuit in the chip.

[0089] The optional embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the embodiments of the present invention are not limited to the specific details in the above embodiments. Within the scope of the technical concept of the embodiments of the present invention, various simple modifications can be made to the technical solutions of the embodiments of the present invention, and these simple modifications all fall within the protection scope of the embodiments of the present invention. Furthermore, it should be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. As long as such combination does not violate the spirit of the embodiments of the present invention, it should also be considered as the content disclosed in the embodiments of the present invention.

Claims

1. An ESD device of an LDMOSFET structure, comprising: The substrate, body region, drift region, source region, drain region and gate structure are characterized in that the body region and the drift region are formed in the substrate, the source region is formed on the surface of the body region, the drain region is formed on the surface of the drift region, and the gate structure is formed above the body region and the drift region. The gate structure comprises a polysilicon gate, an insulating medium layer and a polysilicon resistor which are stacked in order from bottom to top. The source region is connected to a source metal layer, and the drain region is connected to a drain metal layer. The polysilicon resistor is connected to the source metal layer through a first contact end, and the body region is connected to the source metal layer through a second contact end. The side surface of the polysilicon gate is provided with a silicon nitride side wall, the silicon nitride side wall is in contact with the drain metal layer, and the polysilicon gate, the silicon nitride side wall and the drain metal layer form a capacitor structure.

2. The ESD device of the LDMOSFET structure of claim 1, wherein, The gate structure further comprises a gate oxide layer, which is in contact with the lower surface of the polysilicon gate.

3. The ESD device of the LDMOSFET structure of claim 2, wherein, The upper surface of the polysilicon gate is in contact with the lower surface of the insulating medium layer, and the upper surface of the insulating medium layer is in contact with the lower surface of the polysilicon resistor. The side wall of the polysilicon gate, the side wall of the insulating medium layer and the side wall of the polysilicon resistor are all in contact with the silicon nitride side wall.

4. The ESD device of the LDMOSFET structure of claim 1, wherein, The material of the polysilicon gate is heavily doped polysilicon, and the doping concentration of ions in the heavily doped polysilicon is 1x10 20 cm -3 ~1x10 21 cm -3 ; The material of the polysilicon resistor is lightly doped polysilicon, and the doping concentration of ions in the lightly doped polysilicon is 1x10 16 cm -3 ~1x10 18 cm -3 ; The material of the insulating medium layer is undoped polysilicon or silicon dioxide.

5. The ESD device of the LDMOSFET structure of claim 1, wherein, The first contact end is located on the surface of the polysilicon resistor, and the polysilicon resistor is connected to the source metal layer through the first contact end to form an ohmic contact with the source metal layer. The second contact end is located on the surface of the body region, and the body region is connected to the source metal layer through the second contact end.

6. The ESD device of the LDMOSFET structure of claim 1, wherein, Further comprising an N-type well region and a P-type well region, the N-type well region is located below the body region and the drift region. An N+ contact end is provided on the surface of the N-type well region, and the power supply voltage is connected through the N+ contact end. A P+ contact end is provided on the surface of the P-type well region, and the ground is connected through the P+ contact end.

7. The ESD device of the LDMOSFET structure of claim 1, wherein, Further comprising a field plate structure, the field plate structure comprises a shallow trench isolation region formed in the drift region.

8. A method of fabricating an ESD device of an LDMOSFET structure, characterized by, Comprising: forming a body region and a drift region in a substrate; forming a gate oxide layer above the body region and the drift region, and sequentially forming a polysilicon gate, an insulating medium layer and a polysilicon resistor on the surface of the gate oxide layer; forming a source region on the surface of the body region, a drain region on the surface of the drift region, a first contact end on the surface of the polysilicon resistor, and a second contact end on the surface of the body region; forming a silicon nitride side wall on the side surface of the polysilicon gate; forming an isolation oxide layer above the body region, the drift region and the polysilicon resistor, and etching the isolation oxide layer to form a plurality of contact holes, the plurality of contact holes being in communication with the source region, the drain region, the first contact end and the second contact end respectively; depositing metal in the contact holes to form a drain metal layer and a source metal layer.

9. The method of claim 8, wherein the LDMOSFET structure is an ESD device. forming a body region and a drift region in a substrate, comprising: performing P-type ion implantation and N-type ion implantation on the surface of the substrate respectively, and performing high-temperature promotion to form a P-type body region and an N-type drift region.

10. The method of claim 8, wherein the LDMOSFET structure is an ESD device. sequentially forming a polysilicon gate, an insulating medium layer and a polysilicon resistor on the surface of the gate oxide layer, comprising: depositing a first doping concentration of polysilicon on the surface of the gate oxide layer to form a polysilicon gate, the first doping concentration being 1 x 10 20 cm -3 ~ 1 x 10 21 cm -3 ; depositing undoped polysilicon on the surface of the polysilicon gate to form an insulating medium layer; depositing a second doping concentration of polysilicon on the surface of the insulating dielectric layer to form a polysilicon resistor, the second doping concentration being 1 x 10 16 cm -3 ~ 1 x 10 18 cm -3 .

11. The method of claim 8, wherein the LDMOSFET structure is an ESD device. forming a source region on the surface of the body region, forming a drain region on the surface of the drift region, forming a first contact end on the surface of the polysilicon resistor, and forming a second contact end on the surface of the body region, comprising: forming ion implantation windows on the surface of the body region, the surface of the drift region and the surface of the polysilicon resistor respectively by photolithography, implanting N-type ions into the ion implantation windows to form the source region, the drain region and the first contact end; implanting P-type ions into the ion implantation window of the body region to form the second contact end.

12. The method of claim 8, wherein the LDMOSFET structure is an ESD device. forming a silicon nitride side wall on the side of the polysilicon gate, comprising: depositing silicon nitride on the sidewall of the polysilicon gate, the insulating medium layer and the polysilicon resistor, and etching to form the silicon nitride side wall.

13. The method of claim 8, wherein the LDMOSFET structure is an ESD device. depositing metal in the contact hole to form a drain metal layer and a source metal layer, comprising: depositing metal in the contact hole by physical vapor deposition process to form a metal layer; etching the metal layer to form the drain metal layer and the source metal layer, and the body region, the source region and the polysilicon resistor are connected to each other through the source metal layer.

14. The method of claim 9, wherein the LDMOSFET structure is an ESD device. The method further comprises: forming the N-type well region and the P-type well region at the same time when forming the P-type body region and the N-type drift region; forming a shallow trench isolation region on the surface of the N-type drift region and the surface of the N-type well region.

15. A chip, characterized by The chip comprises the ESD device of the LDMOSFET structure according to any one of claims 1-7.

Images