Esd device of ldmosfet structure and manufacturing method, chip

Abstract

The application relates to the field of semiconductor technology and provides an ESD device of an LDMOSFET structure, a manufacturing method and a chip. The device comprises a substrate, a body region, a drift region, a source region, a drain region and a gate structure, the body region and the drift region are formed in the substrate, the source region is connected with a source metal layer, the drain region is connected with a drain metal layer, the gate structure comprises a gate oxide layer, a polysilicon gate, a polysilicon resistor and a metal silicide layer, the polysilicon gate and the polysilicon resistor are formed on the surface of the gate oxide layer, the metal silicide layer is formed on the surface of the polysilicon gate, the polysilicon gate and the polysilicon resistor form a conductive channel through the metal silicide layer; a silicon nitride side wall is arranged at the side end of the polysilicon gate, the silicon nitride side wall is connected with the drain metal layer, and the polysilicon gate, the silicon nitride side wall and the drain metal layer form a capacitor structure. The application is a high-voltage ESD device equivalent to an RC type ESD protection circuit, and the area of the ESD device is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to an ESD device with an LDMOSFET structure, its manufacturing method, and a chip. Background Technology

[0002] ESD (Electrostatic Discharge) refers to the charge transfer caused by objects with different electrostatic potentials approaching or coming into direct contact. When static charge accumulated in the external environment or inside an IC (integrated circuit) chip flows into or out through the chip's pins, the instantaneous ESD current can damage the thick gate oxide and metal lines of the internal components, leading to device failure. With the continuous improvement of VLSI (Very Large Scale Integration) process technology, Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits have entered the ultra-deep submicron stage. The size of MOS devices is constantly shrinking, and the harm of electrostatic discharge (ESD) to integrated circuits is becoming increasingly significant, necessitating ESD protection design for integrated circuits.

[0003] Existing technologies use ESD circuits to protect integrated circuits from electrostatic discharge. Figure 1 This is an RC-type ESD protection circuit employing gate coupling technology. By continuously adjusting the values ​​of capacitor Cn and resistor Rn, a suitable voltage can be coupled to the gate of the NMOS device Mn1 under high ESD stress, thereby reducing the turn-on voltage of the NMOS and achieving electrostatic discharge (ESD) protection. For NMOS and PMOS devices, a high bias voltage coupled to the gate will cause more channel current and a higher electric field, making the thin gate oxide layer more susceptible to damage, and rapidly reducing the robustness of ESD protection. However, in power management chips in the power field, the voltage during ESD discharge can reach several thousand volts or even tens of thousands of volts, making it difficult for this type of ESD circuit to achieve high-voltage ESD protection. Furthermore, this ESD circuit connects capacitors and resistors externally to the NMOS or PMOS device, resulting in a large area occupied by the ESD circuit, which is detrimental to chip miniaturization and integration. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention provides an ESD device with an LDMOSFET structure and a manufacturing method thereof.

[0005] The present invention provides an ESD device with an LDMOSFET structure, comprising: a substrate, a body region, a drift region, a source region, a drain region, and a gate structure, wherein the body region and the drift region are formed in the substrate, the source region is formed on the surface of the body region, the drain region is formed on the surface of the drift region, and the gate structure is formed above the body region and the drift region;

[0006] The source region is connected to the source metal layer, and the drain region is connected to the drain metal layer;

[0007] The gate structure includes: a gate oxide layer, a polysilicon gate, a polysilicon resistor, and a metal silicide layer. The polysilicon gate and the polysilicon resistor are formed on the surface of the gate oxide layer. The metal silicide layer is formed on the surface of the polysilicon gate. The polysilicon resistor is connected to the source metal layer. The polysilicon gate forms a conductive channel with the polysilicon resistor through the metal silicide layer.

[0008] The polysilicon gate has a silicon nitride sidewall at one end, which is connected to the drain metal layer. The polysilicon gate, silicon nitride sidewall, and drain metal layer constitute a capacitor structure.

[0009] In this embodiment of the invention, one end of the polysilicon resistor is connected to a first contact terminal, the first contact terminal is connected to the source metal layer, and the polysilicon resistor is connected to the source metal layer through the first contact terminal.

[0010] In this embodiment of the invention, the other end of the polysilicon resistor is connected to the polysilicon gate and the metal silicide layer.

[0011] In this embodiment of the invention, a second contact end is formed on the surface of the body region, and the second contact end is connected to the source metal layer.

[0012] In this embodiment of the invention, the source metal layer is grounded, and the drain metal layer serves as the input terminal.

[0013] In this embodiment of the invention, the polysilicon gate is made of heavily doped polysilicon, and the doping concentration of ions in the heavily doped polysilicon is 1×10⁻⁶. 20 cm -3 ~1×10 21 cm -3 ;

[0014] The polycrystalline silicon resistor is made of lightly doped polycrystalline silicon, and the doping concentration of ions in the lightly doped polycrystalline silicon is 1×10⁻⁶. 16 cm -3 ~1×10 18 cm -3 .

[0015] In this embodiment of the invention, the ESD device further includes a well region, which is formed below the body region and the drift region.

[0016] In this embodiment of the invention, the ESD device further includes a field plate structure, the field plate structure including a shallow trench isolation region formed within the drift region.

[0017] The present invention also provides a method for manufacturing an ESD device with the above-described LDMOSFET structure, comprising:

[0018] Forming bulk regions and drift regions in the substrate;

[0019] The source region is formed on the surface of the solid region, and the drain region is formed on the surface of the drift region;

[0020] A gate oxide layer is formed above the bulk region and the drift region, and a polysilicon gate and a polysilicon resistor are formed on the surface of the gate oxide layer;

[0021] A silicon nitride sidewall is formed at the side of the polysilicon gate;

[0022] A metal silicide layer is formed on the surface of a polysilicon gate, and the metal silicide layer is connected to a polysilicon resistor;

[0023] A source metal layer connected to the source region and a drain metal layer connected to the drain region are formed.

[0024] In this embodiment of the invention, forming a body region and a drift region in a substrate includes: performing P-type ion implantation and N-type ion implantation on the surface of the substrate, and performing high-temperature propulsion to form a P-type body region and an N-type drift region.

[0025] In this embodiment of the invention, forming a polysilicon gate and a polysilicon resistor on the surface of the gate oxide layer includes: depositing a first-doped polysilicon layer on the surface of the gate oxide layer, wherein the concentration of the first doping is 1×10⁻⁶. 16 cm -3 ~1×10 18 cm -3 ;

[0026] A portion of the polysilicon layer undergoes secondary doping. The secondary-doped polysilicon serves as the polysilicon gate, while the undoped polysilicon serves as the polysilicon resistor. The secondary doping concentration is 1×10⁻⁶. 20 cm -3 ~1×10 21 cm -3 .

[0027] In this embodiment of the invention, secondary doping of a portion of the polysilicon layer includes: secondary doping of the polysilicon at both ends of the polysilicon layer, wherein the secondary doped polysilicon at one end serves as a polysilicon gate, and the secondary doped polysilicon at the other end serves as the first contact end of the polysilicon resistor.

[0028] In this embodiment of the invention, forming a silicon nitride sidewall at the side of a polysilicon gate includes: depositing silicon nitride on a substrate with a polysilicon gate and a polysilicon resistor, and etching to retain the silicon nitride at the side of the polysilicon gate, thereby forming a silicon nitride sidewall.

[0029] In this embodiment of the invention, a metal silicide layer is formed on the surface of a polysilicon gate, comprising:

[0030] Silicon dioxide is formed on a substrate with polysilicon gates and polysilicon resistors as a barrier layer;

[0031] Metal is deposited on the surface of the barrier layer and then heat-treated to form metal silicide;

[0032] Unreacted metal on the surface of the barrier layer is removed to form a metal silicide layer.

[0033] In this embodiment of the invention, forming a source metal layer connected to the source region and a drain metal layer connected to the drain region includes:

[0034] An isolation oxide layer is formed above the body region, drift region, polysilicon gate, and polysilicon resistor, and the isolation oxide layer is etched to form multiple contact holes;

[0035] Metal is deposited inside the contact hole to form a metal layer;

[0036] The metal layer is etched to form a source metal layer connected to the source region and a drain metal layer connected to the drain region.

[0037] The present invention also provides a chip comprising the above-described LDMOSFET structure for ESD devices.

[0038] This invention designs an ESD device based on the LDMOSFET structure. Utilizing the high-voltage withstand capability of the LDMOSFET, a polysilicon resistor and a capacitor structure consisting of a polysilicon gate, silicon nitride sidewalls, and a drain metal layer are added to the LDMOSFET structure. The polysilicon resistor is connected in series with the capacitor structure through a metal silicide layer, forming a high-voltage ESD device equivalent to an RC-type ESD protection circuit. This eliminates the need to add resistors and capacitors external to the MOS device, reducing the area of ​​the ESD device. Furthermore, the metal silicide layer reduces the on-resistance between the polysilicon resistor and the polysilicon gate, increasing conduction and further enhancing the high-voltage protection capability of the ESD device.

[0039] Other features and advantages of the technical solution of the present invention will be described in detail in the following detailed embodiments section. Attached Figure Description

[0040] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0041] Figure 1 It is an existing gate-coupled RC type ESD protection circuit;

[0042] Figure 2This is a schematic diagram of the structure of the ESD device with the LDMOSFET structure provided in the embodiment of the present invention;

[0043] Figure 3 This is a flowchart of a method for manufacturing an ESD device with an LDMOSFET structure provided in an embodiment of the present invention;

[0044] Figure 4a This is a schematic diagram of the structure of the body region and drift region formed in the manufacturing method provided in the embodiments of the present invention;

[0045] Figure 4b This is a schematic diagram of the shallow trench isolation zone formed in the manufacturing method provided in this embodiment of the invention;

[0046] Figure 4c This is a schematic diagram of the source region, drain region, and contact end formed in the manufacturing method provided in the embodiments of the present invention;

[0047] Figure 4d This is a schematic diagram of the structure of the polycrystalline silicon resistor formed in the manufacturing method provided in the embodiments of the present invention;

[0048] Figure 4e This is a schematic diagram of the structure of the polysilicon gate formed in the manufacturing method provided in the embodiments of the present invention;

[0049] Figure 4f This is a schematic diagram of the silicon nitride sidewall formed in the manufacturing method provided in the embodiments of the present invention;

[0050] Figure 4g This is a schematic diagram of the structure of the metal silicide layer formed in the manufacturing method provided in the embodiments of the present invention;

[0051] Figure 4h This is a schematic diagram of the structure of the isolation oxide layer formed in the manufacturing method provided in the embodiments of the present invention;

[0052] Figure 4i This is a schematic diagram of the source metal layer and drain metal layer formed in the manufacturing method provided in the embodiments of the present invention.

[0053] Explanation of reference numerals in the attached figures

[0054] 10-Substrate, 11-Bulk region, 12-Drift region, 13-Well region, 14-Shallow trench isolation region

[0055] 15-Gate oxide layer, 16-Polysilicon gate, 17-Polysilicon resistor, 18-Silicon nitride sidewall.

[0056] 19-Metal silicide layer, 20-Source region, 21-Drain region, 22-First contact terminal, 23-Second contact terminal, 24-Isolation oxide layer, 25-Source metal layer, 26-Drain metal layer. Detailed Implementation

[0057] To make the technical solutions and advantages of the embodiments of the present invention clearer, the exemplary embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of the present invention can be combined with each other.

[0058] In the description of this invention, it should be understood that the terms "center," "upper," "lower," "front," "rear," "left," "right," "side," "bottom," "surface," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0059] In this invention, unless otherwise explicitly specified and limited, the terms "connected," "interlocked," and "linked" should be interpreted broadly. For example, they can refer to direct connection or indirect connection through an intermediate medium, or they can refer to the internal connection of two elements or the interaction between two elements. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0060] Figure 2 This is a schematic diagram of the ESD device with an LDMOSFET structure provided in an embodiment of the present invention. Figure 2As shown, the ESD device with an LDMOSFET structure provided in this embodiment includes: a substrate 10, a body region 11, a drift region 12, a source region 20, a drain region 21, and a gate structure. The body region 11 and the drift region 12 are formed in the substrate 10, the source region 20 is formed on the surface of the body region 11, the drain region 21 is formed on the surface of the drift region 12, and the gate structure is formed above the body region 11 and the drift region 12. The source region 20 is connected to the source metal layer 25, and the drain region 21 is connected to the drain metal layer 26. The gate structure includes a gate oxide layer 15, a polysilicon gate 16, a polysilicon resistor 17, and a metal silicide layer 19. The polysilicon gate 16 and the polysilicon resistor 17 are formed on the surface of the gate oxide layer 15, and the metal silicide layer 19 is formed on the surface of the polysilicon gate 16. The polysilicon gate 16 forms a conductive channel with the polysilicon resistor 17 through the metal silicide layer 19, and the polysilicon resistor 17 is connected to the source metal layer 25. A silicon nitride sidewall 18 is provided on the side of the polysilicon gate 16. The silicon nitride sidewall 18 is connected to the drain metal layer 26. The polysilicon gate 16 and the drain metal layer 26 serve as the two plates of a capacitor, and the silicon nitride sidewall 18 serves as the dielectric layer between the two plates. The polysilicon gate 16, the silicon nitride sidewall 18, and the drain metal layer 26 constitute a capacitor structure. When the source metal layer 25 is grounded and the drain metal layer 26 serves as the input terminal, the above-described LDMOSFET structure is equivalent to an RC-type ESD protection circuit.

[0061] In this embodiment, one end of the polysilicon resistor 17 is connected to the first contact terminal 22, which is connected to the source metal layer 25. The polysilicon resistor 17 is connected to the source metal layer 25 through the first contact terminal 22, thereby forming an ohmic contact with the source metal layer 25. The other end of the polysilicon resistor 17 is connected to the polysilicon gate 16 and the metal silicide layer 19. When the polysilicon resistor 17 is connected in series with the capacitor structure, the resistance between the polysilicon gate 16 and the polysilicon resistor 17 is relatively large, which will form a large on-resistance inside the device. Therefore, a metal silicide layer 19 is added to one end of the polysilicon resistor 17. The polysilicon gate 16 forms a conductive channel with the polysilicon resistor 17 through the metal silicide layer 19. The metal silicide layer 19 reduces the resistance between the polysilicon resistor 17 and the polysilicon gate 16, increasing the conduction effect.

[0062] In this embodiment, the polysilicon gate 16 is made of heavily doped polysilicon, and the doping concentration of ions in the heavily doped polysilicon is 1×10⁻⁶. 20 cm -3 ~1×10 21 cm -3 The polycrystalline silicon resistor 17 is made of lightly doped polycrystalline silicon, with a doping concentration of 1 × 10⁻⁶ ions. 16 cm -3 ~1×10 18 cm -3.

[0063] In this embodiment, a second contact terminal 23 is formed on the surface of the body region 11, and the second contact terminal 23 is connected to the source metal layer 25. The body region 11 is connected to the source metal layer 25 through the second contact terminal 23. A well region 13 is formed below the body region 11 and the drift region 12. An N+ contact terminal is provided on the surface of the well region 13, and the well region 13 is connected to the drain metal layer 26 through the N+ contact terminal. An isolation oxide layer 24 is formed on the surface of the metal silicide layer 19, a portion of the surface of the drain region 21, and a portion of the surface of the second contact terminal 23, which isolates the source metal layer 25 and the drain metal layer 26.

[0064] In an optional embodiment, the ESD device with the above-described LDMOSFET structure further includes a field plate structure, which includes a shallow trench isolation (STI) region 14 formed on the surface of the drift region 12 and the surface of the well region 13. The field plate structure can improve the breakdown voltage of the ESD device and enhance its high-voltage protection capability.

[0065] This invention designs an ESD device based on the LDMOSFET structure. Utilizing the high-voltage withstand capability of the LDMOSFET, a polysilicon resistor and a capacitor structure consisting of a polysilicon gate, silicon nitride sidewalls, and a drain metal layer are added to the LDMOSFET structure. The polysilicon resistor is connected in series with the capacitor structure through a metal silicide layer, forming a high-voltage ESD device equivalent to an RC-type ESD protection circuit. This eliminates the need to add resistors and capacitors external to the MOS device, reducing the area of ​​the ESD device. Furthermore, the metal silicide layer reduces the on-resistance between the polysilicon resistor and the polysilicon gate, increasing conduction and further enhancing the high-voltage protection capability of the ESD device.

[0066] The present invention also provides a method for manufacturing an ESD device with the above-described LDMOSFET structure, such as... Figure 3 As shown, the method includes the following steps:

[0067] S301, forming a bulk region and a drift region in the substrate;

[0068] S302, a source region is formed on the surface of the bulk region, and a drain region is formed on the surface of the drift region;

[0069] S303, a gate oxide layer is formed above the body region and the drift region, and a polysilicon gate and a polysilicon resistor are formed on the surface of the gate oxide layer;

[0070] S304, a silicon nitride sidewall is formed at the side of the polysilicon gate;

[0071] S305, a metal silicide layer is formed on the surface of the polysilicon gate, and the metal silicide layer is connected to the polysilicon resistor;

[0072] S306, forming a source metal layer connected to the source region and a drain metal layer connected to the drain region.

[0073] In one specific embodiment, in step S301 above, a P-type silicon substrate 10 is selected, and P-type ion implantation and N-type ion implantation are performed on the surface of the P-type silicon substrate 10, respectively, followed by high-temperature propagation to form a structure as shown in the figure. Figure 4a The P-type body region 11 and N-type drift region 12 are shown.

[0074] In an optional embodiment, an N-type well region 13 is formed simultaneously with the formation of the P-type body region 11 and the N-type drift region 12. Then, following the standard STI (shallow trench isolation) process, a shallow trench isolation region 14 is formed on the surface of the N-type drift region 12 and the surface of the N-type well region 13, forming a... Figure 4b The structure shown.

[0075] In one specific embodiment, in step S302 above, photolithography is performed on the surface of the P-type body region 11 and the surface of the N-type drift region 12 to form ion implantation windows. N-type ions are implanted into the ion implantation windows and annealing is performed to form the N+ source region 20 and the N+ drain region 21, while simultaneously forming the N+ contact terminal of the N-type well region 13. P-type ions are implanted into the ion implantation window of the P-type body region 11 to form the P+ contact terminal (i.e., the second contact terminal 23) on the surface of the P-type body region 11, forming as shown in the figure. Figure 4c The structure shown.

[0076] In one specific embodiment, in step S303 above, a gate oxide layer 15 is formed above the P-type body region 11 and the N-type drift region 12. Then, a first-doped polysilicon layer is deposited on the surface of the gate oxide layer 15 using a low-pressure chemical vapor deposition (LPCVD) method to form a polysilicon layer. The concentration of the first doping is 1×10⁻⁶. 16 cm -3 ~1×10 18 cm -3 At this point, the doping concentration of the polycrystalline silicon layer is low, and its resistance is high. As a polycrystalline silicon resistor 17, it forms a structure like... Figure 4d The structure is shown. Next, a portion of the polysilicon layer is subjected to secondary doping. The secondary-doped polysilicon serves as the polysilicon gate 16, and the undoped polysilicon serves as the polysilicon resistor 17. The secondary doping concentration is 1 × 10⁻⁶. 20 cm -3 ~1×10 21 cm -3Specifically, the polysilicon at both ends of the polysilicon layer can be doped twice simultaneously. The doped polysilicon at one end serves as the polysilicon gate 16, and the doped polysilicon at the other end serves as the first contact terminal 22 of the polysilicon resistor 17, forming a structure as follows: Figure 4e The structure shown is an example of a process that uses only one polysilicon photolithography process to form a polysilicon resistor and a polysilicon gate (existing technologies typically require two photolithography processes). The polysilicon gate also serves as a capacitor electrode, simplifying the process and reducing the gate's footprint.

[0077] In one specific embodiment, in step S304 above, silicon nitride is deposited on the substrate with polysilicon gate 16 and polysilicon resistor 17, and then etched to retain the silicon nitride at the side of the polysilicon gate 16, forming as shown in the figure. Figure 4f The silicon nitride sidewall 18 is shown. Specifically, silicon nitride can be formed only on the right side of the polysilicon gate 16. In conventional manufacturing processes, silicon nitride is formed on both sides of the gate structure, that is, there is silicon nitride on the left side of the first contact terminal 22 of the polysilicon resistor 17. The silicon nitride on the left side can also be retained without affecting the ohmic contact between the polysilicon resistor 17 and the source metal layer 25.

[0078] In one specific embodiment, in step S305 above, a thin layer of silicon dioxide (SiO2) is formed on the substrate 10 with polysilicon gate 16 and polysilicon resistor 17 as a barrier layer for the silicide region, and the silicon dioxide is dry etched to open the silicide region; a metal (such as Ti, Co, Ni, etc.) is deposited on the surface of the barrier layer, and rapid thermal processing (RTP) is performed to form metal silicide, and then wet etching is used to remove the unreacted metal on the surface of the barrier layer to form a metal silicide. Figure 4g The metal silicide layer 19 is shown.

[0079] In one specific embodiment, in step S306 above, an isolation oxide layer 24 is formed above the body region 11, the drift region 12, the metal silicide layer 19, and the polysilicon resistor 17, and the isolation oxide layer 24 is etched to form multiple contact holes, such as... Figure 4h As shown.

[0080] Next, a physical vapor deposition (PVD) process is used to deposit metal within the contact holes to form a metal layer. This metal layer is then etched to create a surface resembling... Figure 4i The source metal layer 25 and drain metal layer 26 shown indicate that an ESD device with an LDMOSFET structure is obtained.

[0081] The present invention also provides a chip that includes an ESD device with the above-described LDMOSFET structure, thereby achieving electrostatic protection for the integrated circuit in the chip.

[0082] The optional embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the embodiments of the present invention are not limited to the specific details in the above embodiments. Within the scope of the technical concept of the embodiments of the present invention, various simple modifications can be made to the technical solutions of the embodiments of the present invention, and these simple modifications all fall within the protection scope of the embodiments of the present invention. Furthermore, it should be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. As long as such combination does not violate the spirit of the embodiments of the present invention, it should also be considered as the content disclosed in the embodiments of the present invention.

Claims

1. An ESD device of an LDMOSFET structure, comprising: The substrate, body region, drift region, source region, drain region and gate structure are characterized in that the body region and the drift region are formed in the substrate, the source region is formed on the surface of the body region, the drain region is formed on the surface of the drift region, and the gate structure is formed above the body region and the drift region. The source region is connected to a source metal layer, and the drain region is connected to a drain metal layer. The gate structure includes a gate oxide layer, a polysilicon gate, a polysilicon resistor and a metal silicide layer, the polysilicon gate and the polysilicon resistor are formed on the surface of the gate oxide layer, the metal silicide layer is formed on the surface of the polysilicon gate, the polysilicon resistor is connected to the source metal layer, and the polysilicon gate forms a conductive channel with the polysilicon resistor through the metal silicide layer. The side end of the polysilicon gate is provided with a silicon nitride side wall, the silicon nitride side wall is connected to the drain metal layer, and the polysilicon gate, the silicon nitride side wall and the drain metal layer form a capacitor structure.

2. The ESD device of the LDMOSFET structure of claim 1, wherein, One side end of the polysilicon resistor is connected to a first contact end, the first contact end is connected to the source metal layer, and the polysilicon resistor is connected to the source metal layer through the first contact end.

3. The ESD device of the LDMOSFET structure of claim 2, wherein, The other side end of the polysilicon resistor is connected to the polysilicon gate and the metal silicide layer.

4. The ESD device of the LDMOSFET structure of claim 1, wherein, The surface of the body region is provided with a second contact end, and the second contact end is connected to the source metal layer.

5. The ESD device of the LDMOSFET structure of claim 1, wherein, The source metal layer is grounded, and the drain metal layer serves as an input end.

6. The ESD device of the LDMOSFET structure of claim 1, wherein, The material of the polysilicon gate is heavily doped polysilicon, and the doping concentration of ions in the heavily doped polysilicon is 1x10 20 cm -3 ~1x10 21 cm -3 ; The material of the polysilicon resistor is lightly doped polysilicon, and the doping concentration of ions in the lightly doped polysilicon is 1x10 16 cm -3 ~1x10 18 cm -3 .

7. The ESD device of the LDMOSFET structure of claim 1, wherein, Further comprising: A well region is formed below the body region and the drift region.

8. The ESD device of the LDMOSFET structure of claim 1, wherein, Further comprising a field plate structure, the field plate structure includes a shallow trench isolation region, and the shallow trench isolation region is formed in the drift region.

9. A method of fabricating an ESD device of an LDMOSFET structure, characterized by, Comprising: forming a body region and a drift region in a substrate; forming a source region on the surface of the body region and a drain region on the surface of the drift region; forming a gate oxide layer above the body region and the drift region, and forming a polysilicon gate and a polysilicon resistor on the surface of the gate oxide layer; forming a silicon nitride side wall at the side end of the polysilicon gate; forming a metal silicide layer on the surface of the polysilicon gate, and the metal silicide layer is connected to the polysilicon resistor; forming a source metal layer connected to the source region and a drain metal layer connected to the drain region.

10. The method of claim 9, wherein the LDMOSFET structure is an ESD device. forming a body region and a drift region in a substrate, comprising: performing P-type ion implantation and N-type ion implantation on the surface of the substrate respectively, and performing high-temperature promotion to form a P-type body region and an N-type drift region.

11. The method of claim 9, wherein the LDMOSFET structure is an ESD device. forming a polysilicon gate and a polysilicon resistor on the surface of the gate oxide layer, comprising: depositing a first doped polysilicon on the surface of the gate oxide layer to form a polysilicon layer, the first doped polysilicon having a concentration of 1 x 10 16 cm -3 ~ 1 x 10 18 cm -3 . The part of the polysilicon layer is secondarily doped, the polysilicon after secondary doping is used as a polysilicon gate, and the polysilicon without secondary doping is used as a polysilicon resistor, the concentration of secondary doping is 1×10 20 cm -3 ~1×10 21 cm -3 .

12. The method of claim 11, wherein the LDMOSFET structure is an ESD device. performing secondary doping on part of the polysilicon layer, comprising: performing secondary doping on the polysilicon at both ends of the polysilicon layer, wherein the secondary-doped polysilicon at one end serves as a polysilicon gate, and the secondary-doped polysilicon at the other end serves as a first contact end of a polysilicon resistor.

13. The method of claim 9, wherein the LDMOSFET structure is an ESD device. forming a silicon nitride side wall at the side end of the polysilicon gate, comprising: depositing silicon nitride on the substrate with the polysilicon gate and the polysilicon resistor, and performing etching to retain the silicon nitride at the side end of the polysilicon gate to form a silicon nitride side wall.

14. The method of claim 9, wherein the LDMOSFET structure is an ESD device. forming a metal silicide layer on the surface of the polysilicon gate, comprising: forming silicon dioxide on the substrate with the polysilicon gate and the polysilicon resistor as a barrier layer; Depositing a metal on the surface of the barrier layer and performing a heat treatment to form a metal silicide; Removing unreacted metal on the surface of the barrier layer to form a metal silicide layer.

15. The method of claim 9, wherein the LDMOSFET structure is an ESD device. Forming a source metal layer connected to the source region and a drain metal layer connected to the drain region, comprising: Forming an isolation oxide layer above the body region, the drift region, the polysilicon gate and the polysilicon resistor, and etching the isolation oxide layer to form a plurality of contact holes; Depositing a metal in the contact holes to form a metal layer; Etching the metal layer to form a source metal layer connected to the source region and a drain metal layer connected to the drain region.

16. A chip, characterized by The chip comprises an ESD device of the LDMOSFET structure of any one of claims 1-8.

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