Semiconductor device and manufacturing method thereof
By adopting the SOI substrate and conductive layer structure in the RF switching device, the problem of failure of the RF switching device at a lower operating voltage in the prior art is solved, and the effect of improving the breakdown voltage and Pmax performance is achieved.
Patent Information
- Application Number
- CN202311506744.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-10
- Publication Date
- 2025-05-23
AI Technical Summary
Existing RF switching devices fail at lower operating voltages, resulting in poor Pmax performance and urgently need to increase the breakdown voltage.
The SOI substrate and a conductive layer structure are adopted, wherein the conductive layer is located below the gate structure, which is closer to the second S/D region than to the first S/D region, ensuring that the potential of the second S/D region in the operating state is lower than that of the first S/D region.
By reducing the hole concentration in the well region, reducing the charge distribution and electric field aggregation near the gate, the breakdown voltage of the RF switching device is effectively improved, thereby improving the Pmax performance.
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Figure CN120035183A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a semiconductor device and a manufacturing method thereof. Background Art
[0002] Pmax, which reflects the maximum power handling capability of the RF device, is an important indicator for measuring the performance of the RF device. It is defined as the input power when the reflected harmonic changes suddenly. Pmax is positively correlated with the breakdown voltage VBR. Increasing the breakdown voltage between the source and the drain can effectively increase the operating power of the RF switching device.
[0003] However, when existing RF switching devices are working, charges will accumulate near the gate, causing breakdown of the source / drain, which in turn causes the RF switching device to fail at a lower operating voltage and have poor Pmax performance.
[0004] Therefore, how to increase the breakdown voltage of the RF switch device to increase the Pmax of the RF switch device is an urgent problem to be solved. Summary of the invention
[0005] The object of the present invention is to provide a semiconductor device and a method for manufacturing the same, so as to increase the breakdown voltage of a radio frequency switch device and thereby increase the Pmax of the radio frequency switch device.
[0006] To achieve the above object, the present invention provides a semiconductor device, comprising:
[0007] SOI substrate, including a lower substrate, an insulating buried layer and a semiconductor layer from bottom to top;
[0008] a well region formed in the semiconductor layer;
[0009] A gate structure formed on the well region;
[0010] A first S / D region and a second S / D region are respectively formed in the well regions on both sides of the gate structure;
[0011] A conductive layer is formed in the insulating buried layer and is located at least below the gate structure. The conductive layer is closer to the second S / D region than to the first S / D region. In a working state, the potential of the second S / D region is lower than the potential of the first S / D region.
[0012] Optionally, the buried insulating layer includes at least two stacked structures, and the conductive layer is formed in at least one layer of the stacked structure.
[0013] Optionally, the gate structure includes a gate layer and a sidewall formed on a sidewall of the gate layer.
[0014] Optionally, the conductive layer is located below the spacer, or the conductive layer extends from below the spacer to below the second S / D region.
[0015] Optionally, the conductive layer is made of metal or polysilicon.
[0016] The present invention also provides a method for manufacturing a semiconductor device, comprising:
[0017] providing a lower substrate and an upper substrate;
[0018] forming a first insulating dielectric layer on the lower substrate, and forming a second insulating dielectric layer on the upper substrate;
[0019] forming a conductive layer in the first insulating dielectric layer and / or the second insulating dielectric layer;
[0020] The first insulating dielectric layer and the second insulating dielectric layer are bonded to form an SOI substrate, and the first insulating dielectric layer and the second insulating dielectric layer serve as insulating buried layers of the SOI substrate.
[0021] Optionally, before forming the second insulating dielectric layer on the upper substrate, the method for manufacturing the semiconductor device further includes:
[0022] forming a peeling layer inside the upper substrate to separate the upper substrate into two parts;
[0023] After bonding the first insulating dielectric layer to the second insulating dielectric layer, the method for manufacturing the semiconductor device further includes:
[0024] The peeling layer is removed by stripping to thin the upper substrate to form a semiconductor layer.
[0025] Optionally, the method for manufacturing the semiconductor device further includes:
[0026] forming a well region in the upper substrate;
[0027] forming a gate structure on the well region, wherein the conductive layer is at least located below the gate structure;
[0028] A first S / D region and a second S / D region are formed in the well regions on both sides of the gate structure respectively, and the conductive layer is closer to the second S / D region than to the first S / D region, wherein in a working state, the potential of the second S / D region is lower than the potential of the first S / D region.
[0029] Optionally, the gate structure includes a gate layer and a sidewall formed on a sidewall of the gate layer.
[0030] Optionally, the conductive layer is located below the spacer, or the conductive layer extends from below the spacer to below the second S / D region.
[0031] Optionally, the conductive layer is made of metal or polysilicon.
[0032] Optionally, the step of forming the conductive layer in the first insulating dielectric layer and / or the second insulating dielectric layer includes:
[0033] Etching the first insulating dielectric layer and / or the second insulating dielectric layer to form a groove in the first insulating dielectric layer and / or the second insulating dielectric layer;
[0034] Filling the trench with a conductive material to form a conductive layer in the trench.
[0035] Optionally, after bonding the first insulating dielectric layer to the second insulating dielectric layer, the method for manufacturing the semiconductor device further includes:
[0036] An annealing process is performed.
[0037] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:
[0038] 1. The semiconductor device of the present invention comprises: an SOI substrate, comprising a lower substrate, an insulating buried layer and a semiconductor layer from bottom to top; a well region formed in the semiconductor layer; a gate structure formed on the well region; a first S / D region and a second S / D region, respectively formed in the well regions on both sides of the gate structure; a conductive layer, formed in the insulating buried layer and at least located below the gate structure, the conductive layer is closer to the second S / D region than to the first S / D region, wherein, in a working state, the potential of the second S / D region is lower than the potential of the first S / D region, so that the breakdown voltage of the radio frequency switching device can be increased, thereby increasing the Pmax of the radio frequency switching device.
[0039] 2. The manufacturing method of the semiconductor device of the present invention forms a first insulating dielectric layer on a lower substrate and a second insulating dielectric layer on an upper substrate; forms a conductive layer in the first insulating dielectric layer and / or the second insulating dielectric layer; bonds the first insulating dielectric layer to the second insulating dielectric layer to form an SOI substrate, wherein the first insulating dielectric layer and the second insulating dielectric layer serve as an insulating buried layer of the SOI substrate, thereby providing an SOI substrate with a conductive layer embedded in a BOX, and subsequently manufacturing other devices on the SOI substrate, so that the breakdown voltage of the radio frequency switching device can be increased, thereby increasing the Pmax of the radio frequency switching device. BRIEF DESCRIPTION OF THE DRAWINGS
[0040] Figure 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention;
[0041] Figure 2 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
[0042] Figure 3a to Figure 10 yes Figure 2 A schematic diagram of a device in a method for manufacturing a semiconductor device is shown.
[0043] Among them, Figures 1 to 10 The reference numerals are described as follows:
[0044] 11-lower substrate; 12-semiconductor layer; 120-upper substrate; 121-peeling layer; 13-buried insulating layer; 131-first insulating dielectric layer; 132-second insulating dielectric layer; 141-first conductive layer; 1411-first trench; 142-second conductive layer; 1421-second trench; 15-well region; 16-gate layer; 17-sidewall; 18-first S / D region; 19-second S / D region. DETAILED DESCRIPTION
[0045] In order to make the purpose, advantages and features of the present invention more clear, the semiconductor device and the manufacturing method thereof proposed by the present invention are further described in detail below. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.
[0046] An embodiment of the present invention provides a semiconductor device, comprising: an SOI substrate, comprising a lower substrate, an insulating buried layer and a semiconductor layer from bottom to top; a well region formed in the semiconductor layer; a gate structure formed on the well region; a first S / D region and a second S / D region, respectively formed in the well regions on both sides of the gate structure; a conductive layer, formed in the insulating buried layer and at least located below the gate structure, the conductive layer being closer to the second S / D region than to the first S / D region, wherein, in a working state, the potential of the second S / D region is lower than the potential of the first S / D region.
[0047] See below Figure 1 The semiconductor device provided in this embodiment is described in detail. Figure 1 It is also a longitudinal cross-sectional schematic diagram.
[0048] The SOI substrate includes, from bottom to top, a lower substrate 11 , an insulating buried layer 13 and a semiconductor layer 12 .
[0049] The lower substrate 11 and the semiconductor layer 12 may be made of any suitable semiconductor material, including but not limited to silicon, germanium, silicon germanium, silicon germanium carbide, silicon carbide and other semiconductors. The material of the insulating buried layer 13 includes silicon oxide or a material with a low dielectric constant (a dielectric constant lower than that of silicon oxide, such as silicon oxycarbide SiOC or silicon oxyfluoride SiOF).
[0050] The buried insulating layer 13 includes at least two stacked layers.
[0051] like Figure 1 As shown, the buried insulating layer 13 includes a first insulating dielectric layer 131 and a second insulating dielectric layer 132 stacked from bottom to top between the lower substrate 11 and the semiconductor layer 12 , and the first insulating dielectric layer 131 is bonded to the second insulating dielectric layer 132 .
[0052] The first insulating dielectric layer 131 and the second insulating dielectric layer 132 may be a single-layer structure or a stacked structure of at least two layers. One of the first insulating dielectric layer 131 and the second insulating dielectric layer 132 may be used as a bonding layer.
[0053] The conductive layer is formed in the insulating buried layer 13 .
[0054] The material of the conductive layer may include metal (for example, at least one of metal materials such as Cu, Ni, W, Ag and Au) or polysilicon.
[0055] When the conductive layer is made of metal, the conductive layer is formed inside the insulating buried layer 13, that is, the insulating buried layer 13 wraps the conductive layer so that the conductive layer is not in contact with the underlying substrate 11 or the semiconductor layer 12, so as to avoid the metal in the conductive layer from diffusing into the underlying substrate 11 and the semiconductor layer 12.
[0056] When the conductive layer is made of polysilicon, the conductive layer may not be in contact with the underlying substrate 11 or the semiconductor layer 12, or the conductive layer may be in contact with the underlying substrate 11 or the semiconductor layer 12; however, the conductive layer cannot be in contact with the underlying substrate 11 and the semiconductor layer 12 at the same time to avoid conduction between the underlying substrate 11 and the semiconductor layer 12 through the conductive layer.
[0057] The conductive layer is formed in at least one layer of the stacked structure of the buried insulating layer 13. The number of the conductive layer may be at least one.
[0058] When the buried insulating layer 13 includes the first insulating dielectric layer 131 and the second insulating dielectric layer 132, the conductive layer may be formed in the first insulating dielectric layer 131 and / or the second insulating dielectric layer 132. Figure 1 In the illustrated embodiment, a first conductive layer 141 is formed in the first insulating dielectric layer 131, and the first conductive layer 141 does not penetrate the first insulating dielectric layer 131, that is, the first conductive layer 141 does not contact the lower substrate 11; a second conductive layer 142 is formed in the second insulating dielectric layer 132, and the second conductive layer 142 does not penetrate the second insulating dielectric layer 132, that is, the second conductive layer 142 does not contact the semiconductor layer 12.
[0059] The conductive layer includes the first conductive layer 141 and / or the second conductive layer 142 . Further, the number of the first conductive layer 141 may be at least one, and the number of the second conductive layer 142 may be at least one.
[0060] When the conductive layer is formed in both the first insulating dielectric layer 131 and the second insulating dielectric layer 132, that is, the first insulating dielectric layer 131 is formed with the first conductive layer 141 and the second insulating dielectric layer 132 is formed with the second conductive layer 142, the first conductive layer 141 and the second conductive layer 142 can be aligned (e.g. Figure 1 shown) or staggered.
[0061] The well region 15 is formed in the semiconductor layer 12 .
[0062] The well region 15 may be formed in the entire thickness or a portion of the thickness of the semiconductor layer 12 .
[0063] The gate structure is formed on a portion of the well region 15 .
[0064] The gate structure includes a gate layer 16 and sidewall spacers 17 formed on opposite sidewalls of the gate layer 16 .
[0065] The first S / D region 18 and the second S / D region 19 are respectively formed in the well region 15 on both sides of the gate structure, that is, respectively formed in the well region 15 on both sides of the spacer 17 on the opposite side walls of the gate layer 16 .
[0066] The first S / D region 18 and the second S / D region 19 may be formed in the entire thickness or a partial thickness of the semiconductor layer.
[0067] The doping type of the well region 15 is opposite to that of the first S / D region 18 and the second S / D region 19. When the doping type of the well region 15 is P-type, the doping type of the first S / D region 18 and the second S / D region 19 is N-type, and at this time, the semiconductor device is NMOS; when the doping type of the well region 15 is N-type, the doping type of the first S / D region 18 and the second S / D region 19 is P-type, and at this time, the semiconductor device is PMOS.
[0068] The conductive layer is at least located below the gate structure, and the conductive layer is closer to the second S / D region 19 than to the first S / D region 18, wherein in a working state, the potential of the second S / D region 19 is lower than the potential of the first S / D region 18. Figure 1 In the illustrated embodiment, the first conductive layer 141 and the second conductive layer 142 are closer to the second S / D region 19 than to the first S / D region 18 .
[0069] In order to make the semiconductor device in working state, for NMOS, positive voltage can be applied to the first S / D region 18 and the gate layer 16, and the second S / D region 19 can be grounded or negative voltage can be applied. At this time, the first S / D region 18 is the drain region, and the second S / D region 19 is the source region; for PMOS, the first S / D region 18 can be grounded, and negative voltage can be applied to the second S / D region 19 and the gate layer 16. At this time, the first S / D region 18 is the source region, and the second S / D region 19 is the drain region. And, in the working state, the potential is from high to low from the first S / D region 18 to the second S / D region 19. And, preferably, the conductive layer is located below the sidewall 17 on the side of the gate layer 16 close to the second S / D region 19, or the conductive layer extends from below the sidewall 17 on the side of the gate layer 16 close to the second S / D region 19 to below the second S / D region 19. Figure 1 As shown, the first conductive layer 141 and the second conductive layer 142 may be located only within the L1 range below the side wall 17 on the side of the gate layer 16 close to the second S / D region 19; or, the first conductive layer 141 and the second conductive layer 142 may be partially located within the L1 range below the side wall 17, and the other part extends to the L2 range in the direction below the second S / D region 19.
[0070] In the working state, since the potential is from high to low from the first S / D region 18 to the second S / D region 19, the holes in the well region 15 will move from the high potential position to the low potential position, and the charges will gather under the gate, eventually leading to the breakdown of the source and drain, so that the device fails at a lower working voltage; in the present invention, since the conductive layer is formed in the insulating buried layer 13, and the conductive layer is closer to the second S / D region 19 than to the first S / D region 18, the hole concentration in the well region 15 above the conductive layer can be reduced, so that the The holes in the well region 15 that move to the low potential area close to the second S / D region 19 can be attracted into the conductive layer, thereby reducing the hole concentration in the well region 15 near the gate layer 16, reducing the charge distribution near the gate layer 16, improving the electric field distribution in the well region 15, and avoiding the electric field concentration near the gate layer 16, thereby effectively improving the breakdown voltage of the RF switching device, and then increasing the Pmax (input power when the reflected harmonic changes suddenly) of the RF switching device, so that the RF switching device has a higher operating power.
[0071] In one embodiment, when the conductive layer is located below the side wall 17 on the side of the gate layer 16 close to the second S / D region 19, or when the conductive layer extends from below the side wall 17 on the side of the gate layer 16 close to the second S / D region 19 to below the second S / D region 19, the conductive layer is located closer to the low potential region, so that the holes in the well region 15 near the gate layer 16 can be attracted into the conductive layer more and faster, thereby further reducing the hole concentration in the well region 15 near the gate layer 16, further reducing the charge distribution near the gate layer 16, thereby further improving the electric field distribution in the well region 15, and further avoiding electric field concentration near the gate layer 16.
[0072] In summary, the present invention provides a semiconductor device, comprising: an SOI substrate, including a lower substrate, an insulating buried layer and a semiconductor layer from bottom to top; a well region formed in the semiconductor layer; a gate structure formed on the well region; a first S / D region and a second S / D region, respectively formed in the well regions on both sides of the gate structure; a conductive layer, formed in the insulating buried layer, and at least located below the gate structure, the conductive layer is closer to the second S / D region than to the first S / D region, wherein in the working state, the potential of the second S / D region is lower than the potential of the first S / D region. The semiconductor device provided by the present invention enables the breakdown voltage of the radio frequency switching device to be increased, thereby increasing the Pmax of the radio frequency switching device.
[0073] An embodiment of the present invention provides a method for manufacturing a semiconductor device. Figure 2 ,from Figure 2 It can be seen that the method for manufacturing the semiconductor device includes:
[0074] Step S1, providing a lower substrate and an upper substrate;
[0075] Step S2, forming a first insulating dielectric layer on the lower substrate, and forming a second insulating dielectric layer on the upper substrate;
[0076] Step S3, forming a conductive layer in the first insulating dielectric layer and / or the second insulating dielectric layer;
[0077] Step S4: bonding the first insulating dielectric layer and the second insulating dielectric layer to form an SOI substrate, wherein the first insulating dielectric layer and the second insulating dielectric layer serve as an insulating buried layer of the SOI substrate.
[0078] See below Figure 3a to Figure 10 The method for manufacturing the semiconductor device provided in this embodiment is described in detail. Figure 3a to Figure 10 It is also a longitudinal cross-sectional schematic diagram.
[0079] Follow step S1, refer to Figure 3a and Figure 3b , providing a lower substrate 11 and an upper substrate 120.
[0080] The lower substrate 11 and the upper substrate 120 may be made of any appropriate semiconductor material, including but not limited to silicon, germanium, silicon germanium, silicon germanium carbide, silicon carbide and other semiconductors.
[0081] According to step S2, refer to Figure 4a and Figure 4b , a first insulating dielectric layer 131 is formed on the lower substrate 11 , and a second insulating dielectric layer 132 is formed on the upper substrate 120 .
[0082] like Figure 4a As shown, before forming the second insulating dielectric layer 132 on the upper substrate 120, the method for manufacturing the semiconductor device may further include: forming a peeling layer 121 inside the upper substrate 120 to separate the upper substrate 120 into two parts. The peeling layer 121 may be formed by injecting hydrogen ions into the upper substrate 120 at a temperature of 400°C to 600°C, and the injected hydrogen ions condense under heat treatment to break the chemical bonds (such as silicon-silicon bonds) of the material of the upper substrate 120, thereby facilitating the subsequent splitting of the upper substrate 120 through the peeling layer 121 to form the semiconductor layer 12.
[0083] The first insulating dielectric layer 131 and the second insulating dielectric layer 132 may be a single-layer structure or a stacked structure of at least two layers. One of the first insulating dielectric layer 131 and the second insulating dielectric layer 132 may be used as a bonding layer.
[0084] The first insulating dielectric layer 131 and the second insulating dielectric layer 132 are made of silicon oxide or a material with a low dielectric constant (a material with a dielectric constant lower than that of silicon oxide, such as silicon oxycarbide SiOC or silicon oxyfluoride SiOF).
[0085] According to step S3, refer to Figure 5a to Figure 5b , Figure 6a to Figure 6b and Figure 7a to Figure 7b , forming a conductive layer in the first insulating dielectric layer 131 and / or the second insulating dielectric layer 132 .
[0086] The step of forming the conductive layer in the first insulating dielectric layer 131 and / or the second insulating dielectric layer 132 may include: first, etching the first insulating dielectric layer 131 and / or the second insulating dielectric layer 132 to form a groove in the first insulating dielectric layer 131 and / or the second insulating dielectric layer 132; then, filling the conductive material in the groove to form a conductive layer in the groove.
[0087] Among them, Figure 5a , Figure 6a and Figure 7a In the embodiment shown, the second conductive layer 142 (for distinction, the conductive layer in the second insulating dielectric layer 132 is defined as the second conductive layer 142, and the conductive layer in the first insulating dielectric layer 131 is defined as the first conductive layer 141) is formed in the second insulating dielectric layer 132, and the steps include: first, as Figure 5a As shown, the second insulating dielectric layer 132 is etched to form a second trench 1421 in the second insulating dielectric layer 132; then, as shown Figure 6a As shown, a second conductive layer 142 is formed to fill the second trench 1421, and the second conductive layer 142 covers the second insulating dielectric layer 132; then, as shown Figure 7a As shown, the second conductive layer 142 covering the second insulating dielectric layer 132 is polished away by a chemical mechanical polishing process, and the second conductive layer 142 in the second groove 1421 is retained. The polished and planarized surface of the second insulating dielectric layer 132 is easier for subsequent bonding.
[0088] exist Figure 5b , Figure 6b and Figure 7b In the embodiment shown, the first conductive layer 141 is formed in the first insulating dielectric layer 131, and the steps include: first, Figure 5bAs shown, the first insulating dielectric layer 131 is etched to form a first trench 1411 in the first insulating dielectric layer 131; then, as shown Figure 6b As shown, a first conductive layer 141 is formed to fill the first trench 1411, and the first conductive layer 141 covers the first insulating dielectric layer 131; then, as shown Figure 7b As shown, the first conductive layer 141 covering the first insulating dielectric layer 131 is polished away by a chemical mechanical polishing process, and the first conductive layer 141 in the first groove 1411 is retained. The polished and planarized surface of the first insulating dielectric layer 131 is easier for subsequent bonding.
[0089] The material of the conductive layer may include metal (for example, at least one of metal materials such as Cu, Ni, W, Ag and Au) or polysilicon.
[0090] When the conductive layer is made of metal, the conductive layer in the first insulating medium layer 131 does not contact the lower substrate 11, and the conductive layer in the second insulating medium layer 132 does not contact the upper substrate 120, so as to prevent the metal in the conductive layer from diffusing into the lower substrate 11 and the upper substrate 120.
[0091] When the material of the conductive layer is polysilicon, the conductive layer in the first insulating dielectric layer 131 can be in contact with the lower substrate 11, or the conductive layer in the second insulating dielectric layer 132 can be in contact with the upper substrate 120, or the conductive layer in the first insulating dielectric layer 131 is not in contact with the lower substrate 11 and the conductive layer in the second insulating dielectric layer 132 is not in contact with the upper substrate 120; however, the conductive layer in the first insulating dielectric layer 131 cannot be in contact with the lower substrate 11 and the conductive layer in the second insulating dielectric layer 132 cannot be in contact with the upper substrate 120 at the same time, so as to avoid the lower substrate 11 and the upper substrate 120 being conductively connected through the conductive layer after the first insulating dielectric layer 131 and the second insulating dielectric layer 132 are bonded.
[0092] exist Figure 7a In the embodiment shown, the second conductive layer 142 does not penetrate the second insulating dielectric layer 132, that is, the second conductive layer 142 does not contact the upper substrate 120; Figure 7b In the illustrated embodiment, the first conductive layer 141 does not penetrate the first insulating dielectric layer 131 , that is, the first conductive layer 141 does not contact the lower substrate 11 .
[0093] The conductive layer includes the first conductive layer 141 and / or the second conductive layer 142 . Further, the number of the first conductive layer 141 may be at least one, and the number of the second conductive layer 142 may be at least one.
[0094] According to step S4, refer to Figure 8 , the first insulating dielectric layer 131 and the second insulating dielectric layer 132 are bonded to form an SOI substrate, and the first insulating dielectric layer 131 and the second insulating dielectric layer 132 together serve as the insulating buried layer 13 of the SOI substrate.
[0095] When the conductive layer is formed in both the first insulating dielectric layer 131 and the second insulating dielectric layer 132, that is, the first insulating dielectric layer 131 is formed with the first conductive layer 141 and the second insulating dielectric layer 132 is formed with the second conductive layer 142, when the first insulating dielectric layer 131 and the second insulating dielectric layer 132 are bonded, the first conductive layer 141 and the second conductive layer 142 can be aligned (e.g., Figure 8 shown) or staggered.
[0096] After bonding the first insulating dielectric layer 131 and the second insulating dielectric layer 132 and before subsequently forming the well region 15 in the semiconductor layer 12 , the method for manufacturing the semiconductor device further includes: performing an annealing process to improve the bonding strength.
[0097] Before subsequently forming the well region 15 in the semiconductor layer 12, the method for manufacturing the semiconductor device further includes: Fig. 9 As shown, the semiconductor layer 12 is formed after the peeling layer 121 is removed by peeling to thin the upper substrate 120 .
[0098] See also Fig.10 , the method for manufacturing the semiconductor device further comprises:
[0099] First, an ion implantation process is performed to form a well region 15 in the semiconductor layer 12 .
[0100] The well region 15 may be formed in the entire thickness or a portion of the thickness of the semiconductor layer 12 .
[0101] Then, a gate structure is formed on a portion of the well region 15 ; the gate structure includes a gate layer 16 and sidewall spacers 17 formed on opposite side walls of the gate layer 16 .
[0102] Then, an ion implantation process is performed to form the first S / D region 18 and the second S / D region 19 in the well region 15 on both sides of the gate structure, that is, the first S / D region 18 and the second S / D region 19 are formed in the well region 15 on both sides of the sidewalls 17 on the opposite side walls of the gate layer 16.
[0103] The first S / D region 18 and the second S / D region 19 may be formed in the entire thickness or a portion of the thickness of the semiconductor layer 12 .
[0104] The doping type of the well region 15 is opposite to that of the first S / D region 18 and the second S / D region 19. When the doping type of the well region 15 is P-type, the doping type of the first S / D region 18 and the second S / D region 19 is N-type, and at this time, the semiconductor device is NMOS; when the doping type of the well region 15 is N-type, the doping type of the first S / D region 18 and the second S / D region 19 is P-type, and at this time, the semiconductor device is PMOS.
[0105] The conductive layer is at least located below the gate structure, and the conductive layer is closer to the second S / D region 19 than to the first S / D region 18, wherein in a working state, the potential of the second S / D region 19 is lower than the potential of the first S / D region 18. Fig.10 In the illustrated embodiment, the first conductive layer 141 and the second conductive layer 142 are closer to the second S / D region 19 than to the first S / D region 18 .
[0106] In order to make the semiconductor device in working state, for NMOS, positive voltage can be applied to the first S / D region 18 and the gate layer 16, and the second S / D region 19 can be grounded or negative voltage can be applied, at this time, the first S / D region 18 is the drain region, and the second S / D region 19 is the source region; for PMOS, the first S / D region 18 can be grounded, and negative voltage can be applied to the second S / D region 19 and the gate layer 16, at this time, the first S / D region 18 is the source region, and the second S / D region 19 is the drain region. And, in the working state, the potential is from high to low in the direction from the first S / D region 18 to the second S / D region 19.
[0107] Furthermore, preferably, the conductive layer is located below the sidewall 17 on the side of the gate layer 16 close to the second S / D region 19, or the conductive layer extends from below the sidewall 17 on the side of the gate layer 16 close to the second S / D region 19 to below the second S / D region 19. Fig.10As shown, the first conductive layer 141 and the second conductive layer 142 may be located only within the L1 range below the side wall 17 on the side of the gate layer 16 close to the second S / D region 19; or, the first conductive layer 141 and the second conductive layer 142 may be partially located within the L1 range below the side wall 17, and the other part extends to the L2 range in the direction below the second S / D region 19.
[0108] In the working state, since the potential is from high to low from the first S / D region 18 to the second S / D region 19, the holes in the well region 15 will move from the high potential position to the low potential position, and the charges will gather under the gate, eventually leading to the breakdown of the source and drain, so that the device fails at a lower working voltage; in the present invention, since the conductive layer is formed in the insulating buried layer 13, and the conductive layer is closer to the second S / D region 19 than to the first S / D region 18, the hole concentration in the well region 15 above the conductive layer can be reduced, so that the The holes in the well region 15 that move to the low potential area close to the second S / D region 19 can be attracted into the conductive layer, thereby reducing the hole concentration in the well region 15 near the gate layer 16, reducing the charge distribution near the gate layer 16, improving the electric field distribution in the well region 15, and avoiding the electric field concentration near the gate layer 16, thereby effectively improving the breakdown voltage of the RF switching device, and then increasing the Pmax (input power when the reflected harmonic changes suddenly) of the RF switching device, so that the RF switching device has a higher operating power.
[0109] In one embodiment, when the conductive layer is located below the side wall 17 on the side of the gate layer 16 close to the second S / D region 19, or when the conductive layer extends from below the side wall 17 on the side of the gate layer 16 close to the second S / D region 19 to below the second S / D region 19, the conductive layer is located closer to the low potential region, so that the holes in the well region 15 near the gate layer 16 can be attracted into the conductive layer more and faster, thereby further reducing the hole concentration in the well region 15 near the gate layer 16, further reducing the charge distribution near the gate layer 16, thereby further improving the electric field distribution in the well region 15, and further avoiding electric field concentration near the gate layer 16.
[0110] In summary, the present invention provides a method for manufacturing a semiconductor device, including: providing a lower substrate and an upper substrate; forming a first insulating dielectric layer on the lower substrate, and forming a second insulating dielectric layer on the upper substrate; forming a conductive layer in the first insulating dielectric layer and / or the second insulating dielectric layer; bonding the first insulating dielectric layer to the second insulating dielectric layer to form an SOI substrate, wherein the first insulating dielectric layer and the second insulating dielectric layer serve as an insulating buried layer of the SOI substrate. The method for manufacturing a semiconductor device of the present invention enables providing an SOI substrate with a conductive layer embedded in a BOX, and subsequently making other devices on the SOI substrate, which can improve the breakdown voltage of the radio frequency switching device, thereby improving the Pmax of the radio frequency switching device.
[0111] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.
Claims
1. A semiconductor device, It is characterized in that include: SOI substrate, including a lower substrate, an insulating buried layer and a semiconductor layer from bottom to top; a well region formed in the semiconductor layer; A gate structure formed on the well region; A first S / D region and a second S / D region are respectively formed in the well regions on both sides of the gate structure; A conductive layer is formed in the insulating buried layer and is located at least below the gate structure. The conductive layer is closer to the second S / D region than to the first S / D region. In a working state, the potential of the second S / D region is lower than the potential of the first S / D region.
2. The semiconductor device according to claim 1, It is characterized in that The buried insulating layer includes at least two stacked structures, and the conductive layer is formed in at least one layer of the stacked structure.
3. The semiconductor device according to claim 1, It is characterized in that The gate structure includes a gate layer and a sidewall formed on a sidewall of the gate layer.
4. The semiconductor device according to claim 3, It is characterized in that The conductive layer is located below the spacer, or the conductive layer extends from below the spacer to below the second S / D region.
5. The semiconductor device according to claim 1, It is characterized in that The material of the conductive layer includes metal or polysilicon.
6. A method for manufacturing a semiconductor device, It is characterized in that include: providing a lower substrate and an upper substrate; forming a first insulating dielectric layer on the lower substrate, and forming a second insulating dielectric layer on the upper substrate; forming a conductive layer in the first insulating dielectric layer and / or the second insulating dielectric layer; The first insulating dielectric layer and the second insulating dielectric layer are bonded to form an SOI substrate, and the first insulating dielectric layer and the second insulating dielectric layer serve as insulating buried layers of the SOI substrate.
7. The method for manufacturing a semiconductor device according to claim 6, It is characterized in that Before forming the second insulating dielectric layer on the upper substrate, the method for manufacturing the semiconductor device further includes: forming a peeling layer inside the upper substrate to separate the upper substrate into two parts; After bonding the first insulating dielectric layer to the second insulating dielectric layer, the method for manufacturing the semiconductor device further includes: The peeling layer is removed by stripping to thin the upper substrate to form a semiconductor layer.
8. The method for manufacturing a semiconductor device according to claim 6, It is characterized in that The method for manufacturing the semiconductor device further includes: forming a well region in the upper substrate; forming a gate structure on the well region, wherein the conductive layer is at least located below the gate structure; A first S / D region and a second S / D region are formed in the well regions on both sides of the gate structure respectively, and the conductive layer is closer to the second S / D region than to the first S / D region, wherein in a working state, the potential of the second S / D region is lower than the potential of the first S / D region.
9. The method for manufacturing a semiconductor device according to claim 8, It is characterized in that The gate structure includes a gate layer and a sidewall formed on a sidewall of the gate layer.
10. The method for manufacturing a semiconductor device according to claim 9, It is characterized in that The conductive layer is located below the spacer, or the conductive layer extends from below the spacer to below the second S / D region.
11. The method for manufacturing a semiconductor device according to claim 6, It is characterized in that The material of the conductive layer includes metal or polysilicon.
12. The method for manufacturing a semiconductor device according to claim 6, It is characterized in that The step of forming the conductive layer in the first insulating dielectric layer and / or the second insulating dielectric layer comprises: Etching the first insulating dielectric layer and / or the second insulating dielectric layer to form a groove in the first insulating dielectric layer and / or the second insulating dielectric layer; Filling the trench with a conductive material to form a conductive layer in the trench.
13. The method for manufacturing a semiconductor device according to claim 6, It is characterized in that After bonding the first insulating dielectric layer to the second insulating dielectric layer, the method for manufacturing the semiconductor device further includes: An annealing process is performed.