A bidirectional thyristor chip with a lateral structure and a manufacturing method thereof

Abstract

The present invention discloses a lateral - structured triac chip and its manufacturing method, including an N - type silicon substrate. A P - type short base region group is arranged at the upper end of the N - type silicon substrate. A P - type field ring group is arranged outside the P - type short base region group, and an N+-type emitter region group is arranged inside the P - type short base region group. The present invention adopts a lateral - structured triac, without a punch - through ring structure, which can greatly improve the production efficiency. Moreover, the blocking voltage of 1000V can be achieved with the depth of the first P - type field ring and the second P - type field ring only being 35 - 40μm, and the leakage current is lower. The first N+-type emitter region, the second N+-type emitter region, and the third N+-type emitter region make the current density distribution more uniform, can withstand a higher di / dt, have a lower temperature rise, and the distance between the first P - type short base region and the second P - type short base region is far, greater than 250μm, with a small parasitic capacitance and a high dv / dt.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and particularly to a bidirectional thyristor chip with a lateral structure and a manufacturing method thereof. Background Art

[0002] Planar bidirectional thyristors all have a longitudinal structure. The bidirectional thyristor injects an N+ type emitter region on the back and the gate region, and it can be equivalently regarded as a combination of two anti-parallel connected unidirectional thyristors. The thyristor is divided into two regions, each occupying half of the area, to achieve bidirectional conduction.

[0003] Disadvantages of the prior art:

[0004] At present, the formation of the p+ type punch-through ring structure requires a long time for diffusion, with low efficiency. Moreover, the planar thyristor does not have a passivation groove structure. In order to achieve an 800V blocking voltage, a field ring structure needs to be added on both sides of the front p-type short base region to reduce the edge electric field intensity of the curved surface junction. The depth of the field ring is generally 60 - 80um, and it also requires a long time for diffusion. Summary of the Invention

[0005] The purpose of the present invention is to provide a bidirectional thyristor chip with a lateral structure and a manufacturing method thereof, so as to solve the problems raised in the above background art.

[0006] To achieve the above purpose, the present invention provides the following technical solution: A bidirectional thyristor chip with a lateral structure, including an N-type silicon substrate, a P-type short base region group is arranged on the upper end of the N-type silicon substrate, a P-type field ring group is arranged outside the P-type short base region group, and an N+ type emitter region group is arranged inside the P-type short base region group;

[0007] The P-type short base region group includes a first P-type short base region and a second P-type short base region, and the first P-type short base region and the second P-type short base region are respectively arranged on both sides of the upper end of the N-type silicon substrate;

[0008] The P-type field ring group includes a first P-type field ring and a second P-type field ring, the first P-type field ring is arranged outside the first P-type short base region, and the second P-type field ring is arranged outside the second P-type short base region;

[0009] The N+ type emitter region group includes a first N+ type emitter region, a second N+ type emitter region, and a third N+ type emitter region. The first N+ type emitter region is arranged inside the upper end of the first P-type short base region, the second N+ type emitter region is arranged on the upper end of the second P-type short base region and on the side close to the first P-type short base region, and the third N+ type emitter region is arranged on the upper end of the second P-type short base region and on the side far from the first P-type short base region;

[0010] A T1 electrode is provided on the upper end surface of the first N+-type emitter region, a T2 electrode is provided on the second N+-type emitter region, and a gate electrode is provided on the upper end surface of the third N+-type emitter region.

[0011] Preferably, an N+-type cutoff ring is provided on the upper end surface of the N-type silicon substrate around the outer sides of the first P-type short base region and the second P-type short base region; a surface passivation layer is provided on the N-type silicon substrate.

[0012] The present invention also provides a manufacturing method for a lateral structure bidirectional thyristor chip, and the manufacturing method specifically includes the following steps:

[0013] S1. Prepare the N-type silicon substrate with a resistivity of 80-100 Ω·cm, a thickness of 275-285 μm, and a <111> crystal orientation.

[0014] S2. Grow an oxide film with a thickness greater than 1.2 μm.

[0015] S3. Diffuse and push the junctions of the first P-type field ring and the second P-type field ring.

[0016] S4. Diffuse and push the junctions of the first P-type short base region and the second P-type short base region.

[0017] S5. Diffuse and push the junctions of the first N+-type emitter region, the second N+-type emitter region, the third N+-type emitter region, and the N+-type cutoff ring.

[0018] S6. Use BOE buffer etching solution to remove all the oxide layers on the front and back surfaces of the N-type silicon substrate.

[0019] S7. Deposit a SIPOS thin film and a silicon nitride thin film on the front surface of the N-type silicon substrate through an LPCVD device, deposit a TEOS thin film through a PECVD device, and the thicknesses of the SIPOS thin film, the silicon nitride thin film, and the TEOS thin film are 0.6 μm, 0.1 μm, and 1 μm respectively; and evenly coat photoresist on the front surface of the N-type silicon substrate through a spin coater, and after processes such as pre-baking, exposure, post-baking, development, and hard baking, open a lead window, use BOE buffer etching solution to etch away the TEOS thin film in the window, use a dry etching device to etch away the silicon nitride thin film and the SIPOS thin film in the window, and perform degluing, cleaning, and spin drying.

[0020] S8. Deposit a metal aluminum thin film with a thickness of 3 - 5 μm on the front side of the N-type silicon substrate through a high-vacuum electron beam evaporation equipment. Uniformly coat photoresist on the front side of the metal aluminum thin film through a spin coater. After pre-baking, exposure, post-baking, development, and hard baking processes, an anti-etching window is opened. Use a metal etching solution to remove the metal aluminum thin film within the window. After removing the photoresist, cleaning, and spin-drying, the remaining metals are the gate electrode, the T1 electrode, and the T2 electrode respectively.

[0021] Preferably, step S3 specifically includes the following steps:

[0022] a1. Uniformly coat photoresist on the front side of the N-type silicon substrate through a spin coater. After pre-baking, exposure, post-baking, development, and hard baking processes, open the windows for the first P-type field ring and the second P-type field ring. Use BOE buffered etching solution to etch away the silicon dioxide thin film within the windows for the first P-type field ring and the second P-type field ring, and then perform photoresist removal, cleaning, and spin-drying;

[0023] a2. Inject boron ions into the surface layer of the N-type silicon substrate within the windows for the first P-type field ring and the second P-type field ring through an ion implanter. The implantation energy is 30 - 50 keV, the implantation dose is 1.5E14 - 2E14 / cm 2 , and the implantation angle is 7°;

[0024] a3. Place the N-type silicon substrate in a diffusion furnace, introduce a protective gas, and perform diffusion and push-junction at high temperature.

[0025] Preferably, step S4 specifically includes the following steps:

[0026] b1. Uniformly coat photoresist on the front side of the N-type silicon substrate through a spin coater. After pre-baking, exposure, post-baking, development, and hard baking processes, open the windows for the first P-type short base region and the second P-type short base region. Use BOE buffered etching solution to etch away the silicon dioxide thin film within the windows for the first P-type short base region and the second P-type short base region, and then perform photoresist removal, cleaning, and spin-drying;

[0027] b2. Inject boron ions into the surface layer of the N-type silicon substrate within the windows for the first P-type short base region and the second P-type short base region through an ion implanter. The implantation energy is 50 - 80 keV, the implantation dose is 2.5E14 - 3.5E14 / cm 2 , and the implantation angle is 7°;

[0028] b3. Place the N-type silicon substrate in a diffusion furnace, introduce a protective gas, and perform diffusion and push-junction at high temperature. The final junction depth of the first P-type short base region and the second P-type short base region is 15 - 20 μm, and the final junction depth of the field ring is 35 - 40 μm.

[0029] Preferably, the step S5 specifically includes the following steps:

[0030] c1. Use a spin coater to evenly coat the positive surface of the N-type silicon substrate with photoresist. After pre-baking, exposure, post-baking, development, and hard baking processes, open the first N+-type emitter region, the second N+-type emitter region, the third N+-type emitter region, and the N+-type cutoff ring window. Use BOE buffered etchant to etch away the silicon dioxide film in the window, and then perform degumming, cleaning, and spin drying;

[0031] c2. Inject phosphorus ions into the surface layer of the N-type silicon substrate within the first N+-type emitter region, the second N+-type emitter region, the third N+-type emitter region, and the N+-type cutoff ring window through an ion implanter. The implantation energy is 50 - 80 keV, the implantation dose is 1.5E15 - 3E15 / cm 2 , and the implantation angle is 7°;

[0032] c3. Place the N-type silicon substrate in a diffusion furnace, introduce a protective gas, and perform diffusion and push-junction at high temperature. The final junction depth is 5 - 10 μm.

[0033] Compared with the prior art, the beneficial effects of the present invention are:

[0034] The present invention relates to a lateral structure bidirectional thyristor chip and its manufacturing method. The lateral structure bidirectional thyristor is adopted, and there is no need for a punch-through ring structure, which can greatly improve production efficiency. Moreover, a blocking voltage of 1000 V can be achieved with the depth of the first P-type field ring and the second P-type field ring only being 35 - 40 μm, and the leakage current is lower. The first N+-type emitter region, the second N+-type emitter region, and the third N+-type emitter region make the current density distribution more uniform, can withstand a higher di / dt, have a lower temperature rise, and the distance between the first P-type short base region and the second P-type short base region is far, greater than 250 μm, with a small parasitic capacitance and a high dv / dt. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a schematic diagram of the overall structure of the present invention;

[0036] Figure 2 It is a cross-sectional schematic diagram of the present invention;

[0037] Figure 3 It is a schematic diagram of the forward and reverse blocking voltages of the present invention;

[0038] Figure 4 It is a schematic diagram of conduction in three quadrants of the present invention;

[0039] In the figure: 110, N-type silicon substrate; 121, first P-type short base region; 122, second P-type short base region; 131, first P-type field ring; 132, second P-type field ring; 141, first N+-type emitter region; 142, second N+-type emitter region; 143, third N+-type emitter region; 151, T1 electrode; 152, T2 electrode; 153, gate electrode; 160, N+-type cutoff ring; 170, surface passivation layer. Detailed implementation manners

[0040] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0041] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present invention.

[0042] In the description of this patent, it should be noted that unless otherwise clearly defined and limited, the terms "installation", "connection", and "setting" should be understood in a broad sense. For example, it can be fixedly connected and set, or detachably connected and set, or integrally connected and set. For those of ordinary skill in the art, the specific meanings of the above terms in this patent can be understood according to specific circumstances.

[0043] In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "several" means two or more, unless otherwise specifically defined.

[0044] Embodiment

[0045] Please refer to Figures 1-4As shown in the figure, a technical solution of a bidirectional thyristor chip with a lateral structure provided by the present invention: includes an N-type silicon substrate 110, a P-type short base region group is arranged at the upper end of the N-type silicon substrate 110, a P-type field ring group is arranged outside the P-type short base region group, and an N+-type emitter region group is arranged inside the P-type short base region group. The P-type short base region group includes a first P-type short base region 121 and a second P-type short base region 122. The first P-type short base region 121 and the second P-type short base region 122 are respectively arranged on both sides of the upper end of the N-type silicon substrate 110. The P-type field ring group includes a first P-type field ring 131 and a second P-type field ring 132. The first P-type field ring 131 is arranged outside the first P-type short base region 121, and the second P-type field ring 132 is arranged outside the second P-type short base region 122. The N+-type emitter region group includes a first N+-type emitter region 141, a second N+-type emitter region 142, and a third N+-type emitter region 143. The first N+-type emitter region 141 is arranged inside the upper end of the first P-type short base region 121. The second N+-type emitter region 142 is arranged at the upper end of the second P-type short base region 122 and on the side close to the first P-type short base region 121. The third N+-type emitter region 143 is arranged at the upper end of the second P-type short base region 122 and on the side far from the first P-type short base region 121. A T1 electrode 151 is arranged on the upper end surface of the first N+-type emitter region 141, a T2 electrode 152 is arranged on the second N+-type emitter region 142, and a gate electrode 153 is arranged on the upper end surface of the third N+-type emitter region 143. An N+-type cutoff ring 160 is arranged around the outside of the first P-type short base region 121 and the second P-type short base region 122 on the upper end surface of the N-type silicon substrate 110. A surface passivation layer 170 is arranged on the N-type silicon substrate 110; the overall structure does not require a punch-through ring structure, which can greatly improve production efficiency. Moreover, the depth of the first P-type field ring 131 and the second P-type field ring 132 only needs to be 35-40 μm to achieve a blocking voltage of 1000V, and the leakage current is lower. The first N+-type emitter region 141, the second N+-type emitter region 142, and the third N+-type emitter region 143 make the current density distribution more uniform, can withstand a higher di / dt, and have a lower temperature rise. In addition, the distance between the first P-type short base region 121 and the second P-type short base region 122 is far, the distance between the first P-type short base region 121 and the second P-type short base region 122 is greater than 250 μm, the parasitic capacitance is small, and the dv / dt is high.

[0046] Further, the bidirectional conduction is divided into three cases. Case 1: The T1 electrode 151 is connected to the positive, the T2 electrode 152 is connected to the negative, the main current flows from the T1 electrode 151 to the T2 electrode 152, the gate electrode 153 is connected to the positive, the T2 electrode 152 is connected to the negative, and the trigger current flows from the gate electrode 153 to the T2 electrode 152. At this time, it conducts in the first quadrant. Case 2: The T1 electrode 151 is connected to the positive, the T2 electrode 152 is connected to the negative, the main current flows from the T1 electrode 151 to the T2 electrode 152, the gate electrode 153 is connected to the negative, the T2 electrode 152 is connected to the positive, and the trigger current flows from the T2 electrode 152 to the gate electrode 153. At this time, it conducts in the second quadrant. Case 3: The T1 electrode 151 is connected to the negative, the T2 electrode 152 is connected to the positive, the main current flows from the T2 electrode 152 to the T1 electrode 151, the gate electrode 153 is connected to the negative, the T2 electrode 152 is connected to the positive, and the trigger current flows from the T2 electrode 152 to the gate electrode 153. At this time, it conducts in the third quadrant.

[0047] The present invention provides a manufacturing method for a lateral structure bidirectional thyristor chip. The manufacturing method specifically includes the following steps:

[0048] S1. Prepare the N-type silicon substrate 110 with a resistivity of 80 - 100 Ω·cm, a thickness of 275 - 285 μm, and a <111> crystal orientation.

[0049] S2. Grow an oxide film with a thickness greater than 1.2 μm.

[0050] S3. Diffuse and push the first P-type field ring 131 and the second P-type field ring 132.

[0051] a1. Uniformly coat the positive side of the N-type silicon substrate 110 with photoresist through a spin coater. After pre-baking, exposure, post-baking, development, and hardening processes, open windows for the first P-type field ring 131 and the second P-type field ring 132. Use BOE buffer etching solution to etch away the silicon dioxide film within the windows of the first P-type field ring 131 and the second P-type field ring 132, and then perform degluing, cleaning, and spin-drying.

[0052] a2. Inject boron ions into the surface layer of the N-type silicon substrate 110 within the windows of the first P-type field ring 131 and the second P-type field ring 132 through an ion implanter. The injection energy is 30 - 50 keV, the injection dose is 1.5E14 - 2E14 / cm 2 , and the injection angle is 7°.

[0053] a3. Place the N-type silicon substrate 110 in a diffusion furnace, introduce a protective gas, and perform diffusion and push at high temperature.

[0054] S4. Diffuse and push the first P-type short base region 121 and the second P-type short base region 122.

[0055] b1. Use a spin coater to uniformly coat the positive side of the N-type silicon substrate 110 with photoresist. After pre-baking, exposure, post-baking, development, and hard baking processes, open windows for the first P-type short base region 121 and the second P-type short base region 122. Use BOE buffer etching solution to etch away the silicon dioxide film within the windows of the first P-type short base region 121 and the second P-type short base region 122, and then perform photoresist stripping, cleaning, and spin drying;

[0056] b2. Use an ion implanter to implant boron ions into the surface layer of the N-type silicon substrate 110 within the windows of the first P-type short base region 121 and the second P-type short base region 122. The implantation energy is 50 - 80 keV, the implantation dose is 2.5E14 - 3.5E14 / cm 2 , and the implantation angle is 7°;

[0057] b3. Place the N-type silicon substrate 110 in a diffusion furnace, introduce a protective gas, and perform diffusion and push-annealing at high temperature. The final junction depth of the first P-type short base region 121 and the second P-type short base region 122 is 15 - 20 μm, and the final junction depth of the first P-type field ring 131 and the second P-type field ring 132 is 35 - 40 μm;

[0058] S5. Diffuse and push-anneal the first N+ emitter region 141, the second N+ emitter region 142, the third N+ emitter region 143, and the N+ cutoff ring 160;

[0059] c1. Use a spin coater to uniformly coat the positive side of the N-type silicon substrate 110 with photoresist. After pre-baking, exposure, post-baking, development, and hard baking processes, open windows for the first N+ emitter region 141, the second N+ emitter region 142, the third N+ emitter region 143, and the N+ cutoff ring 160. Use BOE buffer etching solution to etch away the silicon dioxide film within the windows, and then perform photoresist stripping, cleaning, and spin drying;

[0060] c2. Use an ion implanter to implant phosphorus ions into the surface layer of the N-type silicon substrate 110 within the windows of the first N+ emitter region 141, the second N+ emitter region 142, the third N+ emitter region 143, and the N+ cutoff ring 160. The implantation energy is 50 - 80 keV, the implantation dose is 1.5E15 - 3E15 / cm 2 , and the implantation angle is 7°;

[0061] c3. Place the N-type silicon substrate 110 in a diffusion furnace, introduce a protective gas, and perform diffusion and push-annealing at high temperature. The final junction depth is 5 - 10 μm;

[0062] S6. Use BOE buffer etching solution to completely remove the oxide layers on the positive and negative sides of the N-type silicon substrate 110;

[0063] S7. Deposit a SIPOS thin film and a silicon nitride thin film on the front side of the N-type silicon substrate 110 through an LPCVD device, deposit a TEOS thin film through a PECVD device. The thicknesses of the SIPOS thin film, the silicon nitride thin film, and the TEOS thin film are 0.6 μm, 0.1 μm, and 1 μm respectively. And uniformly coat photoresist on the front side of the N-type silicon substrate 110 through a spin coater. After processes such as pre-baking, exposure, post-baking, development, and hard baking, lead windows are opened. Use a BOE buffer etching solution to etch away the TEOS thin film within the windows, use a dry etching device to etch away the silicon nitride thin film and the SIPOS thin film within the windows, and then remove the glue, clean, and spin dry.

[0064] S8. Evaporate a layer of aluminum metal thin film on the front side of the N-type silicon substrate 110 through a high-vacuum electron beam evaporation device. The thickness of the aluminum metal thin film is 3 - 5 μm. Uniformly coat photoresist on the front side of the aluminum metal thin film through a spin coater. After processes such as pre-baking, exposure, post-baking, development, and hard baking, an anti-etching window is opened. Use a metal etching solution to remove the aluminum metal thin film within the window. After removing the glue, cleaning, and spin drying, the remaining metals are the gate electrode 153, the T1 electrode 151, and the T2 electrode 152.

[0065] The above shows and describes the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited by the above embodiments. The above embodiments and the descriptions in the specification are only preferred examples of the present invention and are not used to limit the present invention. Without departing from the spirit and scope of the present invention, the present invention will have various changes and improvements, and these changes and improvements all fall within the scope of the present invention claimed. The scope of protection claimed by the present invention is defined by the appended claims and their equivalents.

Claims

1. A bidirectional thyristor chip with a horizontal structure, comprising an N-type silicon substrate (110), characterized in that: An N-type silicon substrate (110) is provided with a P-type short base region group at its upper end. A P-type field ring group is provided outside the P-type short base region group, and an N+-type emitter region group is provided inside the P-type short base region group; The P-type short base region group includes a first P-type short base region (121) and a second P-type short base region (122). The first P-type short base region (121) and the second P-type short base region (122) are respectively provided on both sides of the upper end of the N-type silicon substrate (110); The P-type field ring group includes a first P-type field ring (131) and a second P-type field ring (132). The first P-type field ring (131) is provided outside the first P-type short base region (121), and the second P-type field ring (132) is provided outside the second P-type short base region (122); The N+-type emitter region group includes a first N+-type emitter region (141), a second N+-type emitter region (142), and a third N+-type emitter region (143). The first N+-type emitter region (141) is provided inside the upper end of the first P-type short base region (121). The second N+-type emitter region (142) is provided at the upper end of the second P-type short base region (122) and on the side close to the first P-type short base region (121). The third N+-type emitter region (143) is provided at the upper end of the second P-type short base region (122) and on the side far from the first P-type short base region (121); A T1 electrode (151) is provided on the upper end surface of the first N+-type emitter region (141), a T2 electrode (152) is provided on the second N+-type emitter region (142), and a gate electrode (153) is provided on the upper end surface of the third N+-type emitter region (143).

2. The triac chip with a lateral structure according to claim 1, characterized in that: An N+-type cutoff ring (160) is provided around the outside of the first P-type short base region (121) and the second P-type short base region (122) on the upper end surface of the N-type silicon substrate (110); The N-type silicon substrate (110) is provided with a surface passivation layer (170).

3. A manufacturing method of a bidirectional thyristor chip with a lateral structure according to any one of claims 1-2, characterized in that: The manufacturing method specifically includes the following steps: S1. Prepare the N-type silicon substrate (110) with a resistivity of 80~100 Ω·cm, a thickness of 275~285 μm, and a <111> crystal orientation; S2. Grow an oxide film with a thickness greater than 1.2 μm; S3. Diffuse and push the junctions of the first P-type field ring (131) and the second P-type field ring (132); S4. Diffuse and push the junctions of the first P-type short base region (121) and the second P-type short base region (122); S5. Diffuse and push the junctions of the first N+-type emitter region (141), the second N+-type emitter region (142), the third N+-type emitter region (143), and the N+-type cutoff ring (160); S6. Use a BOE buffer etching solution to remove all the oxide layers on the front and back surfaces of the N-type silicon substrate (110); S7. Deposit a SIPOS thin film and a silicon nitride thin film on the front side of the N-type silicon substrate (110) by an LPCVD device, deposit a TEOS thin film by a PECVD device. The thicknesses of the SIPOS thin film, the silicon nitride thin film, and the TEOS thin film are 0.6 μm, 0.1 μm, and 1 μm respectively. And evenly coat photoresist on the front side of the N-type silicon substrate (110) by a spin coater. After processes of pre-baking, exposure, post-baking, development, and hard baking, open a lead window, etch away the TEOS thin film in the window by using a BOE buffer etching solution, etch away the silicon nitride thin film and the SIPOS thin film in the window by a dry etching device, and perform degumming, cleaning, and spin-drying. S8. Evaporate a layer of aluminum metal thin film on the front side of the N-type silicon substrate (110) by a high-vacuum electron beam evaporation device. The thickness of the aluminum metal thin film is 3 - 5 μm. Evenly coat photoresist on the front side of the aluminum metal thin film by a spin coater. After processes of pre-baking, exposure, post-baking, development, and hard baking, open an etching-back window, use a metal etching solution to remove the aluminum metal thin film in the window. After degumming, cleaning, and spin-drying, the remaining metals are the gate electrode (153), the T1 electrode (151), and the T2 electrode (152).

4. The manufacturing method of a bidirectional thyristor chip with a lateral structure according to claim 3, characterized in that: The step S3 specifically includes the following steps: a1. Evenly coat photoresist on the front side of the N-type silicon substrate (110) by a spin coater. After processes of pre-baking, exposure, post-baking, development, and hard baking, open windows for the first P-type field ring (131) and the second P-type field ring (132), etch away the silicon dioxide thin film in the windows of the first P-type field ring (131) and the second P-type field ring (132) by using a BOE buffer etching solution, and perform degumming, cleaning, and spin-drying. a2. Inject boron ions into the surface layer of the N-type silicon substrate (110) within the windows of the first P-type field ring (131) and the second P-type field ring (132) through an ion implanter, with an implantation energy of 30 - 50 keV and an implantation dose of 1.5E14 - 2E14 / cm 2 , and the implantation angle is 7°; a3. Place the N-type silicon substrate (110) in a diffusion furnace, introduce a protective gas, and perform diffusion and push-joining at high temperature.

5. The manufacturing method of a bidirectional thyristor chip with a lateral structure according to claim 3, characterized in that: The step S4 specifically includes the following steps: b1. Evenly coat photoresist on the front side of the N-type silicon substrate (110) by a spin coater. After processes of pre-baking, exposure, post-baking, development, and hard baking, open windows for the first P-type short base region (121) and the second P-type short base region (122), etch away the silicon dioxide thin film in the windows of the first P-type short base region (121) and the second P-type short base region (122) by using a BOE buffer etching solution, and perform degumming, cleaning, and spin-drying. b2. Inject boron ions into the surface layer of the N-type silicon substrate (110) within the windows of the first P-type short base region (121) and the second P-type short base region (122) through an ion implanter, with an implantation energy of 50 - 80 keV and an implantation dose of 2.5E14 - 3.5E14 / cm 2 , and the implantation angle is 7°; b3. Place the N-type silicon substrate (110) in a diffusion furnace, introduce a protective gas, and perform diffusion and push-joining at high temperature. The final junction depth of the first P-type short base region (121) and the second P-type short base region (122) is 15 - 20 μm, and the final junction depth of the field ring is 35 - 40 μm.

6. The manufacturing method of a bidirectional thyristor chip with a lateral structure according to claim 3, characterized in that: The step S5 specifically includes the following steps: c1. Use a spin coater to evenly coat the positive side of the N-type silicon substrate (110) with photoresist. After pre-baking, exposure, post-baking, development, and hard baking processes, openings are made for the first N+-type emitter region (141), the second N+-type emitter region (142), the third N+-type emitter region (143), and the N+-type cutoff ring (160) window. Use BOE buffered etching solution to etch away the silicon dioxide film within the window, and then perform degumming, cleaning, and spin drying. c2. Inject phosphorus ions into the surface layer of the N-type silicon substrate (110) within the windows of the first N+ emitter region (141), the second N+ emitter region (142), the third N+ emitter region (143), and the N+ cutoff ring (160) through an ion implanter, with an implantation energy of 50 - 80 keV and an implantation dose of 1.5E15 - 3E15 / cm 2 , and an implantation angle of 7°; c3. Place the N-type silicon substrate (110) in a diffusion furnace, introduce a protective gas, and perform diffusion and push-junction at high temperature, with a final junction depth of 5 - 10 μm.

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