Semiconductor structure including high

Abstract

A semiconductor structure including a high kappa (high-kappa) material for a source / drain (S / D) and / or heat spreader and a method of forming the same are provided. The semiconductor structure includes a substrate, a plurality of channel layers stacked over the substrate, a gate structure covering the plurality of channel layers, and S / D regions disposed over the substrate at opposite sides of the gate structure and connecting the plurality of channel layers. The material of the S / D region includes a highly thermally conductive material having a single crystal structure, such as boron arsenide (BAs) having a thermal conductivity greater than 1000 W / mK. In this case, the high thermal conductivity material can effectively dissipate heat generated by the semiconductor structure, thereby improving the yield and reliability of the semiconductor structure.

Description

Technical Field

[0001] An embodiment of the present invention relates to a semiconductor structure including a high thermal conductivity material and a method for forming the same. Background Art

[0002] Technological advances in integrated circuit (IC) materials and design have produced successive generations of ICs, each with smaller and more complex circuits than the previous ones. Over the course of IC evolution, functional density (e.g., the number of interconnected components per chip area) has generally increased while geometry size has decreased. This process of downscaling can often provide benefits by increasing production efficiency and reducing associated costs.

[0003] This reduction in size has also increased the complexity of IC processing and manufacturing, and similar developments in IC processing and manufacturing are needed to achieve these advances. For example, multi-gate components have been introduced to replace planar transistors. On the other hand, the involvement of more different components of different materials means that requirements are placed on thermal management and heat dissipation efficiency due to the high power density of ICs. Summary of the invention

[0004] An embodiment of the present invention provides a semiconductor element including a substrate, a plurality of channel layers stacked on the substrate, a gate structure covering the plurality of channel layers, and a source / drain (S / D) region disposed on the substrate at opposite sides of the gate structure and connected to the plurality of channel layers. The material of the S / D region includes a high thermal conductivity material having a single crystal structure.

[0005] An embodiment of the present invention provides a method for forming a semiconductor structure, comprising: forming a superlattice structure on a substrate, wherein the superlattice structure includes a plurality of alternately stacked nanostructured channel layers; forming a gate structure to cover the plurality of nanostructured channel layers; and forming a source / drain (S / D) region on the substrate at an opposite side of the gate structure to connect the plurality of channel layers, wherein a material of the S / D region includes a high-κ material having a single crystal structure.

[0006] An embodiment of the present invention provides a method for forming a semiconductor structure, including: forming a heat-conducting layer on a carrier, wherein the material of the heat-conducting layer includes a high-κ material with a single crystal structure; forming a first bonding layer on the heat-conducting layer; forming a second bonding layer on a component wafer; and bonding the component wafer to the carrier so that the heat generated by the component wafer can be dissipated to the carrier through the heat-conducting layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 is an isometric view of a nanosheet transistor according to some embodiments.

[0009] Figure 2 is a flow chart of a method of forming a semiconductor structure according to some embodiments.

[0010] Figures 3 to 7 is a cross-sectional view of an intermediate stage in the formation of a semiconductor structure according to some embodiments.

[0011] Figure 8 is a flow chart of a method of forming a semiconductor structure according to some embodiments.

[0012] Figures 9 to 14 is a cross-sectional view of an intermediate stage in the formation of a semiconductor structure according to some embodiments. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are only examples and are not intended to be limiting. For example, the following description may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may reuse reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, rather than representing the relationship between the various embodiments and / or configurations discussed. Throughout the disclosure, unless otherwise described, similar reference numerals represent similar features and may indicate similar compositions or formation processes. Here, for simplicity, features with the same reference numerals may be described only once.

[0014] Additionally, for ease of description, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," and the like, may be used herein to describe the relationship of one element or feature to another (other) element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the element in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0015] The gate-around (GAA) transistor structure can be patterned by any suitable method. For example, one or more photolithography processes (including double patterning or multiple patterning processes) can be used to pattern the structure. In general, the double patterning or multiple patterning process combines the photolithography process with a self-aligned process, thereby allowing the creation of a pattern with a pitch smaller than that obtainable using a single direct photolithography process, for example. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. A self-aligned process is used to form a spacer along the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacer can then be used to pattern the GAA structure.

[0016] The present disclosure is generally related to a semiconductor structure and its process, and more specifically to a multi-gate transistor. The multi-gate transistor includes those transistors whose gate structure is formed on at least two sides of the channel region. These multi-gate elements may include p-type metal oxide semiconductor elements or n-type metal oxide semiconductor multi-gate elements. Due to its fin-like structure, specific examples may be presented herein and referred to as FinFETs. An embodiment of a multi-gate transistor type called a wrap-around gate (GAA) element is also presented herein. GAA elements include any element whose gate structure or part thereof is formed on four sides of the channel region (e.g., wrapping around a portion of the channel region). The elements proposed herein also include embodiments having channel regions arranged in nanosheet channels, strip channels, and / or other suitable channel configurations. Presented herein are embodiments of elements that may have one or more channel regions (e.g., nanosheets) associated with a single continuous gate structure. However, those skilled in the art will understand that the teachings may be applied to a single channel (e.g., a single nanosheet) or any number of channels. Those skilled in the art may understand other examples of semiconductor elements that may benefit from the various aspects of the present disclosure.

[0017] Nanostructured field effect transistors (FETs) include, for example, FinFETs, nanosheet transistors, nanowire transistors, gate-all-around FETs (GAAFETs), multi-bridge channel transistors, and nanoribbon transistors. Figure 1 An isometric view of a nanosheet transistor 10 is shown having a plurality of nanosheets 14 stacked on a substrate 12 and a gate structure 18 encapsulating the nanosheets 14 , wherein active regions are separated from each other by isolation regions 13 .

[0018] The disclosed embodiments are shown and described by way of example as nanosheet transistors 10 having a plurality of channels 14 having a silicon (Si) containing material. The channels 14 described herein may also be applied to other types of FETs, such as FinFETs, GAAFETs, nanowire FETs, complementary field effect transistors (CFETs), or 2D planar FETs.

[0019] Materials containing Si can have good electron mobility, but poor hole mobility. In addition, silicon does not conduct heat very well, which is why overheating problems and expensive cooling systems are common in electronics. In this context, thermal management of modern electronic components becomes very important.

[0020] According to some embodiments, a new material with high thermal conductivity (e.g., boron arsenide (BAs)) can be used to replace traditional Si-containing materials (e.g., epitaxial silicon (Si) or epitaxial silicon germanium (SiGe)) to form BAs source / drain (S / D) regions in nanostructured FETs. BAs can overcome the heat dissipation challenges in integrated circuit (IC) manufacturing with increasing power density to dissipate the heat generated by nanostructured FETs, thereby improving the yield and reliability of nanostructured FETs. In addition, this new material exhibits excellent high mobility for both electrons and holes to increase switching speed, thereby improving component performance. In addition, due to the high thermal conductivity (greater than 1000W / mK), BAs can also be used as a heat sink in the back-end of the line (BEOL) process.

[0021] Figure 2 Reference according to some embodiments is shown Figures 3 to 7 Operations in method 200 of forming a semiconductor structure. The semiconductor structure shown in the following embodiments uses a nanosheet transistor as an exemplary embodiment. However, the embodiments disclosed herein are not limited to this. In some other embodiments, the semiconductor structure can be applied to but not limited to various types of nanostructured FETs, such as FinFETs, nanowire transistors, wrap-around gate FETs (GAAFETs), multi-bridge channel transistors, nanoribbon transistors, CFETs or combinations thereof. The operations may be performed in a different order, or not performed, depending on the specific application. It is worth noting that method 200 may not be able to produce a complete nanosheet transistor. Therefore, it should be understood that additional processes may be provided before, during or after method 200, and some of these additional processes may only be briefly described herein.

[0022] Reference Figure 2 In operation 202, a superlattice structure 155 may be formed on the substrate 100, such as Figure 3As shown. In some embodiments, substrate 100 includes a crystalline silicon substrate (e.g., a wafer). Depending on design requirements, substrate 100 may include various doped regions (e.g., a p-type well and / or an n-type well). In some embodiments, the doped regions may be doped with p-type or n-type dopants. For example, the doped regions may be doped with p-type dopants such as boron or BF2; n-type dopants such as phosphorus or arsenic; and / or combinations thereof. The doped regions may be configured for n-type nanosheet FETs, or alternatively, configured for p-type nanosheet FETs. For clarity, in Figure 3 In some alternative embodiments, the substrate 100 includes an elemental semiconductor such as silicon or germanium, a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide, an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP, or a combination thereof.

[0023] In some embodiments, the superlattice structure 155 may be in the form of a multi-layer nanosheet stack. The superlattice structure 155 may include a stack of alternating nanostructure channel layers 121 and nanostructure sacrificial layers 122. In some embodiments, the nanostructure sacrificial layer 122 may be in contact with the substrate 100. In some alternative embodiments, the nanostructure channel layer 121 may be in contact with the substrate 100. In some embodiments, the superlattice structure 155 is formed by depositing a stack of alternating configurations of two different semiconductor layers. The nanostructure channel layer 121 and the nanostructure sacrificial layer 122 may be different materials with different etching selectivities, so that the nanostructure sacrificial layer 122 is replaced in a subsequent process, while the nanostructure channel layer 121 remains as part of the nanosheet transistor. Although Figure 3 Three nanostructured channel layers 121 and two nanostructured sacrificial layers 122 are shown, but any number of nanostructured layers may be included in each superlattice structure 155 .

[0024] In some embodiments, the nanostructure channel layer 121 and the nanostructure sacrificial layer 122 include different materials. For example, the nanostructure sacrificial layer 122 is a SiGe layer having a germanium percentage in the range between about 15wt% and 40wt%, while the nanostructure channel layer 121 is a Si layer without germanium. However, the embodiments of the present invention are not limited thereto, and in other embodiments, the nanostructure channel layer 121 and the nanostructure sacrificial layer 122 may have materials with different etching selectivities. In some embodiments, the nanostructure channel layer 121 and the nanostructure sacrificial layer 122 are formed by an epitaxial growth process, such as a molecular beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, etc. At this time, the nanostructure channel layer 121 is an epitaxial Si layer, and the nanostructure sacrificial layer 122 is an epitaxial SiGe layer. In some alternative embodiments, the nanostructure channel layer 121 and the nanostructure sacrificial layer 122 are formed by suitable deposition, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. At this time, the nanostructure channel layer 121 is a polycrystalline Si layer, and the nanostructure sacrificial layer 122 is a polycrystalline SiGe layer.

[0025] In some embodiments, the nanostructure channel layer 121 includes materials similar to each other, such as epitaxial Si, and the nanostructure sacrificial layer 122 includes materials similar to each other, such as epitaxial SiGe. The alternating configuration of the superlattice structure 155 can be achieved by alternately depositing or epitaxially growing Si layers and SiGe layers starting from the substrate 100. The thickness of each of the nanostructure layers 121 and 122 can be adjusted according to the technology node, and the embodiments of the present disclosure are not limited thereto. In some embodiments, the uppermost nanostructure layer (e.g., Si layer) of the superlattice structure 155 can be thicker than the underlying nanostructure layer.

[0026] The superlattice structure 155 may be formed by an epitaxial growth process. The epitaxial growth process may include a combination of deposition operations and epitaxial growth operations, such as chemical vapor deposition (CVD), such as plasma enhanced CVD (PECVD), thermal CVD, low pressure CVD (LPCVD), rapid thermal chemical vapor deposition (RTCVD), metal organic chemical vapor deposition (MOCVD), atomic layer CVD (ALCVD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD) or other suitable CVD processes. In some embodiments, the layers of the superlattice structure 155 may be grown by selective epitaxial growth (SEG), in which an etching gas may be added to promote selective growth on exposed semiconductor surfaces rather than on insulating materials.

[0027] In some embodiments, the epitaxial growth process may involve one or more silicon or SiGe precursor gases, such as monosilane (SiH 4 ), disilane (Si2 H 6 ), germane (GeH 4 ) and digermane (Ge 2 H 6 ) to form epitaxial Si and / or epitaxial SiGe for use as the nanostructure channel layer 121 and / or the nanostructure sacrificial layer 122. The doping of the superlattice structure 155 can also be determined by introducing one or more precursors during the above-mentioned epitaxial growth process. For example, the superlattice structure 155 can be in-situ p-type or n-type doped using a p-type or n-type doping precursor during the epitaxial growth process.

[0028] Refer again Figure 2 After forming the superlattice structure 155, operation 204 is performed to form a sacrificial gate structure 107 on the superlattice structure 155. Figure 3 As shown. The sacrificial gate structure 107 may include a polysilicon gate structure having sidewall spacers 128. The polysilicon gate structure may be deposited and then patterned using a hard mask (e.g., an oxide material that may be grown and / or deposited using an ALD process). The sacrificial gate structure 107 will later be replaced by a metal surround gate (GAA) structure 158.

[0029] Reference Figure 2 In operation 206, an epitaxial S / D region 170 may be formed, such as Figure 5 Specifically, the end of the superlattice structure 155 can be removed and etched back to form a recess 165, as shown in FIG. Figure 4 As shown. Herein, the recess 165 may be referred to as a source / drain (S / D) recess 165. In some embodiments, the end of the superlattice structure 155 may be removed by an anisotropic etching process, an isotropic etching process, a combination thereof, or any suitable etching process as described above. After the S / D recess process, the superlattice structure 155 layer remains in the channel region 157 below the sacrificial gate structure 107, as shown in FIG. Figure 4 After forming the S / D recess 165, a portion of the nanostructure sacrificial layer 122 is laterally etched back to form a plurality of cavities between the nanostructure channel layers 121. Then, a dielectric material is formed to fill the cavities to form inner spacers 164 between the nanostructure sacrificial layer 122 and the S / D recess 165. After forming the inner spacers 164, an epitaxial S / D region 170 is formed in the S / D recess 165 to connect the nanostructure channel layers 121, as shown in FIG. Figure 5 shown.

[0030] Specifically, the epitaxial S / D region 170 may include a high thermal conductivity material having a single crystal structure. In some embodiments, the epitaxial S / D region 170 is formed of boron arsenide. In some embodiments, the epitaxial S / D region 170 includes a boron arsenide block. In some embodiments, the epitaxial S / D region 170 does not have silicon or silicon-containing materials. In the present embodiment, the material of the epitaxial S / D region 170 includes boron arsenide (BAs) having a thermal conductivity greater than 1000 W / mK. For example, the thermal conductivity of the epitaxial S / D region 170 may be between 1000 W / mK and 1500 W / mK, such as 1100 W / mK, 1200 W / mK, 1300 W / mK, 1400 W / mK or 1500 W / mK, including any range between any two of the foregoing values. Specifically, the material of the epitaxial S / D region 170 may be cubic boron arsenide (c-BAs) of a single crystal structure. In this embodiment, c-BAs can effectively dissipate the heat generated by nanostructured FETs, thereby improving the yield and reliability of nanostructured FETs. In addition, c-BAs exhibit excellent high electron and hole mobility, which can increase switching speed and improve device performance.

[0031] In some embodiments, the epitaxial S / D regions 170 may be formed via an epitaxial growth process, such as PECVD, thermal CVD, LPCVD, RTCVD, MOCVD, ALCVD, UHVCVD, RPCVD, or another suitable CVD process. In some embodiments, the epitaxial growth process may involve a boron (B)-containing precursor and an arsenic (As)-containing precursor to form epitaxial BAs having a thermal conductivity greater than 1000 W / mK for use as the epitaxial S / D regions 170. Specifically, the boron-containing precursor may include diborane, boron-halide (BF 3 , BCl 3 , BBr 3), triethyl boron, trimethyl boron, borazine, or a combination thereof. The arsenic-containing precursor includes arsine (AsH3), tertiarybutylarsine, trimethylarsine, diethyltertiarybutylarsine, or a combination thereof. The boron-containing precursor and the arsenic-containing precursor can be injected into the chamber separately via two gas lines. In an exemplary embodiment of forming BAs as the epitaxial S / D region 170 by PECVD, the growth temperature can be 200°C-700°C, the process pressure can be 0.01 torr-40 torr, and the plasma frequency can be varied between 40KHz and 40MHz. In an exemplary embodiment of forming BAs as the epitaxial S / D region 170 by thermal CVD, the growth temperature can be 400°C-750°C, and the process pressure can be 0.1 torr-30 torr. It should be noted that in this embodiment, the epitaxial growth process can achieve the deposition of a large-size (about 300 mm wafer size) single-crystal BAs layer. The 300 mm industrial-size uniform defect-free BAs layer exhibits excellent heat dissipation capability and carrier mobility, and can be used for large-scale commercial production of semiconductor structures.

[0032] Reference Figure 2 In operation 208, an interlayer dielectric (ILD) 130 may be formed, such as Figure 6 As shown, electrical contacts (not shown) may pass through an interlayer dielectric (ILD) 130 to reach the source, drain, and gate terminals of the nanosheet FETs. The ILD 130 may include silicon dioxide or a low-k dielectric material, such as fluorosilicate glass, carbon-doped silicon dioxide, porous silicon dioxide, porous carbon-doped silicon dioxide, hydrogen silsesquioxane, methyl silsesquioxane, polyimide, polynorbornene, benzocyclobutene, and / or polytetrafluoroethylene. To form the ILD 130, a deposition process may be performed, such as chemical vapor deposition, plasma enhanced chemical vapor deposition, and / or a spin coating process.

[0033] Reference Figure 2 In operation 210, the sacrificial gate structure 107 may be removed and replaced with a wraparound gate structure, such as Figure 6 to Figure 7 In operation 210, the nanostructure sacrificial layer 122 is selectively removed to form a gate opening 109 in the channel region 157, as shown in FIG. Figure 6 Then, the gate opening 109 is filled by depositing the gate structure 108 to complete the GAA channel region 157, as shown in FIG. Figure 7 shown.

[0034] Figures 3 to 7FIG. 1 shows an enlarged view of operations for forming gate structure 108 and GAA channel region 157 in accordance with some embodiments. Figure 7 , the GAA channel region 157 may include a plurality of GAA structures 158, which encapsulate the channel layer 121 to control the current flow therein. Each GAA structure 158 may be viewed as a radial gate stack, including, from the outermost layer to the innermost layer, an interface layer 160, a gate dielectric layer 161, a work function metal layer 162, and a gate electrode 163. The gate electrode 163 may be operated to maintain a capacitive applied voltage across the nanostructure channel layer 121. The gate dielectric layer 161 may separate the metal layer of the GAA structure 158 from the nanostructure channel layer 121. The inner spacer 164 may electrically isolate the GAA structure 158 from the epitaxial S / D region 170 and prevent current from leaking out of the nanostructure channel layer 121.

[0035] Figure 3 is an enlarged cross-sectional view of the superlattice structure 155 and the sacrificial gate structure 107 .

[0036] Figure 4 is an enlarged cross-sectional view of the GAA channel region 157 after the S / D recess 165 and the inner spacer 164 are formed.

[0037] Figure 5 is an enlarged cross-sectional view of the GAA channel region 157 after forming the epitaxial S / D regions 170 , which may grow laterally outward from the nanostructure layer 121 in the x-direction.

[0038] Figure 6 is an enlarged cross-sectional view of the GAA channel region 157 after removing the nanostructure sacrificial layer 122 and thereby forming the gate opening 109. First, the sacrificial gate structure 107 is removed, leaving the sidewall spacers 128 in place. Then, the nanostructure sacrificial layer 122 is removed to form the gate opening 109. In this way, the nanostructure channel layer 121 is suspended.

[0039] Figure 7 1 is an enlarged view of the GAA channel region 157 after the sacrificial gate structure 107 is replaced by the gate structure 108. The gate structure 108 is grown by a multi-step process to form a metal gate stack to replace the sacrificial gate structure 107. At the same time, a radial gate stack is formed to fill the gate opening 109 from the outside to the inside, starting from the interface layer 160 and ending at the gate electrode 163.

[0040] Reference Figure 7 The interface layer 160 may be conformally formed on the gate opening 109 and in the space between the sidewall spacers 128. In some embodiments, the interface layer 160 includes a dielectric material, such as a silicon oxide layer (SiO2 ) or silicon oxynitride (SiON). In some embodiments, the interface layer 160 is formed by a deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD) and / or other suitable deposition methods. In some alternative embodiments, the interface layer 160 can be formed by oxidizing the nanostructure channel layer 121 by chemical oxidation or thermal oxidation. In some embodiments, the interface layer 160 is suitable for providing a good interface between the semiconductor surface and the gate insulator and suppressing the decrease in the mobility of the channel carriers of the nanosheet FETs.

[0041] The gate dielectric layer 161 may be conformally disposed on the interface layer 160. In some embodiments, the gate dielectric layer 161 includes a high-k material, wherein the term "high-k" refers to a high dielectric constant. In the field of semiconductor device structure and manufacturing process, high-k refers to a dielectric constant greater than SiO 2 A dielectric constant of greater than about 3.9, greater than about 7, greater than about 12, greater than about 16, or even greater than about 20. For example, the high-k material may include a metal oxide such as ZrO 2 , Gd 2 O 3 , HfO 2 、BaTiO 3 、Al 2 O 3 、LaO 2 、TiO 2 、 2 O 5 , Y 2 O 3 , STO, BTO, BaZrO, HfZrO, HfLaO, HfTaO, HfTiO, combinations thereof, or suitable materials. In some alternative embodiments, the high-k material may optionally include silicates, such as HfSiO, HfSiON, LaSiO, AlSiO, combinations thereof, or suitable materials. In some embodiments, the gate dielectric layer 161 is formed by performing at least one suitable deposition technique, such as CVD, PECVD, MOCVD, ALD, remote plasma atomic layer deposition (RPALD), plasma enhanced atomic layer deposition (PEALD), molecular beam deposition (MBD), etc. In some embodiments, the gate dielectric layer 161 may include a single layer or multiple layers of insulating material.

[0042] The gate work function metal layer 162 may include a single metal layer or a metal layer stack. The metal layer stack may include metals having similar or different work functions to each other. In some embodiments, the gate work function metal layer 162 may include, for example, aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), cobalt (Co), metal nitrides, metal silicides, metal alloys, and / or combinations thereof. The gate work function metal layer 162 may be formed using a suitable process, such as ALD, CVD, PVD, electroplating, and combinations thereof.

[0043] The gate electrode 163 may also include a gate metal filling layer. The gate metal filling layer may include a single metal layer or a metal layer stack. The metal layer stack may include metals that are different from each other. In some embodiments, the gate metal filling layer may include one or more suitable conductive materials or alloys, such as Ti, Al, TiN, etc. The gate metal filling layer may be formed by ALD, PVD, CVD or other suitable deposition processes. Other materials, dimensions and formation methods for the interface layer 160, the gate dielectric layer 161, the gate work function metal layer 162 and the gate electrode 163 are also within the scope and spirit of the present disclosure.

[0044] After forming the gate structure 108 and the GAA structure 158 in the GAA channel region 157 , the structure of the nanosheet FETs is substantially completed.

[0045] Figure 8 Reference according to some embodiments is shown Figures 9 to 14 Operations in method 800 of forming a semiconductor structure. The semiconductor structure shown in the following embodiments takes a wafer stacking structure as an exemplary embodiment. However, the embodiments disclosed herein are not limited thereto. In some other embodiments, new materials with high thermal conductivity (e.g., boron arsenide (BAs)) can be applied to, but not limited to, various types of BEOL processes for heat dissipation. The operations may be performed in a different order, or not performed, depending on the specific application. It should be understood that additional processes may be provided before, during, or after method 800, and some of these additional processes may be only briefly described herein.

[0046] Reference Figure 8 In operation 802, a heat conducting layer 1000 may be formed on the carrier 900, such as Figures 9 and 10 In some embodiments, the carrier 900 may be a glass carrier substrate, a ceramic carrier substrate, a wafer (eg, a silicon wafer), etc. The carrier 900 may provide structural support during subsequent processing steps and be used for heat dissipation in the finished component.

[0047] In some embodiments, the material of the thermal conductive layer 1000 includes a high-κ material having a single crystal structure. In the present embodiment, the material of the thermal conductive layer 1000 includes boron arsenide (BAs), whose thermal conductivity is greater than 1000W / mK. For example, the thermal conductivity of the thermal conductive layer 1000 may be between 1000W / mK and 1500W / mK, such as 1100W / mK, 1200W / mK, 1300W / mK, 1400W / mK or 1500W / mK, including any range between any two of the foregoing values. Specifically, the material of the thermal conductive layer 1000 may be cubic boron arsenide (c-BAs) with a single crystal structure. In this embodiment, c-BA can effectively dissipate the thermal conductivity of the subsequently bonded component wafer 1200 ( Fig.13 ) to improve the yield and reliability of semiconductor structures.

[0048] In some embodiments, the thermal conductive layer 1000 may be formed via an epitaxial growth process, such as PECVD, thermal CVD, LPCVD, RTCVD, MOCVD, ALCVD, UHVCVD, RPCVD, or another suitable CVD process. In some embodiments, the epitaxial growth process may involve a boron (B)-containing precursor and an arsenic (As)-containing precursor to form an epitaxial BAs having a thermal conductivity greater than 1000 W / mK for use as the thermal conductive layer 1000. Specifically, the boron-containing precursor may include diborane, boron-halide (BF 3 , BCl 3 , BBr 3 ), triethyl boron, trimethyl boron, borazine or a combination thereof. The arsenic-containing precursor includes arsine (AsH 3), tertiarybutylarsine, trimethylarsine, diethyltertiarybutylarsine or a combination thereof. The boron-containing precursor and the arsenic-containing precursor can be injected into the chamber separately via two gas pipelines. In an exemplary embodiment of forming BAs as the thermal conductive layer 1000 by PECVD, the growth temperature can be 200°C-700°C, the process pressure can be 0.01 Torr-40 Torr, and the plasma frequency can vary between 40KHz and 40MHz. In an exemplary embodiment of forming BAs as the thermal conductive layer 1000 by thermal CVD, the growth temperature can be 400°C-750°C and the process pressure can be 0.1 Torr-30 Torr. It should be noted that in this embodiment, the epitaxial growth process can achieve the deposition of a large-size (about 300mm wafer size) single-crystalline BAs layer. The uniform and defect-free BAs layer with an industrial size of 300 mm exhibits excellent heat dissipation capability and carrier mobility, and can be used for large-scale commercial production of semiconductor structures.

[0049] Refer again Figure 8 After forming the heat conducting layer 1000, in operation 804, a first bonding layer 1100 may be formed on the heat conducting layer 1000. Fig.11 In some embodiments, the first bonding layer 1100 may include an insulating material suitable for a subsequent dielectric-to-dielectric bonding process. Example materials for the first bonding layer 1100 include silicon oxide (e.g., SiO 2 ), silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbon nitride oxynitride, etc. The first bonding layer 1100 can be formed by any suitable deposition process (eg, PVD, CVD, ALD, etc.).

[0050] Reference Figure 8 In operation 806, a second bonding layer 1240 may be formed on the device wafer 1200, such as Fig.12 Specifically, the device wafer 1200 may include a semiconductor substrate 1210 , a device layer 1220 , and a first interconnect structure 1230 .

[0051] In some embodiments, semiconductor substrate 1210 may include silicon or other semiconductor materials. Alternatively or additionally, semiconductor substrate 1210 may include other elemental semiconductor materials, such as germanium. In some embodiments, semiconductor substrate 1210 is made of a compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, semiconductor substrate 1210 is made of an alloy semiconductor, such as silicon germanium, silicon germanium carbide, gallium arsenide phosphide, or gallium indium phosphide. In some embodiments, semiconductor substrate 1210 includes an epitaxial layer. For example, semiconductor substrate 1210 has an epitaxial layer covering a bulk semiconductor.

[0052] In some embodiments, the component layer 1220 is formed on the semiconductor substrate 1210 in the front end of line (FEOL) process. The component layer 1220 includes a variety of components. In some embodiments, these components include active components, passive components, or a combination thereof. In some embodiments, these components may include integrated circuit components. These components are, for example, transistors, capacitors, resistors, diodes, photodiodes, fuse components, or other similar components. In some embodiments, the component layer 1220 includes a gate structure, a source / drain region, and an isolation structure, such as a shallow trench isolation (STI) structure (not shown). In the component layer 1220, various N-type metal oxide semiconductor (NMOS) and / or P-type metal oxide semiconductor (PMOS) components, such as transistors or memories, may be formed and interconnected to perform one or more functions. Other components such as capacitors, resistors, diodes, photodiodes, fuses, etc. may also be formed on the semiconductor substrate 1210. The functions of these components may include memory, processors, sensors, amplifiers, power distribution, input / output circuits, etc.

[0053] In some embodiments, the first interconnect structure 1230 is formed on the element layer 1220. In detail, the first interconnect structure 1230 includes an insulating material and a plurality of metal features. The metal features may be formed in the insulating material and electrically connected to each other. In some embodiments, the insulating material includes an interlayer dielectric (ILD) layer on the semiconductor substrate 1210 and at least one intermetallic dielectric (IMD) layer on the ILD layer. In some embodiments, the insulating material includes silicon oxide, silicon oxynitride, silicon nitride, a low dielectric constant (low-k) material, or a combination thereof. In some alternative embodiments, the insulating material may be a single layer or multiple layers. In some embodiments, the metal features include plugs and metal lines. The plugs may include contacts formed in the ILD layer and vias formed in the ILD layer. The contacts are formed between the element layer 1220 and the bottom metal line and connected to the element layer 1220 and the bottom metal line. The vias are formed between the two metal lines and connected to the two metal lines. The metal features may be made of tungsten (W), copper (Cu), copper alloys, aluminum (Al), aluminum alloys, or a combination thereof. In some optional embodiments, a barrier layer (not shown) may be formed between the metal feature and the insulating material to prevent the material of the metal feature from migrating to the device layer 1220. The material of the barrier layer is, for example, tantalum, tantalum nitride, titanium, titanium nitride, cobalt tungsten (CoW) or a combination thereof.

[0054] In some embodiments, the second bonding layer 1240 may include an insulating material suitable for a subsequent dielectric-to-dielectric bonding process. Example materials for the second bonding layer 1240 include silicon oxide (e.g., SiO 2), silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbon nitride oxynitride, etc. The second bonding layer 1240 can be formed by deposition by any suitable process (e.g., PVD, CVD, ALD, etc.). The material composition of the second bonding layer 1240 can be the same as or different from the material composition of the first bonding layer 1100.

[0055] Reference Figure 8 In operation 808, the device wafer 1200 may be bonded to the carrier 900, as shown in FIG. Fig.13 As shown. In some embodiments, the component wafer 1200 can be bonded to the carrier 900 having the thermal conductive layer 1000 thereon through the bonding layers 1100 and 1240. Specifically, the bonding layers 1100 and 1240 can be bonded together using a suitable technique, such as dielectric to dielectric bonding, etc. After bonding, the first bonding layer 1100 and the second bonding layer 1240 can be collectively referred to as a bonding layer 1310. The bonding layer 1310 may or may not have an interface 1300 configured at the intersection of the first bonding layer 1100 and the second bonding layer 1240. From another perspective, the component wafer 1200 can be bonded to the carrier 900 by making the first bonding layer 1100 and the second bonding layer 1240 directly contact at the interface 1300. It should be noted that the heat generated from the component layer 1220 of the component wafer 1200 can be dissipated to the carrier 900 through the thermal conductive layer 1000 having a thermal conductivity greater than 1000W / mK. In this way, the yield and reliability of the semiconductor structure can be improved due to effective heat dissipation.

[0056] In some embodiments, the dielectric-to-dielectric bonding process includes surface treatment of one or more bonding layers 1100 and 1240 to form hydroxyl (OH) groups at the bonding surfaces of the bonding layers 1100 and 1240. The surface treatment may include plasma treatment, such as nitrogen (N2) plasma treatment. After the plasma treatment, the surface treatment may also include a cleaning process that may be applied to one or more bonding layers 1100 and 1240. The second bonding layer 1240 may then be placed on top of the first bonding layer 1100 and aligned with the first bonding layer 1100. The two bonding layers 1100 and 1240 are then pressed against each other to start pre-bonding of the upper component wafer 1200 with the lower carrier 900. The pre-bonding may be performed at room temperature (e.g., in the range of 20°C to 28°C). After the pre-bonding, an annealing process may be performed by, for example, heating the component wafer 1200 and the carrier 900 to a temperature in the range of 300°C to 500°C. The annealing process drives or triggers the formation of covalent bonds between the bonding layers 1100 and 1240 .

[0057] Reference Figure 13 to Figure 14After bonding the device wafer 1200 to the carrier 900, a thinning process is performed to reduce the thickness of the device wafer 1200 to a desired thickness. The thinning process may include a grinding process, chemical mechanical polishing (CMP), an etch-back process, or a combination thereof. In some embodiments, the thinning process may remove the semiconductor substrate 1210 of the device wafer 1200 to expose the device layer 1220.

[0058] like Fig.14 As shown, the second interconnect structure 1400 can be formed on the back side of the component wafer 1200. Specifically, the second interconnect structure 1400 includes an insulating material and a plurality of metal features. The metal features can be formed in the insulating material and electrically connected to each other. In some embodiments, the metal features can be formed to connect to the component layer 1220. The second interconnect structure 1400 can be formed using similar processes and similar materials as discussed above with respect to the first interconnect structure 1230. In some embodiments, the second interconnect structure 1400 can be referred to as a backside interconnect structure, and the first interconnect structure 1230 can be referred to as a frontside interconnect structure.

[0059] Other features and processes may also be included. For example, a test structure may be included to illustrate performing verification testing of a three-dimensional (3D) package or a three-dimensional integrated circuit device. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate, which enables testing of the 3D package or 3DIC, using a probe and / or a probe card, etc. Verification testing may be performed on intermediate structures and final structures. In addition, the structures and methods disclosed herein may be used in conjunction with test methods including intermediate verification of known good dies to improve yield and reduce costs.

[0060] According to some embodiments, a semiconductor element includes a substrate, a plurality of channel layers stacked on the substrate, a gate structure covering the plurality of channel layers, and a source / drain (S / D) region disposed on the substrate at opposite sides of the gate structure and connected to the plurality of channel layers. The material of the S / D region includes a high thermal conductivity material having a single crystal structure.

[0061] In some embodiments, the high thermal conductivity material includes boron arsenide (BAs) having a thermal conductivity greater than 1000 W / mK. In some embodiments, the S / D region is cubic boron arsenide (c-BAs) having the single crystal structure. In some embodiments, the S / D region does not have silicon or silicon-containing materials. In some embodiments, it further includes: a plurality of inner spacers, respectively disposed between the S / D region and the gate structure. In some embodiments, the gate structure includes: an interface layer, covering the plurality of channel layers; a gate dielectric layer, covering the interface layer; a work function metal layer, covering the gate dielectric layer; and a gate electrode, covering the work function metal layer.

[0062] According to some embodiments, a method for forming a semiconductor structure includes: forming a superlattice structure on a substrate, wherein the superlattice structure includes a plurality of nanostructure channel layers stacked alternately; forming a gate structure to cover the plurality of nanostructure channel layers; and forming a source / drain (S / D) region on the substrate at an opposite side of the gate structure to connect the plurality of channel layers, wherein a material of the S / D region includes a high-κ material having a single crystal structure.

[0063] In some embodiments, the forming of the superlattice structure includes: performing an epitaxial growth process to form a plurality of nanostructure sacrificial layers and the plurality of nanostructure channel layers that are alternately arranged, wherein the plurality of nanostructure sacrificial layers and the plurality of nanostructure channel layers are different materials with different etching selectivities. In some embodiments, the forming of the S / D region includes: removing a portion of the superlattice structure to form an S / D recess; and performing an epitaxial growth process to form the S / D region in the S / D recess. In some embodiments, the epitaxial growth process includes using a boron (B)-containing precursor and an arsenic (As)-containing precursor to form boron arsenide (BAs) having a thermal conductivity greater than 1000 W / mK as the corresponding S / D region. In some embodiments, the boron-containing precursor includes diborane, boron-halide (BF 3 , BCl 3 , BBr 3 ), triethyl boron, trimethyl boron, borazine, or a combination thereof. In some embodiments, the arsenic-containing precursor comprises arsine (AsH 3), tertiarybutylarsine, trimethylarsine, diethyltertiarybutylarsine or a combination thereof. In some embodiments, the high kappa material comprises boron arsenide (BAs) having a thermal conductivity greater than 1000 W / mK. In some embodiments, the S / D region is cubic boron arsenide (c-BAs) having the single crystal structure. In some embodiments, the S / D region does not have silicon or silicon-containing materials.

[0064] According to some embodiments, a method for forming a semiconductor structure includes: forming a thermal conductive layer on a carrier, wherein the material of the thermal conductive layer includes a high-κ material with a single crystal structure; forming a first bonding layer on the thermal conductive layer; forming a second bonding layer on a component wafer; and bonding the component wafer to the carrier so that heat generated by the component wafer can be dissipated to the carrier through the thermal conductive layer.

[0065] In some embodiments, the forming of the thermal conductive layer comprises: using a boron (B)-containing precursor and an arsenic (As)-containing precursor to form boron arsenide (BAs) having a thermal conductivity greater than 1000 W / mK. In some embodiments, the boron-containing precursor comprises diborane, boron-halide (BF 3 , BCl 3 , BBr 3 ), triethyl boron, trimethyl boron, borazine, or a combination thereof. In some embodiments, the arsenic-containing precursor comprises arsine (AsH 3 ), tertiarybutylarsine, trimethylarsine, diethyltertiarybutylarsine, or a combination thereof. In some embodiments, the device wafer is bonded to the carrier by directly contacting the first bonding layer to the second bonding layer.

[0066] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure comprising: substrate; A plurality of channel layers stacked on the substrate; A gate structure covering the plurality of channel layers; as well as A source / drain (S / D) region is disposed on the substrate at an opposite side of the gate structure and connects the plurality of channel layers, wherein a material of the S / D region includes a high thermal conductivity material having a single crystal structure.

2. The semiconductor structure according to claim 1, characterized in that: The high thermal conductivity material includes boron arsenide having a thermal conductivity greater than 1000 W / mK.

3. The semiconductor structure according to claim 1, characterized in that: The S / D regions are cubic boron arsenide having the single crystal structure.

4. The semiconductor structure according to claim 1, characterized in that: The S / D regions do not have silicon or silicon-containing materials.

5. A method for forming a semiconductor structure, comprising: forming a superlattice structure on a substrate, wherein the superlattice structure comprises a plurality of alternately stacked nanostructured channel layers; forming a gate structure to cover the plurality of nanostructure channel layers; as well as Source / drain (S / D) regions are formed over the substrate at opposite sides of the gate structure to connect the plurality of channel layers, wherein a material of the S / D regions includes a high-κ material having a single crystal structure.

6. The method according to claim 5, characterized in that The forming of the S / D region comprises: removing a portion of the superlattice structure to form an S / D recess; and An epitaxial growth process is performed to form the S / D region in the S / D recess.

7. The method according to claim 6, characterized in that The epitaxial growth process includes using a boron-containing precursor and an arsenic-containing precursor to form boron arsenide with a thermal conductivity greater than 1000 W / mK as corresponding S / D regions.

8. The method according to claim 7, characterized in that The boron-containing precursor includes diborane, boron-halide (BF3, BCl3, BBr3), triethyl boron, trimethyl boron, borazine or a combination thereof.

9. The method according to claim 7, characterized in that: The arsenic-containing precursor includes arsine (AsH 3 ), tertiarybutylarsine, trimethylarsine, diethyltertiarybutylarsine, or a combination thereof.

10. A method for forming a semiconductor structure, comprising: forming a heat-conducting layer on the carrier, wherein the material of the heat-conducting layer comprises a high-κ material having a single crystal structure; forming a first bonding layer on the heat conductive layer; forming a second bonding layer on the device wafer; as well as The device wafer is bonded to the carrier so that the heat generated by the device wafer is dissipated to the carrier through the heat conductive layer.

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