Thin film transistor and manufacturing method thereof

Abstract

The invention provides a thin film transistor and a manufacturing method thereof, the thin film transistor comprises a bottom gate electrode layer, a gate dielectric layer, an active layer and a source and drain electrode layer, and the bottom gate electrode layer, the gate dielectric layer, the active layer and the source and drain electrode layer are sequentially stacked and combined from bottom to top; the source and drain electrode layer is composed of two electrodes, each electrode comprises a first electrode layer and a second electrode layer which are sequentially stacked from bottom to top, and the first electrode layer is arranged on the upper end face of the active layer; wherein the first electrode layer is prepared through a thermal evaporation method, and the second electrode layer is prepared through a sputtering method. According to the embodiment of the invention, the sputtering / evaporation laminated structure is realized through two different preparation processes of the thermal evaporation method and the sputtering method, the ESD stress reliability of the thin film transistor is improved, and the structural complexity and the preparation cost of the thin film transistor are reduced.

Description

Technical Field

[0001] The present invention relates to the field of thin film transistors, and in particular to a thin film transistor and a method for manufacturing the same. Background Art

[0002] As a member of field effect transistors, thin film transistors are widely used in the fields of active matrix liquid crystal displays and active matrix light emitting diodes. At the same time, they show great application potential in the fields of sensors, flexible electronics and wearable devices. Electrostatic discharge (ESD) is one of the most common threats to the reliability of electronic components, causing a lot of losses to the integrated circuit industry. ESD usually manifests itself as a transient current of up to several amperes in a very short time, causing dielectric breakdown, melting of metal connections, etc., resulting in permanent or potential failure of electronic devices. According to statistics, about 35% of chip damage is caused by ESD events. Traditional ESD protection design is mainly carried out from three levels: system level, circuit level and device level. Among them, device-level protection focuses on improving the ESD stress reliability of electronic devices themselves, and is a crucial link in the design and manufacturing process of electronic devices.

[0003] At present, there have been some reports on the ESD stress reliability research based on thin film transistors. The vertical gate dielectric layer breakdown is one of the main reasons for the failure of thin film transistors, and its breakdown path is drain-active layer-gate dielectric layer-gate. The gate dielectric layer is a key factor in resisting ESD stress impact. ESD stress may cause the electric field strength of the gate dielectric layer to be too high and breakdown occurs, thereby causing device failure. Therefore, reducing the electric field strength of the gate dielectric layer under ESD stress is the key to improving the ESD stress robustness of thin film transistors.

[0004] For example, in the article "Electrostatic discharge robustness of amorphous indium-gallium-zinc-oxide thin-film transistors" published in Microelectronics Reliability, researchers found that 1. Dual-gate thin-film transistors have better heat dissipation capabilities; 2. The dual-gate structure can effectively weaken the electric field on the active layer, thereby showing better ESD stress reliability; 3. The stacked active layer structure shows significantly enhanced ESD robustness.

[0005] For example, the invention patent with publication number CN117979708A discloses a flexible thin film transistor with a polymer composite modified layer and a method for manufacturing the same, in which a substrate, a bottom gate electrode, a dielectric layer, a polymer composite modified layer, an active layer and a source-drain electrode are stacked in sequence from bottom to top. The dielectric layer is modified by an oxide nanoparticle-polymer composite modified layer, thereby improving the electrical properties of the flexible thin film transistor and the electrostatic discharge reliability under initial flatness and bending conditions.

[0006] In summary, the main limitation of the existing technical solutions is the additional device structure complexity and additional preparation cost. Therefore, the existing thin film transistors have the problems of complex device structure and high preparation cost. Summary of the invention

[0007] The embodiment of the present invention provides a thin film transistor and a method for manufacturing the same, aiming to solve the problems of complex device structure and high manufacturing cost of the existing thin film transistor.

[0008] In a first aspect, an embodiment of the present application provides a thin film transistor and a method for manufacturing the same, wherein the thin film transistor comprises: a bottom gate electrode layer, a gate dielectric layer, an active layer, and a source-drain electrode layer, wherein the bottom gate electrode layer, the gate dielectric layer, the active layer, and the source-drain electrode layer are stacked in sequence from bottom to top;

[0009] The source-drain electrode layer is composed of two electrodes, each of which includes a first electrode layer and a second electrode layer stacked in sequence from bottom to top, and the first electrode layer is arranged on the upper end surface of the active layer; wherein the first electrode layer is made by thermal evaporation, and the second electrode layer is made by sputtering.

[0010] Furthermore, the material of the bottom gate electrode layer is any one of heavily doped silicon, aluminum, copper, silver, gold, and indium tin oxide;

[0011] The bottom gate electrode layer is arranged to have a thickness between 50 nm and 200 nm.

[0012] Furthermore, the gate dielectric layer is made of any one of silicon oxide, aluminum oxide, silicon nitride, hafnium oxide, and polyimide;

[0013] The gate dielectric layer is arranged to have a thickness between 30 nm and 200 nm.

[0014] Furthermore, the material of the active layer is any one of amorphous silicon, polycrystalline silicon, organic semiconductor, metal oxide semiconductor, two-dimensional material, and perovskite material.

[0015] Furthermore, the thickness of the active layer is set between 10nm and 100nm.

[0016] Furthermore, the material of the first electrode layer is the same as the material of the second electrode layer;

[0017] The thickness of the first electrode layer is between 5nm and 10nm, and the thickness of the second electrode layer is between 30nm and 100nm.

[0018] Furthermore, the first electrode layer and the second electrode layer are made of any one of aluminum, copper, silver, molybdenum and gold.

[0019] In a second aspect, an embodiment of the present application further provides a method for manufacturing a thin film transistor, wherein the manufacturing method is used to manufacture the thin film transistor as described in the first aspect above, and the manufacturing method comprises:

[0020] S1. Preparation of a bottom gate electrode layer and a gate dielectric layer, comprising: using a highly conductive material to prepare the bottom gate electrode layer, and depositing an insulating material on the bottom gate electrode layer to prepare the gate dielectric layer;

[0021] S2, preparation of the active layer, comprising: attaching an active layer mask with a width-to-length ratio of 1500um:1000um to the upper surface of the cleaned gate dielectric layer, placing the active layer mask in a magnetron sputtering apparatus, and controlling the magnetron sputtering apparatus to sputter at 5×10 -4 The active layer is obtained by performing sputtering operation under a vacuum degree of Pa; wherein the first sputtering parameter is that the sputtering power is 80W and the sputtering atmosphere ratio is argon:oxygen=28.5:4.5 standard ml / min;

[0022] S3, preparing the source-drain electrode layer, comprising: depositing the first electrode layer on the upper surface of the annealed active layer by a thermal evaporation method; depositing the second electrode layer on the upper surface of the first electrode layer by a sputtering method;

[0023] S4, performing annealing treatment to obtain the thin film transistor.

[0024] Further, step S3 includes:

[0025] S31, preparing the first electrode layer, comprising: attaching a source-drain electrode mask with a width-to-length ratio of 1500um:200um to the upper surface of the active layer after annealing, and placing it in a thermal evaporation apparatus, and waiting for the vacuum degree in the chamber to drop to 2×10 -4 After Pa, depositing a metal material on the active layer at a preset rate to obtain the first electrode layer;

[0026] S32, preparing the second electrode layer, comprising: placing the second electrode layer in a magnetron sputtering instrument, controlling the magnetron sputtering instrument to sputter at 8×10 -4The second electrode layer is obtained by performing sputtering operation under a vacuum degree of Pa; wherein the second sputtering parameters are a sputtering power of 120 W and a sputtering atmosphere ratio of argon gas at 33 standard ml / min.

[0027] Furthermore, after the bottom gate electrode layer is made of a highly conductive material and an insulating material is deposited on the bottom gate electrode layer to make the gate dielectric layer, the method further comprises:

[0028] The primary structural parts prepared in step S1 are cut according to preset specifications and ultrasonically cleaned in a solution containing DECON-90 and deionized water for 20 minutes. The surface moisture of the primary structural parts is dried with a nitrogen gun and then placed in a drying oven at 120° C. for 60 minutes.

[0029] The present invention provides a thin film transistor and a method for manufacturing the same, wherein the thin film transistor comprises: a bottom gate electrode layer, a gate dielectric layer, an active layer and a source-drain electrode layer, wherein the bottom gate electrode layer, the gate dielectric layer, the active layer and the source-drain electrode layer are stacked in sequence from bottom to top; the source-drain electrode layer is composed of two electrodes, each of which comprises a first electrode layer and a second electrode layer stacked in sequence from bottom to top, wherein the first electrode layer is arranged on the upper end surface of the active layer; wherein the first electrode layer is made by thermal evaporation, and the second electrode layer is made by sputtering. The embodiment of the present invention realizes a sputtering / evaporation stacked structure through two different preparation processes, namely, thermal evaporation and sputtering, thereby improving the ESD stress reliability of the thin film transistor and reducing the structural complexity and preparation cost of the thin film transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying any creative work.

[0031] Figure 1 A structural diagram of a thin film transistor provided by an embodiment of the present invention;

[0032] Figure 2 A schematic flow chart of a method for manufacturing a thin film transistor provided by an embodiment of the present invention;

[0033] Figure 3 A statistical diagram of the breakdown voltage of the thin film transistor provided by the embodiment of the present invention and a conventional thin film transistor under ESD stress impact;

[0034] Figure 4 The contact resistance statistics diagram of the thin film transistor provided by the embodiment of the present invention and the conventional thin film transistor under ESD stress impact.

[0035] Reference numerals: 10, thin film transistor; 11, bottom gate electrode layer; 12, gate dielectric layer; 13, active layer; 14, electrode; 141, first electrode layer; 142, second electrode layer. DETAILED DESCRIPTION

[0036] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0037] It should be understood that when used in this specification and the appended claims, the terms "include" and "comprises" indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0038] It should also be understood that the terms used in the present specification are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the present specification and the appended claims, the singular forms "a", "an" and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It should also be further understood that the term "and / or" used in the present specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0039] See also Figure 1 The present invention provides a thin film transistor 10, the thin film transistor 10 comprising: a bottom gate electrode layer 11, a gate dielectric layer 12, an active layer 13 and a source-drain electrode layer, the bottom gate electrode layer 11, the gate dielectric layer 12, the active layer 13 and the source-drain electrode layer being stacked in sequence from bottom to top; the source-drain electrode layer is composed of two electrodes 14, each of the electrodes 14 comprising a first electrode layer 141 and a second electrode layer 142 stacked in sequence from bottom to top, the first electrode layer 141 being arranged on the upper end surface of the active layer 13; wherein the first electrode layer 141 is made by thermal evaporation, and the second electrode layer 142 is made by sputtering.

[0040] In this embodiment, the source-drain electrode layer is composed of two electrodes 14, where one electrode 14 is the source electrode and the other electrode 14 is the drain electrode; the present invention realizes a sputtering / vapor deposition stacked structure through two different preparation processes, namely, the thermal evaporation method and the sputtering method; among them, the first electrode layer 141 is obtained by the thermal evaporation method, and the second electrode layer 142 is obtained by the sputtering method; compared with the prior art, the thin film transistor 10 provided by the embodiment of the present invention has the advantages of low structural complexity and low preparation cost; specifically, the thin film transistor 10 provided by the embodiment of the present invention has the following advantages:

[0041] 1. The first electrode layer 141 obtained by the thermal evaporation method can not only be perfectly compatible with the second electrode layer 142 obtained by the sputtering method, but also be highly matched with the active layer 13, ensuring the overall performance and stability of the thin film transistor 10;

[0042] 2. Since the energy of metal atoms in the thermal evaporation process is small, on the one hand, it can adsorb on the surface of the active layer 13 without damaging the active layer 13, and on the other hand, the first electrode layer 141 obtained by the thermal evaporation method can effectively protect the active layer 13, preventing the high-energy sputtering atoms from colliding with the active layer 13 during the process of sputtering to prepare the second electrode layer 142 and causing damage to the active layer 13;

[0043] 3. The first electrode layer 141 formed by the thermal evaporation method can moderately increase the contact resistance between the active layer 13 and the source-drain electrode layer, thereby effectively reducing the electric field strength of the gate dielectric layer 12 under the action of ESD stress, and further improving the ESD stress reliability of the thin film transistor 10;

[0044] 4. Compared with the thermal evaporation process, the second electrode layer 142 formed by the sputtering process can improve the density and adhesion of the surface of the source-drain electrode layer, enabling the thin film transistor 10 to better interconnect with external devices and facilitating integrated applications.

[0045] In a more specific embodiment, the material of the bottom gate electrode layer 11 is any one of heavily doped silicon, aluminum, copper, silver, gold, and indium tin oxide; the set thickness of the bottom gate electrode layer 11 is between 50 nm and 200 nm.

[0046] In this embodiment, the material of the bottom gate electrode layer 11 is any one of heavily doped silicon, aluminum, copper, silver, gold, and indium tin oxide, but not limited thereto; the set thickness of the bottom gate electrode layer 11 is between 50 nm and 200 nm.

[0047] In a more specific embodiment, the gate dielectric layer 12 is made of any one of silicon oxide, aluminum oxide, silicon nitride, hafnium oxide, and polyimide; and the gate dielectric layer 12 has a thickness between 30 nm and 200 nm.

[0048] In the present embodiment, the gate dielectric layer 12 is made of any one of silicon oxide, aluminum oxide, silicon nitride, hafnium oxide, and polyimide, but is not limited thereto; the gate dielectric layer 12 is set to have a thickness between 30 nm and 200 nm.

[0049] In a more specific embodiment, the material of the active layer 13 is any one of amorphous silicon, polycrystalline silicon, organic semiconductor, metal oxide semiconductor, two-dimensional material, and perovskite material.

[0050] In this embodiment, the material of the active layer 13 is any one of amorphous silicon, polycrystalline silicon, organic semiconductor, metal oxide semiconductor, two-dimensional material, and perovskite material, but is not limited thereto.

[0051] In a more specific embodiment, the thickness of the active layer 13 is set between 10nm and 100nm.

[0052] In a more specific embodiment, the material of the first electrode layer 141 is the same as that of the second electrode layer 142 ; the thickness of the first electrode layer 141 is between 5 nm and 10 nm, and the thickness of the second electrode layer 142 is between 30 nm and 100 nm.

[0053] In this embodiment, the material of the first electrode layer 141 is the same as that of the second electrode layer 142, ensuring that the first electrode layer 141 and the second electrode layer 142 prepared by two different preparation processes have the same energy level structure and transmission performance, thereby ensuring the overall performance and stability of the thin film transistor 10; the thickness of the first electrode layer 141 is set between 5nm and 10nm, and the thickness of the second electrode layer 142 is set between 30nm and 100nm; preferably, the thickness of the active layer is 40nm, the thickness of the first electrode layer is 10nm, and the thickness of the second electrode layer is 70nm.

[0054] In a more specific embodiment, the first electrode layer 141 and the second electrode layer 142 are made of any one of aluminum, copper, silver, molybdenum, and gold.

[0055] In this embodiment, the material of the first electrode layer 141 and the second electrode layer 142 is any one of aluminum, copper, silver, molybdenum, and gold, but is not limited thereto.

[0056] The embodiment of the present invention further provides a method for manufacturing a thin film transistor, wherein the method is used to manufacture the thin film transistor described in the above embodiment. Figure 2 As shown, the manufacturing method includes steps S1-S4.

[0057] S1. Preparation of a bottom gate electrode layer and a gate dielectric layer, including: using a highly conductive material to prepare the bottom gate electrode layer, and depositing an insulating material on the bottom gate electrode layer to prepare the gate dielectric layer.

[0058] In a specific application example, the bottom gate electrode layer is made of a highly conductive material (any one of heavily doped silicon, aluminum, copper, silver, gold, and indium tin oxide); the bottom gate electrode layer is set to have a thickness between 50nm and 200nm; preferably, the thickness of the bottom gate electrode layer is set to 500μm; an insulating material (any one of silicon oxide, aluminum oxide, silicon nitride, hafnium oxide, and polyimide) is deposited on the bottom gate electrode layer to obtain the gate dielectric layer; the gate dielectric layer is set to have a thickness between 30nm and 200nm; preferably, the thickness of the gate dielectric layer is set to 100nm.

[0059] More specifically, after the bottom gate electrode layer is made of a highly conductive material and the gate dielectric layer is made of an insulating material deposited on the bottom gate electrode layer, the method further includes: cutting the primary structural component obtained in step S1 according to preset specifications, and placing it in a solution containing DECON-90 and deionized water for ultrasonic cleaning for 20 minutes; using a nitrogen gun to blow dry the surface moisture of the primary structural component, and then placing it in a drying oven for drying at 120°C for 60 minutes.

[0060] In a specific application example, the primary structural component obtained in step S1 is cut into a size of 2 cm×2 cm according to preset specifications, and is ultrasonically cleaned in a solution containing DECON-90 and deionized water for 20 minutes; wherein the primary structural component includes a bottom gate electrode layer and a gate dielectric layer; subsequently, the surface moisture of the primary structural component is dried with a nitrogen gun, and then placed in a drying oven for drying at 120°C for 60 minutes.

[0061] S2, preparation of the active layer, comprising: attaching an active layer mask with a width-to-length ratio of 1500um:1000um to the upper surface of the cleaned gate dielectric layer, placing the active layer mask in a magnetron sputtering apparatus, and controlling the magnetron sputtering apparatus to sputter at 5×10 -4 The active layer is obtained by performing sputtering operation under a vacuum degree of Pa; wherein the first sputtering parameter is that the sputtering power is 80W and the sputtering atmosphere ratio is argon:oxygen=28.5:4.5 standard ml / min.

[0062] In a specific application example, an active layer mask with a width-to-length ratio of 1500um:1000um is attached to the upper surface of the cleaned gate dielectric layer and placed in a magnetron sputtering apparatus until the vacuum degree in the chamber drops to 5×10 -4 After Pa, first open the target baffle and the sample baffle, and then control the magnetron sputtering instrument to perform sputtering operation according to the first sputtering parameter to obtain the active layer; wherein, the first sputtering parameter is that the sputtering power is 80W, and the sputtering atmosphere ratio is argon: oxygen = 28.5:4.5 standard ml / min; preferably, the thickness of the active layer is 40nm.

[0063] More specifically, the magnetron sputtering instrument is controlled at 5×10 -4 The method further comprises: performing a sputtering operation under a vacuum degree of Pa to obtain the active layer, and further comprising: placing the primary intermediate structure obtained in step S2 in the air, and annealing the primary intermediate structure according to a preset first annealing parameter to obtain an intermediate structure; wherein the first annealing parameter is an annealing temperature of 400°C and an annealing time of 30 minutes; and the intermediate structure comprises a bottom gate electrode layer, a gate dielectric layer and an active layer.

[0064] S3. Preparation of source-drain electrode layers, including: depositing the first electrode layer on the upper surface of the annealed active layer by thermal evaporation; and depositing the second electrode layer on the upper surface of the first electrode layer by sputtering.

[0065] In a specific application example, the first electrode layer is deposited on the upper surface of the active layer after annealing by thermal evaporation; preferably, the thickness of the first electrode layer is 10nm; the second electrode layer is deposited on the upper surface of the first electrode layer by sputtering; preferably, the thickness of the second electrode layer is 70nm.

[0066] More specifically, step S3 includes: S31, preparing the first electrode layer, including: attaching a source-drain electrode mask with a width-to-length ratio of 1500um:200um to the upper surface of the active layer after annealing, and placing it in a thermal evaporation apparatus, and wait until the vacuum degree in the chamber drops to 2×10 -4 Pa, depositing the metal material on the active layer at a preset rate to prepare the first electrode layer; S32, preparing the second electrode layer, comprising: placing the second electrode layer in a magnetron sputtering instrument, controlling the magnetron sputtering instrument to move the first electrode layer at 8×10 -4 The second electrode layer is obtained by performing sputtering operation under a vacuum degree of Pa; wherein the second sputtering parameters are a sputtering power of 120 W and a sputtering atmosphere ratio of argon gas 33 standard ml / min.

[0067] In a specific application example, a source-drain electrode mask with a width-to-length ratio of 1500um:200um is attached to the upper surface of the active layer and placed in a thermal evaporation apparatus until the vacuum degree in the chamber drops to 2×10 -4 After 100 Pa, a metal material (any one of aluminum, copper, silver, molybdenum, and gold) is deposited on the active layer at a preset rate to prepare the first electrode layer; specifically, when high-purity aluminum is used to prepare the first electrode layer, the preset rate is The primary spare structural component prepared in step S31 is placed in a magnetron sputtering apparatus, and the magnetron sputtering apparatus is controlled to be 8×10 -4 The second electrode layer is obtained by performing sputtering operation under a vacuum degree of Pa; wherein the second sputtering parameters are a sputtering power of 120 W and a sputtering atmosphere ratio of argon 33 standard ml / min; the primary spare structural component includes a bottom gate electrode layer, a gate dielectric layer, an active layer and a first electrode layer.

[0068] S4, performing annealing treatment to obtain the thin film transistor.

[0069] In a specific application example, the spare structural component obtained in step S3 is placed in the air, and the spare structural component is annealed according to a preset second annealing parameter to obtain the thin film transistor; wherein the second annealing parameter is an annealing temperature of 300°C and an annealing time of 5 minutes; the spare structural component includes a bottom gate electrode layer, a gate dielectric layer, an active layer and a source-drain electrode layer; preferably, the thickness of the source-drain electrode layer is 80nm; and the distance between the two electrodes is 200μm.

[0070] The source and drain electrode layers of the conventional thin film transistor TFT2 usually adopt a sputtering single-layer structure. Different from the conventional thin film transistor TFT2, the source and drain electrode layers of the thin film transistor TFT1 in the embodiment of the present invention adopt a sputtering / evaporation stacked structure. In order to make the advantages of the embodiment of the present invention clearer, the present invention uses a transmission line pulse (Transmission Line Pulse, TLP) to characterize the ESD stress reliability of the thin film transistor TFT1 and the conventional thin film transistor TFT2. Specifically, the bottom gate electrode layer and the source electrode of the thin film transistor TFT1 and the conventional thin film transistor TFT2 are grounded. At the same time, a TLP pulse with a gradually increasing amplitude is applied to the drain electrode of the thin film transistor TFT1 and the drain electrode of the conventional thin film transistor TFT2, wherein the step size of the TLP pulse is 2V, the duration is 100ns, and the rise / fall time is 10ns. The breakdown voltage of the thin film transistor TFT1 and the conventional thin film transistor TFT2 under ESD stress impact is as shown in FIG. Figure 3As shown in FIG. 1 , the breakdown voltage of the conventional thin film transistor TFT2 is 95.78 V, and the breakdown voltage of the thin film transistor TFT1 is 105.17 V. It can be seen that when the thickness / material of each layer of the thin film transistor TFT1 is consistent with the thickness / material of each layer of the conventional thin film transistor TFT2, the breakdown voltage of the thin film transistor TFT1 increases by 9.80% compared with the conventional thin film transistor TFT2; the contact resistance of the thin film transistor TFT1 and the conventional thin film transistor TFT2 under ESD stress impact is shown in FIG. Figure 4 As shown, the contact resistance of the conventional thin film transistor TFT2 is 1.45 KΩ·cm, and the contact resistance of the thin film transistor TFT1 is 2.99 KΩ·cm. Compared with the conventional thin film transistor TFT2, the contact resistance of the thin film transistor TFT1 increases by 105.41%, which is consistent with the increasing trend of the breakdown voltage.

[0071] Furthermore, combined with Silvaco TCAD software simulation, the bottom gate electrode layer and source electrode of the thin film transistor TFT1 and the conventional thin film transistor TFT2 are grounded. At the same time, a pulse voltage with an amplitude of 100V, a rise time of 10ns, and a duration of 100ns is applied to the drain electrode of the thin film transistor TFT1 and the drain electrode of the conventional thin film transistor TFT2 to simulate the ESD stress impact in reality. By analyzing the obtained simulation results, it can be found that under the ESD stress impact, the electric field strength on the gate dielectric layer of the conventional thin film transistor TFT2 is 8.76×10 6 V / cm, and the electric field strength on the gate dielectric layer of the thin film transistor TFT1 is 6.99×10 6 V / cm, it can be seen that when the thickness / material of each layer of the thin film transistor TFT1 is consistent with the thickness / material of each layer of the conventional thin film transistor TFT2, the electric field strength of the thin film transistor TFT1 is increased from 8.76×10 6 V / cm dropped to 6.99×10 6 V / cm, decreased by 20.21%.

[0072] In summary, the sputtering / evaporation stacked structure can moderately increase the contact resistance of the thin film transistor, play a better voltage division role, and effectively reduce the electric field strength of the gate dielectric layer, thereby improving the ESD stress reliability of the thin film transistor.

[0073] The present invention provides a thin film transistor and a method for manufacturing the same, wherein the thin film transistor comprises: a bottom gate electrode layer, a gate dielectric layer, an active layer and a source-drain electrode layer, wherein the bottom gate electrode layer, the gate dielectric layer, the active layer and the source-drain electrode layer are stacked in sequence from bottom to top; the source-drain electrode layer is composed of two electrodes, each of which comprises a first electrode layer and a second electrode layer stacked in sequence from bottom to top, wherein the first electrode layer is arranged on the upper end surface of the active layer; wherein the first electrode layer is made by thermal evaporation, and the second electrode layer is made by sputtering. The embodiment of the present invention realizes a sputtering / evaporation stacked structure through two different preparation processes, namely, thermal evaporation and sputtering, thereby improving the ESD stress reliability of the thin film transistor and reducing the structural complexity and preparation cost of the thin film transistor.

[0074] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present invention, and these modifications or replacements should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A thin film transistor, characterized in that: The thin film transistor comprises: a bottom gate electrode layer, a gate dielectric layer, an active layer and a source-drain electrode layer, wherein the bottom gate electrode layer, the gate dielectric layer, the active layer and the source-drain electrode layer are stacked in sequence from bottom to top; The source-drain electrode layer is composed of two electrodes, each of which includes a first electrode layer and a second electrode layer stacked in sequence from bottom to top, and the first electrode layer is arranged on the upper end surface of the active layer; wherein the first electrode layer is made by thermal evaporation, and the second electrode layer is made by sputtering.

2. The thin film transistor according to claim 1, characterized in that: The material of the bottom gate electrode layer is any one of heavily doped silicon, aluminum, copper, silver, gold, and indium tin oxide; The bottom gate electrode layer is arranged to have a thickness between 50 nm and 200 nm.

3. The thin film transistor according to claim 1, characterized in that: The gate dielectric layer is made of any one of silicon oxide, aluminum oxide, silicon nitride, hafnium oxide, and polyimide; The gate dielectric layer is arranged to have a thickness between 30 nm and 200 nm.

4. The thin film transistor according to claim 1, characterized in that: The material of the active layer is any one of amorphous silicon, polycrystalline silicon, organic semiconductor, metal oxide semiconductor, two-dimensional material and perovskite material.

5. The thin film transistor according to claim 1, characterized in that: The thickness of the active layer is set between 10nm and 100nm.

6. The thin film transistor according to claim 1, characterized in that: The material of the first electrode layer is the same as the material of the second electrode layer; The thickness of the first electrode layer is between 5nm and 10nm, and the thickness of the second electrode layer is between 30nm and 100nm.

7. The thin film transistor according to claim 6, characterized in that: The first electrode layer and the second electrode layer are made of any one of aluminum, copper, silver, molybdenum and gold.

8. A method for manufacturing a thin film transistor, characterized in that: The manufacturing method is used to manufacture the thin film transistor according to any one of claims 1 to 7, and the manufacturing method comprises: S1. Preparation of a bottom gate electrode layer and a gate dielectric layer, comprising: using a highly conductive material to prepare the bottom gate electrode layer, and depositing an insulating material on the bottom gate electrode layer to prepare the gate dielectric layer; S2, preparation of the active layer, comprising: attaching an active layer mask with a width-to-length ratio of 1500um:1000um to the upper surface of the cleaned gate dielectric layer, placing the active layer mask in a magnetron sputtering apparatus, and controlling the magnetron sputtering apparatus to sputter at 5×10 -4 The active layer is obtained by performing sputtering operation under a vacuum degree of Pa; wherein the first sputtering parameter is that the sputtering power is 80W and the sputtering atmosphere ratio is argon:oxygen=28.5:4.5 standard ml / min; S3, preparing the source-drain electrode layer, comprising: depositing the first electrode layer on the upper surface of the annealed active layer by a thermal evaporation method; depositing the second electrode layer on the upper surface of the first electrode layer by a sputtering method; S4, performing annealing treatment to obtain the thin film transistor.

9. The method for manufacturing a thin film transistor according to claim 8, characterized in that: Step S3 includes: S31, preparing the first electrode layer, comprising: attaching a source-drain electrode mask with a width-to-length ratio of 1500um:200um to the upper surface of the active layer after annealing, and placing it in a thermal evaporation apparatus, and waiting for the vacuum degree in the chamber to drop to 2×10 -4 After Pa, depositing a metal material on the active layer at a preset rate to obtain the first electrode layer; S32, preparing the second electrode layer, comprising: placing the second electrode layer in a magnetron sputtering instrument, controlling the magnetron sputtering instrument to sputter at 8×10 -4 The second electrode layer is obtained by performing sputtering operation under a vacuum degree of Pa; wherein the second sputtering parameters are a sputtering power of 120 W and a sputtering atmosphere ratio of argon gas at 33 standard ml / min.

10. The method for manufacturing a thin film transistor according to claim 8, characterized in that: After the bottom gate electrode layer is made of a highly conductive material and an insulating material is deposited on the bottom gate electrode layer to make the gate dielectric layer, the method further comprises: The primary structural parts prepared in step S1 are cut according to preset specifications and ultrasonically cleaned in a solution containing DECON-90 and deionized water for 20 minutes. The surface moisture of the primary structural parts is dried with a nitrogen gun and then placed in a drying oven at 120° C. for 60 minutes.

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