Method of forming semiconductor device

Abstract

Embodiments of the present disclosure provide a method of forming a semiconductor device, the method comprising: providing a semiconductor structure having a bottom channel region and a top channel region over the bottom channel region; forming a gate dielectric layer over the top channel in the top channel region, wherein the gate dielectric layer wraps around the top channel in the top channel region; performing radical treatment on the gate dielectric layer in a supercritical fluid; and forming a metal gate electrode on the gate dielectric layer. According to other embodiments of the invention, other methods of forming the semiconductor device are also provided.

Description

Technical Field

[0001] Embodiments of the present application relate to methods of forming semiconductor devices. Background Art

[0002] The present disclosure relates to an integrated circuit (IC) structure and a method for manufacturing the same. In particular, the IC structure includes a transistor structure having a plurality of vertically stacked full-ring gate transistors, each full-ring gate transistor including a plurality of vertically stacked nanowires or nanosheets as a channel. More specifically, the IC structure includes a complementary field effect transistor (CFET) structure and a method for manufacturing the CFET. The CFET includes a vertically stacked N-type FET and a P-type FET.

[0003] The CFET structure offers advantages over other field effect transistors in terms of power efficiency, performance, and transistor density. However, these potential benefits depend on overcoming significant technical challenges in manufacturing and design. In particular, CFETs are characterized by the need to use extremely precise lithography (such as High NA EUV (high numerical aperture extreme ultraviolet) tools) to integrate n-type FETs and p-type FETs into a single device, as well as the need to determine the most ideal materials to ensure appropriate electronic performance. For CFETs, processing margins are squeezed in various aspects, including component size, alignment, thermal budget, etc. For example, existing gate structures and methods of forming various materials including gate dielectrics and gate electrodes face more challenges to achieve gate structures of desired quality and threshold voltage, especially when it is associated with more complex and sophisticated process designs. Therefore, although existing CFET devices and their manufacturing methods are generally sufficient for their intended purposes, they are not completely satisfactory in all aspects. Summary of the invention

[0004] According to an embodiment of the present application, a method for forming a semiconductor device is provided, comprising: providing a semiconductor structure, the semiconductor structure having a bottom channel region and a top channel region located above the bottom channel region; forming a gate dielectric layer above the top channel in the top channel region, and the gate dielectric layer wraps around the top channel in the top channel region; performing free radical treatment on the gate dielectric layer in a supercritical fluid; and forming a metal gate electrode on the gate dielectric layer.

[0005] According to another embodiment of the present application, a method for forming a semiconductor device is provided, comprising: providing a semiconductor structure, the semiconductor structure having a bottom channel region and a top channel region located above the bottom channel region; forming an interface dielectric layer above the top channel in the top channel region, the interface dielectric layer wrapping around the top channel in the top channel region; performing a first free radical treatment on the interface dielectric layer in a first supercritical fluid in which a first free radical chemical is dissolved; forming a high-k dielectric layer above the interface dielectric layer, the high-k dielectric layer wrapping around the top channel in the top channel region; performing a second free radical treatment on the high-k dielectric layer in a second supercritical fluid in which a second free radical chemical is dissolved; and forming a metal gate electrode on the high-k dielectric layer.

[0006] According to another embodiment of the present application, a method for forming a semiconductor device is provided, comprising: forming a bottom channel vertically stacked in a bottom channel region on a bottom substrate; forming a bottom source and a bottom drain on the bottom substrate, the bottom channel region being interposed between the bottom source and the bottom drain; forming a bottom gate structure on the bottom channel region, and the bottom gate structure wraps around each of the bottom channels; performing a thermal annealing process on the bottom gate structure at a first temperature greater than 900° C.; forming a semiconductor stack of a first semiconductor layer and a second semiconductor layer alternately stacked on a top substrate; bonding the semiconductor stack formed on the top substrate to the bottom substrate; thinning the top substrate so that the semiconductor stack is exposed; and patterning the semiconductor stack to form a semiconductor stack. The invention relates to a method for forming a top metal gate electrode in a top channel region; forming an active region; forming a dummy gate structure above the active region in the top channel region, the dummy gate structure comprising a dummy gate stack and a gate spacer located on the sidewall of the dummy gate stack; forming a top source and a top drain in the active region, the dummy gate stack being inserted between the top source and the top drain; removing the dummy gate stack and the first semiconductor layer in the top channel region, resulting in the second semiconductor layer serving as a top channel in the top channel region; forming a gate dielectric layer above the top channel in the top channel region, and the gate dielectric layer wraps around the top channel in the top channel region; performing a free radical treatment on the gate dielectric layer in a supercritical fluid at a second temperature below 200° C.; and forming a bottom metal gate electrode on the gate dielectric layer.

[0007] Embodiments of the present application relate to free radical processing in supercritical fluids for gate dielectric quality improvement of CFET structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0009] Figure 1 A cross-sectional view of a CFET semiconductor device according to various aspects of the present disclosure is shown.

[0010] Figure 2A , Figure 2B and Figure 2C is a flow chart of a method of forming a CFET semiconductor device according to various aspects of the present disclosure.

[0011] Figure 3 A schematic diagram of a system for free radical processing in a supercritical fluid according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0012] The present disclosure relates generally to integrated circuit devices and, more particularly, to multi-gate devices such as fin field effect transistors (FinFETs), gate-all-around (GAA) devices, and complementary field effect transistor (CFET) structures.

[0013] The following disclosure provides many different embodiments or examples for realizing different features. Reference numbers and / or letters may be repeated in the various examples described herein. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various disclosed embodiments and / or configurations. In addition, specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component, so that the first component and the second component may not be in direct contact. In addition, in the present disclosure, the formation of a component located on another component, connected to another component and / or coupled to another component may include an embodiment in which the component is formed as a direct contact, and may also include an embodiment in which an additional component may be formed between the components so that the components may not be in direct contact.

[0014] In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the embodiments and / or configurations discussed. In addition, in the following disclosure, the formation of a component located on, connected to, and / or coupled to another component may include an embodiment in which the component is formed to be in direct contact, and may also include an embodiment in which an additional component may be formed between the components so that the components may not be in direct contact. In addition, in order to facilitate the present disclosure to describe the relationship between one component and another component, spatial relative terms are used, for example, "lower", "upper", "horizontal", "vertical", "above", "above", "below", "below", "below", "upward", "downward", "top", "bottom", etc. and their derivatives (e.g., "horizontally", "downward", "upward", etc.). Spatial relative terms are intended to cover different orientations of devices including components. Further, when "about", "approximately", etc. are used to describe a numerical value or a numerical range, the term is intended to cover a numerical value within a reasonable range including the described numerical value, such as within + / -10% of the described numerical value or other values ​​as understood by those skilled in the art. For example, the term "about 5 nm" encompasses a size range from 4.5 nm to 5.5 nm.

[0015] The present disclosure relates to an integrated circuit (IC) structure having one or more CFET devices and a method for manufacturing the same, particularly a method for processing various gate stacks at low temperatures to achieve desired quality without additional thermal annealing that affects other components or devices already formed in the IC structure. In a CFET device, an n-type FET (NFET) and a p-type FET (PFET) are stacked vertically on each other, with a reduced circuit area and improved device performance. The CFET device can be formed in any suitable process, such as a monolithic process, a sequential process, a parallel process, other suitable processes, or a combination thereof. Taking a sequential process as an example, in a sequential process, a bottom layer device is formed first, and then a top layer device is formed. In particular, one of an NFET and a PFET is first formed on one of the bottom layer devices; and then the other is formed on the top layer device, such as first forming an NFET and then forming a PFET. In this case, any thermal process applied to the PFET will also have a negative impact on the already formed NFET, which may exceed the thermal budget of the NFET and reduce the performance of the NFET, such as the threshold voltage and on-state current of the NFET.

[0016] The present disclosure provides methods for treating gate dielectric materials using a supercritical fluid with one or more suitable free radicals at low temperatures below 200° C. or below 100° C. It is desirable to treat a gate stack including a gate dielectric and a gate electrode, typically using a thermal annealing process to improve the characteristics of the gate stack, including reducing defects, densifying the gate material, lowering the threshold voltage, and increasing the threshold voltage.

[0017] In the disclosed method, the gate material (especially the gate dielectric) of the top device is treated in a supercritical carbon dioxide fluid in which one or more free radicals (such as hydrogen radicals (H*), deuterium radicals (D*), oxygen radicals (O*), fluorine radicals (F*) or a combination thereof) are dissolved.

[0018] In existing structures and methods, the gate electrode is formed through a process including a high temperature (such as greater than 800° C. or 900° C.) annealing process, which will affect the electrical performance of the CFET device (such as the underlying device that has been formed).

[0019] In the present disclosure, the integrated circuit structure includes one or more CFET devices, wherein the corresponding gate stack is formed by a process including an ultra-low temperature (less than 200° C. or less than 100° C.) free radical process. In particular, a molten metal having H dissolved therein is applied at an ultra-low temperature (less than 200° C., less than 100° C., or in a range between 100° C. and 200° C.) and a suitable pressure (such as a pressure in a range between 100 Torr and 200 Torr). 2 and D 2 of gas or O 2 and F 2 Supercritical carbon dioxide (CO 2 ) fluid. This process is called a free radical treatment in a supercritical fluid. In some embodiments, a free radical treatment in a supercritical fluid having one or more free radicals dissolved therein, such as hydrogen radicals (H*), deuterium radicals (D*), is applied to the interface layer, and another free radical treatment in a supercritical fluid having one or more free radicals dissolved therein, such as oxygen radicals (O*), fluorine radicals (F*), is applied to the high-k dielectric layer of the gate stack.

[0020] Supercritical carbon dioxide (scCO 2) is the fluid state of carbon dioxide maintained at or above its critical temperature and critical pressure. Carbon dioxide normally behaves as a gas in air at standard temperature and pressure (STP), or as a solid (known as dry ice) when sufficiently cooled and / or pressurized. If both temperature and pressure are increased from STP to or above the critical point of carbon dioxide, it can adopt properties intermediate between those of a gas and a liquid. More specifically, it behaves as a supercritical fluid above its critical temperature (31°C) and critical pressure (72.8atm), expanding to fill its container like a gas but with a density like a liquid. In the present disclosure, carbon dioxide is used as a supercritical fluid due to its relatively low toxicity and environmental impact, as well as the relatively low temperature and pressure of the process. 2 The stability of supercritical CO 2 Used as a solvent.

[0021] A CFET device is a type of transistor that combines n-type FETs and p-type FETs (NFETs and PFETs) on the same stack, allowing for more efficient use of space and power. In some embodiments, a CFET device includes an n-type FET and a p-type FET formed on the bottom and top levels of the same semiconductor substrate, respectively, so that the corresponding n-type FETs and p-type FETs are stacked vertically. The corresponding processing method is called a monolithic method. In some embodiments, a CFET device includes an n-type FET and a p-type FET formed on different semiconductor substrates bonded together at a later stage, respectively, so that the corresponding n-type FETs and p-type FETs are stacked vertically. The corresponding processing method is called a sequential method. In a sequential method according to some embodiments, an NFET (PFET) is first formed on a bottom substrate and then bonded to a top substrate. When a PFET (or NFET) is formed on a top substrate and a high temperature thermal anneal is applied to the gate structure of the PFET (or NFET) of the top substrate, it is also applied to the NFET (or PFET) formed on the bottom substrate bonded to the top substrate, and causes additional undesirable thermal annealing to the NFET (or PFET) formed on the bottom substrate. By utilizing the disclosed supercritical fluid processing, this undesirable thermal annealing can be avoided.

[0022] Figure 1 5 shows a cross-sectional view of an IC structure 100 having one or more CFET semiconductor devices formed by a sequential process 500. As an exemplary embodiment, Figure 1Four CFET devices 108a, 108b, 108c, and 108d are shown formed on substrate 102. Those CFET devices 108a-108d are collectively referred to as numeral 108. The IC structure 100 may include more CFET devices, other active devices, and passive devices integrated on the same substrate 102. In addition, the IC structure 100 includes a bottom structure (or device) 104 and a top structure (or device) 106 that are bonded together during sequential processes. In one embodiment for illustration, each CFET device 108 in the IC structure 100 includes an NFET device 108N vertically stacked above a PFET device 108P. More specifically, the PFET 108P is formed in the bottom structure 104, and the NFET 108N is formed on the top structure 106. However, this is for illustration and is not intended to be limiting. It should be understood that in some other embodiments, the CFET may include a PFET vertically stacked above the NFET. The PFET and NFET are further described separately.

[0023] The bottom structure 104 and the PFET 108P are described below. The bottom structure 104 includes a bottom substrate 102. According to some embodiments, the bottom substrate is a semiconductor substrate, such as a silicon substrate. Each PFET 108P formed in the bottom structure 104 is formed on the bottom substrate 102 and includes a multi-channel structure, which is also called a full-all-around gate (GAA) structure. In the GAA structure, multiple channels (or bottom multiple channels) 112 (such as nanosheets or nanowires) are vertically stacked and separated from each other. The bottom gate structure 114 is configured to wrap around each of the multiple channels 112 vertically stacked on the bottom substrate 102. Each gate structure 114 includes a gate dielectric layer 116 disposed on the channel 112 and a gate electrode 118 disposed on the gate dielectric layer 116. The gate dielectric layer 116 includes a high-k dielectric material, such as a metal oxide, a metal nitride, a metal oxynitride, or a combination thereof. The gate structure 114 may also include an interface layer 119 disposed between the channel 112 and the high-k dielectric material layer of the gate dielectric layer 116. The interface layer 119 may include silicon oxide or other suitable dielectric materials. The gate electrode 118 includes one or more conductive materials, such as a capping layer, a work function metal layer, and a filling metal layer. Note that the work function metal layer is different for PFETs and NFETs. The gate dielectric layer 116 and the gate electrode 118 together form a gate stack corresponding to one PFET 108P. The gate structure 114 includes a plurality of gate stacks corresponding to a plurality of PFETs 108P. The gate structure 114 also includes a gate spacer 120 disposed on the sidewalls of the gate stack 114. The PFET 108P also includes a source and a drain, which are collectively referred to as S / D components 122. The S / D components 122 are disposed on both sides of the channel 112 and are configured to be connected to the channel 112. The gate stack (including the gate dielectric layer 116 and the gate electrode 118) is separated from the S / D component 122 by the internal spacer 124. More specifically, the internal spacer 124 and the gate spacer 120 are vertically aligned to collectively isolate the gate electrode 118 from the S / D component 122. The underlying structure 104 may also include an S / D contact 126 that falls on the S / D component 122 and electrically connects the S / D component 122 to the power signal line. The S / D contact 126 may also include a barrier layer 127 to prevent interdiffusion. The underlying structure 104 may also include a dielectric component 128 formed on the gate electrode 118 and vertically aligned with the gate electrode 118 to protect the gate electrode 118 and facilitate subsequent processing operations applied to the gate electrode 118. In the disclosed embodiment, a bonding dielectric material layer 130 is deposited on the top surface of the underlying structure to provide a suitable bonding surface for bonding the underlying structure 104 and the top structure 106 together at a later stage.In particular, during the formation of the gate structure 114, the dielectric layer 116 is treated for improved gate dielectric integrity and device performance. In some embodiments, the gate dielectric layer is treated by a thermal annealing process with an elevated temperature, such as a temperature greater than 900° C., such as in a range between 900° C. and 1000° C., to reduce the effective oxide thickness (EOT). In further embodiments, the thermal annealing is performed in a nitrogen environment. Optionally, the gate dielectric layer is treated by a supercritical fluid as described above, the temperature of the supercritical fluid being less than 200° C., less than 100° C., or in a range between 100° C. and 200° C.

[0024] The top structure 106 and NFET 108N are described below. NFET 108N is similar to PFET 108P in structure, but is doped oppositely. For example, the S / D components in the PFET are doped with a P-type dopant such as boron, while the S / D components in the NFET are doped with an N-type dopant such as phosphorus. Each NFET 108N formed in the top structure 106 includes a multi-channel structure, which is also called a full-all-around (GAA) structure. In the GAA structure, multiple channels 312 (such as nanosheets or nanowires) are vertically stacked and separated from each other. The gate structure 314 is configured to wrap around each of the multiple channels 312 vertically stacked on the substrate 102. Each gate structure 314 includes a gate dielectric layer 316 disposed on the channel 312 and a gate electrode 318 disposed on the gate dielectric layer 316. The gate structure 314 may also include an interface layer 319, which is disposed between the high-k dielectric material layer of the channel 312 and the gate dielectric layer 316. The interface layer 319 may include silicon oxide or other suitable dielectric materials. The gate electrode 318 includes one or more conductive materials, such as a capping layer, a work function metal layer, and a fill metal layer. Note that the work function metal layer is different for PFET and NFET. The gate dielectric layer 316 and the gate electrode 318 are collectively referred to as a gate stack. The gate structure 314 also includes a gate spacer 320 disposed on the sidewalls of the gate electrode 318. The NFET 108N also includes a source and a drain, which are collectively referred to as S / D components 322. The S / D components 322 are disposed on both sides of the channel 312 and are configured to be connected to the channel 312. The gate stack (including the gate dielectric layer 316 and the gate electrode 318) is separated from the S / D component 322 by an internal spacer 324. More specifically, the internal spacer 324 and the gate spacer 320 are vertically aligned to collectively isolate the gate electrode 318 from the S / D component 322. The top structure 106 may also include an S / D contact 326 that lands on the S / D component 322 and electrically connects the S / D component 322 to the power signal line. The S / D contact 326 may also include a barrier layer 327 to prevent interdiffusion. The top structure 106 may also include a dielectric component 328 formed on and vertically aligned with the gate electrode 318 to protect the gate electrode 318 and facilitate subsequent processing operations applied to the gate electrode 318. In the disclosed embodiment, a bonding dielectric material layer 330 is deposited on the surface of the top structure to provide a suitable bonding surface for bonding the bottom structure 104 and the top structure 106 together at a later stage. The top structure 106 may also include other components, components and structures formed above the NFET, such as an interconnect structure and a passivation layer with a redistribution layer and a bonding pad, a semiconductor through hole (TSV), to electrically connect the PFET in the bottom structure 104 and the NFET in the top structure 106. These components are collectively referred to as numeral 332.

[0025] In particular, during the formation of the gate structure 314, the dielectric layer 316 is treated for improved gate dielectric integrity and device performance. The gate dielectric layer is treated by a supercritical fluid as described above, the temperature of which is below 200° C., below 100° C., or in the range between 100° C. and 200° C. In some embodiments, a supercritical fluid having H dissolved therein is applied at an ultra-low temperature (below 200° C., below 100° C., or in the range between 100° C. and 200° C.) and a suitable pressure (such as a pressure in the range between 100 Torr and 200 Torr). 2 and D 2 of gas or O 2 and F 2 Supercritical carbon dioxide (CO 2 ) fluid. This process is called a free radical treatment in a supercritical fluid. In some embodiments, a free radical treatment in a supercritical fluid having one or more free radicals dissolved therein, such as hydrogen radicals (H*), deuterium radicals (D*), is applied to the interface layer 319, and another free radical treatment in a supercritical fluid having one or more free radicals dissolved therein, such as oxygen radicals (O*), fluorine radicals (F*), is applied to the high-k dielectric layer 316 of the gate stack.

[0026] use FIG. 2A to FIG. 2C and other figures further describe a method 500 of forming the IC structure 100, the method 500 including supercritical fluid processing operations. Figure 2A , Figure 2B and Figure 2C is a flow chart of a method 500 constructed according to some embodiments. Figure 3 is a schematic diagram of a system for supercritical fluid processing constructed in accordance with some embodiments.

[0027] refer to Figure 2A The method 500 includes an operation 502 of forming a bottom device on a first substrate, the bottom device having a plurality of vertically stacked channels, a gate structure wrapped around each of the plurality of channels, and a source / drain feature, wherein the gate structure is interposed between the source / drain features. In some embodiments, the bottom device includes a PFET of a GAA structure, such as Figure 1Those shown. Method 500 includes operation 504, forming a semiconductor stack on a second substrate, the semiconductor stack having alternating first semiconductor layers and second semiconductor layers located above the second substrate, wherein the first semiconductor layers include a first material and the second semiconductor layers include a second material different from the first material. Method 500 includes operation 506, bonding the first substrate and the second substrate together by a suitable bonding method. In some embodiments, the first substrate and the second substrate are bonded together in a manner that a front side of the first substrate and a front side of the second substrate face each other. In further embodiments, a dielectric material layer is deposited on the front side of the first substrate and the front side of the second substrate, such that the dielectric material layer serves as a bonding surface, such as Figure 1 As shown. Method 500 includes operation 508, forming a top device on the semiconductor stack. The top device may include an NFET, such as Figure 1 . In particular, operation 508 includes forming a gate structure, and performing a supercritical fluid treatment on the gate dielectric layer, as described above. Method 500 also includes operation 510, forming other structures, components, and assemblies of IC structure 100, such as an interconnect structure having metal lines distributed in multiple metal layers, vias for vertically routing metal lines, and contacts for coupling FETs and other devices into an integrated circuit; a passivation layer having a redistribution layer and a bonding pad; and a through semiconductor via (TSV) for coupling a bottom device to a top device.

[0028] Operation 502 of forming the bottom device 104 includes a number of processing steps, such as Figure 2B Those shown in . Figure 2B Operation 502 includes a block 512 of forming a first semiconductor stack on a first substrate 102, the first semiconductor stack having alternating first and second semiconductor layers located above the substrate, wherein the first semiconductor layer comprises a first material and the second semiconductor layer comprises a second material different from the first material to achieve etching selectivity. In some embodiments, the first material comprises silicon germanium and the second material comprises silicon. The first substrate 102 is a semiconductor substrate, such as a silicon substrate or a substrate having other semiconductor materials additionally or alternatively. The formation of the first semiconductor stack includes depositing the first and second semiconductor layers, patterning the first and second semiconductor layers to form the first semiconductor stack, and forming an isolation structure surrounding the first semiconductor stack. In some embodiments, the isolation structure is a shallow trench isolation (STI) structure and includes one or more dielectric materials, such as silicon oxide, low-k dielectric materials, silicon oxynitride, other suitable dielectric materials, or combinations thereof.

[0029] Still reference Figure 2BOperation 502 includes a block 514 of forming a first dummy gate structure over a first channel region of a first semiconductor stack. The formation of the dummy gate structure includes deposition (such as polysilicon deposition) and patterning. The formation of the dummy gate structure also includes forming a gate spacer 120 on a sidewall of the dummy gate stack by deposition and anisotropic etching such as plasma etching. The gate spacer 120 includes one or more suitable dielectric materials, such as silicon oxide, silicon nitride, other suitable dielectric materials, or combinations thereof.

[0030] Still reference Figure 2B Operation 502 includes block 516 of forming a first source / drain (S / D) trench by selectively etching the first semiconductor stack in the source / drain region, thereby exposing a side surface of the first semiconductor stack.

[0031] Still reference Figure 2B Operation 502 includes block 518, forming an internal spacer 124 in the first channel region of the first semiconductor stack. The formation of the internal spacer 124 includes laterally recessing the first semiconductor layer of the first semiconductor stack; depositing one or more dielectric material layers (such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof); and performing an anisotropic etch such as a plasma etch.

[0032] Still reference Figure 2B Operation 502 includes forming a first S / D feature 122 in the first S / D trench using selective epitaxial growth at block 520. The first S / D feature 122 may include a semiconductor material that is the same as (such as silicon) or different from (such as silicon germanium) as the substrate 102 to achieve a strain effect.

[0033] Still reference Figure 2B Operation 502 includes a block 522 of forming an interlayer dielectric (ILD) layer over the S / D features 122. The ILD layer includes one or more dielectric materials, such as low-k dielectric materials, silicon oxide, and other suitable dielectric materials, or combinations thereof. The ILD layer may also include an etch stop layer (such as silicon nitride) disposed on the bottom to achieve etch selectivity and stop etching.

[0034] Still reference Figure 2B Operation 502 includes block 524 of removing the dummy gate stack from the first dummy gate structure using an etching process while retaining the gate spacers 120 to create gate trenches.

[0035] Still reference Figure 2B Operation 502 includes block 526 of selectively etching the first semiconductor layer using an etching process to remove the first semiconductor layer of the first semiconductor stack in the gate trench, resulting in the second semiconductor layer serving as the first suspended semiconductor channel 112 .

[0036] Still reference Figure 2B Operation 502 includes a block 528 of forming a gate dielectric layer 116, the gate dielectric layer 116 including a high-k dielectric material, such as hafnium oxide or other suitable high-k dielectric materials (e.g., metal oxides, metal nitrides), or combinations thereof. The gate dielectric layer 116 is deposited by a suitable method, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), other suitable methods, or combinations thereof. The gate dielectric layer 116 is formed around each first channel 112 in the first channel region. The gate dielectric layer 116 may also include an interfacial layer, such as silicon oxide, formed by thermal oxidation, atomic layer deposition, or other suitable methods.

[0037] Still reference Figure 2B Operation 502 includes block 530 of performing a first treatment on the first gate dielectric layer 116. In some embodiments, the first treatment is a thermal annealing, and the annealing temperature of the thermal annealing is greater than 800° C. or greater than 900° C., or in a range between 900° C. and 1000° C. In further embodiments, the first treatment is performed in a nitrogen atmosphere (N 2 ) environment to reduce the EOT of the gate dielectric layer 116. In some optional embodiments, the first treatment is a supercritical fluid treatment as described above.

[0038] Still reference Figure 2B Operation 502 includes a block 532 of forming a first gate electrode 118 over the first gate dielectric layer 116 to form a first metal gate structure for the bottom device. The first gate electrode 118 may include one or more metals or metal alloys. In some embodiments, the first gate electrode 118 includes a capping layer, a p-type work function metal, and a fill metal, such as tungsten, copper, nickel, cobalt, other suitable metals, or combinations thereof. According to some embodiments, the p-type work function metal for the PFET includes titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), or combinations thereof.

[0039] Operation 502 may include other processing steps, such as forming contacts 126 and forming dielectric features 128 aligned with and covering the gate stack (including the gate dielectric layer 116 and the gate electrode 118). Operation 502 includes box 534, forming a bonding dielectric layer 130 over the workpiece. The formation of the bonding dielectric layer 130 may include performing a chemical mechanical polishing (CMP) process to planarize the top surface of the workpiece, and depositing a dielectric material, such as silicon oxide, silicon nitride, other suitable dielectric materials, or combinations thereof.

[0040] Return to reference Figure 2AAt operation 504, a second semiconductor stack is formed on the second substrate. Another bonding dielectric layer 330 may be formed on the second semiconductor stack. At operation 506, the first substrate and the second substrate are bonded together, such as front side to front side. Operation 508 forms a top device on the second semiconductor stack and includes performing a supercritical fluid treatment on a second gate dielectric layer of the top device, which is referred to below. Figure 2C Further description.

[0041] Operation 508 of forming the top device 106 includes multiple processing steps such as Figure 2C Those shown. Figure 2C Operation 508 includes block 540 of thinning the second substrate such that the second semiconductor stack is exposed from the back side.

[0042] Still reference Figure 2C Operation 508 includes block 541, patterning the second semiconductor stack to form an active area surrounded by an isolation structure. According to some embodiments, the isolation structure includes a shallow trench isolation (STI) feature. The formation of the active area and the isolation structure in block 541 may include patterning the second semiconductor stack, forming the isolation structure by deposition, performing CMP and selective etching to recess the isolation structure so that the active area protrudes above the isolation structure.

[0043] Still reference Figure 2C Operation 508 includes a block 542 of forming a second dummy gate structure on a second substrate, the second dummy gate structure being located above a second channel region of the second semiconductor stack. The formation of the second dummy gate structure includes deposition (such as polysilicon deposition) and patterning. The formation of the second dummy gate structure also includes forming a gate spacer 320 on a sidewall of the dummy gate stack by deposition and anisotropic etching such as plasma etching. The gate spacer 320 includes one or more suitable dielectric materials, such as silicon oxide, silicon nitride, other suitable dielectric materials, or combinations thereof.

[0044] Still reference Figure 2C Operation 508 includes block 544 of forming a second source / drain (S / D) trench by selectively etching the second semiconductor stack in the source / drain region, thereby exposing side surfaces of the second semiconductor stack.

[0045] Still reference Figure 2C Operation 508 includes a block 546 of forming an internal spacer 324 in the second channel region of the second semiconductor stack. The formation of the internal spacer 324 includes laterally recessing the first semiconductor layer of the second semiconductor stack; depositing one or more dielectric material layers (such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof); and performing an anisotropic etch such as a plasma etch.

[0046] Still referring to Figure 2C , operation 508 includes block 548, forming a second S / D component 322 in the second S / D trench using selective epitaxial growth. The second S / D component 322 may include a semiconductor material the same as (such as silicon) or different from (such as silicon carbide) the substrate 102 to achieve a strain effect. The second S / D component 322 is doped oppositely to the first S / D component 122. For example, the first S / D component 122 of the PFET is doped with a P-type dopant such as boron, and the second S / D component 322 in the NFET is doped with an N-type dopant such as phosphorus.

[0047] Still referring to Figure 2C , operation 508 includes block 550, forming an interlayer dielectric (ILD) layer over the S / D component 322. The ILD layer includes one or more dielectric materials, such as a low-k dielectric material, silicon oxide, and other suitable dielectric materials or a combination thereof. The ILD layer may also include an etch stop layer (such as silicon nitride) disposed on the bottom to achieve etch selectivity and stop the etching.

[0048] Still referring to Figure 2C , operation 508 includes block 552, removing the dummy gate stack from the second dummy gate structure using an etching process while retaining the gate spacers 320, creating a gate trench.

[0049] Still referring to Figure 2C , operation 508 includes block 554, selectively etching the first semiconductor layer using an etching process, removing the first semiconductor layer of the second semiconductor stack in the gate trench, resulting in the second semiconductor layer as the second suspended semiconductor channel 312.

[0050] Still referring to Figure 2C , operation 508 includes block 556, forming a gate dielectric layer 316, the gate dielectric layer 316 including a high-k dielectric material, such as hafnium oxide or other suitable high-k dielectric materials (e.g., metal oxides, metal nitrides) or a combination thereof. The gate dielectric layer 316 is deposited by a suitable method, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), other suitable methods, or a combination thereof. The gate dielectric layer 316 is formed around each second channel 312 in the second channel region. In the disclosed embodiments, the gate dielectric layer 316 may also include an interface layer 319 formed by thermal oxidation, atomic layer deposition, or other suitable methods, such as silicon oxide.

[0051] Still referring to Figure 2COperation 508 includes a block 558 of performing a second treatment on the second gate dielectric layer 316. The first treatment includes supercritical fluid treatment of the second gate dielectric layer at a temperature below 200° C., or below 100° C., or in a range between 100° C. and 200° C. The dielectric layer 316 is treated for improved gate dielectric integrity and device performance. In some embodiments of the supercritical fluid treatment, a supercritical fluid treatment is applied at an ultra-low temperature (below 200° C., below 100° C., or in a range between 100° C. and 200° C.) and a suitable pressure (such as a pressure in a range between 100 Torr and 200 Torr) to obtain a second gate dielectric layer 316 having H dissolved therein. 2 and D 2 of gas or O 2 and F 2 Supercritical carbon dioxide (CO 2 ) fluid. This process is also referred to as a free radical treatment in a supercritical fluid. In some embodiments, the second treatment includes two free radical treatments: one free radical treatment in a supercritical fluid in which one or more free radicals (such as hydrogen radicals (H*), deuterium radicals (D*)) are dissolved is applied to the interface layer 319, and another free radical treatment in a supercritical fluid in which one or more free radicals (such as oxygen radicals (O*), fluorine radicals (F*)) are dissolved is applied to the high-k dielectric layer 316 of the gate stack. In this case, the formation of the gate dielectric layer 316 includes forming the interface layer 319; performing a first free radical treatment in a first supercritical fluid in which one or more free radicals (such as hydrogen radicals (H*), deuterium radicals (D*), or both) are dissolved; forming the high-k dielectric layer of the gate dielectric layer 316; and performing a second free radical treatment in a second supercritical fluid in which one or more free radicals (such as oxygen radicals (O*), fluorine radicals (F*), or both) are dissolved.

[0052] In some embodiments, the supercritical fluid in the free radical treatment is supercritical carbon dioxide (scCO 2 ) fluid. Supercritical carbon dioxide (scCO 2 ) is the fluid state of carbon dioxide maintained at or above its critical temperature and critical pressure. Carbon dioxide normally behaves as a gas in air at standard temperature and pressure (STP), or as a solid (known as dry ice) when sufficiently cooled and / or pressurized. If both temperature and pressure are increased from STP to or above the critical point of carbon dioxide, it can adopt properties intermediate between those of a gas and a liquid. More specifically, it behaves as a supercritical fluid above its critical temperature (31°C) and critical pressure (72.8atm), expanding to fill its container like a gas but with a density like a liquid. In the present disclosure, carbon dioxide is used as a supercritical fluid due to its relatively low toxicity and environmental impact, as well as the relatively low temperature and pressure of the process. 2 The stability of supercritical CO 2 Used as a solvent.

[0053] exist Figure 3 The schematic diagram of a method for using supercritical carbon dioxide (scCO) according to some embodiments is shown in 2 ) fluid to perform free radical treatment. The free radical treatment system 600 includes a free radical source supply 602 to provide free radical chemicals, such as H 2 The radical source supply 602 may be configured to provide more than one radical chemical species, such as hydrogen radicals (H*), deuterium radicals (D*), oxygen radicals (O*), and fluorine radicals (F*).

[0054] The free radical processing system 600 includes a supercritical fluid source supply 604 to provide chemicals for supercritical fluids, such as supercritical carbon dioxide (CO 2 ) Fluid carbon dioxide (CO 2 ).

[0055] The free radical processing system 600 also includes a cryostat module 606 connected to the supercritical fluid source supply 604 to receive carbon dioxide and generate a supercritical carbon dioxide fluid.

[0056] The free radical processing system 600 also includes a pump 608 connected to the cryostat module 606 to pump the supercritical carbon dioxide fluid to the autoclave module 610 .

[0057] The free radical treatment system 600 also includes an autoclave module 610 coupled to the cryostat module 606 (or directly connected to the pump 608) and the free radical source supply 602, so that the free radical chemicals from the free radical source supply 602 and the supercritical carbon dioxide fluid from the cryostat module 606 are mixed in the autoclave module 610 (the free radical chemicals are dissolved in the supercritical carbon dioxide fluid) and applied to the gate dielectric layer through the outlet 612 for free radical treatment.

[0058] The free radical treatment system 600 also includes various valves 614 to control the flow of the corresponding chemical substances, such as valves 614A, 614B and 614C. The free radical treatment system 600 also includes a controller 616, which is designed to control the flow of the supercritical carbon dioxide fluid dissolved with the free radical chemical substances. The free radical treatment system 600 also includes other components, such as a monitor 618 configured to monitor the flow of the supercritical carbon dioxide fluid. The monitor 618 can be further coupled to the controller 616 to control the flow of the supercritical carbon dioxide fluid in a feedback mode.

[0059] Return to reference Figure 2C, after radical treatment of the gate dielectric layer 316 at box 558, operation 508 also includes box 560, forming a second gate electrode 318 over the second gate dielectric layer 316 to form a second metal gate structure 314 for the top device. The second gate electrode 318 may include one or more metals or metal alloys. In some embodiments, the second gate electrode 318 includes a capping layer, an n-type work function metal, and a fill metal, such as tungsten, copper, nickel, cobalt, other suitable metals, or combinations thereof. According to some embodiments, the n-type work function metal for the NFET includes tantalum (Ta); titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), titanium aluminum oxide (TiAlO), titanium aluminum nitride (TiAlN), or combinations thereof.

[0060] Operation 508 may include other processing steps, such as forming a contact 326 and forming a dielectric feature 328 aligned with the gate stack (including the gate dielectric layer 316 and the gate electrode 318) and covering the gate stack. In some embodiments, the formation of the contact 326 includes patterning the ILD layer by photolithography and etching to form a contact hole; forming a barrier layer 327, such as depositing a titanium film and a titanium nitride film (or depositing a tantalum film and a tantalum nitride film); depositing a metal to fill the contact hole; and performing a chemical mechanical polishing (CMP) process for planarization. In some embodiments, the formation of the dielectric feature 328 includes selectively etching the gate stack to recess the gate stack; depositing one or more suitable dielectric materials in the recess; and performing a CMP process for planarization, thereby forming a dielectric feature 328 that is self-aligned with the gate stack and covers the gate stack.

[0061] The present disclosure provides CFET devices and methods for manufacturing the same according to various embodiments. In particular, the integrated circuit structure includes one or more CFET devices, wherein a corresponding gate stack is formed by a process including ultra-low temperature (less than 200° C. or less than 100° C.) free radical treatment. In particular, at ultra-low temperature (less than 200° C., less than 100° C., or in a range between 100° C. and 200° C.) and a suitable pressure (such as a pressure in a range between 100 Torr and 200 Torr), a molten-liquid crystal containing H dissolved therein is applied. 2 and D 2 of gas or O 2 and F 2 Supercritical carbon dioxide (CO 2 ) fluid. This process is called a free radical treatment in a supercritical fluid. In some embodiments, a free radical treatment in a supercritical fluid having one or more free radicals dissolved therein, such as hydrogen radicals (H*), deuterium radicals (D*), is applied to the interface layer, and another free radical treatment in a supercritical fluid having one or more free radicals dissolved therein, such as oxygen radicals (O*), fluorine radicals (F*), is applied to the high-k dielectric layer of the gate stack.

[0062] By implementing the disclosed device structure and its manufacturing method in various embodiments, some advantages described below can be presented. However, it should be understood that different embodiments disclosed herein provide different advantages, and no specific advantage is necessarily required for all embodiments. As an example, the gate dielectric layer is improved by free radical treatment in a supercritical fluid with free radical chemicals dissolved therein at low temperature without affecting the already formed FET on the bottom device.

[0063] In one exemplary aspect, the present disclosure provides a method comprising: providing a semiconductor structure having a bottom channel region and a top channel region located above the bottom channel region; forming a gate dielectric layer above a top channel in the top channel region, and the gate dielectric layer wraps around the top channel in the top channel region; performing a free radical treatment on the gate dielectric layer in a supercritical fluid; and forming a metal gate electrode on the gate dielectric layer.

[0064] In another example aspect, the present disclosure provides a method comprising: providing a semiconductor structure having a bottom channel region and a top channel region located above the bottom channel region; forming an interfacial dielectric layer above the top channel in the top channel region, the interfacial dielectric layer wrapping around the top channel in the top channel region; performing a first radical treatment on the interfacial dielectric layer in a first supercritical fluid in which a first radical chemical is dissolved; forming a high-k dielectric layer above the interfacial dielectric layer, the high-k dielectric layer wrapping around the top channel in the top channel region; performing a second radical treatment on the high-k dielectric layer in a second supercritical fluid in which a second radical chemical is dissolved; and forming a metal gate electrode on the high-k dielectric layer.

[0065] In yet another exemplary aspect, the present disclosure provides a method, which includes: forming a bottom channel vertically stacked in a bottom channel region on a bottom substrate; forming a bottom source and a bottom drain on the bottom substrate, with the bottom channel region inserted between the bottom source and the bottom drain; forming a bottom gate structure on the bottom channel region, and the bottom gate structure wrapping around each in the bottom channel; performing a thermal annealing process on the bottom gate structure at a first temperature greater than 900 °C; forming a semiconductor stack of a first semiconductor layer and a second semiconductor layer alternately stacked on a top substrate; bonding the semiconductor stack formed on the top substrate to the bottom substrate; thinning the top substrate such that the semiconductor stack is exposed; patterning the semiconductor stack to form an active region; forming a dummy gate structure above the active region in a top channel region, the dummy gate structure including a dummy gate stack and gate spacers located on sidewalls of the dummy gate stack; forming a top source and a top drain in the active region, with the dummy gate stack inserted between the top source and the top drain; removing the dummy gate stack and the first semiconductor layer in the top channel region, resulting in the second semiconductor layer serving as the top channel in the top channel region; forming a gate dielectric layer above the top channel in the top channel region, and the gate dielectric layer wrapping around the top channel in the top channel region; performing a radical treatment on the gate dielectric layer in a supercritical fluid at a second temperature below 200 °C; and forming a bottom metal gate electrode on the gate dielectric layer.

[0066] According to an embodiment of the present application, a method of forming a semiconductor device is provided, including: providing a semiconductor structure having a bottom channel region and a top channel region located above the bottom channel region; forming a gate dielectric layer above the top channel in the top channel region, and the gate dielectric layer wrapping around the top channel in the top channel region; performing a radical treatment on the gate dielectric layer in a supercritical fluid; and forming a metal gate electrode on the gate dielectric layer.

[0067] In some embodiments, the supercritical fluid is a supercritical carbon dioxide fluid; and performing a radical treatment on the gate dielectric layer in a supercritical fluid includes performing a radical treatment on the gate dielectric layer in the supercritical carbon dioxide fluid at a temperature below 100 °C.

[0068] In some embodiments, performing a radical treatment on the gate dielectric layer in a supercritical fluid further includes: dissolving a radical source gas in the supercritical carbon dioxide fluid; and then, applying the supercritical carbon dioxide fluid dissolved with the radical chemical to the gate dielectric layer.

[0069] In some embodiments, the top channels in the top channel region include top channels that are vertically stacked and spaced apart from each other; and a gate dielectric layer is formed above the top channels in the top channel region, and the gate dielectric layer wraps around the top channels in the top channel region and further includes: forming an interface dielectric layer to wrap around each of the top channels, and forming a high-k dielectric material layer on the interface dielectric layer to wrap around each of the top channels.

[0070] In some embodiments, performing a free radical treatment on the gate dielectric layer in a supercritical fluid further includes: dissolving a first free radical source gas in a first supercritical carbon dioxide fluid; applying the first supercritical carbon dioxide fluid having a first free radical chemical dissolved therein to the interface dielectric layer before forming a high-k dielectric material layer on the interface dielectric layer to wrap around each of the top channels; dissolving a second free radical source gas in a second supercritical carbon dioxide fluid after forming the high-k dielectric material layer on the interface dielectric layer to wrap around each of the top channels; and applying the second supercritical carbon dioxide fluid having a second free radical chemical dissolved therein to the high-k dielectric material layer.

[0071] In some embodiments, the first radical chemical species includes hydrogen radicals; and the second radical chemical species includes oxygen radicals.

[0072] In some embodiments, the first radical chemical species includes hydrogen radicals (H*) and deuterium radicals (D*); and the second radical chemical species includes oxygen radicals (O*) and fluorine radicals (F*).

[0073] In some embodiments, providing a semiconductor structure having a bottom channel region and a top channel region also includes: forming a bottom channel vertically stacked in the bottom channel region on a bottom substrate; forming a bottom source and a bottom drain in the bottom substrate, with the bottom channel region inserted between the bottom source and the bottom drain; forming a bottom gate structure on the bottom channel region, and the bottom gate structure wraps around each of the bottom channels; and performing a thermal annealing process on the bottom gate structure at a temperature greater than 900°C.

[0074] In some embodiments, providing a semiconductor structure having a bottom channel region and a top channel region further includes: forming a semiconductor stack of a first semiconductor layer and a second semiconductor layer alternately stacked on a top substrate; bonding the semiconductor stack formed on the top substrate to a bottom substrate; and thinning the top substrate so that the semiconductor stack is exposed.

[0075] In some embodiments, providing a semiconductor structure having a bottom channel region and a top channel region also includes: patterning a semiconductor stack to form an active region; forming a dummy gate structure above the active region in the top channel region, the dummy gate structure including a dummy gate stack and a gate spacer located on the sidewalls of the dummy gate stack; forming a top source and a top drain in the active region, the dummy gate stack being inserted between the top source and the top drain; and removing the dummy gate stack and the first semiconductor layer in the top channel region, resulting in the second semiconductor layer in the top channel region acting as a top channel.

[0076] According to another embodiment of the present application, a method for forming a semiconductor device is provided, comprising: providing a semiconductor structure, the semiconductor structure having a bottom channel region and a top channel region located above the bottom channel region; forming an interface dielectric layer above the top channel in the top channel region, the interface dielectric layer wrapping around the top channel in the top channel region; performing a first free radical treatment on the interface dielectric layer in a first supercritical fluid in which a first free radical chemical is dissolved; forming a high-k dielectric layer above the interface dielectric layer, the high-k dielectric layer wrapping around the top channel in the top channel region; performing a second free radical treatment on the high-k dielectric layer in a second supercritical fluid in which a second free radical chemical is dissolved; and forming a metal gate electrode on the high-k dielectric layer.

[0077] In some embodiments, the second radical chemistry is different from the first radical chemistry; performing the first radical treatment on the interfacial dielectric layer includes performing the first radical treatment on the interfacial dielectric layer at a first temperature below 100°C; and performing the second radical treatment on the high-k dielectric layer includes performing the second radical treatment on the high-k dielectric layer at a second temperature below 100°C.

[0078] In some embodiments, performing a first free radical treatment on the interface dielectric layer in a first supercritical fluid further includes: dissolving a first free radical source gas in a first supercritical carbon dioxide fluid, and applying the first supercritical carbon dioxide fluid having the first free radical chemical dissolved therein to the interface dielectric layer; and performing a second free radical treatment on the high-k dielectric layer in a second supercritical fluid further includes: dissolving a second free radical source gas in a second supercritical carbon dioxide fluid, and applying the second supercritical carbon dioxide fluid having the second free radical chemical dissolved therein to the high-k dielectric layer.

[0079] In some embodiments, the first radical chemical comprises one of a hydrogen radical (H*), a deuterium radical (D*); and combinations thereof; and the second radical chemical comprises one of an oxygen radical (O*), a fluorine radical (F*); and combinations thereof.

[0080] In some embodiments, providing a semiconductor structure having a bottom channel region and a top channel region also includes: forming a bottom channel vertically stacked in the bottom channel region on a bottom substrate; forming a bottom source and a bottom drain in the bottom substrate, with the bottom channel region inserted between the bottom source and the bottom drain; forming a bottom gate structure in the bottom channel region to wrap around each of the bottom channels; performing a thermal annealing process on the bottom gate structure at a temperature greater than 900°C; forming a semiconductor stack of a first semiconductor layer and a second semiconductor layer alternately stacked on a top substrate; bonding the semiconductor stack formed on the top substrate to the bottom substrate; thinning the top substrate; patterning the semiconductor stack to form an active region; forming a dummy gate structure above the active region in the top channel region, the dummy gate structure including a dummy gate stack and a gate spacer located on the sidewalls of the dummy gate stack; forming a top source and a top drain in the active region, with the dummy gate stack inserted between the top source and the top drain; and removing the dummy gate stack and the first semiconductor layer in the top channel region, resulting in the second semiconductor layer serving as a top channel in the top channel region.

[0081] According to another embodiment of the present application, a method for forming a semiconductor device is provided, comprising: forming a bottom channel vertically stacked in a bottom channel region on a bottom substrate; forming a bottom source and a bottom drain on the bottom substrate, the bottom channel region being interposed between the bottom source and the bottom drain; forming a bottom gate structure on the bottom channel region, and the bottom gate structure wraps around each of the bottom channels; performing a thermal annealing process on the bottom gate structure at a first temperature greater than 900° C.; forming a semiconductor stack of a first semiconductor layer and a second semiconductor layer alternately stacked on a top substrate; bonding the semiconductor stack formed on the top substrate to the bottom substrate; thinning the top substrate so that the semiconductor stack is exposed; and patterning the semiconductor stack to form a semiconductor stack. The invention relates to a method for forming a top metal gate electrode in a top channel region; forming an active region; forming a dummy gate structure above the active region in the top channel region, the dummy gate structure comprising a dummy gate stack and a gate spacer located on the sidewall of the dummy gate stack; forming a top source and a top drain in the active region, the dummy gate stack being inserted between the top source and the top drain; removing the dummy gate stack and the first semiconductor layer in the top channel region, resulting in the second semiconductor layer serving as a top channel in the top channel region; forming a gate dielectric layer above the top channel in the top channel region, and the gate dielectric layer wraps around the top channel in the top channel region; performing a free radical treatment on the gate dielectric layer in a supercritical fluid at a second temperature below 200° C.; and forming a bottom metal gate electrode on the gate dielectric layer.

[0082] In some embodiments, a gate dielectric layer is formed over a top channel in a top channel region, and the gate dielectric layer encapsulating the top channel in the top channel region further includes: forming an interfacial dielectric layer to encapsulate each of the top channels, and forming a high-k dielectric material layer over the interfacial dielectric layer to encapsulate each of the top channels.

[0083] In some embodiments, performing a radical treatment on the gate dielectric layer in a supercritical fluid further includes: dissolving a first radical source gas in a first supercritical carbon dioxide fluid; applying the first supercritical carbon dioxide fluid dissolved with the first radical chemical to the interfacial dielectric layer before forming the high-k dielectric material layer over the interfacial dielectric layer to encapsulate each of the top channels; dissolving a second radical source gas in a second supercritical carbon dioxide fluid after forming the high-k dielectric material layer over the interfacial dielectric layer to encapsulate each of the top channels; and applying the second supercritical carbon dioxide fluid dissolved with the second radical chemical to the high-k dielectric material layer.

[0084] In some embodiments, the first radical chemical includes hydrogen radicals; and the second radical chemical includes oxygen radicals.

[0085] In some embodiments, the first radical chemical includes hydrogen radicals (H*) and deuterium radicals (D*); and the second radical chemical includes oxygen radicals (O*) and fluorine radicals (F*).

[0086] The features of several embodiments are outlined above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructs do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor device, comprising: Providing a semiconductor structure having a bottom channel region and a top channel region located above the bottom channel region; forming a gate dielectric layer over the top channel in the top channel region, and the gate dielectric layer wraps around the top channel in the top channel region; performing a free radical treatment on the gate dielectric layer in a supercritical fluid; as well as A metal gate electrode is formed on the gate dielectric layer.

2. The method according to claim 1, wherein: The supercritical fluid is a supercritical carbon dioxide fluid; and Performing the free radical treatment on the gate dielectric layer in the supercritical fluid includes performing the free radical treatment on the gate dielectric layer in the supercritical carbon dioxide fluid at a temperature below 100°C.

3. The method according to claim 2, wherein: Performing the free radical treatment on the gate dielectric layer in the supercritical fluid further comprises: dissolving a free radical source gas in the supercritical carbon dioxide fluid; and Thereafter, the supercritical carbon dioxide fluid having free radical chemicals dissolved therein is applied to the gate dielectric layer.

4. The method according to claim 1, wherein: The top channels in the top channel region include the top channels vertically stacked and spaced apart from each other; and The gate dielectric layer is formed above the top channel in the top channel region, and the gate dielectric layer wraps around the top channel in the top channel region and further comprises: forming an interfacial dielectric layer to wrap around each of the top channels, and A high-k dielectric material layer is formed on the interface dielectric layer to wrap around each of the top trenches.

5. The method according to claim 4, wherein: Performing the free radical treatment on the gate dielectric layer in the supercritical fluid further comprises: dissolving a first free radical source gas in a first supercritical carbon dioxide fluid; applying the first supercritical carbon dioxide fluid having a first radical chemical dissolved therein to the interface dielectric layer before forming the high-k dielectric material layer on the interface dielectric layer to wrap around each of the top trenches; After forming the high-k dielectric material layer on the interface dielectric layer to wrap around each of the top trenches, dissolving a second radical source gas in a second supercritical carbon dioxide fluid; and The second supercritical carbon dioxide fluid having a second radical chemical dissolved therein is applied to the high-k dielectric material layer.

6. The method according to claim 5, wherein: The first radical chemical species includes hydrogen radicals; and The second free radical chemical species includes oxygen free radicals.

7. The method according to claim 6, wherein: The first radical chemical species includes hydrogen radicals and deuterium radicals; and The second free radical chemical species include oxygen free radicals and fluorine free radicals.

8. The method according to claim 1, wherein: The providing the semiconductor structure having the bottom channel region and the top channel region further comprises: forming bottom channels vertically stacked in the bottom channel region on the bottom substrate; forming a bottom source and a bottom drain in the bottom substrate, the bottom channel region being interposed between the bottom source and the bottom drain; forming a bottom gate structure on the bottom channel region and wrapping around each of the bottom channels; and A thermal annealing process is performed on the bottom gate structure at a temperature greater than 900°C.

9. A method of forming a semiconductor device, comprising: Providing a semiconductor structure having a bottom channel region and a top channel region located above the bottom channel region; forming an interfacial dielectric layer above the top channel in the top channel region, wherein the interfacial dielectric layer wraps around the top channel in the top channel region; performing a first free radical treatment on the interfacial dielectric layer in a first supercritical fluid having a first free radical chemical species dissolved therein; forming a high-k dielectric layer over the interface dielectric layer, and the high-k dielectric layer wraps around the top channel in the top channel region; performing a second free radical treatment on the high-k dielectric layer in a second supercritical fluid having a second free radical chemical dissolved therein; as well as A metal gate electrode is formed on the high-k dielectric layer.

10. A method of forming a semiconductor device, comprising: forming a bottom channel vertically stacked in a bottom channel region on a bottom substrate; forming a bottom source and a bottom drain on the bottom substrate, the bottom channel region being interposed between the bottom source and the bottom drain; forming a bottom gate structure on the bottom channel region, and the bottom gate structure wraps around each of the bottom channels; performing a thermal annealing process on the bottom gate structure at a first temperature greater than 900° C.; forming a semiconductor stack of first semiconductor layers and second semiconductor layers alternately stacked on a top substrate; bonding the semiconductor stack formed on the top substrate to the bottom substrate; thinning the top substrate so that the semiconductor stack is exposed; patterning the semiconductor stack to form an active area; forming a dummy gate structure above the active region in the top channel region, the dummy gate structure comprising a dummy gate stack and a gate spacer on a sidewall of the dummy gate stack; forming a top source and a top drain in the active region, the dummy gate stack being interposed between the top source and the top drain; removing the dummy gate stack and the first semiconductor layer in the top channel region, causing the second semiconductor layer to serve as a top channel in the top channel region; forming a gate dielectric layer over the top channel in the top channel region, and the gate dielectric layer wraps around the top channel in the top channel region; performing a free radical treatment on the gate dielectric layer in a supercritical fluid at a second temperature below 200° C.; as well as A bottom metal gate electrode is formed on the gate dielectric layer.

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