Semiconductor device and method of manufacturing the same

Abstract

A method of manufacturing a semiconductor device includes forming a fin structure including a lower fin structure and an upper fin structure disposed on the lower fin structure, where the upper fin structure includes dielectric layers and multilayer films alternately stacked, each multilayer film including a channel layer, a first protective layer, and a second protective layer, the channel layer is located between the first protection layer and the second protection layer. A sacrificial gate structure is formed on the upper fin structure. After a sacrificial gate structure is formed on the upper fin structure, a source / drain epitaxial layer is formed on a source / drain region of the fin structure. After forming the source / drain epitaxial layer, the sacrificial gate structure is removed. After removing the sacrificial gate structure, the dielectric layer is removed. A gate structure is formed around the multilayer film.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a semiconductor device and a method for manufacturing the same. Background Art

[0002] As the semiconductor industry enters the nanotechnology process node, in pursuit of higher device density, higher performance and lower cost, challenges from manufacturing and design issues have led to the development of three-dimensional designs, such as multi-gate field effect transistors (FETs), including fin FETs and gate-all-around (GAA) FETs. In GAA FETs, all sides of the channel region are surrounded by gate electrodes, which allows for more complete depletion in the channel region and reduces short channel effects due to steeper sub-threshold current swing (SS) and smaller drain-source induced barrier lowering (DIBL). As transistor dimensions continue to shrink to the 10-15 nanometer technology node, GAA FETs need further improvements. Summary of the invention

[0003] According to one aspect of the present disclosure, a method for manufacturing a semiconductor device is provided. A fin-shaped structure is formed, the fin-shaped structure comprising a lower fin-shaped structure and an upper fin-shaped structure disposed on the lower fin-shaped structure, wherein the upper fin-shaped structure comprises dielectric layers and semiconductor layers alternately stacked, each semiconductor layer comprising a channel layer, a first protective layer, and a second protective layer, and the channel layer is located between the first protective layer and the second protective layer. A sacrificial gate structure is formed on the upper fin-shaped structure. After the sacrificial gate structure is formed on the upper fin-shaped structure, a source / drain epitaxial layer is formed in the source / drain region of the fin-shaped structure. The sacrificial gate structure is removed after the source / drain epitaxial layer is formed. The dielectric layer is removed after the sacrificial gate structure is removed. A gate structure is formed around the semiconductor layer. In some embodiments, the aforementioned method further comprises: after the fin-shaped structure is formed, an isolation insulating layer is formed around the lower fin-shaped structure. In some embodiments, forming the fin-shaped structure comprises: forming a stack layer on a substrate; and patterning the stack layer and the substrate to form a fin-shaped structure comprising a lower fin-shaped structure and an upper fin-shaped structure. In some embodiments, after removing the sacrificial gate structure, the sidewalls of the channel layer are exposed. In some embodiments, after removing the dielectric layer, the bottom surface of the channel layer is covered by the first protective layer, and the top surface of the channel layer is covered by the second protective layer. In some embodiments, forming the gate structure includes: forming a gate dielectric layer around the semiconductor layer; and forming a gate electrode layer on the gate dielectric layer. In some embodiments, the foregoing method further includes: forming a pair of gate sidewall spacers on opposite sidewalls of the sacrificial gate structure. In some embodiments, after forming the pair of gate sidewall spacers, a source / drain epitaxial layer is formed in the source / drain region of the fin structure, and forming the source / drain epitaxial layer includes: partially removing the dielectric layer to reduce the length of the dielectric layer so that the first end of the dielectric layer is located below the pair of gate sidewall spacers; forming an internal spacer on the first end of the dielectric layer, wherein after forming the internal spacer on the first end of the dielectric layer, the second end of the semiconductor layer protrudes laterally from the internal spacer; and forming a source / drain epitaxial layer to cover the internal spacer and the second end of the semiconductor layer. In some embodiments, the first protective layer includes a first etch resistance layer, and removing the dielectric layer includes an etching process, the etching process has a first etching rate for the first etch resistance layer, a second etching rate for the channel layer, and the first etching rate is less than the second etching rate. In some embodiments, the second protective layer includes an adhesion layer; and a second etch resistance layer, wherein the adhesion layer is located between the second etch resistance layer and the channel layer, and the etching process has a third etching rate for the second etch resistance layer and a fourth etching rate for the adhesion layer, and the third etching rate is less than the second etching rate and the fourth etching rate. In some embodiments, the foregoing method further includes: partially removing the dielectric layer to form a sacrificial gate structure on the upper fin structure, and reducing the width of the dielectric layer.

[0004] According to another aspect of the present disclosure, a method for manufacturing a semiconductor device is provided. A fin-shaped structure is formed, the fin-shaped structure comprising alternatingly stacked sacrificial layers and semiconductor layers, wherein each semiconductor layer comprises a channel layer, a first protective layer, and a second protective layer, and the channel layer is located between the first protective layer and the second protective layer. A first gate structure is formed on the fin-shaped structure. A gate sidewall spacer is formed on the opposite sidewalls of the sacrificial gate structure. A source / drain epitaxial layer is formed on the opposite side of the first gate structure and the gate sidewall spacer. The first gate structure is removed after the source / drain epitaxial layer is formed. The sacrificial layer is removed after the first gate structure is removed. A second gate structure is formed around the semiconductor layer. In some embodiments, forming the source / drain epitaxial layer comprises: partially removing the sacrificial layer to reduce the length of the sacrificial layer so that the first end of the sacrificial layer is located below the gate sidewall spacer; forming an internal spacer on the first end of the sacrificial layer, wherein after the internal spacer is formed on the first end of the sacrificial layer, the second end of the semiconductor layer protrudes laterally from the internal spacer; and forming a source / drain epitaxial layer to cover the internal spacer and the second end of the semiconductor layer. In some embodiments, the inner spacer contacts the first protection layer and the second protection layer. In some embodiments, before removing the first gate structure, the source / drain epitaxial layer is separated from the first gate structure by the inner spacer.

[0005] According to one aspect of the present disclosure, a semiconductor device is provided, which includes a multilayer wire, a gate structure, a gate sidewall spacer, and a source / drain electrode. The multilayer wire is configured on a substrate, wherein each multilayer wire includes a two-dimensional material channel layer, a first protective layer, and a second protective layer, and the two-dimensional material channel layer is located between the first protective layer and the second protective layer. The gate structure is configured on the two-dimensional material channel region of the multilayer wire. The gate sidewall spacer is configured on the opposite sidewall of the gate structure. The source / drain electrode is configured on the opposite side of the gate structure and the gate sidewall spacer. In some embodiments, the semiconductor device further includes an internal spacer, wherein the source / drain electrode is laterally spaced from the gate structure by the internal spacer. In some embodiments, the end of the multilayer wire protrudes laterally from the internal spacer, and the end of the multilayer wire is covered by the source / drain electrode. In some embodiments, the gate structure includes: a gate dielectric layer surrounding the semiconductor layer; and a gate electrode layer configured on the gate dielectric layer, wherein the gate dielectric layer contacts the sidewalls of the first protective layer, the second protective layer, and the two-dimensional material channel layer. In some embodiments, a sidewall of the two-dimensional material channel layer is offset from a sidewall of the first protection layer and a sidewall of the second protection layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure can be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 A diagram is shown of one of the various stages of a sequential process for a GAA FET device according to an embodiment of the present disclosure.

[0008] Figure 2 A diagram is shown of one of the various stages of a sequential process for a GAA FET device according to an embodiment of the present disclosure.

[0009] Figure 3A and Figure 3B Depicted are various views of one of the various stages of a sequential process for a GAA FET device according to an embodiment of the present disclosure.

[0010] Figure 4 A diagram is shown of one of the various stages of a sequential process for a GAA FET device according to an embodiment of the present disclosure.

[0011] Figure 5A , Figure 5B , Figure 5C and Figure 5D Various views are shown of various stages of sequential processing of a GAA FET device according to an embodiment of the present disclosure.

[0012] Fig. 6A , Figure 6B , Figure 6C and Fig.6D Various views are shown of various stages of sequential processing of a GAA FET device according to an embodiment of the present disclosure.

[0013] Fig. 7A , Figure 7B , Figure 7C , Fig.7D and Fig. 7E Various views are shown of one of the various stages of a sequential process for a GAA FET device according to an embodiment of the present disclosure.

[0014] Fig. 8A , Figure 8B , Figure 8C , Fig.8D and Fig. 8E Various views are shown of one of the various stages of a sequential process for a GAA FET device according to an embodiment of the present disclosure.

[0015] Fig.9A , Fig. 9B , Fig. 9C , Fig.9D , Fig.9E and Fig.9F Various views are shown of one of the various stages of a sequential process for a GAA FET device according to an embodiment of the present disclosure.

[0016] Fig. 10A , Fig. 10B , Fig. 10C and Fig. 10D Various views are shown of one of the various stages of a sequential process for a GAA FET device according to an embodiment of the present disclosure.

[0017] FIG. 11A to FIG. 11E Various views are shown of various stages in the sequential process of a GAA FET device according to an embodiment of the present disclosure.

[0018] Fig. 12A and Fig. 12B Various views are shown of one of the various stages in a continuous process for a GAA FET device according to an alternative embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] The following disclosure provides many different embodiments or examples to implement different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. For simplicity and clarity, various features are drawn in different scales.

[0020] In addition, for ease of description, spatially relative terms such as "beneath", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship between one component or feature and another (other) component or feature shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be in other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0021] In the following embodiments, unless otherwise specified, materials, configurations, dimensions, operations, and / or processes of one embodiment may be used in another embodiment, and a detailed explanation thereof may be omitted.

[0022] All-around gate (GAA) FETs, equipped with nanoscale semiconductor wires or nanoscale semiconductor channels such as nanowires or nanosheets, are prospective devices for further technology nodes in semiconductor integrated circuits to achieve lower operating power, higher device performance, higher device density, and lower process costs, etc. In the GAA FET manufacturing process, how to improve the process yield of manufacturing nanoscale semiconductor wires is a key challenge for the above standards.

[0023] In an embodiment of the present disclosure, a semiconductor device (eg, GAAFET device) and a method for manufacturing the same are provided to solve the problem of manufacturing yield. The method for manufacturing the GAAFET device described below is compatible with currently used processes.

[0024] Figures 1 to 11E FIG. 1 shows a sequential process for manufacturing a GAAFET device according to an embodiment of the present disclosure. It should be understood that in additional method embodiments, Figures 1 to 11E Additional process steps are provided before, during, and after the process steps shown, and some of the process steps described below may be replaced or eliminated. The order of the process steps may be interchanged.

[0025] Reference Figure 1 , providing a substrate 10. In some embodiments, the substrate 10 is a semiconductor substrate, such as but not limited to a silicon substrate. Figure 1 As shown, impurity ions (dopants) 12 are implanted into the substrate 10 to form a well region. Ion implantation is performed to prevent a punch-through effect. In some embodiments, the substrate 10 includes a single crystal semiconductor layer at least on a surface portion thereof. The substrate 10 may include a single crystal semiconductor material, such as but not limited to Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. In one embodiment, the substrate 10 is made of crystalline silicon.

[0026] The substrate 10 may include one or more buffer layers (not shown) in its surface region. These buffer layers may be used to gradually change the lattice constant from the lattice constant of the substrate 10 to the lattice constant of the subsequently formed source / drain regions. The buffer layers may be formed of one or more of single crystal semiconductor materials such as silicon, germanium, germanium tin, silicon germanium, gallium arsenide, indium antimony, gallium phosphide, gallium antimonide, aluminum indium antimony, indium gallium arsenic, gallium antimonide phosphide, gallium arsenide antimony, gallium nitride, gallium phosphide, and indium phosphide, but not limited thereto. In some embodiments, the substrate 10 includes a silicon germanium (SiGe) buffer layer epitaxially grown on the silicon substrate 10. The germanium concentration of the silicon germanium buffer layer may increase from 30 atomic percent germanium (atomic %) in the bottommost buffer layer to 70 atomic percent germanium in the topmost buffer layer. The substrate 10 may include various regions that have been appropriately doped with impurities (e.g., p-type or n-type conductivity). For example, for an n-type Fin FET, the dopant 12 is BF 2 , for p-type Fin FETs, the dopant is phosphorus.

[0027] Reference Figure 2 , stacked layers are formed on the substrate 10. The stacked layers include alternately stacked dielectric layers 20 and multilayer films 25. The dielectric layer 20 serves as a sacrificial layer to maintain the position of the multilayer films 25 in the subsequent process. In addition, the shielding layer 15 is formed on the stacked layers including the alternately stacked dielectric layers 20 and the multilayer films 25. Each layer of the multilayer films 25 may include a first protective layer P1 disposed on the surface of the underlying dielectric layer 20, a second protective layer P2 disposed on the first protective layer P1, and a channel layer 25b disposed between the first protective layer P1 and the second protective layer P2, wherein the first protective layer P1 includes a first etch-resistant layer 25a, the second protective layer P2 includes a second etch-resistant layer 25d disposed on the first etch-resistant layer 25a, and an adhesive layer 25c disposed between the channel layer 25b and the second etch-resistant layer 25d. As Figure 2 As shown, the first protective layer P1 includes a single-layer structure, and the second protective layer P2 includes a multi-layer structure.

[0028] The material of the first etch resistance layer 25a may be or include AlO x Or other suitable dielectric materials. The material of the adhesive layer 25c may be or include AlO x Or other suitable dielectric materials. Adhesion layer 25c may be a metal-rich high-k dielectric layer. The metal ratio in adhesion layer 25c may be greater than the metal ratio in etch resistance layer 25a. The material of second etch resistance layer 25d may be or include AlO xOr other suitable dielectric materials. For example, the first etch resistance layer 25a and the second etch resistance layer 25d are substantially the same in material and thickness. In addition, the film density of the first etch resistance layer 25a and the second etch resistance layer 25d may be greater than the film density of the adhesion layer 25c. In an embodiment where the channel layer 25b includes a two-dimensional material (2D material), the channel layer 25 can be easily adhered to the first etch resistance layer 25a, and the adhesion layer 25c can enhance the adhesion between the channel layer 25b and the second etch resistance layer 25d, so that the top and bottom surfaces of the channel layer 25b can be well protected by the adhesion layer 25c and the second etch resistance layer 25d in subsequent processes. Figure 2 As shown, no adhesion layer is formed between the first etch resistance layer 25a and the channel layer 25b. In some other embodiments not shown in the figure, if necessary, an additional adhesion layer is formed between the first etch resistance layer and the channel layer.

[0029] In some other embodiments, the dielectric layer 20 is made of a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride (SiON) or other suitable dielectric materials. In some embodiments, the channel layer 25b of the multilayer film 25 is made of a two-dimensional material, such as a transition metal chalcogenide monolayer (e.g., MoS 2 ), graphene or the like. In some other embodiments, the channel layer 25b of the multilayer film 25 is made of materials with different lattice constants and may include one or more layers of silicon, germanium, silicon germanium, germanium tin, silicon germanium tin, gallium arsenide, indium antimony, gallium phosphide, gallium antimonide, indium aluminum arsenide, indium gallium arsenide, gallium antimony phosphide, gallium antimony arsenide or indium phosphide. In some alternative embodiments, the channel layer 25b of the multilayer film 25 is made of silicon, silicon compounds, silicon germanium, germanium or germanium compounds. For example, the channel layer 25b of the multilayer film 25 is made of silicon or Si 1-y Ge y Made, where y is equal to or less than about 0.2, and 1>y.

[0030] like Figure 2 As shown, five dielectric layers 20 and five multilayer films 25 are configured. However, the number of dielectric layers 20 and multilayer films 25 is not limited to five layers, and can be as few as one layer (each dielectric layer and semiconductor layer), and in some embodiments, two to twenty dielectric layers 20 and multilayer films 25 can be formed. By properly adjusting the number of stacked layers, the drive current of the GAAFET device can be adjusted.

[0031] In some other embodiments, the dielectric layer 20 and the multilayer film 25 are deposited or epitaxially grown on the substrate 10. In some embodiments, the thickness of the dielectric layer 20 may be substantially equal to or less than the thickness of the multilayer film 25, and may be in the range of about 2 nanometers to about 10 nanometers, and in some other embodiments, may be in the range of about 3 nanometers to about 5 nanometers. In some embodiments, the thickness of the multilayer film 25 may be in the range of about 5 nanometers to about 20 nanometers, and in some other embodiments, may be in the range of about 7.5 nanometers to about 12.5 nanometers. The thickness of each layer of the dielectric layer 20 and the multilayer film 25 may be the same or different.

[0032] In some embodiments, the bottommost dielectric layer (the dielectric layer closest to substrate 10) is thicker than the remaining dielectric layers. In some embodiments, the bottommost dielectric layer has a thickness ranging from about 10 nanometers to 50 nanometers, or in other embodiments, the bottommost dielectric layer has a thickness ranging from about 20 nanometers to 40 nanometers.

[0033] In some embodiments, the shielding layer 15 includes a first shielding layer 15A and a second shielding layer 15B. The first shielding layer 15A may be a pad oxide layer made of silicon oxide, which may be formed by a thermal oxidation process. The second shielding layer 15B may be made of silicon nitride (SiN), which is formed by chemical vapor deposition (CVD), including low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other appropriate processes. The shielding layer 15 is patterned into a shielding pattern using a patterning process including photolithography and subsequent etching.

[0034] Reference Figure 3A and Figure 3B The stacked layers of the dielectric layer 20 and the multilayer film 25 are patterned using the patterned shielding layer 15, so that the stacked layers are formed into a plurality of fin-shaped structures 30. Figure 3A As shown, the fin structure 30 extends in the Y direction and is arranged in the X direction. The fin structure 30 can be patterned using any suitable method. For example, the fin structure can be patterned using one or more photolithography processes, including double patterning or multi-patterning processes. In general, double patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches than can be obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can be used to pattern the fin structure.

[0035] exist Figure 3A and Figure 3B In the figure, two upper fin structures 30A and 30B are shown, and the upper fin structures 30A and 30B are arranged in the X direction. However, the number of fin structures 30 is not limited to two, and can be as few as one, or three or more. In some embodiments, one or more pseudo-fin structures (not shown in the figure) are formed on both sides of the fin structure 30 to improve the pattern fidelity in the patterning process. In other words, the pseudo-fin structure can minimize the loading effect. Figure 3A and Figure 3B As shown, the fin structure 30 includes an upper portion composed of stacked layers 20 and 25, and the fin structure 30 also includes a well portion 11 located below the upper fin structures 30A and 30B. The upper portion is referred to as the upper fin structure 30A and 30B of the fin structure 30, and the well portion 11 is referred to as the lower fin structure of the fin structure 30. In some embodiments, the upper fin structure 30A is used for a p-channel GAA FET, and the fin structure 30B is used for an n-channel GAA FET. Figure 3B As shown, upper fin structures 30A and 30B are disposed on lower fin structures 11A and 11B, respectively. In some other embodiments, upper fin structures 30A and 30B are used for the same type of FETs.

[0036] In some embodiments, the upper width W1 of the fin structure 30 along the X direction ranges from about 5 nanometers to about 30 nanometers, while in other embodiments, the upper width W1 of the fin structure 30 along the X direction ranges from about 7.5 nanometers to about 15 nanometers. The height H1 of the fin structure 30 along the Z direction ranges from about 50 nanometers to about 200 nanometers.

[0037] Reference Figure 4 , one or more fin liners 35 and an isolation insulating layer 40 are formed on the substrate 10. For example, an insulating material layer including one or more insulating material layers is formed on the substrate 10, so that the upper fin structures 30A and 30B are completely embedded in the insulating material layer. The insulating material of the insulating material layer may be or include silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG) or a low-k dielectric material formed by low-pressure chemical vapor deposition (LPCVD), plasma CVD or flowable CVD. After forming the insulating material layer, an annealing treatment may be performed. Then, a planarization treatment is performed, such as a chemical mechanical polishing (CMP) method and / or an etch-back method, so that the upper surface of the uppermost multilayer film 25 is exposed from the insulating material layer.

[0038] In some embodiments, Figure 4As shown, before forming the insulating material layer, one or more fin liners 35 are formed. The fin liner 35 is made of silicon nitride (SiN) or a silicon nitride base material (e.g., SiON, SiCN, or SiOCN). In some embodiments, the fin liner 35 includes a first fin liner 35A formed on the sides of the substrate 10 and the bottom fin structure 11, and a second fin liner 35B formed on the first fin liner 35A. In some embodiments, the thickness of each liner is between about 1 nanometer and about 20 nanometers. For example, the first fin liner 35A includes silicon oxide with a thickness between about 0.5 nanometers and about 5 nanometers, and the second fin liner 35B includes silicon nitride with a thickness between about 0.5 nanometers and about 5 nanometers. The fin liner 35 can be deposited through one or more processes, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD), although any acceptable process can be used.

[0039] Then, if Figure 4 As shown, a recessing process (e.g., an etching process) of the insulating material layer is performed, so that the insulating material layer is recessed to form an isolation insulating layer 40, thereby exposing the upper portion of the fin structure 30. Through this operation, the upper portions of the fin structure 30 are electrically separated from each other by the isolation insulating layer 40, and the isolation insulating layer 40 is also called shallow trench isolation (STI). Figure 4 In the illustrated embodiment, the insulating material layer is recessed until the top of the lower fin structure 11 is exposed. The dielectric layer 20 serves as a sacrificial layer that can be partially removed in subsequent processes, and the multilayer film 25 is subsequently formed and serves as the channel layer of the GAA FET. In the recessing process of the insulating material layer, the width of the dielectric layer 20 is reduced due to the etchant used in the recessing process.

[0040] Reference FIG. 5A to FIG. 5D After forming the isolation insulating layer 40 , a sacrificial gate structure 50 is formed on the upper fin structures 30A and 30B. Figure 5A Draw a perspective view, Figure 5B A cross-sectional view of the sacrificial gate structure cut along the X direction is shown. Figure 5C A cross-sectional view of the upper fin structure 30A cut along the Y direction is shown; and Figure 5D A cross-sectional view of the upper fin structure 30B cut along the Y direction is shown.

[0041] like Figure 5AAs shown, the sacrificial gate structure 50 includes a sacrificial gate electrode 54. In some embodiments, the sacrificial gate structure 50 does not include a sacrificial gate dielectric layer. The sacrificial gate structure 50 is formed on a portion of the upper fin structures 30A and 30B, and the portion of the upper fin structures 30A and 30B covered by the sacrificial gate structure 50 will become the channel region. In other words, the sacrificial gate structure 50 defines the channel region of the GAA FET.

[0042] The sacrificial gate structure 50 is formed by first depositing a sacrificial gate electrode layer on the upper fin structures 30A and 30B so that the upper fin structures 30A and 30B are completely embedded in the sacrificial gate electrode layer. The sacrificial gate electrode layer includes silicon, such as polycrystalline silicon or amorphous silicon. In some embodiments, the thickness of the sacrificial gate electrode layer ranges from about 100 nanometers to about 200 nanometers. In some embodiments, the sacrificial gate electrode layer is planarized. The sacrificial gate electrode layer can be deposited using chemical vapor deposition (CVD), including low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other appropriate processes. Subsequently, a shielding layer 56 is formed on the sacrificial gate electrode layer. The shielding layer 56 includes one or more silicon nitride (SiN) layers and a silicon oxide layer.

[0043] Then, a patterning process is performed on the shielding layer 56 so that the sacrificial gate electrode layer below is patterned into a sacrificial gate structure 50, such as FIG. 5A to FIG. 5D The sacrificial gate structure 50 may include a sacrificial gate electrode layer 54 (eg, a polysilicon layer) and a shielding layer 56 .

[0044] By patterning the sacrificial gate structure 50, the upper fin structures 30A and 30B including the dielectric layer 20 and the multilayer film 25 are partially exposed on opposite sides of the sacrificial gate structure 50, thereby defining the source / drain (S / D) regions of the upper fin structures 30A and 30B, such as FIG. 5A to FIG. 5D In this embodiment, the source and drain can be used interchangeably, and their structures are substantially the same. FIG. 5A to FIG. 5D In the figure, only one sacrificial gate structure 50 is shown, but the number of sacrificial gate structures 50 is not limited to one. In some embodiments, two or more sacrificial gate structures 50 are arranged in the Y direction. In some alternative embodiments, one or more quasi-sacrificial gate structures are formed on both sides of the sacrificial gate structure to improve pattern fidelity. In other words, the quasi-sacrificial gate structure can minimize the loading effect.

[0045] After forming the sacrificial gate structure 50, as shown in FIG. FIG. 6A to FIG. 6D As shown, gate sidewall spacers 55 are formed on opposite sidewalls of the sacrificial gate structure 50 . Fig. 6A Draw a perspective view, Figure 6B FIG. 4 shows a cross-sectional view of the sacrificial gate structure 50 cut along the X direction. Figure 6C A cross-sectional view of the upper fin structure 30A cut along the Y direction is shown. Fig.6D A cross-sectional view of the upper fin structure 30B cut along the Y direction is shown.

[0046] In order to form the gate sidewall spacer 55, a blanket layer of an insulating material is conformally formed using chemical vapor deposition or other appropriate methods. The blanket layer is deposited in a conformal manner so that it has substantially equal thickness on vertical surfaces (such as sidewalls), horizontal surfaces, and the top of the sacrificial gate structure 50. In some embodiments, the thickness of the blanket layer ranges from about 2 nanometers to 20 nanometers. In some embodiments, the insulating material of the blanket layer is a silicon nitride-based material, such as SiN, SiON, SiOCN or SiCN and combinations thereof. In some other embodiments, the insulating material is one of SiOC, SiCON, and SiCN.

[0047] Furthermore, if FIG. 6A to FIG. 6D As shown, gate sidewall spacers 55 are formed on opposite sidewalls of the sacrificial gate structure 50 by anisotropic etching. After forming the capping layer, the capping layer is anisotropically etched, for example, using reactive ion etching (RIE). In the anisotropic etching process, most of the insulating material is removed from the horizontal surfaces, leaving only the dielectric spacers on the vertical surfaces, such as the sidewalls of the sacrificial gate structure 50 and the exposed upper fin structures 30A and 30B. The shielding layer 56 can be exposed from the gate sidewall spacers 55. In some embodiments, an isotropic etching process can be subsequently performed to remove the insulating material from the upper portion of the S / D regions of the exposed upper fin structures 30A and 30B.

[0048] Reference 7A to 7E , removing the portion of the semiconductor layer 20 not covered by the sacrificial gate structure 50 . Fig. 7A Draw a perspective view, Figure 7B FIG. 4 is a cross-sectional view of the sacrificial gate structure 50 cut along the X direction. Figure 7C Draw a cross-sectional view of the upper fin structure 30A cut along the Y direction, Fig.7D A cross-sectional view of the upper fin structure 30B cut along the Y direction is shown; and Fig. 7E A cross-sectional view of the S / D region cut along the X direction is shown.

[0049] like 7A to 7EAs shown, the dielectric layer 20 is partially removed to reduce the length of the dielectric layer 20, so that multiple first ends of the dielectric layer 20 are located below the gate sidewall spacer 55. After the dielectric layer 20 is partially removed, multiple indentations are formed in the gate sidewall spacer 55 between adjacent multilayer films 25. In some embodiments, an anisotropic etching process can be performed to partially remove the dielectric layer 20 in the S / D region of the upper fin structure 30A and 30B, so that multiple second ends of the multilayer film 25 can protrude from the sidewall of the sacrificial gate structure 50. For example, a dry etching process using a gaseous etchant is performed to remove a portion of the dielectric layer 20, the dielectric layer 20 is etched by the gaseous etchant at a first etching rate, and the multilayer film 25 is etched by the gaseous etchant at a second etching rate, and the first etching rate is greater than the second etching rate. Due to the significant difference between the first etching rate and the second etching rate, the multilayer film 25, especially the sidewall of the channel layer 25b, is not significantly damaged. In some embodiments, the etching process of the dielectric layer 20 has a lower etching rate for the first etch resistance layer 25a of the multilayer film 25, and the etching process of the dielectric layer 20 has a higher etching rate for the channel layer 25b of the multilayer film 25. In addition, the etching process of the dielectric layer 20 has a lower etching rate for the second etch resistance layer 25d of the multilayer film 25, and the etching process of the dielectric layer 20 has a higher etching rate for the adhesion layer 25c of the multilayer film 25. In some embodiments, the sidewall of the channel layer 25b is laterally offset from the sidewall of the first protection layer P1 (e.g., the first etch resistance layer 25a) and the sidewall of the second protection layer P2 (e.g., the adhesion layer 25c and / or the second etch resistance layer 25d).

[0050] At this stage, the second end of the multilayer film 25 is laterally spaced apart from the sidewalls of the sacrificial gate structure 50 and the gate sidewall spacers 55. In addition, the second end of the multilayer film 25 is exposed and does not contact the remaining dielectric layer 20 covered by the sacrificial gate structure 50.

[0051] After partially removing the dielectric layer 20 to reduce the length of the dielectric layer 20, the inner spacer 28 is selectively formed on the first end (e.g., end surface) of the dielectric layer 20. At this stage, the second end of the multilayer film 25 may protrude laterally from the inner spacer 28, and since the first end (e.g., end surface) of the dielectric layer 20 is covered by the inner spacer 28, the portion of the dielectric layer 20 with a reduced width is exposed. In addition, the inner spacer 28 is in contact with the multilayer film 25. For example, each inner spacer 28 extends vertically from the second etch-resistant layer 25d of the lower multilayer film 25 to the first etch-resistant layer 25a of the upper multilayer film 25. Figure 7C and Fig.7DAs shown in the figure, the inner spacers 28 are located below the gate sidewall spacers 55, and the width of each inner spacer 28 is less than the width of each gate sidewall spacer 55. In other words, the inner spacers 28 are directly located below the gate sidewall spacers 55. In some other embodiments, not shown in the figure, the inner spacers 28 are located below the gate sidewall spacers 55, and the width of each inner spacer 28 is greater than the width of each gate sidewall spacer 55. In other words, the inner spacers 28 are not completely covered by the gate sidewall spacers 55.

[0052] The conformal deposition of insulating material and the subsequent back etching method can selectively form an internal spacer 28 on the end face of the dielectric layer 20. In order to form the internal spacer 28, a cover layer of an insulating material can be conformally formed using chemical vapor deposition (CVD) or other appropriate methods. In some embodiments, the insulating material used to make the cover layer of the internal spacer 28 is a silicon nitride base material, such as SiN, SiON, SiOCN or SiCN and a combination thereof. In some other embodiments, the insulating material used to make the cover layer of the internal spacer 28 is one of SiOC, SiCON and SiCN. For example, in some embodiments, the thickness of the internal spacer 28 ranges from about 0.2 nanometers to about 2 nanometers.

[0053] Reference FIG. 8A to FIG. 8E , source / drain epitaxial layers 60A and 60B are formed on opposite sides of the sacrificial gate structure 50. The channel layer 25b (eg Figure 3A The sidewalls of the first source / drain epitaxial layer 60A and the second source / drain epitaxial layer 60B are in contact with each other, so that the channel layer 25b (as shown in FIG. Figure 3A As shown) is electrically connected to the first source / drain epitaxial layer 60A and the second source / drain epitaxial layer 60B. Fig. 8A Draw a perspective view, Figure 8B FIG. 4 is a cross-sectional view of the sacrificial gate structure 50 cut along the X direction. Figure 8C A cross-sectional view of the upper fin structure 30A cut along the Y direction is shown. Fig.8D A cross-sectional view of the upper fin structure 30B cut along the Y direction is shown; and Fig. 8E A cross-sectional view of the S / D region cut along the X direction is shown.

[0054] A first source / drain epitaxial layer 60A is formed to cover the multilayer film 25 in the S / D region of the upper fin structure 30A. The first source / drain epitaxial layer 60A includes one or more layers of silicon, silicon germanium, and silicon germanium phosphorus for p-channel FETs. The first source / drain epitaxial layer 60A is formed by an epitaxial growth method using chemical vapor deposition, atomic layer deposition, or molecular beam epitaxy (MBE). In some embodiments, boron (B) is included in the first source / drain epitaxial layer 60A. A second source / drain epitaxial layer 60B is formed to cover the multilayer film 25 in the S / D region of the upper fin structure 30B. The second source / drain epitaxial layer 60B includes one or more layers of silicon, silicon phosphorus, silicon carbon, and silicon carbon phosphorus for n-channel FETs. The second source / drain epitaxial layer 60B is formed by an epitaxial growth method using chemical vapor deposition, atomic layer deposition, or molecular beam epitaxy (MBE). In some embodiments, the first source / drain epitaxial layer 60A for p-channel FET and the second source / drain epitaxial layer 60B for n-channel FET are formed separately. The order of forming the first source / drain epitaxial layer 60A and the second source / drain epitaxial layer 60B is not limited. In some embodiments, the formation of the first source / drain epitaxial layer 60A may be before the formation of the second source / drain epitaxial layer 60B, and when the second source / drain epitaxial layer 60B is formed, the upper fin structure 30A may be covered and protected by a layer (e.g., a dielectric layer, a photomask layer, or other appropriate layer). In some other embodiments, the formation of the second source / drain epitaxial layer 60B may be before the formation of the first source / drain epitaxial layer 60A, and when the first source / drain epitaxial layer 60A is formed, the upper fin structure 30B may be covered and protected by a layer (e.g., a dielectric layer, a photomask layer, or other appropriate layer).

[0055] like FIG. 8A to FIG. 8E As shown, when the inner spacer 28 is formed at the first end of the dielectric layer 20, the second end of the multilayer film 25 will protrude laterally from the inner spacer 28. In addition, when the source / drain epitaxial layers 60A and 60B are formed, the source / drain epitaxial layers 60A and 60B not only cover the inner spacer 28, but also cover the second end of the multilayer film 25.

[0056] like FIG. 8A to FIG. 8E As shown, the source / drain epitaxial layers 60A and 60B are separated from the sacrificial gate electrode layer 54 by the inner spacers 28 .

[0057] Reference 9A to 9F Subsequently, a first insulating liner 63 is formed, and then a dielectric layer (ILD) layer 65 is formed, and then the sacrificial gate structure 50 is removed to form a gate space between the gate sidewall spacers 55 . Fig.9A Draw a perspective view, Fig. 9B A cross-sectional view of the channel region cut along the X direction is shown. Fig. 9CA cross-sectional view of the upper fin structure 30A cut along the Y direction is shown. Fig.9D A cross-sectional view of the upper fin structure 30B cut along the Y direction is shown. Fig.9E A cross-sectional view of the source / drain region cut along the X direction is shown, and Fig.9F A cross-sectional view of the gate sidewall spacer 55 cut along the X direction is shown.

[0058] The first insulating liner 63 is made of a silicon nitride base material, such as silicon nitride, and acts as a first contact etch stop layer (CESL) in a subsequent etching process. The material of the first ILD layer 65 includes a compound including Si, O, C and / or H, such as silicon oxide, SiCOH and SiOC. An organic material, such as a polymer, may be used for the first ILD layer 65. After the first ILD layer 65 is formed, a planarization process, such as CMP, is performed to expose the sacrificial gate electrode layer 54.

[0059] Then, if 9A to 9F As shown, after the sacrificial gate electrode layer 54 is removed, multiple portions of the dielectric layer 20 in the gate space and multiple portions of the multilayer film 25 (e.g., nano-sized semiconductor lines) are exposed. Specifically, multiple portions of the dielectric layer 20 laterally distributed between the inner spacers 28 are removed. The first ILD layer 65 can protect the first source / drain epitaxial layer 60A and the second source / drain epitaxial layer 60B from damage during the removal of the sacrificial gate structure 54. The sacrificial gate structure 54 can be removed using plasma dry etching and / or wet etching. When the sacrificial gate electrode layer 54 is polysilicon and the first ILD layer 65 is silicon oxide, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution can be used to selectively remove the sacrificial gate electrode layer 54.

[0060] Reference FIG. 10A to FIG. 10D After the nano-sized semiconductor wires of the multilayer film 25 are exposed, a gate replacement process is performed to form a gate dielectric layer 104 around the nano-sized semiconductor wires of the multilayer film 25 of the upper fin structure 30A and the upper fin structure 30B. Fig. 10A Draw a perspective view, Fig. 10B A cross-sectional view of the channel region cut along the X direction is shown. Fig. 10C A cross-sectional view of the upper fin structure 30A cut along the Y direction is shown; and Fig. 10D A cross-sectional view of the upper fin structure 30B cut along the Y direction is shown.

[0061] In some embodiments, the gate dielectric layer 104 includes one or more layers of dielectric materials, such as silicon oxide, silicon nitride, or a high dielectric constant material, other suitable dielectric materials, and / or combinations thereof. Examples of high dielectric constant materials include HfO 2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、zirconium oxide、aluminum oxide、titanium oxide、hafnium dioxide-alumina (hafniumdioxide-alumina, HfO 2 -Al 2 O 3 ) alloy, other suitable high dielectric constant materials, and / or combinations thereof. In some embodiments, an interface layer (not shown) is formed between the channel layer and the gate dielectric layer 104. The gate dielectric layer 104 can be formed by chemical vapor deposition, atomic layer deposition, or any suitable method. In one embodiment, the gate dielectric layer 104 uses a highly conformal deposition process, such as atomic layer deposition, to ensure that a gate dielectric layer with a consistent thickness around each channel layer is formed. In one embodiment, the thickness of the gate dielectric layer 104 is in the range of about 1 nanometer to about 6 nanometers.

[0062] Further, if FIG. 10A to FIG. 10D As shown, the gate electrode layer 108 is formed on the gate dielectric layer 104. In some embodiments, the gate electrode layer 108 is formed on the gate dielectric layer 104 to surround each channel layer. The gate electrode 108 includes one or more layers of conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. The gate electrode layer 108 can be formed by CVD, ALD, electroplating or other suitable methods. The gate electrode layer is also deposited on the upper surface of the first ILD layer 65. Then, the gate dielectric layer and the gate electrode layer formed on the first ILD layer 65 are planarized using a method such as CMP until the first ILD layer 65 is exposed.

[0063] In some embodiments, one or more work function adjustment layers 106 are disposed between the gate dielectric layer 104 and the gate electrode layer 108. The work function adjustment layer 106 is made of a conductive material, such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi or TiAlC, or a multilayer of two or more of these materials. For n-channel FETs, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi and TaSi may be used as the work function adjustment layer. The work function adjustment layer 106 may be formed by ALD, PVD, CVD, electron beam evaporation or other appropriate processes. In addition, different metal layers may be used to form the work function adjustment layer 106 for n-channel FETs and p-channel FETs.

[0064] Reference FIG. 11A to FIG. 11ESubsequently, a second insulating substrate layer 110 is formed on the first ILD layer 65 , and a second ILD layer 115 is formed on the second insulating layer 110 . Fig.11A Draw a perspective view, Fig. 11B A cross-sectional view of the channel region cut along the X direction is shown. Fig. 11C A cross-sectional view of the upper fin structure 30A cut along the Y direction is shown. Fig.11D A cross-sectional view of the upper fin structure 30B cut along the Y direction is shown; and Fig.11E A cross-sectional view of the source / drain region cut along the X direction is shown.

[0065] The second insulating substrate layer 110 is made of a silicon nitride base material, such as silicon nitride, and acts as a second CESL in a subsequent etching process. The material of the second ILD layer 115 includes a compound including silicon, oxygen, carbon and / or hydrogen, such as silicon oxide, SiCOH and SiOC. An organic dielectric material, such as a polymer, may be used for the second ILD layer 110. After forming the second ILD layer 110, a planarization process, such as CMP, may be performed.

[0066] Then, contact openings are formed to expose the source / drain epitaxial layers 60A and 60B, respectively. The contact openings are filled with one or more layers of conductive material to form source / drain contacts, such as FIG. 11A to FIG. 11E As shown. One or more layers of conductive material are formed in and above the contact openings, and then a planarization process, such as a CMP process, is performed to form a source / drain contact with a flat top surface. In some embodiments, the source / drain contact includes a liner 122 and a source / drain conductor 120. The liner 122 is a barrier layer and / or an adhesion layer. In some embodiments, a Ti layer is formed on the source / drain epitaxial layers 60A and 60B, and a TiN or TaN layer is formed on the Ti layer, wherein the Ti layer and the TiN layer are collectively referred to as a liner 122. The source / drain conductor 120 may include one or more layers of Co, Ni, W, Ti, Ta, Cu and Al, or any other suitable material. As FIG. 11A to FIG. 11E As shown, source / drain contacts wrap around source / drain epitaxial layers 60A and 60B.

[0067] It should be understood that GAA FETs may undergo further CMOS processing to form various features such as metal contacts / vias, interconnect metal layers, interconnect dielectric layers, insulating layers, etc.

[0068] Fig. 12A and Fig. 12B Various views are shown of one of the various stages in a continuous process for a GAA FET device according to an alternative embodiment of the present disclosure.

[0069] In forming the fin structure 30 (such as Figure 3Aand Figure 3B As shown) and in forming the fin liner 35 and the isolation insulating layer 40 (as shown Figure 4 As shown), before the dielectric layer 20 is removed, a process may be performed, such as Fig. 12A and Fig. 12B After the above-mentioned removal process of the dielectric layer 20 is performed, the dielectric layer 20 will be etched laterally and partially, so that undercut profiles are generated on the end surface or sidewall of the dielectric layer 20, as shown in FIG. Fig. 12A and Fig. 12B In some embodiments, relative to the multilayer film 25, plasma dry etching is used to selectively etch the dielectric layer 20, and then a slow-release HF is used for a wet cleaning process. For example, the plasma source gas used in the above plasma dry etching includes O 2 In some other embodiments, a wet etching process is used to selectively etch the dielectric layer 20. The etching solution (etchant) may include NH 4 OH, H 2 O 2 and H 2 Aqueous solution of O and / or H 2 SO 4 , H 2 O 2 and H 2 O aqueous solution. In other embodiments, the wet etchant includes a tetramethylammonium hydroxide (TMAH) solution. In some embodiments, an additional wet cleaning process using slow-release HF is performed. In some other embodiments, plasma dry etching and wet etching are used simultaneously. In some embodiments, the etching amount D1 ranges from about 1 nanometer to about 10 nanometers, and the etching amount D2 ranges from about 2 nanometers to about 5 nanometers. Fig. 12B As shown, the cross-sectional shapes of the etched dielectric layer 20 and the multilayer film 25 include a dog-bone shape or a thread-spool shape or a bobbin shape.

[0070] The above-mentioned removal process of the dielectric layer 20 can be performed at various time points. For example, the above-mentioned removal process of the dielectric layer 20 can be performed at the time of forming the isolation insulating layer 40 (such as Figure 4 ) and after forming a sacrificial gate structure 50 (as shown FIG. 5A to FIG. 5D as shown).

[0071] The dielectric layer 20 (such as Fig. 12A and Fig. 12B The removal process of the insulating layer 40 (as shown) can be omitted, and the insulating layer 40 (as shown) can be removed by removing the insulating layer 40 (as shown) ... Figure 4The recess process (eg, etching process) of FIG. 2 may laterally and partially etch the dielectric layer 20 , so that an undercut profile is generated on the end surface or sidewall of the dielectric layer 20 .

[0072] In some embodiments, the undercut profile of the end surface or sidewall of the dielectric layer 20 is obtained by the above-mentioned removal process of the dielectric layer 20 (eg, Fig. 12A and Fig. 12B As shown) and a recess process (eg, an etching process) for forming the isolation insulating layer 40 (eg, Figure 4 shown).

[0073] In some other embodiments, the dielectric layer 20 (eg Fig. 12A and Fig. 12B The removal process of the dielectric layer 20 is omitted, and the undercut profile of the end surface or sidewall of the dielectric layer 20 is due to the formation of the isolation insulating layer 40 (as shown in FIG. Figure 4 As shown in FIG. 1 , the recessed portion of the substrate is formed by a recessed process (eg, an etching process).

[0074] In other embodiments, the undercut profile of the end surface or sidewall of the dielectric layer 20 is formed by forming an isolation insulating layer 40 (eg, Figure 4 As shown in FIG. 1 ), a recess process (eg, an etching process) and a process for forming an isolation insulating layer 40 (eg, Figure 4 ) and after forming a sacrificial gate structure 50 (as shown FIG. 5A to FIG. 5D This is caused by the removal process of the dielectric layer 20 performed before (as shown).

[0075] In some alternative embodiments, the undercut profile of the end surface or sidewall of the dielectric layer 20 is formed by forming an isolation insulating layer 40 (eg, Figure 4 As shown) of the recess process (eg, etching process), as Fig. 12A and Fig. 12B The first removal process of the dielectric layer 20 shown in FIG. 1 and the formation of the isolation insulating layer 40 (eg Figure 4 ) and after forming a sacrificial gate structure 50 (as shown FIG. 5A to FIG. 5D This is caused by the second removal process of the dielectric layer 20 performed before (as shown).

[0076] In another embodiment, the undercut profile of the end surface or sidewall of the dielectric layer 20 is due to the first removal process (such as Fig. 12A and Fig. 12B As shown) and the second removal process of the dielectric layer 20, and the aforementioned second removal process is formed in the isolation insulating layer 40 (as shown) Figure 4 As shown) and in forming a sacrificial gate structure 50 (as shown FIG. 5A to FIG. 5D as shown).

[0077] It should be understood that not all advantages are discussed herein, and not all embodiments or examples require specific advantages, and other embodiments or examples may also provide different advantages.

[0078] According to one aspect of the present disclosure, a method for manufacturing a semiconductor device is provided. A fin-shaped structure is formed, the fin-shaped structure comprising a lower fin-shaped structure and an upper fin-shaped structure disposed on the lower fin-shaped structure, wherein the upper fin-shaped structure comprises dielectric layers and semiconductor layers alternately stacked, each semiconductor layer comprising a channel layer, a first protective layer, and a second protective layer, and the channel layer is located between the first protective layer and the second protective layer. A sacrificial gate structure is formed on the upper fin-shaped structure. After the sacrificial gate structure is formed on the upper fin-shaped structure, a source / drain epitaxial layer is formed in the source / drain region of the fin-shaped structure. The sacrificial gate structure is removed after the source / drain epitaxial layer is formed. The dielectric layer is removed after the sacrificial gate structure is removed. A gate structure is formed around the semiconductor layer. In some embodiments, the aforementioned method further comprises: after the fin-shaped structure is formed, an isolation insulating layer is formed around the lower fin-shaped structure. In some embodiments, forming the fin-shaped structure comprises: forming a stack layer on a substrate; and patterning the stack layer and the substrate to form a fin-shaped structure comprising a lower fin-shaped structure and an upper fin-shaped structure. In some embodiments, after removing the sacrificial gate structure, the sidewalls of the channel layer are exposed. In some embodiments, after removing the dielectric layer, the bottom surface of the channel layer is covered by the first protective layer, and the top surface of the channel layer is covered by the second protective layer. In some embodiments, forming the gate structure includes: forming a gate dielectric layer around the semiconductor layer; and forming a gate electrode layer on the gate dielectric layer. In some embodiments, the foregoing method further includes: forming a pair of gate sidewall spacers on opposite sidewalls of the sacrificial gate structure. In some embodiments, after forming the pair of gate sidewall spacers, a source / drain epitaxial layer is formed in the source / drain region of the fin structure, and forming the source / drain epitaxial layer includes: partially removing the dielectric layer to reduce the length of the dielectric layer so that the first end of the dielectric layer is located below the pair of gate sidewall spacers; forming an internal spacer on the first end of the dielectric layer, wherein after forming the internal spacer on the first end of the dielectric layer, the second end of the semiconductor layer protrudes laterally from the internal spacer; and forming a source / drain epitaxial layer to cover the internal spacer and the second end of the semiconductor layer. In some embodiments, the first protective layer includes a first etch resistance layer, and removing the dielectric layer includes an etching process, the etching process has a first etching rate for the first etch resistance layer, a second etching rate for the channel layer, and the first etching rate is less than the second etching rate. In some embodiments, the second protective layer includes an adhesion layer; and a second etch resistance layer, wherein the adhesion layer is located between the second etch resistance layer and the channel layer, and the etching process has a third etching rate for the second etch resistance layer and a fourth etching rate for the adhesion layer, and the third etching rate is less than the second etching rate and the fourth etching rate. In some embodiments, the foregoing method further includes: partially removing the dielectric layer to form a sacrificial gate structure on the upper fin structure, and reducing the width of the dielectric layer.

[0079] According to another aspect of the present disclosure, a method for manufacturing a semiconductor device is provided. A fin-shaped structure is formed, the fin-shaped structure comprising alternatingly stacked sacrificial layers and semiconductor layers, wherein each semiconductor layer comprises a channel layer, a first protective layer, and a second protective layer, and the channel layer is located between the first protective layer and the second protective layer. A first gate structure is formed on the fin-shaped structure. A gate sidewall spacer is formed on the opposite sidewalls of the sacrificial gate structure. A source / drain epitaxial layer is formed on the opposite side of the first gate structure and the gate sidewall spacer. The first gate structure is removed after the source / drain epitaxial layer is formed. The sacrificial layer is removed after the first gate structure is removed. A second gate structure is formed around the semiconductor layer. In some embodiments, forming the source / drain epitaxial layer comprises: partially removing the sacrificial layer to reduce the length of the sacrificial layer so that the first end of the sacrificial layer is located below the gate sidewall spacer; forming an internal spacer on the first end of the sacrificial layer, wherein after the internal spacer is formed on the first end of the sacrificial layer, the second end of the semiconductor layer protrudes laterally from the internal spacer; and forming a source / drain epitaxial layer to cover the internal spacer and the second end of the semiconductor layer. In some embodiments, the inner spacer contacts the first protection layer and the second protection layer. In some embodiments, before removing the first gate structure, the source / drain epitaxial layer is separated from the first gate structure by the inner spacer.

[0080] According to one aspect of the present disclosure, a semiconductor device is provided, which includes a multilayer wire, a gate structure, a gate sidewall spacer, and a source / drain electrode. The multilayer wire is configured on a substrate, wherein each multilayer wire includes a two-dimensional material channel layer, a first protective layer, and a second protective layer, and the two-dimensional material channel layer is located between the first protective layer and the second protective layer. The gate structure is configured on the two-dimensional material channel region of the multilayer wire. The gate sidewall spacer is configured on the opposite sidewall of the gate structure. The source / drain electrode is configured on the opposite side of the gate structure and the gate sidewall spacer. In some embodiments, the semiconductor device further includes an internal spacer, wherein the source / drain electrode is laterally spaced from the gate structure by the internal spacer. In some embodiments, the end of the multilayer wire protrudes laterally from the internal spacer, and the end of the multilayer wire is covered by the source / drain electrode. In some embodiments, the gate structure includes: a gate dielectric layer surrounding the semiconductor layer; and a gate electrode layer configured on the gate dielectric layer, wherein the gate dielectric layer contacts the sidewalls of the first protective layer, the second protective layer, and the two-dimensional material channel layer. In some embodiments, a sidewall of the two-dimensional material channel layer is offset from a sidewall of the first protection layer and a sidewall of the second protection layer.

[0081] The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they may easily use the present disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: forming a fin-shaped structure, the fin-shaped structure comprising a lower fin-shaped structure and an upper fin-shaped structure disposed on the lower fin-shaped structure, the upper fin-shaped structure comprising alternately stacked dielectric layers and multilayer films, wherein each of the multilayer films comprises a channel layer, a first protective layer and a second protective layer, and the channel layer is located between the first protective layer and the second protective layer; forming a sacrificial gate structure on the upper fin structure; After forming the sacrificial gate structure on the upper fin structure, forming a source / drain epitaxial layer on the source / drain region of the fin structure; After forming the source / drain epitaxial layer, removing the sacrificial gate structure; After removing the sacrificial gate structure, removing the dielectric layer; and A gate structure is formed around the multilayer film.

2. The method according to claim 1, characterized in that After removing the dielectric layer, a bottom surface of the channel layer is covered by the first protection layer, and a top surface of the channel layer is covered by the second protection layer.

3. The method according to claim 1, characterized in that Further including: A pair of gate sidewall spacers are formed on opposite sidewalls of the sacrificial gate structure.

4. The method according to claim 3, characterized in that After forming the pair of gate sidewall spacers, forming a source / drain epitaxial layer on the source / drain region of the fin structure, and forming the source / drain epitaxial layer includes: Partially removing the dielectric layer to reduce the length of the dielectric layer so that the first end of the dielectric layer is located below the gate sidewall spacer; forming an inner spacer on the first end of the dielectric layer, wherein after forming the inner spacer on the first end of the dielectric layer, a second end of the multilayer film protrudes laterally from the inner spacer; and A source / drain epitaxial layer is formed to cover the inner spacer and the second end of the multilayer film.

5. The method according to claim 1, characterized in that The first protective layer includes a first etch resistance layer, and removing the dielectric layer includes an etching process, the etching process has a first etching rate for the first etch resistance layer, the etching process has a second etching rate for the channel layer, and the first etching rate is less than the second etching rate.

6. The method according to claim 5, characterized in that The second protective layer comprises: an adhesive layer; and A second resistive layer, wherein the adhesion layer is located between the second resistive layer and the channel layer, the etching process has a third etching rate for the second resistive layer, the etching process has a fourth etching rate for the adhesion layer, and the third etching rate is less than the second etching rate and the fourth etching rate.

7. The method according to claim 1, characterized in that Further including: Before forming the sacrificial gate structure on the upper fin structure, the dielectric layer is partially removed to reduce the width of the dielectric layer.

8. A method for manufacturing a semiconductor device, characterized in that: include: forming a fin-shaped structure, the structure comprising alternately stacked sacrificial layers and multi-layer films, wherein each of the multi-layer films comprises a channel layer, a first protective layer and a second protective layer, and the channel layer is located between the first protective layer and the second protective layer; forming a first gate structure on the fin structure; forming gate sidewall spacers on opposite sidewalls of the first gate structure; forming a source / drain epitaxial layer on the opposite side of the first gate structure and the gate sidewall spacer; After forming the source / drain epitaxial layer, removing the first gate structure; After removing the first gate structure, removing the sacrificial layer; and A second gate structure is formed around the multilayer film.

9. The method according to claim 8, characterized in that Forming the source / drain epitaxial layer includes: Partially removing the sacrificial layer to reduce the length of the sacrificial layer so that the first end of the sacrificial layer is located below the gate sidewall spacer; forming an inner spacer on the first end of the sacrificial layer, wherein after the inner spacer is formed on the first end of the sacrificial layer, the second end of the multilayer film protrudes laterally from the inner spacer; and The source / drain epitaxial layer is formed to cover the inner spacer and the second end of the multilayer film.

10. A semiconductor device, characterized in that: include: A multilayer wire disposed on a substrate, wherein each of the multilayer wires comprises a two-dimensional material channel layer, a first protective layer and a second protective layer, and the two-dimensional material channel layer is located between the first protective layer and the second protective layer; A gate structure is disposed above the channel region of the multilayer wire; A gate sidewall spacer is disposed on an opposite sidewall of the gate structure; as well as The source / drain electrode is disposed on the opposite side of the gate structure and the gate sidewall spacer.

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