Method for improving gate oxide leakage current
By optimizing the ashing process after contact hole etching and using plasma gas to clean the contact hole surface, the gate oxide leakage current problem in the deep submicron process is solved, and the effect of effectively reducing leakage current is achieved, and device performance and reliability are improved.
Patent Information
- Application Number
- CN202510208291.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-25
- Publication Date
- 2025-05-23
AI Technical Summary
In the deep submicron process, the leakage current problem of the gate oxide layer is serious, affecting the performance and reliability of the device. The existing methods have little room for improvement, making it difficult to effectively reduce the leakage current.
By optimizing the ashing process after contact hole etching, the contact hole surface is cleaned using plasma gas to reduce the trap generated by gate oxygen to the plasma bombardment, thereby reducing gate oxygen leakage current.
It effectively reduces the gate oxygen leakage current, improves device performance and reliability, specifically manifested as the minimum improvement of N/P MOS gate oxygen leakage current of more than 7%.
Smart Images
Figure CN120035204A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of semiconductor technology, and in particular to a method for improving gate oxide layer leakage current. Background Art
[0002] When the process enters the deep submicron stage, the gate oxide thickness gradually decreases, the voltage does not decrease proportionally, the electric field strength borne by the gate dielectric continues to increase, and the leakage of the MOS tube becomes more serious, affecting the performance and reliability of the device;
[0003] When the gate oxide thickness is reduced to a certain extent, the gate oxide leakage is as serious as the subthreshold leakage. In future technologies, leakage current may become the main power consumption source of nano CMOS circuits, accounting for about 50% of the total power consumption.
[0004] At the 40nm technology node, leakage current is also a major concern for logic products. Currently, the method of reducing leakage is mostly adopted, such as changing the thickness of gate oxide or pre-cleaning conditions before gate oxide growth. However, there is little room for improvement, and it is urgent to develop new processes to improve gate oxide leakage.
[0005] In order to solve the above problems, a new method for improving gate oxide layer leakage current needs to be proposed. Summary of the invention
[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a method for improving the leakage current of the gate oxide layer, which is used to solve the problem that the prior art mostly adopts changing the thickness of the gate oxide or pre-cleaning conditions before the gate oxide growth to achieve the purpose of reducing leakage, but the improvement space is small.
[0007] To achieve the above-mentioned object and other related objects, the present invention provides a method for improving gate oxide layer leakage current, comprising:
[0008] Step 1, providing a substrate, on which an NMOS device and a PMOS device are formed, forming an interlayer dielectric layer covering the NMOS device and the PMOS device, forming a photoresist layer on the interlayer dielectric layer, photolithographically opening the photoresist layer to define a formation area for a contact hole, etching the interlayer dielectric layer to form contact holes for leading out source and drain regions of the NMOS device and the PMOS device, and removing the photoresist layer;
[0009] Step 2: placing the substrate in a reaction chamber, introducing a reducing gas into the reaction chamber, ionizing the reducing gas into a first plasma, and using the first plasma to process the surface of the contact hole;
[0010] Step three: introducing an oxidizing gas into the reaction chamber, ionizing the oxidizing gas into a second plasma, and using the second plasma to process the surface of the contact hole.
[0011] Preferably, the substrate in step one is a silicon substrate.
[0012] Preferably, the NMOS device and the PMOS device in step one include respective gate structures, the gate structure including a gate oxide layer formed on the substrate and a gate layer located on the gate oxide layer, sidewalls of the gate structure are formed with sidewalls, and source and drain regions are formed on the substrate on both sides of the gate structure by ion implantation.
[0013] Preferably, the material of the interlayer dielectric layer in step 1 is silicon dioxide.
[0014] Preferably, in step one, the photoresist layer is removed by using an ashing process and a wet cleaning method.
[0015] Preferably, the reducing gas in step 2 is N2H2.
[0016] Preferably, in step 2, first, N2H20 with a gas flow rate of 1000-3000sccm is introduced for 5 seconds; then, N2H20 with a gas flow rate of 6000-8000sccm is introduced for 5 seconds; finally, N2H2 with a gas flow rate of 6000-8000sccm is introduced for 100 to 200 seconds.
[0017] Preferably, the oxidizing gas in step three is O2.
[0018] Preferably, step three also includes introducing an inert gas to dilute O2.
[0019] Preferably, in step three, a mixed gas of O2 and N2 is introduced for 10 to 50 seconds.
[0020] As described above, the method for improving gate oxide layer leakage current of the present invention has the following beneficial effects:
[0021] The present invention optimizes the plasma gas for ashing treatment after etching the contact hole to clean the contact hole surface and reduce the trap (collection) of charges generated by plasma bombardment of the gate oxide, thereby achieving the purpose of reducing gate oxide leakage. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Figure 1 Shown is a schematic diagram of the process flow of the present invention;
[0023] Figure 2 It shows a schematic diagram comparing the gate oxide leakage current of the NMOS device of the present invention and the prior art;
[0024] Figure 3 It is a schematic diagram showing a comparison of gate oxide leakage current of a PMOS device of the present invention and the prior art. DETAILED DESCRIPTION
[0025] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0026] See also Figure 1 The present invention provides a method for improving gate oxide layer leakage current, comprising:
[0027] Step 1, providing a substrate, forming an NMOS device and a PMOS device on the substrate, forming an interlayer dielectric layer covering the NMOS device and the PMOS device, forming a photoresist layer on the interlayer dielectric layer, photolithography opening the photoresist layer to define a contact hole formation area, etching the interlayer dielectric layer to form contact holes for leading out source and drain regions of the NMOS device and the PMOS device, and removing the photoresist layer;
[0028] In an embodiment of the present invention, the substrate in step 1 is a silicon substrate.
[0029] In an embodiment of the present invention, the NMOS device and the PMOS device in step one include respective gate structures, the gate structure includes a gate oxide layer formed on a substrate and a gate layer located on the gate oxide layer, sidewalls of the gate structure are formed with sidewalls, and source and drain regions are formed on the substrate on both sides of the gate structure by ion implantation.
[0030] In an embodiment of the present invention, the material of the interlayer dielectric layer in step 1 is silicon dioxide.
[0031] In an embodiment of the present invention, in step 1, the photoresist layer is removed by using an ashing process and a wet cleaning method.
[0032] Step 2: placing the substrate in a reaction chamber, introducing a reducing gas into the reaction chamber, ionizing the reducing gas into a first plasma, and treating the surface of the contact hole with the first plasma. This step can make the surface of the contact hole smoother.
[0033] In an embodiment of the present invention, the reducing gas in step 2 is N2H2.
[0034] In an embodiment of the present invention, in step 2, first, N2H20 with a gas flow rate of 1000-3000sccm is introduced for 5 seconds; then, N2H20 with a gas flow rate of 6000-8000sccm is introduced for 5 seconds; finally, N2H2 with a gas flow rate of 6000-8000sccm is introduced for 100-200 seconds.
[0035] Step three: introducing an oxidizing gas into the reaction chamber, ionizing the oxidizing gas into a second plasma, and using the second plasma to process the surface of the contact hole. This step can oxidize the silicon at the bottom of the contact hole into an oxide layer, thereby increasing the gate oxide thickness.
[0036] In an embodiment of the present invention, the oxidizing gas in step three is O2.
[0037] In an embodiment of the present invention, step three also includes introducing an inert gas to dilute O2.
[0038] In an embodiment of the present invention, in step three, a mixed gas of O2 and N2 is introduced for 10 to 50 seconds.
[0039] By optimizing the plasma gas used in the ashing process after contact hole etching, the surface of the contact hole can be cleaned, and the trapping (collection) of charges generated by plasma bombardment on the gate oxide can be reduced, thereby reducing gate oxide leakage. Figure 2 and Figure 3 The data show that the present invention can improve the N / P MOS gate oxide leakage current by at least 7%.
[0040] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0041] In summary, the present invention optimizes the plasma gas for the ashing treatment after contact hole etching to clean the contact hole surface and reduce the trap (collection) of charges generated by gate oxide bombardment with plasma, thereby achieving the purpose of reducing gate oxide leakage. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.
[0042] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A method for improving gate oxide layer leakage current, characterized in that: At least: Step 1, providing a substrate, on which an NMOS device and a PMOS device are formed, forming an interlayer dielectric layer covering the NMOS device and the PMOS device, forming a photoresist layer on the interlayer dielectric layer, photolithographically opening the photoresist layer to define a formation area for a contact hole, etching the interlayer dielectric layer to form contact holes for leading out source and drain regions of the NMOS device and the PMOS device, and removing the photoresist layer; Step 2: placing the substrate in a reaction chamber, introducing a reducing gas into the reaction chamber, ionizing the reducing gas into a first plasma, and using the first plasma to process the surface of the contact hole; Step three: introducing an oxidizing gas into the reaction chamber, ionizing the oxidizing gas into a second plasma, and using the second plasma to process the surface of the contact hole.
2. The method for improving gate oxide leakage current according to claim 1, characterized in that: The substrate in step one is a silicon substrate.
3. The method for improving gate oxide leakage current according to claim 1, characterized in that: The NMOS device and the PMOS device in step one include respective gate structures, wherein the gate structure includes a gate oxide layer formed on the substrate and a gate layer located on the gate oxide layer, sidewalls of the gate structure are formed with sidewalls, and source and drain regions are formed on the substrate on both sides of the gate structure by ion implantation.
4. The method for improving gate oxide leakage current according to claim 1, characterized in that: The material of the interlayer dielectric layer in step 1 is silicon dioxide.
5. The method for improving gate oxide leakage current according to claim 1, characterized in that: In step one, the photoresist layer is removed by using an ashing process and a wet cleaning method.
6. The method for improving gate oxide layer leakage current according to claim 1, characterized in that: The reducing gas in step 2 is N2H2.
7. The method for improving gate oxide layer leakage current according to claim 6, characterized in that: Step 2: First, introduce N2H20 with a gas flow rate of 1000-3000sccm for 5 seconds; then introduce N2H20 with a gas flow rate of 6000-8000sccm for 5 seconds; finally, introduce N2H2 with a gas flow rate of 6000-8000sccm for 100-200 seconds.
8. The method for improving gate oxide leakage current according to claim 1, characterized in that: The oxidizing gas in step three is O2.
9. The method for improving gate oxide layer leakage current according to claim 8, characterized in that: Step three also includes introducing an inert gas to dilute O2.
10. The method for improving gate oxide layer leakage current according to claim 9, characterized in that: In step 3, a mixed gas of O2 and N2 is introduced for 10 to 50 seconds.