A planar gate MOSFET structure and a method of fabricating the same

Abstract

The application discloses a planar gate MOSFET structure and a preparation method thereof, and belongs to the technical field of planar gate MOSFETs.The planar gate MOSFET structure comprises a cell structure, wherein the cell structure comprises an N-type substrate, an N-type epitaxial layer, two P-well regions, a JFET region formed between the two P-well regions, and a gate oxide layer comprising a first gate oxide region, a second gate oxide region and a third gate oxide region; the first gate oxide region is located between the channel region and the gate structure; the second gate oxide region is located between the N-type region and the gate structure; the third gate oxide region is located between the JFET region and the gate structure; the maximum thickness of the second gate oxide region is greater than the thickness of the first gate oxide region; and the maximum thickness of the third gate oxide region is greater than the thickness of the first gate oxide region.The application optimizes the thickness distribution of the MOSFET gate oxide, guarantees that the gate oxide at the channel has the advantages of low interface state density and high mobility, reduces the gate oxide leakage current, improves the reliability of the gate oxide, reduces the gate oxide capacitance, and improves the switching speed of the MOSFET.

Description

Technical Field

[0001] The present invention belongs to the technical field of planar gate MOSFET, and in particular relates to a planar gate MOSFET structure and a preparation method thereof. Background Art

[0002] Planar gate MOSFET is a power semiconductor device characterized by a gate formed on a plane. It has the advantages of high voltage resistance, high switching speed, small size, and low conduction loss, and is widely used in various working environments.

[0003] The specific on-resistance, gate oxide capacitance and gate leakage of planar gate MOSFET devices are the core indicators for evaluating device performance, affecting the performance and cost of the device.

[0004] Gate oxide capacitance refers to the capacitance between the gate and the channel in a MOSFET. It plays multiple roles in MOSFETs, including controlling on- and off-state conduction, influencing speed and noise, determining threshold voltage, affecting power consumption and reliability, and acting as an insulating dielectric. These roles collectively determine the performance and application range of MOSFETs.

[0005] Gate oxide leakage current refers to the phenomenon that a weak current flows between the gate electrode and the substrate even under normal operating voltage. This leakage current has a significant impact on the performance of MOS devices, as it can lead to problems such as device performance degradation and increased power consumption.

[0006] Currently, in traditional planar gate MOSFETs, in order to reduce the on-resistance, a thin gate oxide method is usually adopted to increase the channel mobility by reducing the gate oxide interface state density.

[0007] However, thin gate oxide will lead to an increase in gate oxide capacitance and gate oxide leakage current, affecting the switching speed and gate reliability of the device.

[0008] Therefore, there is an urgent need to develop a planar gate MOSFET structure and a preparation method thereof to solve the problems in the prior art. Summary of the Invention

[0009] The purpose of the present invention is to provide a planar gate MOSFET structure and a preparation method thereof, which can reduce the gate oxide capacitance and gate oxide leakage current while ensuring the channel mobility, so as to solve the problem of excessive gate oxide capacitance and gate oxide leakage current caused by traditional thin gate oxide proposed in the above background technology.

[0010] In order to solve the above technical problems, the specific technical solutions of the present invention are as follows:

[0011] A planar gate MOSFET structure includes a cellular structure, wherein the cellular structure includes:

[0012] N-type substrate;

[0013] An N-type epitaxial layer, wherein the N-type epitaxial layer is disposed on the substrate;

[0014] P-well regions, wherein two P-well regions are provided, and the two P-well regions are provided on both sides of the top of the N-type epitaxial layer, and the two P-well regions are provided with an N-type region and a P-type region, and a channel region is formed on the top of the two P-well regions; a JFET region is formed between the two P-well regions;

[0015] A gate oxide layer is provided on the upper surface of the N-type epitaxial layer, and a gate structure is provided on the gate oxide layer; the gate oxide layer includes a first gate oxide region, a second gate oxide region and a third gate oxide region, the first gate oxide region is located between the channel region and the gate structure, the second gate oxide region is located between the N-type region and the gate structure, and the third gate oxide region is located between the JFET region and the gate structure, the maximum thickness of the second gate oxide region is greater than the thickness of the first gate oxide region, and the maximum thickness of the third gate oxide region is greater than the thickness of the first gate oxide region.

[0016] Furthermore, the length of the first gate oxide region is greater than the length of the channel region, and the first gate oxide region covers the channel region.

[0017] Furthermore, the thickness of the second gate oxide region is the same as the thickness of the third gate oxide region.

[0018] Furthermore, the thickness of the first gate oxide region is in the range of 30 nm to 60 nm, the thickness of the second gate oxide region is in the range of 60 nm to 200 nm, and the thickness of the third gate oxide region is in the range of 60 nm to 200 nm.

[0019] Furthermore, the thicknesses of the first gate oxide region, the second gate oxide region and the third gate oxide region include a maximum thickness and a minimum thickness; the minimum thickness of the second gate oxide region is greater than or equal to the maximum thickness of the first gate oxide region, and the maximum thickness of the second gate oxide region is greater than the maximum thickness of the first gate oxide region; the minimum thickness of the third gate oxide region is greater than or equal to the maximum thickness of the first gate oxide region, and the maximum thickness of the third gate oxide region is greater than the maximum thickness of the first gate oxide region.

[0020] Furthermore, the thickness of the second gate oxide region is a gradient thickness, and the thickness of the third gate oxide region is also a gradient thickness.

[0021] Furthermore, the cellular structure further comprises:

[0022] a dielectric layer, the dielectric layer being disposed on the upper surfaces of the gate oxide layer and the gate structure;

[0023] an ohmic contact region, the ohmic contact region being arranged on top of the N-type region and the P-type region;

[0024] A metal layer is provided on the ohmic contact region and the dielectric layer to connect the two ohmic contact regions.

[0025] A method for preparing a planar gate MOSFET structure comprises the following steps:

[0026] Providing an N-type epitaxial wafer, and sequentially constructing a P-well region, an N-type region, and a P-type region in the N-type epitaxial wafer;

[0027] Obtaining a first thickness and a second thickness; constructing a first oxide layer on the upper surface of the N-type epitaxial layer according to the first thickness and the second thickness; wherein the thickness of the first oxide layer is the difference between the second thickness and the first thickness;

[0028] Removing the first oxide layer above the channel region; wherein the channel region is located on top of the P-well region;

[0029] constructing a second oxide layer on the upper surface of the channel region and the upper surface of the first oxide layer, wherein the thickness of the second oxide layer is the first thickness;

[0030] Constructing a gate structure, a dielectric layer, an ohmic contact region and a metal layer.

[0031] Furthermore, the construction of the P-well region, the N-type region and the P-type region includes the following steps:

[0032] Al ions are implanted on the top of both sides of the epitaxial layer to form two P-well regions. The doping concentration of the ion implantation in the P-well region is in the range of 1e16 cm -3 ~1e19cm -3 ;

[0033] Al ions are implanted on the top of the two P-well regions to form two P-type regions. The doping concentration range of the P-type region ion implantation is 1e18cm -3 ~1e21cm -3 ;

[0034] N ions are implanted into the two P-well regions and the P-type region to form two N-type regions. The doping concentration range of the N-type region ion implantation is 1e18 cm -3 ~1e21cm -3 .

[0035] Furthermore, the construction of the gate structure, the dielectric layer, the ohmic contact region and the metal layer comprises the following steps:

[0036] constructing a gate structure on the second oxide layer;

[0037] constructing a dielectric layer on the second oxide layer and the gate structure;

[0038] Constructing an ohmic contact region on top of the N-type region and the P-type region;

[0039] A metal layer is constructed on the ohmic contact region and the dielectric layer.

[0040] The present invention has the following advantages:

[0041] By optimizing the gate oxide thickness, on the one hand, a thinner gate oxide structure is provided in the channel region, which can easily form a low interface state density during thermal oxidation or deposition processes compared to a thick gate oxide structure. This ensures that the planar gate MOSFET has a higher channel mobility. On the other hand, a thick gate oxide structure is provided in the JFET region and the N-type region, which can minimize the gate oxide capacitance and gate oxide leakage current of the MOSFET. Assuming that the gate oxide thickness of the JFET region and the N-type region is doubled, the gate oxide capacitance and gate oxide leakage current can be reduced by more than 50%.

[0042] In the above scheme, the gate oxide thickness is optimized. First, in the gate oxide, there is a relationship: gate oxide capacitance , gate oxide electric field .in, is the dielectric constant of the gate oxide, is the thickness of the gate oxide, A voltage is applied to the gate oxide. Because the gate oxide in the JFET and N-type regions is thicker, the gate oxide capacitance in these areas is smaller, and the gate oxide electric field is smaller at the same gate oxide voltage, resulting in lower gate oxide leakage current. In the channel region, a thinner gate oxide structure facilitates a low interface state density process, thereby ensuring higher channel mobility.

[0043] Other features and advantages of the present invention will be disclosed in detail in the following specific embodiments and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 This is a schematic diagram of the overall structure of Example 1;

[0045] Figure 2 This is a schematic diagram of the structure of the P-well region, N-type region and P-type region in Example 1;

[0046] Figure 3 This is a schematic diagram of the structure after the first oxide layer is constructed in Example 1;

[0047] Figure 4 This is a schematic diagram of the structure after the photoresist mask is constructed in Example 1;

[0048] Figure 5 This is a schematic diagram of the structure after etching the first oxide layer in Example 1;

[0049] Figure 6This is a schematic diagram of the structure after the photoresist mask is washed away in Example 1;

[0050] Figure 7 This is a schematic diagram of the structure after the gate oxide layer is constructed in Example 1;

[0051] Figure 8 This is a schematic diagram of the structure after the gate structure is constructed in Example 1;

[0052] Figure 9 Schematic diagram of the structure after the dielectric layer is constructed in Example 1 Figure 1 ;

[0053] Figure 10 Schematic diagram of the structure after the dielectric layer is constructed in Example 1 Figure 2 ;

[0054] Figure 11 This is a schematic diagram of the overall structure of Example 2;

[0055] Figure 12 This is a schematic diagram of the overall structure of Example 3;

[0056] Figure 13 This is a schematic diagram of the overall structure of Example 4.

[0057] Explanation of the marks in the figure: 1. N-type substrate; 2. N-type epitaxial layer; 3. P-well region; 4. N-type region; 5. P-type region; 6. Gate oxide layer; 611. First gate oxide region; 612. Second gate oxide region; 613. Third gate oxide region; 621. First oxide layer; 7. Photoresist mask; 8. Polysilicon gate; 9. Dielectric layer; 10. Ohmic contact region; 11. Metal layer. DETAILED DESCRIPTION

[0058] In order to better understand the purpose, structure and function of the present invention, the present invention is further described in detail below with reference to the accompanying drawings.

[0059] Example 1

[0060] A planar gate MOSFET structure, such as Figure 1 As shown, it includes a cellular structure, and the cellular structure includes:

[0061] N-type substrate 1;

[0062] An N-type epitaxial layer 2 is provided on the substrate;

[0063] Two P-well regions 3 are provided, and the two P-well regions 3 are symmetrically distributed on both sides of the top of the N-type epitaxial layer 2. An N-type region 4 and a P-type region 5 are provided in each of the two P-well regions 3. The N-type region 4 is provided on the top of the P-well region 3, and the P-type region 5 is provided on the side of the P-well region 3 close to the side of the cell structure. A channel region is formed on the top of each of the two P-well regions 3; a JFET region is formed between the two P-well regions 3;

[0064] A gate oxide layer 6 is provided on the upper surface of the N-type epitaxial layer 2, and a gate structure is provided on the gate oxide layer 6;

[0065] The gate oxide layer 6 includes a first gate oxide region, a second gate oxide region and a third gate oxide region. The first gate oxide region is located between the channel region and the gate structure, the second gate oxide region is located between the N-type region 4 and the gate structure, and the third gate oxide region is located between the JFET region and the gate structure. The thickness of the second gate oxide region is greater than that of the first gate oxide region, and the thickness of the third gate oxide region is greater than that of the first gate oxide region.

[0066] In this embodiment, the thickness of the first gate oxide region is the thickness of the gate oxide layer 6 between the channel region and the gate structure, the thickness of the second gate oxide region is the thickness of the gate oxide layer 6 between the N-type region 4 and the gate structure, and the thickness of the third gate oxide region is the thickness of the gate oxide layer 6 between the JFET region and the gate structure.

[0067] In this embodiment, the thickness of the first gate oxide region is in the range of 30 nm to 60 nm, the thickness of the second gate oxide region is in the range of 60 nm to 200 nm, and the thickness of the third gate oxide region is in the range of 60 nm to 200 nm.

[0068] In this embodiment, the thickness of the second gate oxide region is the same as the thickness of the third gate oxide region, so as to facilitate the construction of the cellular structure.

[0069] The length of the first gate oxide region is greater than the length of the channel region, and the first gate oxide region covers the channel region. The difference between the length of the first gate oxide region and the length of the channel region is twice the photolithography etching margin, and the photolithography etching margin is related to the overlay accuracy and the thickness of the second gate oxide region or the third gate oxide region. The thicker the second gate oxide region or the third gate oxide region, the larger the photolithography and etching margin required.

[0070] The cellular structure further includes:

[0071] a dielectric layer 9, the dielectric layer 9 being disposed on the upper surfaces of the gate oxide layer 6 and the gate structure;

[0072] an ohmic contact region 10, the ohmic contact region 10 being disposed on top of the N-type region 4 and the P-type region 5; the ohmic contact regions 10 on top of the N-type region 4 and the P-type region 5 on the same side of the cell structure being connected;

[0073] The metal layer 11 is disposed on the ohmic contact region 10 and the dielectric layer 9 to connect the two ohmic contact regions 10 .

[0074] In this embodiment, the gate structure is a polysilicon gate 8, and the thickness of the polysilicon gate 8 is 200nm-600nm. In this embodiment, two gate structures are provided, and the gate structure is in an inverted "convex" shape.

[0075] The dielectric layer 9 is made of SiO2 and has a thickness of 1 μm to 200 μm. The material of the dielectric layer 9 may be the same as or different from that of the gate oxide layer 6. In this embodiment, the material of the dielectric layer 9 is the same as that of the gate oxide layer 6. The dielectric layer 9 and the gate oxide layer 6 form an integral structure, and the performance of the dielectric layer 9 may be slightly inferior to that of the gate oxide layer 6.

[0076] The material of the ohmic contact region 10 includes Ni, Ti, Ni alloy or Ti alloy.

[0077] A method for preparing a planar gate MOSFET structure, such as Figures 1 to 10 , including the following steps:

[0078] S1: providing an N-type epitaxial wafer, and sequentially constructing a P-well region 3, an N-type region 4, and a P-type region 5 in the N-type epitaxial wafer;

[0079] The N-type epitaxial wafer includes an N-type substrate 1 and an N-type epitaxial layer 2 arranged on one side of the N-type substrate 1 .

[0080] S2: Obtaining a first thickness and a second thickness; constructing a first oxide layer 621 on the upper surface of the N-type epitaxial layer 2 based on the first thickness and the second thickness; wherein the thickness of the first oxide layer 621 is the difference between the second thickness and the first thickness. The first thickness is the thickness of the first gate oxide region, and the second thickness is the thickness of the second and third gate oxide regions.

[0081] S3: removing the first oxide layer 621 above the channel region; wherein the channel region is located at the top of the P-well region 3; the top of the P-well region 3 is used to form a channel and is the channel region.

[0082] S4: A second oxide layer is formed on the upper surface of the channel region and the upper surface of the first oxide layer 621. The thickness of the second oxide layer is the first thickness. The materials of the first oxide layer 621 and the second oxide layer can be the same or different. Preferably, in this embodiment, the first oxide layer 621 and the second oxide layer are made of the same material and are an integral structure.

[0083] S5: constructing a gate structure, a dielectric layer 9, an ohmic contact region 10 and a metal layer 11.

[0084] like Figure 2 As shown, the construction of the P-well region 3, the N-type region 4 and the P-type region 5 in S1 includes the following steps:

[0085] S11: Al ions are implanted on the top of both sides of the epitaxial layer to form two P-well regions 3. The doping concentration of the ion implantation in the P-well region 3 is in the range of 1e16 cm -3 ~1e19cm -3 ;

[0086] S12: Al ions are implanted on the top of the two P-well regions 3 to form two P-type regions 5. The doping concentration of the ion implantation in the P-type region 5 is in the range of 1e18 cm -3 ~1e21cm -3 ;

[0087] S13: N ions are implanted into the two P-well regions 3 and the P-type region 5 to form two N-type regions 4. The doping concentration of the ion implantation in the N-type region 4 is in the range of 1e18 cm -3 ~1e21cm -3 .

[0088] like Figure 3 As shown, in this embodiment, the first oxide layer 621 in S2 can be formed on the surface of the N-type epitaxial wafer by methods such as thermal oxidation or chemical deposition. Forming an oxide layer by methods such as thermal oxidation or chemical deposition is an existing technology and will not be described in detail in this application.

[0089] like Figures 4 to 6 As shown, the removal of the first oxide layer 621 above the channel region in S3 includes the following steps:

[0090] S31: constructing a photoresist mask 7 on the upper surface of the first oxide layer 621;

[0091] S32: etching the first oxide layer 621 above the channel region;

[0092] S33: Wash away the photoresist mask 7 on the upper surface of the first oxide layer 621.

[0093] like Figure 7 As shown, in S4, a second oxide layer is constructed on the upper surface of the channel region and the upper surface of the first oxide layer 621 to form a gate oxide layer 6, which includes the following steps:

[0094] An oxide layer is formed simultaneously on the surface of the channel region and the surface of the first oxide layer 621 by thermal oxidation or chemical deposition.

[0095] Among them, the thermal oxidation or chemical deposition method is existing technology and will not be described in detail in this application.

[0096] like Figures 8 to 10 and Figure 1 As shown, the gate structure, dielectric layer 9, ohmic contact region 10 and metal layer 11 are constructed in S5, including the following steps:

[0097] S51: constructing a gate structure on the second oxide layer;

[0098] S52: constructing a dielectric layer 9 on the second oxide layer and the gate structure;

[0099] S53: constructing an ohmic contact region 10 on top of the N-type region 4 and the P-type region 5;

[0100] S54 : constructing a metal layer 11 on the ohmic contact region 10 and the dielectric layer 9 .

[0101] The gate structure in S51 is a polysilicon gate 8 having a thickness of 200 nm to 600 nm. The gate structure is disposed on the first oxide layer 621 and the second oxide layer. In this embodiment, two gate structures are provided, each of which is in an inverted "convex" shape.

[0102] The dielectric layer 9 in S52 is made of SiO2, and has a thickness of 200 μm to 1 μm. The material of the dielectric layer 9 may be the same as or different from the material of the first oxide layer 621 or the second oxide layer. In this embodiment, the material of the dielectric layer 9 is the same as that of the first oxide layer 621 and the second oxide layer. The dielectric layer 9, the first oxide layer 621, and the second oxide layer form an integral structure, and the material of the dielectric layer 9 is slightly inferior to that of the first oxide layer 621 or the second oxide layer.

[0103] The material of the ohmic contact region 10 in S53 includes Ni, Ti, Ni alloy or Ti alloy.

[0104] This application achieves an optimized distribution of MOSFET gate oxide thickness through a precisely designed MOSFET gate oxide structure. This not only ensures the low interface state density and high mobility of the gate oxide in the channel, but also reduces gate oxide leakage current to a certain extent, improving gate oxide reliability. Furthermore, this structure reduces gate oxide capacitance, thereby increasing MOSFET switching speed.

[0105] Example 2

[0106] like Figure 11 As shown, the difference between this embodiment and the first embodiment is that one cell structure is provided with only one gate structure, and the gate structure is provided above the two N-type regions 4, the two channel regions and one JFET region.

[0107] In this embodiment, the two gate structures are changed into one gate structure, which can simplify the manufacturing process and help reduce the processing difficulty.

[0108] Example 3

[0109] like Figure 12 As shown, the difference between this embodiment and the first embodiment is that the thickness of the second gate oxide region 612 is a gradient thickness, and the thickness of the third gate oxide region 613 is also a gradient thickness.

[0110] The thicknesses of the first gate oxide region 611, the second gate oxide region 612, and the third gate oxide region 613 include a maximum thickness and a minimum thickness. The minimum thickness of the second gate oxide region 612 is greater than or equal to the maximum thickness of the first gate oxide region 611, and the maximum thickness of the second gate oxide region 612 is greater than the maximum thickness of the first gate oxide region 611; the minimum thickness of the third gate oxide region 613 is greater than or equal to the maximum thickness of the first gate oxide region 611, and the maximum thickness of the third gate oxide region 613 is greater than the maximum thickness of the first gate oxide region 611.

[0111] In this embodiment, the gradient thickness of the second gate oxide region 612 means that the side of the second gate oxide region 612 close to the first gate oxide region 611 has the smallest thickness, and the side away from the first gate oxide region 611 has the largest thickness; the thickness of the second gate oxide region 612 gradually increases from the side close to the first gate oxide region 611 to the side away from the first gate oxide region 611. The gradient thickness of the third gate oxide region 613 means that the side of the third gate oxide region 613 close to the first gate oxide region 611 has the smallest thickness, and the side away from the first gate oxide region 611 has the largest thickness; the thickness of the third gate oxide region 613 gradually increases from the side close to the first gate oxide region 611 to the side away from the first gate oxide region 611.

[0112] In this embodiment, the maximum thickness and the minimum thickness of the first gate oxide region 611 are the same.

[0113] Example 4

[0114] like Figure 12 As shown, the difference between this embodiment and the third embodiment is that one cell structure is provided with only one gate structure, and the gate structure is provided above the two N-type regions 4, the two channel regions and one JFET region.

[0115] It will be understood that the present invention is described by way of some embodiments, and it will be appreciated by those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are intended to be protected by the present invention.

[0116] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A planar gate MOSFET structure, characterized in that: Comprising a cellular structure, the cellular structure comprising: N-type substrate; An N-type epitaxial layer, wherein the N-type epitaxial layer is disposed on the substrate; P-well regions, wherein two P-well regions are provided, and the two P-well regions are provided on both sides of the top of the N-type epitaxial layer, and the two P-well regions are provided with an N-type region and a P-type region, and a channel region is formed on the top of the two P-well regions; a JFET region is formed between the two P-well regions; A gate oxide layer is provided on the upper surface of the N-type epitaxial layer, and a gate structure is provided on the gate oxide layer; the gate oxide layer includes a first gate oxide region, a second gate oxide region and a third gate oxide region, the first gate oxide region is located between the channel region and the gate structure, the second gate oxide region is located between the N-type region and the gate structure, and the third gate oxide region is located between the JFET region and the gate structure, the maximum thickness of the second gate oxide region is greater than the thickness of the first gate oxide region, and the maximum thickness of the third gate oxide region is greater than the thickness of the first gate oxide region.

2. The planar gate MOSFET structure according to claim 1, wherein: The length of the first gate oxide region is greater than that of the channel region, and the first gate oxide region covers the channel region.

3. The planar gate MOSFET structure according to claim 2, wherein: The thickness of the second gate oxide region is the same as that of the third gate oxide region.

4. The planar gate MOSFET structure according to claim 3, wherein: The thickness of the first gate oxide region is in the range of 30 nm to 60 nm, the thickness of the second gate oxide region is in the range of 60 nm to 200 nm, and the thickness of the third gate oxide region is in the range of 60 nm to 200 nm.

5. The planar gate MOSFET structure according to any one of claims 1 to 4, wherein: The thicknesses of the first gate oxide region, the second gate oxide region and the third gate oxide region include a maximum thickness and a minimum thickness; the minimum thickness of the second gate oxide region is greater than or equal to the maximum thickness of the first gate oxide region, and the maximum thickness of the second gate oxide region is greater than the maximum thickness of the first gate oxide region; the minimum thickness of the third gate oxide region is greater than or equal to the maximum thickness of the first gate oxide region, and the maximum thickness of the third gate oxide region is greater than the maximum thickness of the first gate oxide region.

6. The planar gate MOSFET structure according to claim 5, wherein: The thickness of the second gate oxide region is a gradient thickness, and the thickness of the third gate oxide region is also a gradient thickness.

7. The planar gate MOSFET structure according to claim 5, wherein: The cellular structure further includes: a dielectric layer, the dielectric layer being disposed on the upper surfaces of the gate oxide layer and the gate structure; an ohmic contact region, the ohmic contact region being arranged on top of the N-type region and the P-type region; A metal layer is provided on the ohmic contact region and the dielectric layer to connect the two ohmic contact regions.

8. A method for preparing a planar gate MOSFET structure, characterized in that: The method for preparing the planar gate MOSFET structure according to any one of claims 1 to 7 comprises the following steps: Providing an N-type epitaxial wafer, and sequentially constructing a P-well region, an N-type region, and a P-type region in the N-type epitaxial wafer; Obtaining a first thickness and a second thickness; constructing a first oxide layer on the upper surface of the N-type epitaxial layer according to the first thickness and the second thickness; wherein the first thickness is the thickness of the first gate oxide region, the second thickness is the thickness of the second gate oxide region and the third gate oxide region; and the thickness of the first oxide layer is the difference between the second thickness and the first thickness; Removing the first oxide layer above the channel region; wherein the channel region is located on top of the P-well region; constructing a second oxide layer on the upper surface of the channel region and the upper surface of the first oxide layer, wherein the thickness of the second oxide layer is the first thickness; Constructing a gate structure, a dielectric layer, an ohmic contact region and a metal layer.

9. The method for preparing a planar gate MOSFET structure according to claim 8, wherein: The construction of the P-well region, the N-type region and the P-type region comprises the following steps: Al ions are implanted on the top of both sides of the epitaxial layer to form two P-well regions. The doping concentration of the ion implantation in the P-well region is in the range of 1e16 cm -3 ~1e19cm -3 ; Al ions are implanted on the top of the two P-well regions to form two P-type regions. The doping concentration range of the P-type region ion implantation is 1e18cm -3 ~1e21cm -3 ; N ions are implanted into the two P-well regions and the P-type region to form two N-type regions. The doping concentration range of the N-type region ion implantation is 1e18 cm -3 ~1e21cm -3 .

10. The method for preparing a planar gate MOSFET structure according to claim 8, wherein: The construction of the gate structure, the dielectric layer, the ohmic contact region and the metal layer comprises the following steps: constructing a gate structure on the second oxide layer; constructing a dielectric layer on the second oxide layer and the gate structure; Constructing an ohmic contact region on top of the N-type region and the P-type region; A metal layer is constructed on the ohmic contact region and the dielectric layer.

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