A thyristor integrated chip with high dv / dt and its manufacturing method

Abstract

The present invention discloses a thyristor integrated chip with high dv / dt and a preparation method thereof, including an N-type substrate. On the upper surface of the N-type substrate, there are a first P-type diffusion region, a second P-type diffusion region, and a third P-type diffusion region. At the upper and lower ends of the third P-type diffusion region, there are a first P-type diffusion region and a second P-type diffusion region. On one side of the upper surface of the second P-type diffusion region close to the first P-type diffusion region, there is a first N+-type diffusion region. On the upper surface of the first P-type diffusion region, there is a second N+-type diffusion region. At one end of the upper surface of the second P-type diffusion region, there are two third N+-type diffusion regions; the present invention can withstand voltage spikes caused by high-frequency switching in the industrial field, prevent mis-triggering, reduce the need for an external protection circuit, reduce circuit design costs, and reduce circuit power consumption; the design of the optically triggered thyristor can electrically isolate the input side and the output side, improving the anti-interference ability.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and particularly to a thyristor integrated chip with a high dv / dt and a manufacturing method thereof. Background Art

[0002] Due to the limitations of its own performance, the application of general thyristor discrete devices in the industrial field has become difficult. The voltage spikes caused by high-frequency switching can easily lead to mis-triggering of the thyristor. It is necessary to increase the peripheral RC absorption circuit to improve the dv / dt tolerance of the thyristor. This not only increases the circuit design cost but also increases the energy consumption. In order to ensure accurate triggering of the thyristor, the design of the drive circuit is also relatively complex. At the same time, in order to improve the anti-interference ability of the system, it is necessary to increase the isolation circuit design. Summary of the Invention

[0003] The purpose of the present invention is to provide a thyristor integrated chip with a high dv / dt and a manufacturing method thereof, so as to solve the problems raised in the above background art.

[0004] To achieve the above purpose, the present invention provides the following technical solution: A thyristor integrated chip with a high dv / dt, including an N-type substrate. On the upper surface of the N-type substrate, there are a first P-type diffusion region, a second P-type diffusion region, and a third P-type diffusion region. At the upper and lower ends of the third P-type diffusion region, there are a first P-type diffusion region and a second P-type diffusion region. On the upper surface of the second P-type diffusion region, close to one side of the first P-type diffusion region, there is a first N+ type diffusion region. On the upper surface of the first P-type diffusion region, there is a second N+ type diffusion region. At one end of the upper surface of the second P-type diffusion region, there are two third N+ type diffusion regions, and the two third N+ type diffusion regions are connected by an N-type depletion region.

[0005] Preferably, the first P-type diffusion region is arranged at one end of the upper surface of the N-type substrate, the second P-type diffusion region and the third P-type diffusion region are arranged at the other end of the upper surface of the N-type substrate, and the second P-type diffusion region and the third P-type diffusion region are connected by a P-type diffusion resistor.

[0006] Preferably, on the upper surface of the first P-type diffusion region, there is a first POLY, on the upper surface of the second P-type diffusion region, there is a second POLY, and on the upper surface of the N-type substrate, there is a third POLY between the first P-type diffusion region and the second P-type diffusion region.

[0007] Preferably, a thyristor anode lead window is provided on the upper surface of the first P-type diffusion region, a thyristor cathode lead window is provided on the upper surface of the first N+-type diffusion region, and a plurality of lead windows are provided on one side of the second P-type diffusion region close to the third P-type diffusion region and on the upper surface of the third P-type diffusion region; an anode electrode is provided on the upper surface of the first P-type diffusion region, and a cathode electrode, a first metal, and a second metal are provided on the upper surfaces of the second P-type diffusion region and the third P-type diffusion region.

[0008] Preferably, a ring of N+-type cutoff rings is provided around the first P-type diffusion region, the second P-type diffusion region, and the third P-type diffusion region; a passivation layer, silicon nitride, and TEOS are provided on the surface of the N-type substrate; and a gate oxide is provided in the first P-type diffusion region.

[0009] The present invention also provides a method for manufacturing a thyristor integrated chip with a high dv / dt, and the manufacturing method specifically includes the following steps:

[0010] S1. Select an N-type silicon wafer with a resistivity of 60 - 80 Ω·cm, a thickness of 275 - 285 μm, and a <100> crystal orientation;

[0011] S2. Perform a first oxidation;

[0012] S3. Etch the active region oxide layer;

[0013] S4. Photolithograph the first POLY, the second POLY, the third POLY, the silicon nitride, the first N+-type diffusion region, the second N+-type diffusion region, the third N+-type diffusion region, and the TEOS;

[0014] S5. Reverse etch the anode electrode, the cathode electrode, the first metal, and the second metal.

[0015] Preferably, the step S2 specifically includes the following steps:

[0016] a1. Grow a thermal oxide layer with a thickness of 1.2 μm;

[0017] a2. Open the windows of the first P-type diffusion region, the second P-type diffusion region, and the third P-type diffusion region, and etch the oxide layer in the windows;

[0018] a3. Inject boron with a dose of 6.5e14 - 8e14 / cm 2 , an injection energy of 30 - 50 keV, and an injection angle of 7°;

[0019] a4. Open the windows of the first P-type diffusion region, the second P-type diffusion region, and the P-type diffusion resistor, and etch the oxide layer in the windows;

[0020] a5. Boron implantation dose: 1.2e13 - 2.5e13 / cm 2 , implantation energy: 30 - 50 keV, implantation angle: 7°;

[0021] a6. The junction depth of the first P-type diffusion region, the second P-type diffusion region, and the third P-type diffusion region is 4 - 5 μm, and the junction depth of the first P-type diffusion region, the second P-type diffusion region, and the P-type diffusion resistor is 2.5 - 3 μm;

[0022] a7. Etch the oxide layer within the windows of the first P-type diffusion region, the second P-type diffusion region, the third P-type diffusion region, the first P-type diffusion region, the second P-type diffusion region, and the P-type diffusion resistor.

[0023] Preferably, step S3 specifically includes the following steps:

[0024] b1. Generate a gate oxide layer with a thickness of 280 Å.

[0025] b2. Open the window of the N-type depletion region.

[0026] b3. Arsenic implantation dose: 3.5e12 - 4e12 / cm2, implantation energy: 100 - 120 keV, implantation angle: 7°;

[0027] b4. Etch the oxide layer within the active region completely.

[0028] Preferably, step S4 specifically includes the following steps:

[0029] c1. Generate an oxide layer with a thickness of 400 Å.

[0030] c2. Deposit phosphorus-doped first POLY, second POLY, and third POLY with a thickness of 5000 Å for each.

[0031] c3. Open the windows outside the first POLY, second POLY, and third POLY regions and etch the POLY within the windows.

[0032] c4. Open the windows of the first N+-type diffusion region, the second N+-type diffusion region, the third N+-type diffusion region, and the N+-type cutoff ring.

[0033] c5. Phosphorus implantation dose: 6e15 / cm2, implantation energy: 60 - 80 keV, implantation angle: 7°;

[0034] c6. Deposit a TEOS thin film with a thickness of 1150 Å.

[0035] c7. Deposit BPSG with a thickness of 11150 Å, and perform high-temperature reflow after deposition;

[0036] c8. Deposit the silicon nitride with a thickness of 900 Å;

[0037] c9. Deposit the TEOS with a thickness greater than 40000 Å;

[0038] c10. Etch the TEOS and the silicon nitride to form a beveled terminal.

[0039] Preferably, the step S5 specifically includes the following steps:

[0040] d1. Open the thyristor anode lead window, the thyristor cathode lead window, and the lead window;

[0041] d2. Deposit metallic aluminum with a thickness greater than 3 μm;

[0042] d3. Etch away the metallic aluminum outside the anode electrode, the cathode electrode, the first metal, and the second metal regions.

[0043] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0044] 1. For the thyristor integrated chip with high dv / dt and its manufacturing method of the present invention, the dv / dt can reach 12000 V / μs at room temperature and can also reach 6000 V / μs at high temperature (85 °C). It can withstand the voltage spikes caused by high-frequency switching in the industrial field, prevent mis-triggering, reduce the need for external protection circuits, reduce circuit design costs, and lower circuit power consumption. The design of the optically triggered thyristor can electrically isolate the input side from the output side and improve the anti-interference ability.

[0045] 2. For the thyristor integrated chip with high dv / dt and its manufacturing method of the present invention, through the structural design of the metal field plate and the beveled thick-oxide terminal, a breakdown voltage of 800 V is achieved in the case of a shallow junction, without the need for the structural design of multiple floating field rings, reducing the waste of chip area; nor is a deep-junction structure like that of a planar thyristor required, which can significantly reduce the diffusion and push-junction time during manufacturing and improve production efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 It is a specific schematic diagram of the overall structure of the present invention;

[0047] Figure 2 It is a cross-sectional view taken at A of the present invention;

[0048] Figure 3 It is a cross-sectional view taken at B of the present invention;

[0049] Figure 4 is the equivalent circuit diagram of the present invention;

[0050] In the figure: 110, N-type substrate; 111, N+-type cutoff ring; 121, first P-type diffusion region; 122, second P-type diffusion region; 123, third P-type diffusion region; 124, P-type diffusion resistor; 131, first P-type diffusion region; 132, second P-type diffusion region; 141, first N+-type diffusion region; 142, second N+-type diffusion region; 143, third N+-type diffusion region; 150, N-type depletion region; 161, first POLY; 162, second POLY; 163, third POLY; 171, thyristor anode lead window; 172, thyristor cathode lead window; 173, lead window; 181, anode electrode; 182, cathode electrode; 183, first metal; 184, second metal; 191, passivation layer; 192, silicon nitride; 193, TEOS; 194, gate oxide. Detailed implementation manners

[0051] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0052] In the description of the present invention, it should be understood that the orientation or positional relationships indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. are based on the orientation or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present invention.

[0053] In the description of this patent, it should be noted that unless otherwise clearly defined and limited, the terms "installation", "connection", and "setting" should be understood in a broad sense. For example, it can be fixedly connected and set, or detachably connected and set, or integrally connected and set. For those of ordinary skill in the art, the specific meanings of the above terms in this patent can be understood according to specific circumstances.

[0054] In addition, the terms "first" and "second" are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a number of" means two or more unless otherwise specifically defined.

[0055] Embodiment

[0056] Please refer to Figures 1-4 As shown, a thyristor integrated chip technical solution with a high dv / dt provided by the present invention: includes an N-type substrate 110, on the upper surface of the N-type substrate 110, there are a first P-type diffusion region 121, a second P-type diffusion region 122, and a third P-type diffusion region 123. The first P-type diffusion region 121 is disposed at one end of the upper surface of the N-type substrate 110, and the second P-type diffusion region 122 and the third P-type diffusion region 123 are disposed at the other end of the upper surface of the N-type substrate 110. The second P-type diffusion region 122 and the third P-type diffusion region 123 are connected by a P-type diffusion resistor 124. A ring of N+-type cutoff rings 111 is disposed around the first P-type diffusion region 121, the second P-type diffusion region 122, and the third P-type diffusion region 123. At the upper and lower ends of the third P-type diffusion region 123, there are a first P-type diffusion region 131 and a second P-type diffusion region 132. A gate oxide 194 is disposed on the first P-type diffusion region 131. On the side of the upper surface of the second P-type diffusion region 122 close to the first P-type diffusion region 121, a first N+-type diffusion region 141 is disposed. On the upper surface of the first P-type diffusion region 131, a second N+-type diffusion region 142 is disposed. At one end of the upper surface of the second P-type diffusion region 132, there are two third N+-type diffusion regions 143, and the two third N+-type diffusion regions 143 are connected by an N-type depletion region 150.

[0057] Furthermore, a first POLY 161 is disposed on the upper surface of the first P-type diffusion region 131, a second POLY 162 is disposed on the upper surface of the second P-type diffusion region 132, and a third POLY 163 is disposed between the first P-type diffusion region 131 and the second P-type diffusion region 132 on the upper surface of the N-type substrate 110.

[0058] Furthermore, a thyristor anode lead window 171 is disposed on the upper surface of the first P-type diffusion region 121, a thyristor cathode lead window 172 is disposed on the upper surface of the first N+-type diffusion region 141, and a number of lead windows 173 are disposed on the side of the second P-type diffusion region 122 close to the third P-type diffusion region 123 and on the upper surface of the third P-type diffusion region 123. An anode electrode 181 is disposed on the upper surface of the first P-type diffusion region 121, and a cathode electrode 182, a first metal 183, and a second metal 184 are disposed on the upper surfaces of the second P-type diffusion region 122 and the third P-type diffusion region 123.

[0059] Further, a passivation layer 191, silicon nitride 192, and TEOS 193 are disposed on the surface of the N-type substrate 110.

[0060] Further, the thyristor is composed of a four-layer structure including a first P-type diffusion region 121, an N-type substrate 110, a second P-type diffusion region 122, and a first N+-type diffusion region 141. The enhancement-mode NMOS transistor uses the first P-type diffusion region 131 as the p-well, the second N+-type diffusion region 142 as the source and drain, and the first POLY 161 as the gate; the depletion-mode NMOS transistor uses the second P-type diffusion region 132 as the P-well, the third N+-type diffusion region 143 as the source and drain, the second POLY 162 as the gate, and the N-type depletion region 150 as the conductive channel; the capacitor is a planar capacitor composed of the N-type substrate 110, gate oxide 194, and the third POLY 163.

[0061] Further, as Figure 4 can be shown, the thyristor is equivalently replaced by PNP (Q1) and NPN (Q2) triodes with the base and collector connected to each other. The principle of achieving high dv / dt is as follows: When the voltage between AK rises rapidly, such as in the case of a voltage spike, the positive potential of capacitor C will be instantaneously pulled up at this time. Since the voltage across the capacitor cannot change abruptly, the negative potential of capacitor C, that is, the gate potential of M1, is also pulled up. When the gate voltage Vgs of M1 is greater than the threshold voltage Vth, M1 conducts, pulling the base of triode Q2, that is, the gate of the thyristor, to the ground potential, blocking the triggering path of the thyristor. The gate and source of M2 are short-circuited, Vgs is equal to 0, and M2 is always in the conducting state; therefore, after the voltage spike, capacitor C discharges through the conducting path of depletion transistor M2, and the gate voltage of M1 gradually drops back to 0. At this time, Vgs is less than Vth, and M1 returns from the conducting state to the cut-off state, and the circuit returns to the normal working state, and the thyristor can be normally triggered; when the voltage between AK is stable, light is applied to the base of Q2 to generate a photocurrent. When this current is greater than the triggering current of the thyristor, the thyristor will conduct; in the steady state, the low-resistance conducting state of M2 makes it impossible for capacitor C to accumulate charge, and the gate of M1 is always pulled to the ground potential, and M1 is in the cut-off state, avoiding mis-triggering of the protection mechanism and causing the thyristor to fail to conduct normally.

[0062] The present invention provides a method for manufacturing a thyristor integrated chip with high dv / dt. The manufacturing method specifically includes the following steps:

[0063] S1. Select an N-type silicon wafer with a resistivity of 60 - 80 Ω·cm, a thickness of 275 - 285 μm, and a <100> crystal orientation;

[0064] S2. Perform a first oxidation;

[0065] a1. Grow a thermal oxide layer with a thickness of 1.2 μm.

[0066] a2. Open the windows of the first P-type diffusion region 121, the second P-type diffusion region 122, and the third P-type diffusion region 123, and etch the oxide layer within the windows.

[0067] a3. Inject boron with a dose of 6.5e14 - 8e14 / cm 2 , an injection energy of 30 - 50 keV, and an injection angle of 7°.

[0068] a4. Open the windows of the first P-type diffusion region 131, the second P-type diffusion region 132, and the P-type diffusion resistor 124, and etch the oxide layer within the windows.

[0069] a5. Inject boron with a dose of 1.2e13 - 2.5e13 / cm 2 , an injection energy of 30 - 50 keV, and an injection angle of 7°.

[0070] a6. The junction depth of the first P-type diffusion region 121, the second P-type diffusion region 122, and the third P-type diffusion region 123 is 4 - 5 μm, and the junction depth of the first P-type diffusion region 131, the second P-type diffusion region 132, and the P-type diffusion resistor 124 is 2.5 - 3 μm.

[0071] a7. Etch the oxide layer within the windows of the first P-type diffusion region 121, the second P-type diffusion region 122, the third P-type diffusion region 123, the first P-type diffusion region 131, the second P-type diffusion region 132, and the P-type diffusion resistor 124.

[0072] S3. Etch the oxide layer of the active region.

[0073] b1. Generate a gate oxide 194 layer with a film thickness of 280 Å.

[0074] b2. Open the window of the N-type depletion region 150.

[0075] b3. Inject arsenic with a dose of 3.5e12 - 4e12 / cm2, an injection energy of 100 - 120 keV, and an injection angle of 7°.

[0076] b4. Etch the oxide layer within the active region completely.

[0077] S4. Photolithograph the first POLY161, the second POLY162, the third POLY163, the silicon nitride 192, the first N+-type diffusion region 141, the second N+-type diffusion region 142, the third N+-type diffusion region 143, and the TEOS193.

[0078] c1. Generate an oxide layer with a thickness of 400 Å.

[0079] c2. Deposit phosphorus-doped first POLY161, second POLY162, and third POLY163, with the thickness of the first POLY161, second POLY162, and third POLY163 being 5000 Å;

[0080] c3. Open the windows outside the areas of the first POLY161, second POLY162, and third POLY163, and etch the POLY within the windows;

[0081] c4. Open the windows of the first N+-type diffusion region 141, second N+-type diffusion region 142, third N+-type diffusion region 143, and N+-type cutoff ring 111;

[0082] c5. Inject phosphorus with a dose of 6e15 / cm2, an injection energy of 60 - 80 keV, and an injection angle of 7°;

[0083] c6. Deposit a TEOS film with a thickness of 1150 Å;

[0084] c7. Deposit BPSG with a thickness of 11150 Å, and perform high-temperature reflow after deposition;

[0085] c8. Deposit a silicon nitride 192 film with a thickness of 900 Å;

[0086] c9. Deposit TEOS193 with a thickness greater than 40000 Å;

[0087] c10. Etch TEOS193 and silicon nitride 192 to form a beveled terminal;

[0088] S5. Etch the anode electrode 181, cathode electrode 182, first metal 183, and second metal 184;

[0089] d1. Open the thyristor anode lead window 171, thyristor cathode lead window 172, and lead window 173;

[0090] d2. Deposit aluminum metal with a thickness greater than 3 μm;

[0091] d3. Etch away the aluminum metal outside the areas of the anode electrode 181, cathode electrode 182, first metal 183, and second metal 184.

[0092] The foregoing has shown and described the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited by the above embodiments, and the above embodiments and the descriptions in the specification are only preferred examples of the present invention, and are not used to limit the present invention. Without departing from the spirit and scope of the present invention, the present invention will have various changes and improvements, and these changes and improvements fall within the scope of the present invention claimed. The scope of the present invention claimed is defined by the appended claims and their equivalents.

Claims

1. A high dv / dt thyristor integrated chip, comprising an N-type substrate (110), characterized in that: The upper surface of the N-type substrate (110) is provided with a first P-type diffusion region (121), a second P-type diffusion region (122) and a third P-type diffusion region (123); the upper and lower ends of the third P-type diffusion region (123) are provided with a first P-type diffusion region (131) and a second P-type diffusion region (132); a first N+ type diffusion region (141) is provided on the upper surface of the second P-type diffusion region (122) on a side close to the first P-type diffusion region (121); a second N+ type diffusion region (142) is provided on the upper surface of the first P-type diffusion region (131); two third N+ type diffusion regions (143) are provided on one end of the upper surface of the second P-type diffusion region (132); and the two third N+ type diffusion regions (143) are connected by providing an N-type depletion region (150).

2. The high dv / dt thyristor integrated chip according to claim 1, characterized in that: The first P-type diffusion region (121) is arranged at one end of the upper surface of the N-type substrate (110), the second P-type diffusion region (122) and the third P-type diffusion region (123) are arranged at the other end of the upper surface of the N-type substrate (110), and the second P-type diffusion region (122) and the third P-type diffusion region (123) are connected by arranging a P-type diffusion resistor (124).

3. The high dv / dt thyristor integrated chip according to claim 1, characterized in that: A first POLY (161) is arranged on the upper surface of the first P-type diffusion region (131), a second POLY (162) is arranged on the upper surface of the second P-type diffusion region (132), and a third POLY (163) is arranged between the first P-type diffusion region (131) and the second P-type diffusion region (132) on the upper surface of the N-type substrate (110).

4. The high dv / dt thyristor integrated chip according to claim 1, characterized in that: A thyristor anode lead window (171) is provided on the upper surface of the first P-type diffusion region (121), a thyristor cathode lead window (172) is provided on the upper surface of the first N+ type diffusion region (141), and a plurality of lead windows (173) are provided on one side of the second P-type diffusion region (122) close to the third P-type diffusion region (123) and on the upper surface of the third P-type diffusion region (123); an anode electrode (181) is provided on the upper surface of the first P-type diffusion region (121), and a cathode electrode (182), a first metal (183) and a second metal (184) are provided on the upper surfaces of the second P-type diffusion region (122) and the third P-type diffusion region (123).

5. The high dv / dt thyristor integrated chip according to claim 1, characterized in that: An N+ type cut-off ring (111) is arranged around the first P-type diffusion region (121), the second P-type diffusion region (122) and the third P-type diffusion region (123); a passivation layer (191), silicon nitride (192) and TEOS (193) are arranged on the surface of the N-type substrate (110); and a gate oxide (194) is arranged on the first P-type diffusion region (131).

6. A method for preparing a high dv / dt thyristor integrated chip according to any one of claims 1 to 5, characterized in that: The preparation method specifically comprises the following steps: S1, select resistivity 60-80Ω·cm, thickness 275~285μm and <100> N-type silicon wafer with different crystal orientations; S2, perform an oxidation; S3, etching the oxide layer in the active area; S4, photolithography of the first POLY (161), the second POLY (162), the third POLY (163), the silicon nitride (192), the first N+ type diffusion region (141), the second N+ type diffusion region (142), the third N+ type diffusion region (143), and the TEOS (193); S5. Reverse-etching the anode electrode (181), the cathode electrode (182), the first metal (183), and the second metal (184).

7. The method for preparing a high dv / dt thyristor integrated chip according to any one of claim 6, characterized in that: The step S2 specifically includes the following steps: a1. Grow a thermal oxide layer with a thickness of 1.2 μm; a2, opening windows of the first P-type diffusion region (121), the second P-type diffusion region (122) and the third P-type diffusion region (123), and etching the oxide layers in the windows; a3. Boron injection dose 6.5e14~8e14 / cm 2 , injection energy 30~50 keV, injection angle 7°; a4, opening the windows of the first P-type diffusion region (131), the second P-type diffusion region (132), and the P-type diffusion resistor (124), and etching the oxide layer in the windows; a5. Boron injection dose 1.2e13~2.5e13 / cm 2 , injection energy 30~50 keV, injection angle 7°; a6, the junction depth of the first P-type diffusion region (121), the second P-type diffusion region (122) and the third P-type diffusion region (123) is 4-5 μm, and the junction depth of the first P-type diffusion region (131), the second P-type diffusion region (132) and the P-type diffusion resistor (124) is 2.5-3 μm; a7. Etching the oxide layer in the windows of the first P-type diffusion region (121), the second P-type diffusion region (122), the third P-type diffusion region (123), the first P-type diffusion region (131), the second P-type diffusion region (132) and the P-type diffusion resistor (124).

8. The method for preparing a high dv / dt thyristor integrated chip according to any one of claim 6, characterized in that: The step S3 specifically comprises the following steps: b1. Generate a gate oxide (194) oxide layer with a thickness of 280A; b2. Opening the N-type depletion region (150) window; b3, the arsenic injection dose is 3.5e12~4e12 / cm2, the injection energy is 100~120 keV, and the injection angle is 7°; b4. Etch the oxide layer in the active area cleanly.

9. The method for preparing a high dv / dt thyristor integrated chip according to any one of claim 6, characterized in that: The step S4 specifically comprises the following steps: c1. Generate an oxide layer with a thickness of 400A; c2. Depositing the first POLY (161), the second POLY (162) and the third POLY (163) doped with phosphorus, wherein the thickness of the first POLY (161), the second POLY (162) and the third POLY (163) is 5000A; c3, opening windows outside the regions of the first POLY (161), the second POLY (162) and the third POLY (163), and etching the POLY within the windows; c4, opening the windows of the first N+ type diffusion region (141), the second N+ type diffusion region (142), the third N+ type diffusion region (143) and the N+ type cut-off ring (111); c5, implantation dose 6e15 / cm2, implantation energy 60~80keV, implantation angle 7°; c6. Depositing a TEOS film with a thickness of 1150A; c7, deposit BPSG, BPSG thickness 11150A, and perform high temperature reflow after deposition; c8, depositing the silicon nitride (192), wherein the thickness of the silicon nitride (192) is 900 Å; c9, depositing the TEOS (193), wherein the thickness of the TEOS (193) is greater than 40000 Å; c10. Etching the TEOS (193) and the silicon nitride (192) to form an angled terminal.

10. The method for preparing a high dv / dt thyristor integrated chip according to any one of claim 6, characterized in that: The step S5 specifically comprises the following steps: d1. Opening the thyristor anode lead window (171), the thyristor cathode lead window (172), and the lead window (173); d2. Deposit metal aluminum, the thickness of which is greater than 3 μm; d3. Etch away the metal aluminum outside the regions of the anode electrode (181), the cathode electrode (182), the first metal (183) and the second metal (184).

Images