Integrated circuit device

Abstract

An integrated circuit device includes: a substrate including a back surface; a fin-type active region, the fin-type active region protruding from the substrate to define a trench region on the substrate; the device isolation layer covers the side wall of each fin type active region in the groove region, and the device isolation layer covers the side wall of each fin type active region in the groove region; a via power rail extending vertically through the device isolation layer between the fin-type active regions; and a backside power rail extending vertically through the substrate and connected to one end of the via power rail, where the via power rail includes a first portion connected to the backside power rail and a second portion on the first portion, and wherein the two sidewalls of the first portion each include a sloped surface that is sloped so as to be closer to the pair of fin-type active regions as the two sidewalls approach the backside power rail.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to an integrated circuit device, and in particular to an integrated circuit device including a power rail. Background Art

[0002] As electronic devices require miniaturization, multi-functions and high performance, integrated circuit devices are required to have high capacity and high integration. Therefore, it is necessary to effectively design wiring structures to achieve high integration while increasing the functions and operating speed required by integrated circuit devices. Summary of the invention

[0003] According to an embodiment of the present disclosure, an integrated circuit device having improved electrical characteristics and reliability is provided.

[0004] Various aspects achieved by the embodiments of the present disclosure are not limited to the above-mentioned purposes, and other purposes can be clearly understood by those skilled in the art from the following description.

[0005] According to an embodiment of the present disclosure, an integrated circuit device is provided, and the integrated circuit device includes: a substrate, the substrate including a back side; a pair of fin-type active regions, the pair of fin-type active regions protruding from the substrate on a side of the substrate opposite to the back side to define a trench region on the substrate; a device isolation layer, the device isolation layer covering the sidewall of each of the pair of fin-type active regions in the trench region; a through-hole power rail, the through-hole power rail vertically extending through the device isolation layer between the pair of fin-type active regions; and a back side power rail, the back side power rail vertically extending from the back side of the substrate through the substrate and connected to one end of the through-hole power rail, wherein the through-hole power rail includes a first portion connected to the back side power rail and a second portion located on the first portion, and wherein two sidewalls of the first portion that are opposite to each other and respectively face the pair of fin-type active regions each include an inclined surface, the inclined surface being inclined so as to be closer to the pair of fin-type active regions as the two sidewalls approach the back side power rail.

[0006] According to an embodiment of the present disclosure, an integrated circuit device is provided, and the integrated circuit device includes: a substrate including a back side; a substrate, the substrate including a back side; a pair of fin-type active regions, the pair of fin-type active regions protruding from the substrate so as to define a groove region on the substrate on a side of the substrate opposite to the back side; a pair of source / drain regions, the pair of source / drain regions being respectively located above the pair of fin-type active regions; a device isolation layer, the device isolation layer covering each of the pair of fin-type active regions in the groove region a through-hole power rail, the through-hole power rail being located between the pair of fin-type active regions and between the pair of source / drain regions and vertically extending through the device isolation layer; and a back-side power rail, the back-side power rail vertically extending from the back side of the substrate through the substrate and connected to one end of the through-hole power rail, wherein the through-hole power rail includes a first portion connected to the back-side power rail and a second portion located on the first portion, and wherein two sidewalls of the first portion respectively face the pair of fin-type active regions and are curved surfaces.

[0007] According to an embodiment of the present disclosure, an integrated circuit device is provided, and the integrated circuit device includes: a substrate, the substrate including a back side; a fin-type active area, the fin-type active area protruding from the substrate on a side of the substrate opposite to the back side so as to define a portion of a trench area on the substrate, the fin-type active area extending in a first horizontal direction; at least one nanosheet, the at least one nanosheet being located on the fin-type active area and being vertically separated from an upper surface of the fin-type active area; a gate line, the gate line surrounding the at least one nanosheet on the fin-type active area, the gate line extending in a second horizontal direction intersecting the first horizontal direction; a source / drain area, the source / drain area being adjacent to the gate line and located on the fin-type active area, the source / drain area being connected to the at least one a nanosheet; a device isolation layer located on the substrate and covering a portion of a sidewall of the fin-type active region in the trench region; a through-hole power rail horizontally separated from each of the fin-type active region, the source / drain region, and the gate line and vertically extending through the device isolation layer and the gate line; and a back power rail vertically extending from the back side of the substrate through the substrate and connected to one end of the through-hole power rail, wherein the through-hole power rail includes a first portion connected to the back power rail and a second portion located on the first portion, wherein the first portion includes at least a portion whose width in the second horizontal direction increases toward the back side, and wherein the second portion whose width in the second horizontal direction decreases toward the back side. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a plan layout view showing a unit block of an integrated circuit device according to an embodiment;

[0010] Figure 2 is a plan layout view showing an integrated circuit device according to an embodiment;

[0011] Figure 3A It is along Figure 2 A cross-sectional view taken along the line X1-X1';

[0012] Figure 3B It is along Figure 2 A cross-sectional view taken along the line Y1-Y1';

[0013] Figure 3C It is along Figure 2 A cross-sectional view taken along line Y2-Y2';

[0014] Figure 3D yes Figure 3B an enlarged cross-sectional view of a portion “EX2”;

[0015] Figure 4 is a view showing an integrated circuit device according to another embodiment;

[0016] Figure 5A is a view showing an integrated circuit device according to another embodiment;

[0017] Figure 5B is a view showing an integrated circuit device according to another embodiment;

[0018] Figure 6 is a view showing an integrated circuit device according to another embodiment;

[0019] Figure 7 is a view showing an integrated circuit device according to another embodiment;

[0020] Figure 8 is a view showing an integrated circuit device according to another embodiment;

[0021] Fig. 9 is a view showing an integrated circuit device according to another embodiment; and

[0022] Fig.10 , Fig.11 , Fig. 12A , Fig. 12B , Fig. 12C , Fig.13 , Fig.14A , Fig. 14B , Fig. 14C , Fig.15 , Fig.16 , Fig.17 , Fig.18A , Fig.18B , Fig.18C , Fig.19A , Fig.19B , Fig.19C , Fig. 20A , Fig. 20B , Fig.21A , Fig.21B , Fig.22A , Fig. 22B , Fig.23A , Fig. 23B , Fig.23C , Fig.24A , Fig. 24B , Fig.25A , Fig.25B , Fig.26A , Fig.26B and Fig.26C is a diagram showing a method of manufacturing an integrated circuit device in process order according to an embodiment; and

[0023] For example, Fig.10 , Fig.11 , Fig. 12B , Fig.13 , Fig. 14B , Fig.18B , Fig.19B , Fig. 20A , Fig.21A , Fig.22A , Fig.23A , Fig.24A , Fig.25A and Fig.26B is based on and along Figure 2 The process sequence of the section corresponding to the section taken along the line Y1-Y1' is a cross-sectional view showing the cross-sectional structure; Fig. 12A , Fig.14A , Fig.15 , Fig.16 , Fig.17 , Fig.18A , Fig.19A and Fig.26A is based on and along Figure 2 A cross-sectional view showing a cross-sectional structure in the process sequence corresponding to a portion of the cross-sectional view taken along the line X1-X1'; and Fig. 12C , Fig. 14C , Fig.18C , Fig.19C , Fig. 20B , Fig.21B , Fig. 22B , Fig. 23B , Fig. 24B , Fig.25B and Fig.26C is based on and along Figure 2 The cross section taken along the line Y2 - Y2 ′ corresponds to the process sequence of the portion, showing a cross-sectional view of the cross-sectional structure. DETAILED DESCRIPTION

[0024] The embodiments described herein are non-limiting example embodiments, and thus the present disclosure is not limited thereto.

[0025] It should be understood that although the terms first, second, third, fourth, etc. may be used herein to describe various elements, components, regions, layers and / or sections (collectively referred to as "elements"), these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element described in this specification section may be referred to as the second element in the claims, and vice versa.

[0026] It should be understood that when an element or layer is referred to as being “on,” “on,” “under,” or “connected to” another element or layer, it can be directly on, on, under, or connected to another element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly on,” “directly under,” or “directly connected to” another element or layer, there are no intervening elements or layers.

[0027] Hereinafter, non-limiting exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals are used for the same components, and redundant descriptions thereof may be omitted.

[0028] Figure 1 1 is a plan layout diagram showing a unit block 12 of an integrated circuit device 10 according to an embodiment.

[0029] refer to Figure 1 The cell block 12 of the integrated circuit device 10 may include a plurality of logic cells LC including circuit patterns for configuring various circuits. The plurality of logic cells LC may be arranged in a matrix along the first horizontal direction X and the second horizontal direction Y in the cell block 12.

[0030] The plurality of logic cells LC may include a circuit pattern of a layout designed according to a place and route (PnR) technology to perform at least one logic function. The plurality of logic cells LC may each have a function of performing various logic functions. In an embodiment, the plurality of logic cells LC may include a plurality of standard cells. In an embodiment, at least some of the plurality of logic cells LC may perform the same logic function. In other embodiments, at least some of the plurality of logic cells LC may perform different logic functions.

[0031] The plurality of logic cells LC may include various types of logic cells including a plurality of circuit elements. For example, the plurality of logic cells LC may each be composed of an AND gate, a NAND gate, an OR gate, a NOR gate, an XOR gate, an XNOR gate, an inverter (INV), an adder (ADD), a buffer (BUF), a delay (DLY), a filter (FIL), a multiplexer (MXT / MXIT), an OR / AND / inverter (OR / AND / inverter, OAI) gate, an AND / OR (AND / OR, AO) gate, an AND / OR / inverter (AND / OR / inverter, AOI), a D flip-flop, a reset flip-flop, a master-slave flip-flop, a latch, or one or more combinations thereof, but are not limited thereto.

[0032] In the cell block 12, at least some of the plurality of logic cells LC in a row (e.g., row R1, row R2, row R3, row R4, row R5, or row R6) in the first horizontal direction X may have the same width. Also, at least some of the plurality of logic cells LC in a row (e.g., row R1, row R2, row R3, row R4, row R5, or row R6) may have the same height. However, embodiments of the present disclosure are not limited to Figure 1 , and at least some of the plurality of logic cells LC in a row (eg, row R1, row R2, row R3, row R4, row R5, or row R6) may also have different widths and heights from each other.

[0033] The area of ​​each of the plurality of logic cells LC included in the cell block 12 of the integrated circuit device 10 may be limited by the cell boundary CBD. An on-cell contact portion CBC connecting the cell boundaries CBD to each other may be located between two logic cells LC adjacent to each other in the first horizontal direction X or the second horizontal direction Y among the plurality of logic cells LC.

[0034] In an embodiment, two logic cells LC adjacent to each other in the first horizontal direction among the plurality of logic cells LC in a row (e.g., row R1, row R2, row R3, row R4, row R5, or row R6) may be connected to each other at the on-cell contact portion CBC without any separation distance between the two logic cells LC. In other embodiments, two logic cells LC adjacent to each other in the first horizontal direction X among the plurality of logic cells LC in a row (e.g., row R1, row R2, row R3, row R4, row R5, or row R6) may be separated from each other with a predetermined separation distance between the two logic cells LC.

[0035] In an embodiment, two logic cells LC adjacent to each other among a plurality of logic cells LC in a row (e.g., row R1, row R2, row R3, row R4, row R5, or row R6) may perform the same function. In this case, the two adjacent logic cells LC may have the same structure. In other embodiments, two logic cells LC adjacent to each other among a plurality of logic cells LC in a row (e.g., row R1, row R2, row R3, row R4, row R5, or row R6) may have different functions from each other.

[0036] In the embodiment, one logic cell LC selected from among a plurality of logic cells LC included in the cell block 12 of the integrated circuit device 10 and another logic cell LC adjacent to the selected logic cell LC in the second horizontal direction Y (refer to Figure 1 ) may have a symmetrical structure with respect to the cell upper contact portion CBC therebetween. For example, the reference logic cell LC_R in row R3 (e.g., the third row) and the lower logic cell LC_L in row R2 (e.g., the second row) may have a symmetrical structure with respect to the cell upper contact portion CBC therebetween. Also, the reference logic cell LC_R in row R3 and the upper logic cell LC_H in row R4 (e.g., the fourth row) may have a symmetrical structure with respect to the cell upper contact portion CBC therebetween.

[0037] although Figure 1 The cell block 12 including six rows is shown, but this is only an example, and the cell block 12 may include various numbers of rows, and each row may include various numbers of logic cells.

[0038] One line selected from the plurality of ground lines VSS and the plurality of power lines VDD may be located between two rows among a plurality of rows (e.g., row R1, row R2, row R3, row R4, row R5, and row R6), each row including a plurality of logic cells LC arranged in a row in the first horizontal direction X. The plurality of ground lines VSS and the plurality of power lines VDD may each extend in the first horizontal direction X, may be separated from each other in the second horizontal direction Y, and may be alternately arranged. Therefore, the plurality of ground lines VSS and the plurality of power lines VDD may be arranged to overlap with cell boundaries CBD of the respective logic cells LC in the second horizontal direction Y.

[0039] Figure 2 is a plan layout view showing an integrated circuit device 100 according to an embodiment. Figure 3A It is along Figure 2 A cross-sectional view taken along line X1-X1'. Figure 3B It is along Figure 2 A cross-sectional view taken along line Y1-Y1'. Figure 3C It is along Figure 2 A cross-sectional view taken along line Y2-Y2'. Figure 3D It is shown Figure 3B An enlarged cross-sectional view of portion “EX2”. Figure 2 , Figure 3A , Figure 3B , Figure 3C and Figure 3D An integrated circuit device 100 including a field effect transistor having a gate-all-around structure including an active region in a nanowire shape or a nanosheet shape and a gate surrounding the active region is shown. The integrated circuit device 100 may be formed Figure 1 A portion of a plurality of logic cells LC is shown in FIG.

[0040] refer to Figure 2 , Figure 3A , Figure 3B , Figure 3C and Figure 3D , the integrated circuit device 100 may include two logic cells LC adjacent to each other in the second horizontal direction Y, with a via power rail VPR therebetween. The via power rail VPR may form Figure 1 The ground line VSS is shown in FIG.

[0041] The integrated circuit device 100 may include a substrate 102 having a back side 102B and a plurality of fin type active regions F1 protruding from the substrate 102 on a side of the substrate 102 opposite to the back side 102B to define a plurality of trench regions T1. The plurality of fin type active regions F1 may be elongated in a first horizontal direction X on the substrate 102 and may extend parallel to each other.

[0042] The substrate 102 may include a semiconductor such as Si or Ge, or a compound semiconductor such as SiGe, SiC, GaAs, InAs, InGaAs, or InP. The terms "SiGe", "SiC", "GaAs", "InAs", "InGaAs", and "InP" used in the present disclosure may each refer to a material composed of elements included in each term, rather than a chemical formula representing a stoichiometric relationship. The substrate 102 may include a conductive region such as a well doped with impurities or a structure doped with impurities.

[0043] The device isolation layer 112 may be located in the trench region T1 defining the plurality of fin-type active regions F1. The device isolation layer 112 covers a portion of a sidewall of each of the plurality of fin-type active regions F1 in the plurality of trench regions T1 and may be separated from the substrate 102 in the vertical direction Z. The device isolation layer 112 may include a silicon oxide film.

[0044] like Figure 3B and Figure 3C As shown, the via power rail VPR may extend in the vertical direction Z between a pair of adjacent fin-type active regions F1 selected from among a plurality of fin-type active regions F1 and between a pair of source / drain regions 130 on the pair of fin-type active regions F1 .

[0045] In an embodiment, the via power rail VPR may include a first metal wiring layer. The first metal wiring layer may include a low resistance metal, such as Ru, Co, W, Mo, Cu, Rh, Ir, Ti, or a combination thereof. In an embodiment, the via power rail VPR may include a single metal wiring layer, and the metal wiring layer may include any one selected from Ru, Co, W, Mo, Cu, Rh, Ir, and Ti. In other embodiments, the via power rail VPR may include multiple metal wiring layers, and the multiple metal wiring layers may each include any one selected from Ru, Co, W, Mo, Cu, Rh, Ir, and Ti.

[0046] The via power rail VPR may include a first portion LVR1 connected to the back side power rail BPW and a second portion UVR1 located on the first portion LVR1. For example, a portion of the lower portion of the via power rail VPR may be defined as the first portion LVR1, and another portion of the lower portion may be defined as the second portion UVR1.

[0047] like Figure 3B , Figure 3C and Figure 3DAs shown, the first portion LVR1 may have a shape in which the width in the second horizontal direction Y increases uniformly from the top toward the bottom, while the second portion UVR1 may have a shape in which the width in the second horizontal direction Y decreases uniformly from the top toward the bottom. For example, the first portion LVR1 may have a shape in which the width in the second horizontal direction Y increases uniformly toward the back side 102B of the substrate 102, while the second portion UVR1 may have a shape in which the width in the second horizontal direction Y decreases uniformly toward the back side 102B of the substrate 102. The cross-sectional area of ​​the first portion LVR1 may increase from the top toward the bottom, while the cross-sectional area of ​​the second portion UVR1 may decrease from the top toward the bottom. In addition, the cross-sectional area of ​​the first portion LVR1 may increase toward the back side 102B, while the cross-sectional area of ​​the second portion UVR1 may decrease toward the back side 102B.

[0048] Because the paired fin active regions F1 are separated from the first portion LVR1 , the maximum width of the first portion LVR1 may be less than the separation distance between the paired fin active regions F1 . In an embodiment, the minimum width of the first portion LVR1 may be equal to the minimum width of the second portion UVR1 .

[0049] In an embodiment, when the through-hole power rail VPR is cut in the second horizontal direction Y, the first portion LVR1 may have a trapezoidal shape, i.e., a trapezoidal cross-section having a lower portion wider than an upper portion, and the second portion UVR1 may have an inverted trapezoidal shape, i.e., a trapezoidal cross-section having an upper portion wider than a lower portion. For example, the first portion LVR1 may include two side walls LS1 that are inclined surfaces, and the second portion UVR1 may have two side walls US1 that are inclined surfaces having an inclination direction different from the inclination direction of the two side walls LS1 of the first portion LVR1. For example, the two side walls LS1 of the first portion LVR1 may be side walls of a hexahedron having a trapezoidal cross-section, and the two side walls US1 of the second portion UVR1 may be side walls of a hexahedron having an inverted trapezoidal cross-section. In an embodiment, the two side walls LS1 of the first portion LVR1 may be connected to the lower ends of the two side walls US1 of the second portion UVR1.

[0050] In an embodiment, a vertical height LV1 where the first portion LVR1 intersects the second portion UVR1 may be located between a vertical height LV2 of a portion of the paired source / drain regions 130 adjacent to the via power rail VPR that is closest to the via power rail VPR and a vertical height LV3 of an upper surface of the back side power rail BPW. The term "vertical height" used herein refers to a distance from the back side 102B of the substrate 102 in the vertical direction Z or -Z.

[0051] Part of the sidewall of the via power rail VPR may be covered by the insulating spacer 189. For example, the insulating spacer 189 may cover part of the sidewall of the first portion LVR1 of the via power rail VPR, and cover the entire sidewall of the second portion UVR1 of the via power rail VPR. The insulating spacer 189 may conformally extend along the sidewall of the second portion UVR1 to be connected to the sidewall LS1 of the first portion LVR1. In this case, the portion where the insulating spacer 189 is connected to the sidewall LS1 of the first portion LVR1 may have a sharp shape toward the back side 102B. In an embodiment, the insulating spacer 189 may include a silicon oxide film, a silicon oxynitride film, or a combination thereof.

[0052] The entire sidewall of the second portion UVR1 of the via power rail VPR may be covered by the insulating spacer 189, but a portion of the sidewall of the first portion LVR1 may not be covered by the insulating spacer 189. For example, an upper portion of the first portion LVR1 may be separated from the device isolation layer 112 with the insulating spacer 189 interposed therebetween, but a lower portion of the first portion LVR1 may be directly connected to the device isolation layer 112.

[0053] The back side 102B of the substrate 102 may be covered by a back side insulating layer 109. The back side insulating layer 109 may include a silicon oxide film, a silicon nitride film, a silicon carbide film, a low dielectric film, or a combination thereof. The low dielectric film may include fluorine-doped silicon oxide, organic silicate glass, carbon-doped oxide, porous silicon oxide, porous organic silicate glass, spin-on organic polymer dielectric, spin-on silicon-based polymer dielectric, or a combination thereof, but is not limited thereto.

[0054] like Figure 3B , Figure 3C and Figure 3D As shown, a back power rail BPW extending through the back insulating layer 109 and the substrate 102 in the vertical direction Z may be provided. The back power rail BPW may pass through the substrate 102 from the back side 102B of the substrate 102 in the vertical direction Z to be connected to one end of the via power rail VPR.

[0055] In an embodiment, the back power rail BPW may include a second metal wiring layer. The second metal wiring layer may include a low resistance metal, such as Ru, Co, W, Mo, Cu, Rh, Ir, Ti, or a combination thereof. In other embodiments, the back power rail BPW may include a second metal wiring layer and a conductive barrier layer surrounding the second metal wiring layer. The conductive barrier layer may include Ti, TiN, Ta, TaN, or a combination thereof.

[0056] In an embodiment, the back side power rail BPW may cover the entire lower surface of the via power rail VPR and the lower surface of the device isolation layer 112 adjacent to the via power rail VPR. In other embodiments, the back side power rail BPW may cover all or part of the lower surface of the via power rail VPR, and may not cover the lower surface of the device isolation layer 112 adjacent to the via power rail VPR.

[0057] like Figure 2 , Figure 3A and Figure 3C As shown, a plurality of gate lines 160 may be arranged on a plurality of fin-type active areas F1. The plurality of gate lines 160 may be elongated in a second horizontal direction Y. In the region where the plurality of fin-type active areas F1 intersect with the plurality of gate lines 160, a plurality of nanosheet stacks NSS may be arranged on the upper surface FT of each of the plurality of fin-type active areas F1. The plurality of nanosheet stacks NSS may each include at least one nanosheet facing the upper surface FT at a position separated from the upper surface FT of the fin-type active area F1 in the vertical direction Z. The term "nanosheet" as used herein refers to a conductive structure having a cross section substantially perpendicular to the direction of current flow. The nanosheet may include a nanowire.

[0058] like Figure 3A and Figure 3C As shown, the plurality of nanosheet stacks NSS may each include a first nanosheet N1, a second nanosheet N2, and a third nanosheet N3 overlapping each other on the fin type active region F1 in the vertical direction Z. The first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 may have different vertical distances from the upper surface FT of the fin type active region F1 in the vertical direction Z. The plurality of gate lines 160 may surround the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in the nanosheet stack NSS and overlapping each other in the vertical direction Z.

[0059] although Figure 2 The case where the planar shape of the nanosheet stack NSS is approximately a square is shown, but the embodiments of the present disclosure are not limited thereto. The nanosheet stack NSS may have various planar shapes according to the planar shapes of the fin active region F1 and the gate line 160. The present embodiment provides a structure in which a plurality of nanosheet stacks (NSS) and a plurality of gate lines 160 are arranged on one fin active region in the fin active region F1, and a plurality of nanosheet stacks NSS are arranged on one fin active region in the fin active region F1 in a row in the first horizontal direction X. However, the number of nanosheet stacks NSS arranged on one fin active region in the fin active region F1 and the number of gate lines 160 arranged on one fin active region in the fin active region F1 are not limited.

[0060] The first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in the nanosheet stack NSS may each serve as a channel region. In an embodiment, the thickness of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 may each be selected from a range of about 4 nm to about 6 nm, but is not limited thereto. Here, the thickness of each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 refers to the dimension in the vertical direction Z. In an embodiment, the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 may have substantially the same thickness in the vertical direction Z. In other embodiments, the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 may have different thicknesses from each other in the vertical direction Z. In an embodiment, the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in the nanosheet stack (NSS) may each include a Si layer, a SiGe layer, or a combination thereof.

[0061] like Figure 3A As shown, the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in a nanosheet stack NSS may have sizes equal to or similar to each other. In other embodiments, the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in a nanosheet stack NSS may have partially different sizes in the first horizontal direction X. Although the present embodiment provides a case where a plurality of nanosheet stacks NSS each have three nanosheets, the embodiments of the present disclosure are not limited thereto. For example, a nanosheet stack NSS may include at least one nanosheet, and the number of nanosheets included in the nanosheet stack NSS is not limited.

[0062] like Figure 3A and Figure 3C As shown, the plurality of gate lines 160 may each include a main gate portion 160M and a plurality of sub-gate portions 160S. The main gate portion 160M covers the upper surface of the nanosheet stack NSS and may be elongated in the second horizontal direction Y. The plurality of sub-gate portions 160S may be integrally connected to the main gate portion 160M, and the plurality of sub-gate portions 160S may each be located between the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3, and the plurality of sub-gate portions 160S may each be located between the first nanosheet N1 and at least one fin-type active region F1. In the vertical direction Z, the thickness of each of the plurality of sub-gate portions 160S may be less than the thickness of the main gate portion 160M.

[0063] like Figure 3A and Figure 3B As shown, a plurality of active region recesses R1 may be formed on the fin type active region F1 . A vertical height of a lowermost surface of each of the plurality of active region recesses R1 may be lower than a vertical height of an upper surface FT of the fin type active region F1 .

[0064] like Figure 3A and Figure 3B As shown, the plurality of source / drain regions 130 may be respectively located in the plurality of active region recesses R1. The plurality of source / drain regions 130 may each be adjacent to at least one gate line among the plurality of gate lines 160. The plurality of source / drain regions 130 may each have a surface facing the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in the adjacent nanosheet stack NSS. The plurality of source / drain regions 130 may each be connected to the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in the adjacent nanosheet stack NSS.

[0065] The plurality of gate lines 160 may each include a metal, a metal nitride, a metal carbide, or a combination thereof. The metal may be selected from Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd. The metal nitride may be selected from TiN and TaN. The metal carbide may be TiAlC. However, the material forming each of the plurality of gate lines 160 is not limited thereto.

[0066] The gate dielectric layer 152 may be located between the nanosheet stack NSS and the gate line 160. In an embodiment, the gate dielectric layer 152 may have a structure in which an interface dielectric layer and a high-k dielectric layer are stacked. The interface dielectric layer may include a low dielectric material layer having a dielectric constant of about 9 or less, such as a silicon oxide film, a silicon oxynitride film, or a combination thereof. In an embodiment, the interface dielectric layer may be omitted. The high-k dielectric layer may include a material having a dielectric constant higher than that of the silicon oxide film. For example, the dielectric constant of the high-k dielectric layer may be about 10 to about 25. The high-k dielectric layer may include hafnium oxide, but is not limited thereto.

[0067] like Figure 3A and Figure 3C As shown, an upper surface of each of the gate dielectric layer 152 and the gate line 160 may be covered by a capping insulating pattern 168. The capping insulating pattern 168 may include a silicon nitride film or a silicon oxide film.

[0068] Both sidewalls of at least one gate line 160 (e.g., main gate portion 160M) and the capping insulating pattern 168 may be covered by an outer insulating spacer 118. The outer insulating spacer 118 may cover both sidewalls of the main gate portion 160M on the upper surface of each nanosheet stack NSS. The outer insulating spacer 118 may be separated from the at least one gate line 160, with the gate dielectric layer 152 interposed between the outer insulating spacer and the at least one gate line.

[0069] like Figure 3BAs shown, a plurality of recess side insulating spacers 119 may be located on the upper surface of the device isolation layer 112 to cover the sidewalls of the plurality of source / drain regions 130. In an embodiment, the plurality of recess side insulating spacers 119 may each be integrally connected to at least one outer insulating spacer 118 adjacent thereto.

[0070] The plurality of outer insulating spacers 118 and the plurality of recess side insulating spacers 119 may each include silicon nitride, silicon oxide, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, or a combination thereof. The terms "SiCN", "SiBN", "SiON", "SiOCN", "SiBCN", and "SiOC" used herein each refer to a material composed of the elements included in each term, rather than a chemical formula representing a stoichiometric relationship.

[0071] The metal silicide layer 172 may be formed on the upper surface of each of the plurality of source / drain regions 130. The metal silicide layer 172 may include a metal made of Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, or Pd. For example, the metal silicide layer 172 may include titanium silicide, but is not limited thereto.

[0072] On the substrate 102, a plurality of source / drain regions 130, a plurality of metal silicide layers 172, and a plurality of external insulating spacers 118 may be covered by an insulating liner 142. In an embodiment, the insulating liner 142 may be omitted. An inter-gate insulating layer 144 may be located on the insulating liner 142. When the insulating liner 142 is omitted, the inter-gate insulating layer 144 may be connected to the plurality of source / drain regions 130.

[0073] The insulating liner 142 and the inter-gate insulating layer 144 may be sequentially arranged on the plurality of source / drain regions 130 and the plurality of metal silicide layers 172. The insulating liner 142 and the inter-gate insulating layer 144 may form an insulating structure. In an embodiment, the insulating liner 142 may include silicon nitride, SiCN, SiBN, SiON, SiOCN, SiBCN, or a combination thereof, but is not limited thereto. The inter-gate insulating layer 144 may include a silicon oxide film, but is not limited thereto.

[0074] Both sidewalls of each of the plurality of sub-gate portions 160S included in the plurality of gate lines 160 may be separated from the plurality of source / drain regions 130, and a gate dielectric layer 152 is interposed between the two sidewalls and the plurality of source / drain regions. The gate dielectric layer 152 may be located between the sub-gate portion 160S included in the gate line 160 and each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3, and may be located between the sub-gate portion 160 included in the gate line 160 and the source / drain region 130.

[0075] In the region where the plurality of fin active regions F1 intersect the plurality of gate lines 160, the plurality of nanosheet stacks NSS may be respectively located on the upper surface FT of each of the plurality of fin active regions F1, and may face the upper surface FT of the fin active region F1 at a position separated from the fin active region F1. The plurality of nanosheet transistors may be formed in the portion where the plurality of fin active regions F1 intersect the plurality of gate lines 160 on the substrate 102.

[0076] like Figure 3A and Figure 3B As shown, a plurality of source / drain contacts CA may be respectively arranged on a plurality of source / drain regions 130. The plurality of source / drain contacts CA may each pass through the inter-gate insulating layer 144 and the insulating liner 142 in the vertical direction Z to be connected to the metal silicide layer 172. The plurality of source / drain contacts CA may each be electrically connected to at least one source / drain region 130 through the metal silicide layer 172. The plurality of source / drain contacts CA may each be separated from the main gate portion 160M in the first horizontal direction X, with the external insulating spacer 118 interposed between the source / drain contacts and the main gate portion.

[0077] The plurality of source / drain contacts CA may each include a conductive barrier pattern 174 and a contact plug 176 sequentially stacked on one of the source / drain regions 130. The conductive barrier pattern 174 surrounds the bottom surface and sidewalls of the contact plug 176 and may be connected to the bottom surface and sidewalls of the contact plug 176. The plurality of source / drain contacts CA may each be elongated in the vertical direction Z through the inter-gate insulating layer 144 and the insulating liner 142. The conductive barrier pattern 174 may be located between the metal silicide layer 172 and the contact plug 176. The conductive barrier pattern 174 may have a surface connected to the metal silicide layer 172 and a surface connected to the contact plug 176. In an embodiment, the conductive barrier pattern 174 may include a metal or a metal nitride. For example, the conductive barrier pattern 174 may include Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or a combination thereof, but is not limited thereto. The contact plug 176 may include molybdenum (Mo), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), a combination thereof, or an alloy thereof, but is not limited thereto.

[0078] like Figure 3B As shown, at least one source / drain contact among the plurality of source / drain contacts CA adjacent to the via power rail VPR may be separated from the via power rail VPR in the second horizontal direction Y.

[0079] like FIG. 3A to FIG. 3C As shown, the upper surfaces of the plurality of source / drain contacts CA, the upper surfaces of the plurality of capping insulating patterns 168, and the upper surfaces of the gate inter-insulating layer 144 may be covered by an upper insulating structure 180. The upper insulating structure 180 may include an etch stop layer 182 and an interlayer insulating layer 184 sequentially stacked on the plurality of source / drain contacts CA, the plurality of capping insulating patterns 168, and the gate inter-insulating layer 144. The etch stop layer 182 may include silicon carbide (SiC), SiN, nitrogen-doped silicon carbide (SiC:N), SiOC, AlN, AlON, AlO, AlOC, or a combination thereof. The interlayer insulating layer 184 may include an oxide film, a nitride film, an ultra-low K (ULK) film having an ultra-low dielectric constant K of about 2.2 to about 2.4, or a combination thereof. For example, the interlayer insulating layer 184 may include a tetraethyl orthosilicate (TEOS) film, a high density plasma (HDP) oxide film, a borophosphosilicate glass (BPSG) film, a flowable chemical vapor deposition (FCVD) oxide film, a SiON film, a SiN film, a SiOC film, a SiCOH film, or a combination thereof, but is not limited thereto.

[0080] like Figure 3A and Figure 3BAs shown, a plurality of source / drain via contacts VA may be arranged on a plurality of source / drain contacts CA, respectively. A plurality of source / drain via contacts VA may each pass through the upper insulating structure 180 to be connected to one of the source / drain contacts in the source / drain contacts CA. A plurality of source / drain regions 130 may each be electrically connected to one of the source / drain via contacts in the source / drain via contacts VA through the metal silicide layer 172 and one of the source / drain contacts in the source / drain contacts CA. The bottom surface of each of the plurality of source / drain via contacts VA may be connected to the upper surface of one of the source / drain contacts in the source / drain contacts CA. A plurality of source / drain via contacts VA may each include molybdenum (Mo) or tungsten (W), but is not limited thereto.

[0081] like Figure 2 and Figure 3C As shown, the gate contact CB may be located on the gate line 160. The gate contact CB may pass through the upper insulating structure 180 and the capping insulating pattern 168 in the vertical direction Z to connect to the gate line 160. The bottom surface of the gate contact CB may be connected to the upper surface of the gate line 160. The gate contact CB may include molybdenum (Mo), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), a combination thereof, or an alloy thereof, but the constituent material of the contact plug CB is not limited thereto. In an embodiment, the gate contact CB may also include a conductive barrier pattern surrounding a portion of the contact plug. The conductive barrier pattern included in the gate contact CB may include a metal or a metal nitride. For example, the conductive barrier pattern may include Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or a combination thereof, but is not limited thereto.

[0082] The via power rail VPR may pass through the upper insulating structure 180, the capping insulating pattern 168, the gate line 160, the inter-gate insulating layer 144, the insulating liner 142, and the device isolation layer 112 in the vertical direction Z. The insulating spacer 189 may surround the sidewall of the via power rail VPR and pass through the upper insulating structure 180, the capping insulating pattern 168, the gate line 160, the inter-gate insulating layer 144, and the insulating liner 142 in the vertical direction Z, and pass through a portion of the device isolation layer 112 in the vertical direction Z. The portion of the gate line 160 through which the via power rail VPR and the insulating spacer 189 pass may be a region between a plurality of nanosheet stacks NSS. The via power rail VPR may be separated from the gate line 160 in the horizontal direction (e.g., the second horizontal direction Y), with the insulating spacer 189 interposed between the via power rail and the gate line. The via power rail VPR and the insulating spacer 189 may be separated from the pair of source / drain regions 130 and the pair of fin type active regions F1 in a horizontal direction (eg, a second horizontal direction).

[0083] In an embodiment, two side walls LS1 of the first portion LVR1 of the through-hole power rail VPR may face the pair of fin-type active regions F1, respectively, and two side walls US1 of the second portion UVR1 may face the pair of fin-type active regions F1, respectively. The two side walls LS1 of the first portion LVR1 may be inclined to be closer to the pair of fin-type active regions F1 as the two side walls LS1 are closer to the back side power rail BPW. Also, the two side walls US1 of the second portion UVR1 may be inclined to be away from the pair of fin-type active regions F1 as the two side walls US1 are closer to the first portion LVR1.

[0084] In an embodiment, an upper surface of the via power rail VPR, an upper surface of the upper insulating structure 180 , an upper surface of each of the plurality of source / drain via contacts VA, and an upper surface of the gate contact CB may be coplanar with each other.

[0085] An upper surface of each of the upper insulating structures 180, an upper surface of the back power rail BPW, an upper surface of each of the plurality of source / drain via contacts VA, and an upper surface of the gate contact CB may be covered by an upper insulating layer 192. The constituent material of the upper insulating layer 192 is substantially the same as the constituent material of the above-mentioned interlayer insulating layer 184.

[0086] The plurality of upper wiring layers M1 may pass through the upper insulating layer 192. The plurality of upper wiring layers M1 may each be connected to one source / drain via contact among the plurality of source / drain via contacts VA located below, or one gate contact among the plurality of gate contacts CB (see Figure 2The plurality of upper wiring layers M1 may each include molybdenum (Mo), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), a combination thereof, or an alloy thereof, but is not limited thereto.

[0087] The plurality of upper wiring layers M1 may each include a power connection conductive layer PCL connected to the through-hole power rail VPR on the through-hole power rail VPR. One source / drain through-hole contact among the plurality of source / drain through-hole contacts VA may connect the source / drain contact CA to the power connection conductive layer PCL at a position separated from the through-hole power rail VPR in the second horizontal direction Y. One source / drain region 130 connected to the through-hole power rail VPR among the plurality of source / drain regions 130 may be electrically connected to the through-hole power rail VPR through one source / drain contact in the source / drain contact CA, one source / drain through-hole contact in the source / drain through-hole contact VA, and the power connection conductive layer PCL.

[0088] As reference Figure 2 , Figure 3A , Figure 3B , Figure 3C and Figure 3D As described above, the via power rail VPR of the integrated circuit device 100 may have a first portion LVR1 whose cross-sectional area increases from the upper portion toward the lower portion and a second portion UVR1 whose cross-sectional area decreases from the upper portion toward the lower portion. Since the via power rail VPR has the first portion LVR1 whose cross-sectional area increases from the upper portion toward the lower portion, the contact area between the via power rail VPR and the back side power rail BPW may be increased, the resistance may be reduced, and thus the integrated circuit device 100 having improved electrical characteristics and reliability may be provided.

[0089] Figure 4 is a view showing an integrated circuit device 200 according to another embodiment. Figure 4 Shows the corresponding Figure 3B The integrated circuit device 200 may be formed in the region "EX2". Figure 1 A portion of a plurality of logic cells LC is shown in FIG. Figure 4 In, with Figure 2 , Figure 3A , Figure 3B , Figure 3C and Figure 3D The same reference numerals in the drawings denote the same components, and redundant descriptions thereof may be omitted below.

[0090] refer to Figure 4 , the integrated circuit device 200 has a reference Figure 2 , Figure 3A , Figure 3B , Figure 3Cand Figure 3D The integrated circuit device 200 is substantially the same configuration as described above. However, the integrated circuit device 200 may include a via power rail VPR2 including a first portion LVR2, instead of the reference Figure 2 , Figure 3A , Figure 3B , Figure 3C and Figure 3D The depicted integrated circuit device 100 includes a via power rail VPR of a first portion LVR1 and may include an insulating spacer 189 ′ instead of the insulating spacer 189 .

[0091] like Figure 4 As shown, the first portion LVR2 may have a shape in which the width in the second horizontal direction Y increases uniformly from the top toward the bottom, while the second portion UVR1 may have a shape in which the width in the second horizontal direction Y decreases uniformly from the top toward the bottom. For example, the first portion LVR2 may have a shape in which the width in the second horizontal direction Y increases uniformly toward the back side 102B of the substrate 102, while the second portion UVR1 may have a shape in which the width in the second horizontal direction Y decreases uniformly toward the back side 102B of the substrate 102. The cross-sectional area of ​​the first portion LVR2 may increase from the top toward the bottom, while the cross-sectional area of ​​the second portion UVR1 may decrease from the top toward the bottom. Similarly, the cross-sectional area of ​​the first portion LVR2 may increase toward the back side 102B, while the cross-sectional area of ​​the second portion UVR1 may decrease toward the back side 102B.

[0092] Because the paired fin type active regions F1 are separated from the first portion LVR2 , the maximum width of the first portion LVR2 may be less than the separation distance between the paired fin type active regions F1 . The minimum width of the first portion LVR2 may be greater than the minimum width of the second portion UVR1 .

[0093] In an embodiment, when the through-hole power rail VPR2 is cut in the second horizontal direction Y, the first portion LVR2 may have a trapezoidal cross-section, and the second portion UVR1 may have an inverted trapezoidal cross-section. For example, the first portion LVR2 may include two side walls LS2 that are inclined surfaces, and the second portion UVR1 may include two side walls US1 that are inclined surfaces having an inclination direction different from the inclination direction of the two side walls LS2 of the first portion LVR2. The two side walls LS2 of the first portion LVR2 may be side walls of a hexahedron having a trapezoidal cross-section, and the two side walls US1 of the second portion UVR1 may be side walls of a hexahedron having an inverted trapezoidal cross-section.

[0094] In an embodiment, the sidewalls of the through-hole power rails VPR2 facing the paired fin-type active regions F1 may each have a step structure P1. For example, the two sidewalls of the first portion LVR2 may be separated from the two sidewalls of the second portion UVR1 in a horizontal direction (e.g., a horizontal direction Y at a position where the first portion LVR2 intersects the second portion UVR1), and the upper surface of the first portion LVR2 may be located between the two sidewalls LS2 of the first portion LVR2 and the two sidewalls US1 of the second portion UVR1.

[0095] A portion of the sidewall of the via power rail VPR2 may be covered by the insulating spacer 189'. For example, the insulating spacer 189' may not cover the sidewall LS2 of the first portion LVR2 of the via power rail VPR2, but may completely cover the sidewall US1 of the second portion UVR1. The insulating spacer 189' may conformally extend along the sidewall US1 of the second portion UVR1 to be connected to the upper surface of the first portion LVR2. In an embodiment, the insulating spacer 189' may include a silicon oxide film, a silicon oxynitride film, or a combination thereof.

[0096] The sidewall LS2 of the first portion LVR2 of the via power rail VPR2 may not be covered by the insulating spacer 189', but the sidewall US1 of the second portion UVR1 may be covered by the insulating spacer 189'. For example, the first portion LVR2 may be connected to the device isolation layer 112, but the second portion UVR1 may be separated from the device isolation layer 112 with the insulating spacer 189' interposed therebetween.

[0097] In an embodiment, two side walls LS2 of the first portion LVR2 of the through-hole power rail VPR2 may face the pair of fin-type active regions F1, respectively, and two side walls US1 of the second portion UVR1 may face the pair of fin-type active regions F1, respectively. The two side walls LS2 of the first portion LVR2 may be inclined to be closer to the pair of fin-type active regions F1 as the two side walls LS2 approach the back side power rail BPW. Also, the two side walls US1 of the second portion UVR1 may be inclined to be away from the pair of fin-type active regions F1 as the two side walls US1 approach the first portion LVR2.

[0098] Figure 5A is a view showing an integrated circuit device according to another embodiment. Figure 5A Shows the corresponding Figure 3B The integrated circuit device 300a may be formed Figure 1 A portion of a plurality of logic cells LC is shown in FIG. Figure 5A In, with Figure 2 , Figure 3A , Figure 3B , Figure 3C and Figure 3D The same reference numerals in the drawings denote the same components, and redundant descriptions thereof may be omitted below.

[0099] refer to Figure 5A , the integrated circuit device 300a may have a reference Figure 2 , Figure 3A , Figure 3B , Figure 3C and Figure 3D The integrated circuit device 300a is substantially the same configuration as described above. However, the integrated circuit device 300a may include a via power rail VPR3 including a first portion LVR3, instead of the reference Figure 2 , Figure 3A , Figure 3B , Figure 3C and Figure 3D The depicted integrated circuit device 100 includes a via power rail VPR of a first portion LVR1 and may include an insulating spacer 189 ″ instead of the insulating spacer 189 .

[0100] like Figure 5A As shown, the first portion LVR3 may have a shape in which the width in the second horizontal direction Y increases from the top toward the bottom and then decreases, while the second portion UVR1 may have a shape in which the width in the second horizontal direction Y decreases from the top toward the bottom. For example, the first portion LVR3 may have a shape in which the width in the second horizontal direction Y increases and then decreases toward the back side 102B of the substrate 102, while the second portion UVR1 may have a shape in which the width in the second horizontal direction Y decreases uniformly toward the back side 102B of the substrate 102. For example, the width of the first portion LVR3 in the second horizontal direction Y at the middle may be relatively large compared to the width of the first portion LVR3 in the second horizontal direction Y at the upper and lower portions of the first portion LVR3. The cross-sectional area of ​​the first portion LVR3 may increase from the top toward the bottom and then decrease, while the cross-sectional area of ​​the second portion UVR1 may decrease from the top toward the bottom. Similarly, the first portion LVR3 may have a shape in which the cross-sectional area increases and then decreases toward the back side 102B of the substrate 102, while the second portion UVR1 may have a shape in which the cross-sectional area decreases uniformly toward the back side 102B of the substrate 102.

[0101] Because the paired fin type active regions F1 are separated from the first portion LVR3 , the maximum width of the first portion LVR3 may be less than the separation distance between the paired fin type active regions F1 . The minimum width of the first portion LVR3 may be the same as the minimum width of the second portion UVR1 .

[0102] In an embodiment, when the through-hole power rail VPR3 is cut in the second horizontal direction Y, the first portion LVR3 may have a cross-section including a partial circle or a partial ellipse, and the second portion UVR1 may have a trapezoidal cross-section whose upper portion is wider than the lower portion of the trapezoidal cross-section. For example, the first portion LVR3 may include two curved side walls LS3, and the second portion UVR1 may include two side walls US1 that are inclined surfaces, unlike the first portion LVR3. In an embodiment, the two side walls LS3 of the first portion LVR3 may be connected to the ends of the two side walls US1 of the second portion UVR1.

[0103] Partial sidewalls of the via power rail VPR3 may be covered by the insulating spacer 189″. For example, the insulating spacer 189″ may not cover the two sidewalls LS3 of the first portion LVR3 of the via power rail VPR3, but may completely cover the two sidewalls US1 of the second portion UVR1. The insulating spacer 189″ may conformally extend along the sidewall US1 of the second portion UVR1 to be connected to the sidewall LS3 of the first portion LVR3. In an embodiment, the insulating spacer 189″ may include a silicon oxide film, a silicon oxynitride film, or a combination thereof.

[0104] The sidewall LS3 of the first portion LVR3 of the through-hole power rail VPR3 may not be covered by the insulating spacer 189", but the sidewall US1 of the second portion UVR1 may be covered by the insulating spacer 189". For example, the first portion LVR3 may be connected to the device isolation layer 112, but the second portion UVR1 may be separated from the device isolation layer 112 with the insulating spacer 189" interposed therebetween.

[0105] In an embodiment, the two side walls LS3 of the first portion LVR3 of the through-hole power rail VPR3 may face the paired fin-type active regions F1, respectively, and the two side walls US1 of the second portion UVR1 may face the paired fin-type active regions F1, respectively. The two side walls LS3 of the first portion LVR3 may have a convex shape facing the paired fin-type active regions F1. For example, the two side walls LS3 of the first portion LVR3 may be closest to the paired fin-type active regions F1 at the middle of the first portion LVR3 rather than at the upper and lower portions of the first portion LVR3. In addition, the two side walls US1 of the second portion UVR1 may be inclined to move away from the paired fin-type active regions F1 as the two side walls US1 approach the first portion LVR3.

[0106] The via power rail VPR3 may be connected to the center region of the back power rail BPWa, but may be separated from the edge region of the back power rail BPWa. A portion of the device isolation layer 112 may be between the via power rail VPR3 and the edge region of the back power rail BPWa. The separation distance between the via power rail VPR3 and the back power rail BPWa in the vertical direction Z may increase toward the edge of the back power rail BPWa.

[0107] Figure 5B is a view showing an integrated circuit device 300 b according to another embodiment. Figure 5B Shows the corresponding Figure 3B The integrated circuit device 300b may be formed Figure 1 A portion of a plurality of logic cells LC is shown in FIG. Figure 5B In, with Figure 2 , Figure 3A , Figure 3B , Figure 3C and Figure 3D The same reference numerals in the drawings denote the same components, and redundant descriptions thereof may be omitted below.

[0108] refer to Figure 5B , the integrated circuit device 300b may have a reference Figure 2 , Figure 3A , Figure 3B , Figure 3C and Figure 3D The integrated circuit device 300b is substantially the same configuration as the integrated circuit device 100 described above. However, the integrated circuit device 300b may include a via power rail VPR3 including a first portion LVR3, instead of the reference Figure 2 , Figure 3A , Figure 3B , Figure 3C and Figure 3D The depicted integrated circuit device 100 includes a via power rail VPR of a first portion LVR1 and may include an insulating spacer 189 ″ instead of the insulating spacer 189 .

[0109] like Figure 5B As shown, the first portion LVR3 may have a shape in which the width in the second horizontal direction Y increases from the top toward the bottom and then decreases, and the second portion UVR1 may have a shape in which the width in the second horizontal direction Y decreases from the top to the bottom. The specific shapes of the first portion LVR3 and the second portion UVR1 are similar to those of reference Figure 5A Describe the shape.

[0110] A portion of the sidewall of the via power rail VPR3 may be covered by the insulating spacer 189". For example, the insulating spacer 189" may not cover the sidewall LS3 of the first portion LVR3 of the via power rail VPR3, but may completely cover the sidewall US1 of the second portion UVR1. The insulating spacer 189" may conformally extend along the sidewall US1 of the second portion UVR1 to be connected to the sidewall LS3 of the first portion LVR3. In an embodiment, the insulating spacer 189" may include a silicon oxide film, a silicon oxynitride film, or a combination thereof.

[0111] The sidewall LS3 of the first portion LVR3 of the through-hole power rail VPR3 may not be covered by the insulating spacer 189", but the sidewall US1 of the second portion UVR1 may be covered by the insulating spacer 189". For example, the first portion LVR3 may be connected to the device isolation layer 112, but the second portion UVR1 may be separated from the device isolation layer 112 with the insulating spacer 189" interposed therebetween.

[0112] In an embodiment, two sidewalls LS3 of the first portion LVR3 of the through-hole power rail VPR3 may face the pair of fin-type active regions F1, respectively, and two sidewalls US1 of the second portion UVR1 may face the pair of fin-type active regions F1, respectively. The shapes of the two sidewalls LS3 of the first portion LVR3 and the two sidewalls US1 of the second portion UVR1 are similar to those of the reference Figure 5A Describe the shape.

[0113] The via power rail VPR3 may be connected to a central region of the back power rail BPWb and an edge region of the back power rail BPWb. The edge region of the back power rail BPWb may extend through the device isolation layer 112 to be connected to one end of the via power rail VPR3. The height of the edge region of the back power rail BPWb in the vertical direction Z may be greater than the height of the central region in the vertical direction Z. For example, the back power rail BPWb may have a concave shape in the center.

[0114] Figure 6 is a view showing an integrated circuit device 400 according to another embodiment. Figure 6 Shows the corresponding Figure 3B The integrated circuit device 400 may be formed in the region "EX2". Figure 1 A portion of a plurality of logic cells LC is shown in FIG. Figure 6 In, with Figure 2 , Figure 3A , Figure 3B , Figure 3C and Figure 3D The same reference numerals in the drawings denote the same components, and redundant descriptions thereof may be omitted below.

[0115] refer to Figure 6 , the integrated circuit device 400 may have a reference Figure 2 , Figure 3A , Figure 3B , Figure 3C and Figure 3D The integrated circuit device 100 is substantially the same configuration as described above. Figure 2 , Figure 3A , Figure 3B , Figure 3C and Figure 3D Different from the configuration described, the integrated circuit device 400 may further include a conductive barrier layer 190 a between the via power rail VPR and the insulating spacer 189 , and between the via power rail VPR and the backside power rail BPW.

[0116] In an embodiment, the via power rail VPR may include a first metal wiring layer. The first metal wiring layer may include a low resistance metal, such as Ru, Co, W, Mo, Cu, Rh, Ir, Ti, or a combination thereof.

[0117] The conductive barrier layer 190a may cover the lower surface and both sidewalls of the via power rail VPR. The conductive barrier layer 190a may include Ti, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or a combination thereof, but is not limited thereto.

[0118] The conductive barrier layer 190a may include a portion between the via power rail VPR and the back power rail BPW, and may include a portion between the via power rail VPR and the insulating spacer 189. The via power rail VPR may be separated from the back power rail BPW in the vertical direction Z, with the conductive barrier layer 190a interposed therebetween, and may be separated from the insulating spacer 189 in the horizontal direction (e.g., the second horizontal direction Y), with the conductive barrier layer 190a interposed therebetween.

[0119] Figure 7 is a view showing an integrated circuit device 500 according to another embodiment. Figure 7 Shows the corresponding Figure 3B The integrated circuit device 500 may be formed in the region "EX2". Figure 1 A portion of a plurality of logic cells LC is shown in FIG. Figure 7 In, with Figure 2 , Figure 3A , Figure 3B , Figure 3C and Figure 3D The same reference numerals in the drawings denote the same components, and redundant descriptions thereof may be omitted below.

[0120] refer to Figure 7 , the integrated circuit device 500 may have a reference Figure 2 , Figure 3A , Figure 3B , Figure 3C and Figure 3D The integrated circuit device 500 is substantially the same configuration as described above. However, the integrated circuit device 500 may include a via power rail VPR4 including a second portion UVR2, instead of the reference Figure 2 , Figure 3A , Figure 3B , Figure 3C and Figure 3D The depicted via power rail VPR includes the second portion UVR1 , and may also include a conductive barrier layer 190 b between the via power rail VPR4 and the insulating spacer 189 .

[0121] In an embodiment, the via power rail VPR4 may include a first metal wiring layer. The first metal wiring layer may include a low resistance metal, such as Ru, Co, W, Mo, Cu, Rh, Ir, Ti, or a combination thereof.

[0122] The conductive barrier layer 190b may cover a portion of both sidewalls of the via power rail VPR4 and a lower surface of the via power rail VPR4. For example, the conductive barrier layer 190b may completely cover the lower surface and both sidewalls of the first portion LVR1 of the via power rail VPR4, and only cover a portion of both sidewalls of the second portion UVR2. The upper surface of the conductive barrier layer 190b may be at various vertical heights, but is not limited to the vertical height shown. The conductive barrier layer 190b may include Ti, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or a combination thereof, but is not limited thereto.

[0123] The conductive barrier layer 190b may include a portion between the via power rail VPR4 and the back power rail BPW, and may include a portion between the via power rail VPR4 and the insulating spacer 189. The via power rail VPR4 may be separated from the back power rail BPW in the vertical direction Z, and the conductive barrier layer 190b is interposed between the via power rail and the back power rail. The upper portion of the via power rail VPR4 may be separated from the inter-gate insulating layer 144 in the horizontal direction (e.g., the second horizontal direction Y), and the insulating spacer 189 is interposed between the upper portion and the inter-gate insulating layer. The middle portion of the via power rail VPR4 may be separated from the device isolation layer 112 in the horizontal direction (e.g., the second horizontal direction Y), and the insulating spacer 189 and the conductive barrier layer 190b are interposed between the middle portion and the device isolation layer. The lower portion of the via power rail VPR4 may be separated from the device isolation layer 112 in the horizontal direction (e.g., the second horizontal direction Y), and the conductive barrier layer 190b is interposed between the lower portion and the device isolation layer.

[0124] The via power rail VPR4 may include a first portion LVR1 connected to the back side power rail BPW and a second portion UVR2 located on the first portion LVR1. In an embodiment, the second portion UVR2 may have a shape in which the width in the second horizontal direction Y uniformly decreases from the top toward the bottom, and may include a step structure P2. For example, the upper surface of the conductive barrier layer 190b may be located between a portion of the sidewall of the second portion UVR2 covered by the conductive barrier layer 190b and a portion of the sidewall of the second portion UVR2 not covered by the conductive barrier layer 190b and exposed.

[0125] In an embodiment, the first portion LVR1 may also include a step structure P2, and in this case, the upper surface of the conductive barrier layer 190b may be located between a portion of the sidewall of the first portion LVR1 covered by the conductive barrier layer 190b and a portion of the sidewall of the first portion LVR1 not covered by the conductive barrier layer 190b and exposed.

[0126] Figure 8 is a view showing an integrated circuit device 600 according to another embodiment. Figure 8 Shows the corresponding Figure 3B The integrated circuit device 600 may be formed in the region "EX2". Figure 1 A portion of a plurality of logic cells LC is shown in FIG. Figure 8 In, with Figure 2 , Figure 3A , Figure 3B , Figure 3C and Figure 3D The same reference numerals in the drawings denote the same components, and redundant descriptions thereof may be omitted below.

[0127] refer to Figure 8 , the integrated circuit device 600 may have a reference Figure 2 , Figure 3A , Figure 3B , Figure 3C and Figure 3D The integrated circuit device 100 is substantially the same configuration as described above. Figure 2 , Figure 3A , Figure 3B , Figure 3C and Figure 3D Different from the configuration described, the integrated circuit device 600 may further include a metal wiring silicide layer 186 covering the lower surface of the via power rail VPR.

[0128] In an embodiment, the via power rail VPR may include a first metal wiring layer. The first metal wiring layer may include a first metal, and the first metal may include, for example, Ru, Co, W, Mo, Cu, Rh, Ir, Ti, or a combination thereof.

[0129] The metal wiring silicide layer 186 may include a first metal, and may include a combination of the first metal and silicon. For example, when the first metal wiring layer forming the via power rail VPR includes Mo, the metal wiring silicide layer 186 may include a combination of Mo and Si.

[0130] The metal wiring silicide layer 186 may be located between the via power rail VPR and the back power rail BPW. The metal wiring silicide layer 186 may include a portion overlapping the back power rail BPW in the second horizontal direction Y. For example, the vertical height of the lower surface of the metal wiring silicide layer 186 may be between the vertical height of the upper surface of the back power rail BPW and the vertical height of the lower surface of the back power rail BPW. The via power rail VPR may be separated from the back power rail BPW, with the metal wiring silicide layer 186 interposed between the via power rail and the back power rail.

[0131] Fig. 9 is a view showing an integrated circuit device 700 according to another embodiment. Fig. 9 Shows the corresponding Figure 3B The integrated circuit device 700 may be formed as a portion of the region "EX2". Figure 1 A portion of a plurality of logic cells LC is shown in FIG. Fig. 9 In, with Figure 2 , Figure 3A , Figure 3B , Figure 3C and Figure 3D The same reference numerals in the drawings denote the same components, and redundant descriptions thereof may be omitted below.

[0132] refer to Fig. 9 , the integrated circuit device 700 may have a reference Figure 2 , Figure 3A , Figure 3B , Figure 3C and Figure 3D The integrated circuit device 100 is substantially the same configuration as described above. Figure 2 , Figure 3A , Figure 3B , 3C and Figure 3D Different from the configuration described, the integrated circuit device 700 may further include a metal wiring silicide layer 186 and a connection metal layer 188 between the via power rail VPR and the back side power rail BPW.

[0133] In an embodiment, the via power rail VPR may include a first metal wiring layer. The first metal wiring layer may include a first metal, and the first metal may include, for example, Ru, Co, W, Mo, Cu, Rh, Ir, Ti, or a combination thereof.

[0134] The metal wiring silicide layer 186 may include a first metal, and may include a combination of the first metal and silicon. For example, when the first metal wiring layer forming the via power rail VPR may include Mo, the metal wiring silicide layer 186 may include a combination of Mo and Si.

[0135] The metal wiring silicide layer 186 may be located between the via power rail VPR and the back power rail BPW. The metal wiring silicide layer 186 may include a portion overlapping the back power rail BPW in the second horizontal direction Y. For example, the vertical height of the lower surface of the metal wiring silicide layer 186 may be between the vertical height of the upper surface of the back power rail BPW and the vertical height of the lower surface of the back power rail BPW.

[0136] The connection metal layer 188 may be located between the metal wiring silicide layer 186 and the via power rail VPR. The connection metal layer 188 may cover the lower surface of the via power rail VPR and the upper surface of the metal wiring silicide layer 186. The connection metal layer 188 may include a second metal, and the second metal may include, for example, Ru, Co, W, Mo, Cu, Rh, Ir, Ti, or a combination thereof. The second metal forming the connection metal layer 188 may be different from the first metal. For example, when the first metal wiring layer forming the via power rail VPR includes Mo, the connection metal layer 188 may include W, Ru, Co, Cu, Rh, Ir, Ti, or a combination thereof. The via power rail VPR may be separated from the back power rail BPW, and the metal wiring silicide layer 186 and the connection metal layer 188 are between the via power rail and the back power rail.

[0137] With reference Figure 2 , Figure 3A , Figure 3B , Figure 3C and Figure 3D The integrated circuit device 100 is similar to the one described in reference Figures 4 to 9 The via power rails VPR, VPR2, VPR3, and VPR4 of the described integrated circuit devices 200, 300, 400, 500, 600, and 700 include the first portions LVR1, LVR2, and LVR3, and therefore, the area in which the via power rails VPR, VPR2, VPR3, and VPR4 can be connected to the back side power rail BPW, the metal wiring silicide layer 186, or the connection metal layer 188 can be relatively large. Therefore, an integrated circuit device with lower resistance and improved reliability and electrical characteristics can be provided.

[0138] Next, a method of manufacturing an integrated circuit device according to an embodiment is described.

[0139] Fig.10 , Fig.11 , Fig. 12A , Fig. 12B , Fig. 12C , Fig.13 , Fig.14A , Fig. 14B , Fig. 14C , Fig.15 , Fig.16 , Fig.17 , Fig.18A , Fig.18B , Fig.18C , Fig.19A , Fig.19B , Fig.19C , Fig. 20A , Fig. 20B , Fig.21A , Fig.21B , Fig.22A , Fig. 22B , Fig.23A , Fig. 23B , Fig.23C , Fig.24A , Fig. 24B , Fig.25A , Fig.25B , Fig.26A , Fig.26B and Fig.26C is a view showing a method of manufacturing an integrated circuit device in process order according to an embodiment.

[0140] For example, Fig.10 , Fig.11 , Fig. 12B , Fig.13 , Fig. 14B , Fig.18B , Fig.19B , Fig. 20A , Fig.21A , Fig.22A , Fig.23A , Fig.24A , Fig.25A and Fig.26B It is shown that according to and along Figure 2 A cross-sectional view of a cross-sectional structure of a portion of the process sequence corresponding to the cross-sectional view taken along the line Y1-Y1'; and Fig. 12A , Fig.14A , Fig.15 , Fig.16 , Fig.17 , Fig.18A , Fig.19A and Fig.26A It is shown that according to and along Figure 2A cross-sectional view of a cross-sectional structure of a portion of the process sequence corresponding to the cross-sectional view taken along the line X1-X1'; and Fig. 12C , Fig. 14C , Fig.18C , Fig.19C , Fig. 20B , Fig.21B , Fig. 22B , Fig. 23B , Fig. 24B , Fig.25B and Fig.26C It is shown that according to and along Figure 2 The cross section taken along the line Y2 - Y2 ′ corresponds to a cross-sectional view of the cross-sectional structure of the portion in the process sequence.

[0141] exist Fig.10 , Fig.11 , Fig. 12A , Fig. 12B , Fig. 12C , Fig.13 , Fig.14A , Fig. 14B , Fig. 14C , Fig.15 , Fig.16 , Fig.17 , Fig.18A , Fig.18B , Fig.18C , Fig.19A , Fig.19B , Fig.19C , Fig. 20A , Fig. 20B , Fig.21A , Fig.21B , Fig.22A , Fig. 22B , Fig.23A , Fig. 23B , Fig.23C , Fig.24A , Fig. 24B , Fig.25A , Fig.25B , Fig.26A , Fig.26B and Fig.26C In, with Figure 2 , Figure 3A , Figure 3B , Figure 3C and Figure 3D The same reference numerals in the drawings denote the same elements, and a detailed description thereof will be omitted below.

[0142] refer to Fig.10 , a plurality of sacrificial semiconductor layers 103 and a plurality of nanosheet semiconductor layers NS may be alternately stacked on the substrate 102 .

[0143] The plurality of sacrificial semiconductor layers 103 and the plurality of nanosheet semiconductor layers NS may include semiconductor materials having different etching selectivities. In an embodiment, the plurality of nanosheet semiconductor layers NS may each include a Si layer, and the plurality of sacrificial semiconductor layers 103 may each include a SiGe layer. In an embodiment, the Ge content of each of the plurality of sacrificial semiconductor layers 103 may be constant. The constant Ge content of the SiGe layer constituting each of the plurality of sacrificial semiconductor layers 103 may be selected in the range of about 5 atomic % to about 60 atomic % (e.g., about 10 atomic % to about 40 atomic %). The Ge content of the SiGe layer constituting each of the plurality of sacrificial semiconductor layers 103 may be selected in various ways as needed.

[0144] refer to Fig.11 ,exist Fig.10 After forming a mask pattern MP1 on the resulting structure, a portion of the substrate 102, a plurality of sacrificial semiconductor layers 103, and a plurality of nanosheet semiconductor layers NS may be etched by using the mask pattern MP1 as an etching mask to form a plurality of fin-type active regions F1 on the substrate 102. A plurality of trench regions T1 may be defined on the substrate 102 by the plurality of fin-type active regions F1. In an embodiment, the mask patterns MP1 may each have a stacked structure of an oxide film pattern and a silicon nitride film pattern. The mask patterns MP1 may extend parallel to each other in a first horizontal direction X on the substrate 102. The stacked structure of the plurality of sacrificial semiconductor layers 103 and the plurality of nanosheet semiconductor layers NS may be located on the upper surface FT of each of the plurality of fin-type active regions F1.

[0145] Thereafter, a device isolation insulating layer P112 may be formed on the obtained resultant structure. The device isolation insulating layer P112 may be formed to have a sufficient thickness to fill the remaining space of the plurality of trench regions T1 on the substrate 102. The device isolation insulating layer P112 may include a silicon oxide film.

[0146] In order to form the device isolation insulating layer P112, plasma enhanced chemical vapor deposition (PECVD), high density plasma (HDP) CVD, inductively coupled plasma (ICP) CVD, capacitively coupled plasma (CCP) CVD, flowable chemical vapor deposition (FCVD), spin coating process, etc. can be used.

[0147] refer to Fig. 12A , Fig. 12B and Fig. 12C , in the right Fig.11After the resulting structure is planarized to expose the upper surface of the mask pattern MP1, the exposed mask pattern MP1 may be removed, and a recessing process for removing a portion of the device isolation insulating layer P112 may be performed on the isolation insulating layer P112. Fig.11 ) may protrude onto the upper surface of the device isolation layer 112.

[0148] In order to perform the recess process of the device isolation insulating layer P112, a dry etching process, a wet etching process, or a combination of a dry etching process and a wet etching process may be used. In this case, the NH 4 OH, tetramethylammonium hydroxide (TMAH), potassium hydroxide (KOH), etc. as an etchant, or a dry etching process using inductively coupled plasma (ICP), transformer coupled plasma (TCP), electron cyclotron resonance (ECR), reactive ion etching (RIE), etc. When the recess process is performed on the device isolation insulating layer P112 by using the dry etching process, a CF 4 Fluorine-containing gases, such as Cl 2 Chlorine-containing gas, HBr, etc. are used as etching gas.

[0149] Thereafter, a plurality of dummy gate structures DGS may be formed on the stacked structure of the plurality of sacrificial semiconductor layers 103 and the plurality of nanosheet semiconductor layers NS. The plurality of dummy gate structures DGS may be elongated in the second horizontal direction Y. The plurality of dummy gate structures DGS may each have a structure in which an oxide film D122, a dummy gate layer D124, and a capping layer D126 are sequentially stacked. In an embodiment, the oxide film D122 may be a film obtained by oxidizing the surfaces of the plurality of sacrificial semiconductor layers 103 and the surfaces of the plurality of nanosheet semiconductor layers NS (see FIG. 12 ). The dummy gate layer D124 may include polycrystalline silicon, and the capping layer D126 may include a silicon nitride film.

[0150] After a plurality of external insulating spacers 118 are provided to cover the two side walls of each of the plurality of dummy gate structures DGS, the plurality of sacrificial semiconductor layers 103, the plurality of nanosheet semiconductor layers NS, and the fin-type active region F1 may be partially etched by using the plurality of dummy gate structures DGS and the plurality of external insulating spacers 118 as etching masks to divide the plurality of nanosheet semiconductor layers NS into a plurality of nanosheet stacks NSS each including a first nanosheet N1, a second nanosheet N2, and a third nanosheet N3. Thus, a plurality of active region recesses R1 may be formed on the fin-type active region F1. In order to form the plurality of active region recesses R1, etching may be performed by using dry etching, wet etching, or a combination thereof. After the plurality of active region recesses R1 are formed, a plurality of recess side insulating spacers 119 arranged adjacent to the plurality of active region recesses R1 may be formed on the device isolation layer 112 on both sides of the fin-type active region F1.

[0151] refer to Fig.13 , you can Fig. 12A , Fig. 12B and Fig. 12C A plurality of source / drain regions 130 filling the plurality of active region recesses R1 are formed in the resulting structure.

[0152] To form the plurality of source / drain regions 130 , a semiconductor material may be epitaxially grown from a surface of the fin type active region F1 exposed at the bottom surface of the plurality of active region recesses R1 and a sidewall of each of the first, second, and third nanosheets N1 , N2 , and N3 included in the nanosheet stack NSS.

[0153] refer to Fig.14A , Fig. 14B and Fig. 14C , can form coverage Fig.13 The insulating liner 142 of the resulting structure, the gate insulating layer 144 can be formed on the insulating liner 142, and then the insulating liner 142 and the gate insulating layer 144 can be partially etched, and thereby the upper surface of the plurality of cover layers D126 can be exposed. Thereafter, the plurality of cover layers D126 can be removed to expose the dummy gate layer D124, and the insulating liner 142 and the gate insulating layer 144 can be partially removed so that the height of the upper surface of the dummy gate layer D124 can be substantially the same as the height of the upper surface of the gate insulating layer 144.

[0154] refer to Fig.15 , can be obtained from Fig.14A , Fig. 14B and Fig. 14CThe dummy gate layer D124 and the oxide film D122 thereunder are removed from the resulting structure to form a gate space GS, and the plurality of nanosheet stacks NSS may be exposed through the gate space GS. Thereafter, the plurality of sacrificial semiconductor layers 103 remaining on the fin-type active region F1 may be removed through the gate space GS, and thereby the gate space GS may extend to the space between the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3, and the space between the first nanosheet N1 and the upper surface FT. In an embodiment, in order to selectively remove the plurality of sacrificial semiconductor layers 103, the difference between the selectivity ratios of the first nanosheet N1, the second nanosheet N2, the third nanosheet N3, and the plurality of sacrificial semiconductor layers 103 may be utilized.

[0155] The plurality of sacrificial semiconductor layers 103 may be selectively removed using a liquid or vapor etchant. In an embodiment, a CH-based 3 COOH etchants (such as CH 3 COOH、HNO 3 and HF mixture, or CH 3 COOH, H 2 O 2 The plurality of sacrificial semiconductor layers 103 may be selectively removed by using an etchant composed of a mixture of HF and HF, but the invention is not limited thereto.

[0156] refer to Fig.16 , you can Fig.15 A gate dielectric layer 152 is formed in the resulting structure covering the exposed surface of each of the first nanosheet N1, the second nanosheet N2, the third nanosheet N3, and the at least one fin-type active region F1. The gate dielectric layer 152 may be formed using an atomic layer deposition (ALD) process.

[0157] refer to Fig.17 , a gate space GS filling the gate dielectric layer 152 may be formed (see Fig.17 ) and covers the gate line 160 on the upper surface of the gate inter-insulating layer 144, and the covering insulating pattern 168 covering the gate line 160 and the upper surface of the gate dielectric layer 152 on the gate space GS.

[0158] refer to Fig.18A , Fig.18B and Fig.18C , you can Fig.17A source / drain contact hole is formed in the resulting structure through the insulating structure including the insulating liner 142 and the inter-gate insulating layer 144 to expose the at least one source / drain region 130, and then a portion of the at least one source / drain region 130 may be removed through the source / drain contact hole by an anisotropic etching process, and thereby the source / drain contact hole may be further extended toward the substrate 102. Thereafter, a metal silicide layer 172 may be formed in the at least one source / drain region 130 exposed at the bottom side of the source / drain contact hole. In an embodiment, the metal silicide layer 172 may be formed by performing the following process: forming a metal liner conformally covering the exposed surface of the at least one source / drain region 130, and heat-treating the metal liner to cause a reaction between the at least one source / drain region 130 and the metal forming the metal liner. After the metal silicide layer 172 is formed, the remaining portion of the metal liner may be removed. A portion of at least one source / drain region 130 may be consumed during the process of forming the metal silicide layer 172. In an embodiment, when the metal silicide layer 172 includes a titanium silicide layer, the metal liner may include a Ti film.

[0159] Thereafter, source / drain contacts CA including a conductive barrier pattern 174 and a contact plug 176 may be formed on the metal silicide layer 172 .

[0160] refer to Fig.19A , Fig.19B and Fig.19C , can be formed by sequentially Fig.19A , Fig.19B and Fig.19C An upper insulating structure 180 is formed by covering the inter-gate insulating layer 144 , the plurality of source / drain contacts CA, and the plurality of etching stop layers 182 and the interlayer insulating layer 184 covering the upper surfaces of the insulating patterns 168 in the resulting structure.

[0161] Thereafter, a plurality of source / drain via contacts VA extending through the upper insulating structure 180 in the vertical direction Z to be connected to the plurality of source / drain contacts CA, a gate contact CB extending through the upper insulating structure 180 and the capping insulating pattern 168 in the vertical direction Z to be connected to at least one gate line 160, and a via power trench VPT may be formed. Although the formation order of the source / drain via contacts VA, the gate contacts CB, and the via power trench VPT is not particularly limited, the following description is made by assuming that the source / drain via contacts VA and the gate contacts CB are formed earlier than the via power trench VPT.

[0162] In order to form a through hole power trench VPT, it can be Fig.18A , Fig.18B and Fig.18CA mask pattern MP2 is formed on the structure, and then the upper insulating structure 180, the inter-gate insulating layer 144, the insulating liner 142, the gate line 160, the gate dielectric layer 152, and the device isolation layer 112 can be partially etched by using the mask pattern MP2 as an etching barrier. Through the etching process, a through-hole power trench VPT that penetrates the upper insulating structure 180, the inter-gate insulating layer 144, the insulating liner 142, the gate line 160, the gate dielectric layer 152, and the device isolation layer 112 in the vertical direction Z can be formed. In an embodiment, a dry etching process can be used to form the through-hole power trench VPT. In this case, the bottom of the through-hole power trench VPT can expose a portion of the upper surface of the substrate 102.

[0163] refer to Fig. 20A and Fig. 20B , in order to remove Fig.19A , Fig.19B and Fig.19C The mask pattern MP2 may be removed by performing an ashing process using plasma including oxygen radicals or oxygen ions. Thereafter, in order to remove the remaining mask pattern or remaining impurities, the resultant structure of the ashing process may be cleaned.

[0164] Thereafter, a preliminary insulating spacer P189 extending along the sidewall of the through hole power trench VPT may be formed. For example, the preliminary insulating spacer P189 may include a silicon oxide film, a silicon oxynitride film, or a combination thereof. The preliminary insulating spacer P189 may be deposited by various methods, such as plasma enhanced chemical vapor deposition (PECVD), high density plasma CVD (HDP CVD), inductively coupled plasma CVD (ICP CVD), capacitively coupled plasma CVD (CCP CVD), and flowable chemical vapor deposition (FCVD), and a spin coating process.

[0165] A preliminary via power rail PVR may be formed below the via power trench VPT forming the preliminary insulating spacer P189. In an embodiment, the preliminary via power rail PVR may include a metal layer, which may include, for example, Ru, Co, W, Mo, Cu, Rh, Ir, Ti, or a combination thereof. The metal layer may be deposited using various processes, such as a CVD process (such as PECVD, thermal CVD, atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD)), an ALD process, etc.

[0166] In an embodiment, the metal layer may be selectively deposited on the upper surface of the substrate 102 exposed by the through-hole power trench VPT compared to the sidewall of the preliminary insulating spacer P189. For example, when the metal layer includes Mo, the metal layer may be deposited by using MoCl 5 or MoO2 Cl 2 As a precursor to deposit metal layers. 5 or MoO 2 Cl 2 When used as a precursor, MoCl 5 or MoO 2 Cl 2 The deposition effect on Si is better than that on the silicon oxide film, and therefore, the metal layer can be grown on the upper surface of the substrate 102 exposed by the through-hole power trench VPT. In this case, when heat is used in the metal layer deposition process, a silicide layer including the same metal as the metal layer can also be formed on the upper surface of the substrate 102 connected to the metal layer.

[0167] In this case, a vertical height LV1P of the upper surface of the preliminary via power rail PVR may be located between a vertical height LV2 of a portion of the paired source / drain regions 130 adjacent to and closest to the via power trench VPT and a vertical height LV3 of the upper surface of the back side power rail BPW.

[0168] refer to Fig.21A and Fig.21B , you can Fig. 20A and Fig. 20B A sacrificial insulating liner SFL is formed on the resulting structure. The sacrificial insulating liner SFL may cover the upper surface of the plurality of source / drain via contacts VA, the upper surface of the upper insulating structure 180, the upper surface and sidewalls of the preliminary insulating spacer P189, and the upper surface of the preliminary via power rail PVR. The sacrificial insulating liner SFL may be conformally deposited on the upper surface of the plurality of source / drain via contacts VA, the upper surface of the upper insulating structure 180, the upper surface and sidewalls of the preliminary insulating spacer P189, and the upper surface of the preliminary via power rail PVR. In an embodiment, the sacrificial insulating liner SFL may include a dielectric film, such as a silicon nitride film or a silicon oxide film, or a metal film having a selectivity with a metal layer forming the preliminary via power rail PVR.

[0169] refer to Fig.22A and Fig. 22B , you can Fig.21A and Fig.21B An anisotropic etching process for removing a portion of the sacrificial insulating liner SFL to expose the upper surface of the preliminary via power rail PVR is performed on the resulting structure. In an embodiment, a dry etching process (such as an RIE process) may be performed to remove a portion of the sacrificial insulating liner SFL covering the upper surface of the plurality of source / drain via contacts VA, a portion of the sacrificial insulating liner SFL covering the upper surface of the upper insulating structure 180, and a portion of the sacrificial insulating liner SFL covering the upper surface of the preliminary via power rail PVR.

[0170] refer to Fig.23A and Fig. 23B , a dry etching process, a wet etching process, or a combination thereof may be performed to selectively remove the preliminary via power rail PVR. For example, in order to selectively remove the preliminary via power rail PVR, a dry etching process such as atomic layer etching (ALE) or a wet etching process such as a sulfur peroxide mixture (SPM) process using an SPM (piranha) solution or an SC1 process using a cleaning solution mixed with ammonia, hydrogen peroxide, and water in a certain ratio may be performed.

[0171] Thereafter, the preliminary through-hole power rail PVR may be removed, and thereby a portion of the preliminary insulating spacer P189 that is not covered and exposed by the sacrificial insulating liner SFL may be exposed. Thereafter, a portion of the preliminary insulating spacer P189 that is not covered and exposed by the sacrificial insulating liner SFL may be removed, and a portion of the device isolation layer 112 exposed by removing a portion of the preliminary insulating spacer P189 may be removed to form a recess RS. In order to remove a portion of the preliminary insulating spacer P189 and a portion of the device isolation layer 112, anisotropic etching or isotropic etching may be performed. For example, a dry etching process such as an RIE process may be performed, and a wet etching process using a buffered oxide etching (BOE) solution including HF as an etchant may be performed.

[0172] In an embodiment, when the anisotropic etching process is performed, the sidewalls of the preliminary insulating spacer P189 and the sidewalls of the device isolation layer 112 exposed by removing a portion of the preliminary insulating spacer P189 may be formed as inclined surfaces, and thus, the lower portion of the preliminary insulating spacer P189 may be removed more than the upper portion of the preliminary insulating spacer P189, and the lower portion of the device isolation layer 112 may be removed more than the upper portion of the device isolation layer 112. Fig.23A and Fig. 23B As shown, the recess RS may be formed such that the width of the lower portion of the recess RS in the second horizontal direction Y is greater than the width of the upper portion of the recess RS in the second horizontal direction Y. By adjusting the amount of removing a portion of the preliminary insulating spacer P189 and a portion of the device isolation layer 112, the recess RS may have Fig.23A and Fig. 23B Alternatively, the recess RS may have a shape similar to Figure 4 The shape of the first portion LVR2 of the through-hole power rail VPR2 is the same as the shape shown in FIG.

[0173] In other embodiments, when the isotropic etching process is performed, the upper, lower, and middle portions of the preliminary insulating spacer P189 may be similarly removed, and the upper, lower, and middle portions of the device isolation layer 112 may be similarly removed. Therefore, when the isotropic etching process is performed, the recess RS may have a thickness similar to that of the recess RS. Figure 5A and Figure 5B The first portion LVR3 of the through hole power rail VPR3 is shown in the same shape.

[0174] refer to Fig.24A and Fig. 24B , a dry etching process or a wet etching process may be performed to Fig.23A and Fig. 23B The sacrificial insulating liner SFL is selectively removed from the resulting structure. For example, a dry etching process may be performed by using hydrogen radicals and fluorine radicals, or a dry etching process may be performed by using a method including phosphoric acid (H 3 PO 4 ) as an etchant solution to perform a wet etching process.

[0175] refer to Fig.25A and Fig.25B , you can Fig.24A and Fig. 24B The via power rail VPR is formed on the resulting structure. The via power rail VPR may be formed by depositing a metal wiring layer inside the via power trench VPT and inside the recess RS. The deposition process of the metal wiring layer is similar to the deposition process of the metal layer forming the preliminary via power rail PVR. For example, the metal wiring layer may be deposited by various processes, such as a CVD process (such as PECVD, thermal CVD, APCVD, or LPCVD), an ALD process, and the like.

[0176] In an embodiment, the metal wiring layer may include a first metal, and the first metal may include, for example, Ru, Co, W, Mo, Cu, Rh, Ir, Ti, or a combination thereof. In an embodiment, when the first metal includes Mo, the first metal may be formed by using MoO 2 Cl 2 or MoCl 5 The deposition process of the metal wiring layer is performed by a CVD process or an ALD process as a precursor. Thereafter, a chemical mechanical polishing process may be performed to planarize the upper surface of the metal wiring layer.

[0177] In an embodiment, before depositing the metal wiring layer, a process of removing impurities (such as a natural oxide film) inside the via power trench VPT and inside the recess RS may be performed first to reduce the Fig.24A and Fig. 24B The resistance of the metal wiring layer formed in the resulting structure.

[0178] Therefore, the through-hole power rail VPR can be Fig.25A and Fig.25B However, Fig.25A and Fig.25B The process shown is an example, and the through-hole power rail VPR can be Fig.25A and Fig.25B The various processes shown in the process are formed.

[0179] In another embodiment, if Figure 6 As shown, before depositing the metal wiring layer forming the via power rail VPR, a conductive barrier layer 190a may be deposited inside the via power trench VPT and inside the recess RS. The conductive barrier layer 190a may be conformally deposited along the inner wall of the insulating spacer 189 and the inner wall of the recess RS. The conductive barrier layer 190a may include, for example, Ti, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or a combination thereof, but is not limited thereto.

[0180] In another embodiment, if Figure 7 As shown, before depositing the metal wiring layer forming the through-hole power rail VPR, a conductive barrier layer 190b may also be formed inside the through-hole power trench VPT and inside the recess RS. For example, in order to form the conductive barrier layer 190b, a barrier layer may be conformally formed on the inner wall of the through-hole power trench VPT and the inner wall of the recess RS. The barrier layer may include, for example, Ti, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or a combination thereof, but is not limited thereto. Thereafter, the upper portion of the barrier layer may be removed by an etch-back process, etc., and a conductive barrier layer 190b including the remaining barrier layer may be formed.

[0181] In another embodiment, if Figure 8 As shown, before depositing the metal wiring layer forming the via power rail VPR, a metal wiring silicide layer 186 may also be formed on the upper surface of the substrate 102 exposed by the bottom of the via power trench VPT. For example, in order to form the metal wiring silicide layer 186, a preliminary metal wiring layer including a first metal may be deposited on the upper surface of the substrate 102 exposed by the bottom of the via power trench VPT. The first metal is similar to the first metal described for the via power rail VPR. Thereafter, the preliminary metal wiring layer may be heated to form the metal wiring silicide layer 186.

[0182] In another embodiment, if Fig. 9As shown, before depositing the metal wiring layer forming the through-hole power rail VPR, a metal wiring silicide layer 186 may also be formed on the upper surface of the substrate 102 exposed by the bottom of the through-hole power trench VPT, and a connecting metal layer 188 may also be formed on the metal wiring silicide layer 186. In order to form the metal wiring silicide layer 186, a preliminary metal wiring layer including a first metal may be deposited on the upper surface of the substrate 102 exposed by the bottom of the through-hole power trench VPT. The first metal is similar to the first metal described for the through-hole power rail VPR. Thereafter, the preliminary metal wiring layer may be heated to form the metal wiring silicide layer 186. The connecting metal layer 188 may be formed by depositing a metal layer including a second metal different from the first metal. For example, the connecting metal layer 188 may be formed by an ALD process.

[0183] refer to Fig.26A , Fig.26B and Fig.26C , you can Fig.25A and Fig.25B In the resulting structure, an upper insulating layer 192 covering the upper insulating structure 180 and a plurality of upper wiring layers M1 extending through the upper insulating layer 192 to be connected to the source / drain via contacts VA, the gate contacts CB, and the via power rails VPR are formed. The plurality of upper wiring layers M1 may include a power connection conductive layer PCL connected to the via power rails VPR on the via power rails VPR.

[0184] A back insulating layer 109 may be formed to cover the back side 102B of the substrate 102 , and a back power rail BPW extending through the back insulating layer 109 and the substrate 102 in the vertical direction Z to be connected to one end of the via power rail VPR may be formed.

[0185] According to an embodiment, a process including forming a recess RS is used to form a power rail VPR, and thus, a via power rail VPR having a relatively large contact area with a back power rail BPW can be formed. Therefore, an integrated circuit device having reduced resistance between the back power rail BPW and the via power rail VPR, improved reliability, and improved electrical characteristics can be provided.

[0186] As described above, non-limiting example embodiments are described in the present disclosure and illustrated in the accompanying drawings. In the present disclosure, non-limiting example embodiments are described by using certain terms, but these terms are only used for the purpose of describing examples and are not used to limit the meaning or scope of the present disclosure. Therefore, those skilled in the art will understand that various modifications and other equivalent embodiments can be derived therefrom.

[0187] While the present disclosure has been particularly shown and described with reference to non-limiting example embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated circuit device, comprising: a substrate, the substrate comprising a back surface; a pair of fin-type active regions protruding from the substrate on a side of the substrate opposite to the back surface to define a trench region on the substrate; a device isolation layer, wherein the device isolation layer covers a side wall of each of the pair of fin-type active regions in the trench region; a through-hole power rail extending vertically through the device isolation layer between the pairs of fin-type active areas; as well as a back power rail extending vertically from the back side of the substrate through the substrate and connected to one end of the through-hole power rail, wherein the through-hole power rail comprises a first portion connected to the back power rail and a second portion located on the first portion, and Two side walls of the first portion facing each other and facing the pair of fin-type active regions respectively include inclined surfaces, and the inclined surfaces are inclined so as to be closer to the pair of fin-type active regions as the two side walls approach the back power rail.

2. The integrated circuit device according to claim 1, wherein: Two side walls of the second portion that are opposite to each other and face the pair of fin-type active regions each include an inclined surface that is inclined so as to be away from the pair of fin-type active regions as the two side walls approach the first portion.

3. The integrated circuit device according to claim 1, wherein: An upper surface of the first portion connects the two side walls of the first portion to the two side walls of the second portion.

4. The integrated circuit device according to claim 1, wherein: The two side walls of the first portion are directly connected to the two side walls of the second portion. 5 . The integrated circuit device of claim 1 , further comprising a conductive barrier layer including a portion located between the through-via power rail and the backside power rail.

6. The integrated circuit device of claim 1, further comprising a conductive barrier layer covering the two sidewalls of the first portion, partially covering the two sidewalls of the second portion, and covering a lower surface of the through-hole power rail. 7 . The integrated circuit device of claim 1 , further comprising a conductive barrier layer covering the two sidewalls of the first portion, the two sidewalls of the second portion, and a lower surface of the through-hole power rail.

8. The integrated circuit device according to claim 1, wherein: The through-hole power rail includes a metal wiring layer, and The metal wiring layer includes any one of Ru, Co, W, Mo, Cu, Rh, Ir and Ti.

9. The integrated circuit device of claim 1, further comprising a metal wiring silicide layer between the via power rail and the backside power rail.

10. The integrated circuit device according to claim 1, further comprising: a metal wiring silicide layer, the metal wiring silicide layer being located between the through-hole power rail and the backside power rail; as well as A connection metal layer is located between the through-hole power rail and the metal wiring silicide layer.

11. The integrated circuit device according to claim 1 , further comprising: an insulating spacer covering a portion of a sidewall of the through-hole power rail, wherein the first portion is directly connected to the device isolation layer, and The second portion is separated from the device isolation layer, and the insulating spacer is interposed between the second portion and the device isolation layer.

12. The integrated circuit device according to claim 1, wherein: The horizontal width of the first portion increases from the upper end of the first portion toward the lower end of the first portion, and The horizontal width of the second portion decreases from an upper end of the second portion toward a lower end of the second portion.

13. An integrated circuit device, comprising: a substrate, the substrate comprising a back surface; a pair of fin-type active regions protruding from the substrate so as to define a trench region on the substrate on a side of the substrate opposite to the back surface; A pair of source / drain regions, wherein the pair of source / drain regions are respectively located above the pair of fin-type active regions; a device isolation layer, wherein the device isolation layer covers a side wall of each of the pair of fin-type active regions in the trench region; a through-hole power rail, the through-hole power rail being located between the paired fin-type active regions and between the paired source / drain regions and extending vertically through the device isolation layer; as well as a back power rail extending vertically from the back side of the substrate through the substrate and connected to one end of the through-hole power rail, wherein the through-hole power rail comprises a first portion connected to the back power rail and a second portion located on the first portion, and Wherein, two side walls of the first portion respectively face the paired fin-type active regions and are curved surfaces.

14. The integrated circuit device according to claim 13, wherein: Two side walls of the second portion respectively face the pair of fin-type active regions and are flat.

15. The integrated circuit device according to claim 13, wherein: Both sidewalls of the first portion are convex toward a corresponding one of the pair of fin-type active regions.

16. The integrated circuit device according to claim 13, wherein: A cross-sectional area of ​​a lowermost portion of the first portion connected to the back power rail is greater than a cross-sectional area of ​​an uppermost portion of the second portion connected to the first portion.

17. An integrated circuit device, comprising: a substrate, the substrate comprising a back surface; a fin-type active region protruding from the substrate on a side of the substrate opposite to the back surface so as to define a portion of a trench region on the substrate, the fin-type active region being elongated in a first horizontal direction; at least one nanosheet, the at least one nanosheet being located on the fin-type active region and vertically separated from an upper surface of the fin-type active region; a gate line, the gate line surrounding the at least one nanosheet on the fin-type active area, the gate line extending in a second horizontal direction intersecting the first horizontal direction; a source / drain region, the source / drain region being adjacent to the gate line and located on the fin-type active region, the source / drain region being connected to the at least one nanosheet; a device isolation layer, the device isolation layer being located on the substrate and covering a portion of a sidewall of the fin type active area in the trench region; a through-hole power rail horizontally separated from each of the fin-type active region, the source / drain region, and the gate line and extending vertically through the device isolation layer and the gate line; as well as a back power rail extending vertically from the back side of the substrate through the substrate and connected to one end of the through-hole power rail, wherein the through-hole power rail comprises a first portion connected to the back power rail and a second portion located on the first portion, wherein the first portion at least includes a portion whose width in the second horizontal direction increases toward the back surface, and Wherein, a width of the second portion in the second horizontal direction decreases toward the back side.

18. The integrated circuit device according to claim 17, wherein: A vertical height where the first portion is connected to the second portion is between a vertical height of a portion of the fin-type active region closest to the through-hole power rail and a vertical height of an upper surface of the backside power rail.

19. The integrated circuit device according to claim 17, wherein: The width of the first portion in the second horizontal direction increases from an upper portion of the first portion toward a lower portion of the first portion connected to the rear surface.

20. The integrated circuit device according to claim 17, wherein: The width of the first portion in the second horizontal direction increases and then decreases from an upper portion of the first portion toward a lower portion of the first portion connected to the rear surface.

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